ETC IBM25PPC750L

PowerPC 740 and PowerPC 750
Microprocessor Datasheet
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Version 1.02
12/8/99
IBM Microelectronics Division
Notices
Before using this information and the product it supports, be sure to read the general information on the
back cover of this book.
Trademarks
The following are trademarks of International Business Machines Corporation in the United States, or
other countries, or both:
IBM
IBM Logo
PowerPC
AIX
PowerPC 750
PowerPC 740
Other company, product, and service names may be trademarks or service marks of others.
This document contains information on a new product under development by IBM. IBM reserves the
right to change or discontinue this product without notice.
© International Business Machines Corporation 1999.
Portions hereof ©International Business Machines Corporation, 1991-1999.
All rights reserved.
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Table of Contents
Preface ..................................................................................................................................................... 4
New Features for dd3.x ............................................................................................................................ 4
Overview ................................................................................................................................................... 5
Features ................................................................................................................................................... 6
General Parameters ................................................................................................................................. 8
Electrical and Thermal Characteristics ..................................................................................................... 9
DC Electrical Characteristics ................................................................................................................ 9
AC Electrical Characteristics .................................................................................................................. 13
Clock AC Specifications ...................................................................................................................... 13
60x Bus Input AC Specifications ......................................................................................................... 14
60x Bus Output AC Specifications ...................................................................................................... 16
L2 Clock AC Specifications ................................................................................................................. 18
L2 Bus Input AC Specifications ........................................................................................................... 20
L2 Bus Output AC Specifications ........................................................................................................ 21
IEEE 1149.1 AC Timing Specifications .................................................................................................. 22
PowerPC 740 Microprocessor Pin Assignments .................................................................................... 24
PowerPC 740 Microprocessor Pinout Listings ....................................................................................... 25
PowerPC 740 Package .......................................................................................................................... 28
Mechanical Dimensions of the PowerPC 740 255 CBGA Package .................................................... 29
PowerPC 750 Microprocessor Pin Assignments .................................................................................... 30
PowerPC 750 Package .......................................................................................................................... 33
Mechanical Dimensions of the PowerPC 750 360 CBGA Package .................................................... 34
System Design Information .................................................................................................................... 36
PLL Configuration ............................................................................................................................... 36
PLL Power Supply Filtering ................................................................................................................. 37
Decoupling Recommendations ........................................................................................................... 37
Connection Recommendations ........................................................................................................... 37
Output Buffer DC Impedance .............................................................................................................. 38
Pull-up Resistor Requirements ........................................................................................................... 39
Thermal Management Information ...................................................................................................... 40
Internal Package Conduction Resistance ........................................................................................... 41
Heat Sink Selection Example .............................................................................................................. 44
Ordering Information ............................................................................................................................... 46
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Version 1.02
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Preface
The PowerPC 740 and PowerPC 750 are members of the PowerPC family of reduced instruction set computer (RISC) microprocessors. The PPC740L and PPC750L microprocessors are the PID-8p implementations of the PowerPC 740 and PowerPC 750 in IBM CMOS 7S 0.20 µm copper technology. They are referred
to in the body of this document as “740“ and “750.”
Information in this document does not apply to implementations of the PowerPC 740 and PowerPC 750 in
other technologies, such as the PID-8t.
The information in this document is also specific to revision level dd3.2 of the (PID-8p) PPC740L and
PPC750L, and does not apply to previous revisions.
This document is generally written in terms of the 750. Unless otherwise noted, information that applies to the
750 also applies to the 740. Exceptions are detailed. The 740 die is identical to the 750 die, but the 740 package and pinout are different, in that the 740 does not pin out the L2 interface.
The 740 uses the same die as the 750, but the 740 does not pin out the L2 cache interface.
New Features for dd3.x
• Selectable I/O voltages on 60X bus and L2 bus. See Table , “Recommended Operating Conditions,” on
page 9. Older revs must leave these pins “no connect” or “tied high” for 3.3v I/Os. Ac timings are the
same for all I/O voltages modes unless otherwise noted.
• 60X bus to core frequency now also supports the 10x ratio. See Table , “PLL Configuration,” on page 36.
• Extra output hold on the 60x bus by L2_TSTCLK pin tied low is no longer available. The L2_TSTCLK pin
must now be tied to OVDD for normal operation. See Table , “60X Bus Output AC Timing Specifications for
the 7501,” on page 16.
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Version 1.02
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Overview
The 750 is targeted for high performance, low power systems and supports the following power management
features: doze, nap, sleep, and dynamic power management. The 750 consists of a processor core and an
internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. The L2 cache is not available
with the 740.
Figure 1 shows a block diagram of the 750.
Figure 1. 750 Block Diagram
Control Unit
Completion
Instruction Fetch
Branch Unit
32K ICache
System
Unit
BHT /
BTIC
Dispatch
GPRs
FXU1
FPRs
LSU
FXU2
32K DCache
FPU
Rename
Buffers
Rename
Buffers
L2 Tags
L2 Cache
BIU
12/8/99
Version 1.02
60X
BIU
Page 5
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Features
This section summarizes features of the implementation of the PowerPC 750 architecture. For details, see
the PowerPC 740 and PowerPC750 User’s Manual.
• Branch processing unit
- Four instructions fetched per clock.
- One branch processed per cycle (plus resolving 2 speculations).
- Up to 1 speculative stream in execution, 1 additional speculative stream in fetch.
- 512-entry branch history table (BHT) for dynamic prediction.
- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay
slots.
• Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units).
- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1,
fixed-point unit 2, or floating-point).
- Serialization control (predispatch, postdispatch, execution, serialization).
• Decode
- Register file access.
- Forwarding control.
- Partial instruction decode.
• Load/store unit
- One cycle load or store cache access (byte, half word, word, double word).
- Effective address generation.
- Hits under misses (one outstanding miss).
- Single-cycle misaligned access within double word boundary.
- Alignment, zero padding, sign extend for integer register file.
- Floating-point internal format conversion (alignment, normalization).
- Sequencing for load/store multiples and string operations.
- Store gathering.
- Cache and TLB instructions.
- Big and little-endian byte addressing supported.
- Misaligned little-endian support in hardware.
• Fixed-point units
- Fixed-point unit 1 (FXU1); multiply, divide, shift, rotate, arithmetic, logical.
- Fixed-point unit 2 (FXU2); shift, rotate, arithmetic, logical.
- Single-cycle arithmetic, shift, rotate, logical.
- Multiply and divide support (multi-cycle).
- Early out multiply.
• Floating-point unit
- Support for IEEE-754 standard single- and double-precision floating-point arithmetic.
- 3 cycle latency, 1 cycle throughput, single-precision multiply-add.
- 3 cycle latency, 1 cycle throughput, double-precision add.
- 4 cycle latency, 2 cycle throughput, double-precision multiply-add.
- Hardware support for divide.
- Hardware support for denormalized numbers.
- Time deterministic non-IEEE mode.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
• System unit
- Executes CR logical instructions and miscellaneous system instructions.
- Special register transfer instructions.
• Cache structure
- 32K, 32-byte line, 8-way set associative instruction cache.
- 32K, 32-byte line, 8-way set associative data cache.
- Single-cycle cache access.
- Pseudo-LRU replacement.
- Copy-back or write-through data cache (on a page per page basis).
- Supports all PowerPC memory coherency modes.
- Non-blocking instruction and data cache (one outstanding miss under hits).
- No snooping of instruction cache.
• Memory management unit
- 128 entry, 2-way set associative instruction TLB.
- 128 entry, 2-way set associative data TLB.
- Hardware reload for TLB's.
- 4 instruction BAT's and 4 data BATs.
- Virtual memory support for up to 4 exabytes (252) virtual memory.
- Real memory support for up to 4 gigabytes (232) of physical memory.
• Level 2 (L2) cache interface (Not available on the 740)
- Internal L2 cache controller and 4K-entry tags; external data SRAMs.
- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support.
- Copy-back or write-through data cache (on a page basis, or for all L2).
- 64-byte (256K/512K) and 128-byte (l-Mbyte) sectored line size.
- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst
SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs with optional parity checking.
- Supports Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3. The 750 supports the L2 frequency range specified in Section “L2 Clock AC Specifications,” on page 18. For higher L2 frequencies, please contact [email protected].
• Bus interface
- Compatible with 60x processor interface.
- 32-bit address bus with optional parity checking.
- 64-bit data bus (can be operated in 32-bit data bus mode) with optional parity checking.
- Bus-to-core frequency multipliers from 2x to 10x. See the Table , “PLL Configuration,” on page 36.
• Integrated power management
- Low-power 2.0/3.3V design.
- Three static power saving modes: doze, nap, and sleep.
- Automatic dynamic power reduction when internal functional units are idle.
• Integrated Thermal Management Assist Unit
- On-chip thermal sensor and control logic.
- Thermal Management Interrupts for software regulation of junction temperature.
• Testability
- JTAG interface.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
General Parameters
The following list provides a summary of the general parameters of the 750.
Technology
0.20µm CMOS (general lithography), six-layer copper metallization
0.12 ± 0.04µm Leff
Die Size
5.14mm x 7.78mm (40mm2)
Transistor count
6.35 million
Logic design
Fully-static
Package
740: Surface mount 21x21mm, 255-lead ceramic ball grid array (CBGA)
750: Surface mount 25x25mm, 360-lead ceramic ball grid array (CBGA)
PPC 740/PPC 750 core
power supply
2V Nominal (see Application Conditions)
I/O power supply
3.3V 2.5V, or 1.8V Nominal Selectable)
Page 8
Version 1.02
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Electrical and Thermal Characteristics
DC Electrical Characteristics
The 750 60x bus power supply can be either 3.3V, 2.5V, or 1.8V nominal; likewise, the L2 power supply can
be either 3.3V, 2.5V, or 1.8V nominal. See the pinout listing for more information
Absolute Maximum Ratings See Notes
Characteristic
Symbol
Value
Unit
Core supply voltage
VDD
-0.3 to 2.5
V
PLL supply voltage
AVDD
-0.3 to 2.5
V
L2 DLL supply voltage
L2AVDD
-0.3 to 2.5
V
60x bus supply voltage
OVDD(3.3V)
-0.3 to 3.6
V
OVDD(2.5V)
-0.3 to 2.8
OVDD(1.8V)
-0.3 to 2.1
L2OVDD
-0.3 to 3.6
V
VIN(3.3V)
-0.3 to 3.6
V
VIN(2.5V)
-0.3 to 2.8
VIN(1.8V)
-0.3 to 2.1
TSTG
-55 to 150
L2 bus supply voltage
Input voltage
Storage temperature range
°C
Note:
1. Functional and tested operating conditions are given in Table ”Recommended Operating Conditions,” below. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. Caution: VIN must not exceed OVDD by more than 0.3V at any time, including during power-on reset. This is a DC specification only. VIN overshoot transients up to OVDD+1V, and undershoots down to GND-1V (both measured with the 740 in the circuit) are allowed for up to 5ns.
3. Caution: OVDD must not exceed VDD/AVDD by more than 2.0V at any time during normal operation. On power up and power down, OVDD is allowed to
exceed VDD/AVDD by up to 3.3V for up to 20 ms, or by up to 2.5V for 40 ms. Excursions beyond 40 ms or 3.3V are not allowed.
4. Caution: VDD/AVDD must not exceed OVDD by more than 0.4V during normal operation. On power up and power down, VDD/AVDD is allowed to exceed
OVDD by up to1.0V for up to 20 ms, or by up to 0.7V for 40 ms. Excursions beyond 40 ms or 1.0V are not allowed.
Recommended Operating Conditions
Characteristic
Symbol
Value
Unit
Notes
Core supply voltage
VDD
2.0
V
1, 2
PLL supply voltage
AVDD
VDD
V
1
L2DLL supply voltage
L2AVDD
VDD
V
1
60x bus supply voltage, pin W1 tied high
OVDD(3.3V)
3.135 to 3.465
V
1
60x bus supply voltage pin W1 tied to HRESET
OVDD(2.5V)
2.375 to 2.625
V
1
60x bus supply voltage, pin W1 tied to GND
OVDD(1.8V)
1.71 to 1.89
V
1
L2 bus supply voltage, pin A19 tied high
L2OVDD(3.3V)
3.135 to 3.465
V
1
L2 bus supply voltage, pin A19 tied to HRESET
L2OVDD(2.5V)
2.375 to 2.625
V
1
Note:
1. These are recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
2. VDD and TJ are specified by the Application Conditions designator in the part number. See the Part Number Key on Page 43 for more information.
12/8/99
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Recommended Operating Conditions
Characteristic
L2 bus supply voltage, pin A19 tied to GND
Input voltage (Under AC conditions, inputs must go rail-torail for maximum AC timing performance.)
Symbol
Value
Unit
Notes
L2OVDD(1.8V)
1.71 to 1.89
V
1
VIN(60X)
GND to OVDD
V
1
VIN(L2)
GND to L2OVDD
V
1
TJ
-40 to 105
°C
1, 2
Die-junction temperature
Note:
1. These are recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
2. VDD and TJ are specified by the Application Conditions designator in the part number. See the Part Number Key on Page 43 for more information.
Package Thermal Characteristics1
Characteristic
Symbol
740
750
Unit
Thermal resistance, junction-to-case (top surface of die) typical
θJC
0.03
0.03
°C/W
Thermal resistance, junction-to-balls, typical
θJB
3.8 - 7.12
3.8 - 7.62
°C/W
50 FPM
16.0
15.1
°C/W
100 FPM
15.4
16.4
°C/W
150 FPM
14.9
14.2
°C/W
200 FPM
14.4
13.7
°C/W
21 x 21
25 x 25
mm2
5.12 x 7.78
5.12 x 7.78
mm2
Thermal resistance, junction-to-ambient, at airflow, no heat sink, typical
Package Size
Die Size
Note:
1. Refer to Section “Thermal Management Information,” on page 40 for more information about thermal management.
2. 3.8 °C/W is theoretical θJB mounted to infinite heat sink. The larger number applies to module mounted to a 1.8 mm thick, 2P card using 1 oz. copper
power/gnd planes, with effective area for heat transfer of 75mm x 75mm.
The 750 incorporates a thermal management assist unit (TAU) composed of a thermal sensor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). See the PowerPC
740 and PowerPC 750 User’s Manual for more information on the use of this feature. Specifications for the
thermal sensor portion of the TAU are found in the table below.
.
Thermal Sensor Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Minimum
Maximum
Unit
Notes
1
Temperature range
0
128
°C
1
2
Comparator settling time
20
—
ms
2
Note:
1. The temperature is the junction temperature of the die. The thermal assist unit's (TAU) raw output does not indicate an absolute temperature, but it
must be interpreted by software to derive the absolute junction temperature. For information on how to use and calibrate the TAU, contact
[email protected]. This specification reflects the temperature span supported by the design.
2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. For parts with
nominal operating frequencies (speed sort) above 266 MHz, the settling time = 20 µs × (266/nominal frequency). For example: for 500 MHz parts,
settling time = 20 µs × (266/500) = 10.6 µs. It is recommended that the maximum value be set in THRM3 under all conditions.
3. This value is guaranteed by design and is not tested.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Thermal Sensor Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Minimum
Maximum
Unit
Notes
3
3
Resolution
4
—
°C
4
Drift, all sources
—
.25
LSb
5
Linearity, error over range
—
1
LSb
6
Offset error, reducible
—
2
LSb
Note:
1. The temperature is the junction temperature of the die. The thermal assist unit's (TAU) raw output does not indicate an absolute temperature, but it
must be interpreted by software to derive the absolute junction temperature. For information on how to use and calibrate the TAU, contact
[email protected]. This specification reflects the temperature span supported by the design.
2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. For parts with
nominal operating frequencies (speed sort) above 266 MHz, the settling time = 20 µs × (266/nominal frequency). For example: for 500 MHz parts,
settling time = 20 µs × (266/500) = 10.6 µs. It is recommended that the maximum value be set in THRM3 under all conditions.
3. This value is guaranteed by design and is not tested.
DC Electrical Specifications
See Section “Recommended Operating Conditions,” on page 9, for operating conditions.
Characteristic
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except SYSCLK)
VIH(3.3V)
2.0
3.465
V
1,2
VIH(2.5V)
1.75
2.625
VIH()1.8V
1.4
1.89
VIL(3.3V)
GND
0.8
VIL(2.5V)
GND
0.7
VIL()1.8V
GND
0.5
CVIH(3.3V)
2.0
3.465
CVIH(2.5V)
2.0
2.625
CVIH(1.8V)
1.5
1.89
CVIL
–
Input leakage current, VIN = OVDD
IIN
Hi-Z (off state) leakage current, Vin = OVDD
Input low voltage (all inputs except SYSCLK)
SYSCLK input high voltage
V
V
1, 4
0.4
V
4
–
20
µA
1,2
ITSI
–
20
µA
1,2
Output high voltage, IOH = –6mA
VOH(3.3V)
2.4
–
V
Output high voltage, IOH = –6mA
VOH((2.5V))
1.9
–
V
Output high voltage, IOH = –3mA
VOH(1.8V)
1.4
–
V
Output low voltage, IOL = 6mA
VOL
–
0.4
V
Capacitance, VIN =0 V, f = 1MHz
CIN
–
5.0
pF
SYSCLK input low voltage
2,3
Note:
1. For 60x bus signals, the reference is OVDD, while L2OVDD is the reference for the L2 bus signals.
2. JTAG port signal levels are controlled by the BVSEL pin and are the same as those shown for the 60x bus. LSSD_MODE, L1_TSTCLK, and L2TSTCLK
receiver voltage levels are those shown for OVdd = 1.8V nominal, regardless of BVSEL. JTAG, LSSD_MODE, L1_TSTCLK, and L2TSTCLK values in
this table are guaranteed by design and characterization, and are not tested.
3. Capacitance values are guaranteed by design and characterization, and are not tested.
4. SYSCLK input high and low voltage: I/O timings are measured using a “rail to rail” SYSCLK; I/O timing may be less favorable if SYSCLK does not travel
from GND to OVDD.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Power Consumption for 740 and 750
See Table “Recommended Operating Conditions,” on page 9, for operating conditions
Actual Processor CPU Frequency
Unit
Notes
300
333
350
366
375
400
433
466
500
Typical
3.7
4.0
4.1
4.3
4.4
4.5
5.0
5.5
6.0
W
1,3,4
Maximum
4.5
5.0
5.2
5.5
5.7
6.0
6.3
6.8
7.5
W
1,2,4
1.7
1.7
1.7
1.8
1.8
1.9
2.1
2.2
2.3
W
1,2,4
250
250
250
250
250
250
250
250
250
mW
1, 4
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mW
1, 4
Full-On Mode
Doze Mode
Maximum
Nap Mode
Maximum
Sleep Mode
Maximum
Note:
1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include I/O Supply Power (OVDD and L2OVDD) or PLL/DLL supply power
(AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically <10% of VDD power. Worst case power consumption for AVDD =
15mW and L2AVDD = 15mW.
2. Maximum power is shown for a system executing worst case benchmark sequences at:
• VDD = AVDD = L2VDD = 2.1V;
• OVDD = L2OVDD = 3.3V;
• Tj = 65 °C
Maximum power at 85 °C can be derived by adding 0.1 W to the maximum power shown at 65 °C. Maximum power at 105 °C can be derived by adding 0.3 W to the maximum power shown at 65 °C.
3. Typical power is an average value shown for a system executing typical applications and benchmark sequences at:
• VDD = AVDD = L2AVDD = 2.0V (300 through 400 MHz);
• VDD = AVDD = L2AVDD = 2.05V (433 through 500 MHz);
• OVDD = L2OVDD = 3.3V;
• Tj = 45 °C.
4. Guaranteed by design and characterization, and is not tested.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the 750. After fabrication, parts are sorted by maximum processor core frequency as shown in the Section “Clock AC Specifications,” on page 13, and tested for
conformance to the AC specifications for that frequency. Parts are sold by maximum processor core frequency, subject to the specified application conditions; see Section “Ordering Information,” on page 46.
Unless otherwise noted, all timings apply for all I/O supply voltages.
Clock AC Specifications
The following table provides the clock AC timing specifications as defined in Figure 2.
Clock AC Timing Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
1
2,3
4
Characteristic
Fmax ≥ 400MHz
Fmax = 300-375MHz
Unit
Notes
Min
Max
Min
Max
Processor frequency
TBD
As specified by
part number
250
As specified by
part number
MHz
6
SYSCLK frequency
25
100
31
100
MHz
1
SYSCLK cycle time
10
40
10
32
ns
SYSCLK rise and fall time
–
1.0
–
1.0
ns
2,3
SYSCLK duty cycle measured
at Vm
40
60
40
60
%
3
SYSCLK jitter
–
±150
–
±150
ps
4,3
Internal PLL relock time
–
100
–
100
µs
5
Note:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, and CPU (core)
frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section “PLL
Configuration,” on page 36 for valid PLL_CFG[0:3] settings. Bus operation above 100 MHz is possible, but requires careful timing analysis. Contact
IBM for details.
2. Rise and fall times for the SYSCLK input are measured from 0.5 to 1.5V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under ±150ps. Contact IBM for operation with Spread Spectrum clocks or clocks
with more than ± 150 ps total jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
6. Under certain conditions, operation at core frequencies below those stated is possible. Contact IBM for details.
Figure 2. SYSCLK Input Timing Diagram
1
2
4
3
4
CVIH
VM
SYSCLK
CVIL
Vm = OVdd/2
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
60x Bus Input AC Specifications
The following table provides the 60X bus input AC timing specifications for the 750 as defined in Figure 3 and
Figure 4. Input timing specifications for the L2 bus are provided in Section, “L2 Bus Input AC Specifications”
on page 20.
60X Bus Input Timing Specifications1
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
All Frequencies
Minimum
Maximum
Unit
Notes
10a
Address/Data/Transfer Attribute Inputs Valid to SYSCLK (Input
Setup)
2.5
—
ns
2
10b
All Other Inputs Valid to SYSCLK (Input Setup)
2.5
—
ns
3
10c
Mode Select Input Setup to HRESET (DRTRY,TLBISYNC)
8
—
tsysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute Inputs Invalid (Input
Hold)
0.6
—
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input Hold)
0.6
—
ns
3
11c
HRESET to mode select input hold
0
—
ns
4,6,7
(DRTRY, TLBISYNC)
Note:
1. Input specifications are measured from the Vm of the signal in question to the Vm of the rising edge of the input SYSCLK. Input and output timings are
measured at the pin (see Figure 3).
2. Address/Data Transfer Attribute inputs are composed of the following–A[0:31], AP[0:3], TT[0:4],TBST, TSIZ[0:2], GBL, DH[0:31], DL[0:31], DP[0:7].
3. All other signal inputs are composed of the following–TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, TBEN, QACK,
TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4).
5. tSYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK
to compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the
PLL re-lock time during the power-on reset sequence.
Page 14
Version 1.02
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 3. Input Timing Diagram
VM
SYSCLK
10a 10b
11a 11b
ALL INPUTS
VM
VM
Vm = 1.4 V for OVdd = 3.3 V., else Vm = OVdd/2
Figure 4. Mode Select Input Timing Diagram
VIH
HRESET
10c
11c
MODE PINS
VIH = 2.0V
12/8/99
Version 1.02
Page 15
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
60x Bus Output AC Specifications
The following table provides the 60x bus output AC timing specifications for the 750 as defined in Figure 5.
Output timing specification for the L2 bus are provided in the Section “L2 Bus Output AC Specifications,” on
page 21.
60X Bus Output AC Timing Specifications for the 7501
See Table “Recommended Operating Conditions,” on page 9 for operating conditions, CL = 50pF2
Num
Characteristic
All Frequencies
Minimum
Unit
Notes
ns
8
Maximum
12
SYSCLK to Output Driven (Output Enable Time)
0.5
13
SYSCLK to Output Valid (TS, ABB, ARTRY, DBB, and TBST)
–
4.5
ns
5
14
SYSCLK to all other Output Valid (all except TS, ABB, ARTRY,
DBB, and TBST)
–
5.0
ns
5
15
SYSCLK to Output Invalid (Output Hold)
ns
3, 8, 9
16
SYSCLK to Output High Impedance (all signals except ABB,
ARTRY, and DBB)
–
6.0
ns
8
17
SYSCLK to ABB and DBB high impedance after precharge
–
1.0
tSYSCLK
4, 6, 8
18
SYSCLK to ARTRY high impedance before precharge
–
5.5
ns
8
19
SYSCLK to ARTRY precharge enable
ns
3, 4, 7
20
Maximum delay to ARTRY precharge
1
tSYSCLK
4, 7
21
SYSCLK to ARTRY high impedance after precharge
2
tSYSCLK
4, 7, 8
1.0
0.2×tSYSCLK + 1.0
Note:
1. All output specifications are measured from Vm of the rising edge of SYSCLK to Vm of the signal in question. Both input and output timings are measured at the pin.
2. All maximum timing specifications assume CL = 50pF.
3. This minimum parameter assumes CL = 0pF.
4. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
5. This footnote has been deleted.
6. Nominal precharge width for ABB and DBB is 0.5 tSYSCLK.
7. Nominal precharge width for ARTRY is 1.0 tSYSCLK.
8. Guaranteed by design and characterization, and not tested.
9. Connecting L2_TSTCLK to GND no longer provides additional Output Hold. For new designs, L2_TSTCLK should be pulled up to OVdd, but it can be
left connected to GND in Legacy systems.
Page 16
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 5. Output Timing Diagram
SYSCLK
VM
VM
VM
14
15
All Outputs
(Except TS,
ABB, DBB,
ARTRY)
16
12
VM
VM
13
15
13
TS
16
VM
17
ABB, DBB
21
20
19
ARTRY
18
Vm = 1.4 V for OVdd = 3.3 V., else Vm = OVdd/2
12/8/99
Version 1.02
Page 17
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Clock AC Specifications
The following table provides the L2CLK output AC timing specifications for the 750 as defined in Figure 6.
L2CLK Output AC Timing Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
L2CLK frequency
80
250
MHz
1, 5
22
L2CLK cycle time
4.0
12.5
ns
23
L2CLK duty cycle
50
%
2
—
L2CLK
4
L2CLK jitter
±150
ps
3, 6
L2CLK skew
0
ps
7
Internal DLL-relock time
640
Note:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The internal design supports higher L2CLK frequencies. Consult IBM PowerPC Application Engineering ([email protected]) before operating the L2 SRAMs above 250 MHz. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating
frequencies. L2CLKOUTA and L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The major component of L2CLK jitter is passed through from SYSCLK. While SYSCLK jitter is less then ±150 ps, L2CLK jitter is also less than ±150 ps.
SYSCLK jitter in excess of ±150 ps causes L2CLK jitter to exceed ±150 ps.
4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time
duration in nanoseconds. Re-lock timing is guaranteed by design and characterization, and is not tested.
5. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
6. Guaranteed by design and characterization, not tested.
7. Skew between the L2 output clocks is included in the other timing specs.
Page 18
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 6. L2CLK_OUT Output Timing Diagram
L2 SIngle-Ended Clock Mode
22
23
VM
VM
VM
VM
VM
VM
VM
VM
VM
L2CLK_OUTA
L2CLK_OUTB
L2SYNC_OUT
Vm = 1.4 V for L2OVdd = 3.3 V., else Vm = L2OVdd/2
L2 Differential Clock Mode
22
L2OVDD
23
L2CLK_OUTB
VM
VM
VM
VM
VM
VM
L2CLK_OUTA
GND
L2SYNC_OUT
Vm = 1.4 V for L2OVdd = 3.3 V., else Vm = L2OVdd/2
12/8/99
Version 1.02
Page 19
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Bus Input AC Specifications
Some specifications are shown in the following table as a Function of Maximum Core Frequency (Fmax).
These specifications refer to the effective Fmax of the part after derating for application conditions. For example, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or
exceed the specifications shown for Fmax = 400 MHz.
L2 Bus Input Interface AC Timing Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Min
Max
Unit
L2SYNC_IN rise and fall time
—
1.0
ns
2,3
24
Data and parity input setup to L2SYNC_IN, Fmax up
through 375 MHz.
1.5
—
ns
1
24
Data and parity input setup to L2SYNC_IN, Fmax = 400
MHz.
1.4
—
ns
1
24
Data and parity input setup to L2SYNC_IN, Fmax = 433 and
450 MHz.
1.1
—
ns
1
24
Data and parity input setup to L2SYNC_IN, Fmax = 466 and
500 MHz.
1.0
—
ns
1
25
L2SYNC_IN to data and parity input hold
0.5
—
ns
1
29,30
Notes
Note:
1. All input specifications are measured from the Vm of the signal in question to the Vm of the rising edge of the input L2SYNC_IN. Input timings are
measured at the pins (see Figure 7).
2. Rise and fall times for the L2SYNC_IN input are measured from 0.5 to 1.5V.
3. Guaranteed by design and characterization, and not tested.
Figure 7. L2 Bus Input Timing Diagrams
29
L2SYNC_IN
30
VM
24
25
ALL INPUTS
VM
VM
Vm = 1.4 V for L2OVdd = 3.3 V., else Vm = L2OVdd/2
Page 20
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Bus Output AC Specifications
L2 Bus Output Interface AC Timing Specifications1
See Table “Recommended Operating Conditions,” on page 9 for operating conditions, CL = 20pF3
Num
Characteristic
L2CR[14:15] is equivalent to:
01
002
Unit
10
Notes
11
Min
Max
Min
Max
Min
Max
Min
Max
26
L2SYNC_IN to output valid,
Fmax7 up through 375 MHz.
—
3.2
—
3.7
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid, Fmax
= 400 MHz.
—
3.0
—
3.5
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid, Fmax
= 433 and 450 MHz.
—
2.6
—
3.1
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid, Fmax
= 466 and 500 MHz.
—
2.4
—
2.9
—
Rsv5
—
Rsv5
ns
27
L2SYNC_IN to output hold
0.5
—
1.0
—
Rsv5
—
Rsv5
—
ns
4,6
28
L2SYNC_IN to high impedance
—
3.5
—
4.0
—
Rsv5
—
Rsv5
ns
6
Note:
1. All outputs are measured from the Vm of the rising edge of L2SYNC_IN to the Vm of the signal in question. The output timings are measured at the pins
(see Figure 8).
2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,
L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 01 is recommended.
3. All maximum timing specifications assume CL = 20pF.
4. This measurement assumes CL= 5pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
7. Specifications are shown as a Function of Maximum Core Frequency (Fmax). They refer to the effective Fmax of the part after derating for application
conditions. For example, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or exceed the specifications shown for Fmax = 400 MHz.
Figure 8. L2 Bus Output Timing Diagrams
VM
VM
L2SYNC_IN
26
27
ALL OUTPUTS
VM
VM
28
L2DATA BUS
Vm = 1.4 V for L2OVdd = 3.3 V., else Vm = L2OVdd/2
12/8/99
Version 1.02
Page 21
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
IEEE 1149.1 AC Timing Specifications
The table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9, Figure 10,
Figure 11, and Figure 12. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
JTAG AC Timing Specifications (Independent of SYSCLK)
See Table “Recommended Operating Conditions,” on page 9 for operating conditions, CL = 50pF.
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
—
ns
2
TCK clock pulse width measured at 1.4V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
4
spec obsolete, intentionally omitted
5
TRST assert time
25
—
ns
1
6
Boundary-scan input data setup time
4
—
ns
2
7
Boundary-scan input data hold time
16
—
ns
2
8
TCK to output data valid
4
20
ns
3, 5
9
TCK to output high impedance
3
19
ns
3, 4
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
16
—
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9. JTAG Clock Input Timing Diagram
1
2
TCK
3
VM
2
VM
VM
3
Vm = 1.4 V for OVdd = 3.3 V., else Vm = OVdd/2
Page 22
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 10. TRST Timing Diagram
TRST
5
Figure 11. Boundary-Scan Timing Diagram
TCK
7
6
Data Inputs
Input Data Valid
8
Data Outputs
Output Data Valid
9
Data Outputs
Figure 12. Test Access Port Timing Diagram
TCK
10
TDI, TMS
11
Input Data Valid
12
Output Data Valid
TDO
13
9
TDO
12/8/99
Version 1.02
Page 23
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PowerPC 740 Microprocessor Pin Assignments
The following sections contain the pinout diagrams for the PowerPC 740, a 255 pin ceramic ball grid array
(BGA) package.
Figure 13 (in part A) shows the pinout of the PPC 740, a 255 pin Ceramic Ball Grid Array (CBGA) package as
viewed from the top surface. Part B shows the side profile.
Figure 13. Pinout of the PowerPC 740 BGA Package as Viewed from the Top Surface
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
Part A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Not to Scale
Part B
Substrate Assembly.
View
Encapsulation
Page 24
Die
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PowerPC 740 Microprocessor Pinout Listings
Pinout Listing for the PowerPC 740 255 CBGA Package
Signal Name
Pin Number
Active
I/O
A[0:31]
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13,
GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03,
F16, F04, G13, K01, G15, K02, H16, M01, J15, P01
High
I/O
AACK
L02
Low
Input
ABB
K04
Low
I/O
AP[0:3]
C01, B04, B03, B02
High
I/O
ARTRY
J04
Low
I/O
AVDD
A10
—
—
BG
L01
Low
Input
BR
B06
Low
Output
BVSEL1
H04
CI
E01
Low
Output
CKSTP_IN
D08
Low
Input
CKSTP_OUT
A06
Low
Output
CLK_OUT
D07
—
Output
DBB
J14
Low
I/O
DBG
N01
Low
Input
DBDIS
H15
Low
Input
DBWO
G04
Low
Input
DH[0:31]
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11,
R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07,
R07, T07, P06, N06, R06, T06, R05, N05, T05, T04
High
I/O
DL[0:31]
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16,
N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12,
T13, P03, N03, N04, R03, T01, T02, P04, T03, R04
High
I/O
DP[0:7]
M02, L03, N02, L04, R01, P02, M04, R02
High
I/O
DRTRY
G16
Low
Input
GBL
F01
Low
I/O
GND
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10,
F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07,
J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03,
M06, M08, M09, M11, M14, P05, P12
—
—
12/8/99
Input
Version 1.02
Page 25
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pinout Listing for the PowerPC 740 255 CBGA Package (cont.)
Signal Name
Pin Number
Active
I/O
HRESET
A07
Low
Input
INT
B15
Low
Input
L1_TSTCLK 2
D11
High
Input
L2_TSTCLK 2
D12
High
Input
LSSD_MODE 2
B10
Low
Input
MCP
C13
Low
Input
NC (No-Connect)
B07, B08, C03, C06, C08, D05, D06, J16, A04, A05, A02, A03,
B01, B05
—
—
OVDD
C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05,
K12, K14, M05, M07, M10, M12, P07, P10
—
—
PLL_CFG[0:3]
A08, B09, A09, D09
High
Input
QACK
D03
Low
Input
QREQ
J03
Low
Output
RSRV
D01
Low
Output
SMI
A16
Low
Input
SRESET
B14
Low
Input
SYSCLK
C09
—
Input
TA
H14
Low
Input
TBEN
C02
High
Input
TBST
A14
Low
I/O
TCK
C11
High
Input
TDI
A11
High
Input
TDO
A12
High
Output
TEA
H13
Low
Input
TLBISYNC
C04
Low
Input
TMS
B11
High
Input
TRST
C10
Low
Input
TS
J13
Low
I/O
TSIZ[0:2]
A13, D10, B12,
High
Output
TT[0:4]
B13, A15, B16, C14, C15
High
I/O
WT
D02
Low
Output
Page 26
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pinout Listing for the PowerPC 740 255 CBGA Package (cont.)
Signal Name
Pin Number
Active
I/O
VDD 3
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06,
J08, J09, J11, K07, K10, L06, L08, L09, L11
—
—
VOLTDET4
F03
Low
Output
Note:
1. BVSEL Function
Unconnected or Pulled to OVdd (3.3V nominal)
OVdd = 3.3 V nominal
Connected to HRESET
OVdd = 2.5 V nominal
Connected to GND
OVdd = 1.8 V nominal
If BVSEL is connected to GND with a series resistor, the resistor value must be 10 Ω or less.
2. These are test signals for factory use only and must be pulled up to OVdd for normal operation.
3. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
4. Internally tied to GND in the 255 CBGA package. This is NOT a supply pin.
12/8/99
Version 1.02
Page 27
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PowerPC 740 Package
Package Type
Ceramic Ball Grid Array (CBGA)
Package outline
21 x 21mm
Interconnects
255 (16 x 16 ball array - 1)
Pitch
1.27mm (50mil)
Minimum module height
2.45mm
Maximum module height
3.00mm
Ball diameter
0.89mm (35mil)
Page 28
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Mechanical Dimensions of the PowerPC 740 255 CBGA Package
Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature of the 255 CBGA
Package
2X
Top View
0.2
D
A1 CORNER
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
DESIGNATED WITH A BALL MISSING FROM
MILLIMETERS
E
E1
DIM
A
A1
A2
b
D
D1
e
E
E1
MIN
MAX
2.45
3.00
0.80
1.00
0.90
1.10
0.82
0.93
21.00 BSC
5.443 BSC
1.27 BSC
21.00 BSC
8.075 BSC
C
0.15 C
2X
0.2
D1
B
A1 CORNER
1 2 3 4 5 6 7 8 9 10111213141516
There is no ball
in the A01 position
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
e/2
X-ray view of balls
from top of package
e
e/2
255X
b
0.3 C A B
A2
A1
0.15 C
A
12/8/99
Version 1.02
Page 29
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PowerPC 750 Microprocessor Pin Assignments
The following sections contain the pinout diagrams for the PowerPC 750 ceramic ball grid array 360 CBGA
packages.
Figure 15 (in part A) shows the pinout of the 360 CBGA package as viewed from the top surface. Part B
shows the side profile of the 360 CBGA package to indicate the direction of the top surface view.
Figure 15. Pinout of the 750 360 CBGA Package as Viewed from the Top Surface
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19
Part A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Part B
W
Substrate Assembly.
Encapsulation
Page 30
Version 1.02
Not to Scale
View
Die
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pinout Listing for the PowerPC 750 360 CBGA package
Signal Name
Pin Number
Active
I/O
A[0:31]
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2,
L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2
High
I/O
AACK
N3
Low
Input
ABB
L7
Low
I/O
AP[0:3]
C4, C5, C6, C7
High
I/O
ARTRY
L6
Low
I/O
AVDD 1
A8
—
—
BG
H1
Low
Input
BR
E7
Low
Output
BVSEL2
W012
—
Input
CKSTP_OUT
D7
Low
Output
CI
C2
Low
Output
CKSTP_IN
B8
Low
Input
CLKOUT
E3
—
Output
DBB
K5
Low
I/O
DBDIS
G1
Low
Input
DBG
K1
Low
Input
DBWO
D1
Low
Input
DH[0:31]
W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10,
W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3,
U4, R5
High
I/O
DL[0:31]
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13,
W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3,
U3, W2
High
I/O
DP[0:7]
L1, P2, M2, V2, M1, N2, T3, R1
High
I/O
DRTRY
H6
Low
Input
GBL
B1
Low
I/O
GND
D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11,
H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16,
L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16,
R8, R12, T4, T6, T10, T14, T16
—
—
HRESET
B6
Low
Input
C11
Low
Input
F8
High
Input
L2ADDR[0:16]
L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17,
J14, J13, H19, G18
High
Output
L2AVDD
L13
—
—
L2CE
P17
Low
Output
L2CLKOUTA
N15
—
Output
INT
L1_TSTCLK
12/8/99
3
Version 1.02
Page 31
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pinout Listing for the PowerPC 750 360 CBGA package (cont.)
Signal Name
Pin Number
Active
I/O
L2CLKOUTB
L16
—
Output
L2DATA[0:63]
U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18,
V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13,
N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14,
G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17,
B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14,
E13
High
I/O
L2DP[0:7]
V14, U16, T19, N18, H14, F17, C19, B15
High
I/O
L2OVDD
D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, F15
—
—
L2SYNC_IN
L14
—
Input
L2SYNC_OUT
M14
—
Output
L2_TSTCLK3
F7
High
Input
L2VSEL
A192
—
Input
L2WE
N16
Low
Output
L2ZZ
G17
High
Output
LSSD_MODE3
F9
Low
Input
MCP
B11
Low
Input
—
—
—
—
NC (No-Connect)
B3, B4, B5, W19, K9,
OVDD 2
D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9,
R11, T5, T8, T12
PLL_CFG[0:3]
A4, A5, A6, A7
High
Input
QACK
B2
Low
Input
QREQ
J3
Low
Output
RSRV
D3
Low
Output
SMI
A12
Low
Input
SRESET
E10
Low
Input
SYSCLK
H9
—
Input
TA
F1
Low
Input
TBEN
A2
High
Input
TBST
A11
Low
I/O
TCK
B10
High
Input
TDI
B7
High
Input
TDO
D9
High
Output
TEA
J1
Low
Input
TLBISYNC
A3
Low
Input
TMS
C8
High
Input
TRST
A10
Low
Input
TS
K7
Low
I/O
Page 32
K114,
K194
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pinout Listing for the PowerPC 750 360 CBGA package (cont.)
Signal Name
Pin Number
Active
I/O
TSIZ[0:2]
A9, B9, C9
High
Output
TT[0:4]
C10, D11, B12, C12, F11
High
I/O
WT
C3
Low
Output
VDD 5
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
—
—
VOLTDET6
K13
High
Output
Note:
1. For dd3.x on the 750 only, AVdd is no longer connected to the BGA pin. AVdd is filtered on the module
from Vdd. The 740 dd3.2 does require AVdd.
2. BVSEL and L2VSEL Function
Unconnected
L2OVdd = 3.3 V nominal
Connected to HRESET
OVdd = 2.5 V nominal
Connected to GND
OVdd = 1.8 V nominal
If BVSEL or L2VSEL is connected to GND with a series resistor, the resistor value must be 10 Ω or less.
3. These are test signals for factory use only and must be pulled up to OVdd for normal operation. During
normal operation, L2_TSTCLK can be connected to GND if required.
4. These pins are reserved for potential future use as additional L2 address pins.
5. OVdd inputs supply power to the I/O drivers, and Vdd inputs supply power to the processor core.
6. Internally tied to L2OVDD in the 750 360 CBGA package. This is NOT a supply pin.
PowerPC 750 Package
Package Type
Ceramic Ball Grid Array (CBGA)
Package outline
25 x 25mm
Interconnects
360 (19 x 19 ball array - 1)
Pitch
1.27mm (50mil)
Minimum module height
2.65mm
Maximum module height
3.20mm
Ball diameter
0.89mm (35mil)
12/8/99
Version 1.02
Page 33
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Mechanical Dimensions of the PowerPC 750 360 CBGA Package
Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature of the 360 CBGA Package
2X
0.2
Top View
A
D
CAPACITOR
D1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
DESIGNATED WITH A BALL MISSING FROM
THE ARRAY.
MILLIMETERS
CHIP
E3
E2
E1
E
E2
E3
D2
D3
D2
D3
2X
0.2
DIM
Minimum
Maximum
A
2.65
3.20
A1
0.80
1.00
A2
1.10
1.30
b
0.82
0.93
D
25.00 BSC
D1
5.443
D2
2.48
D3
6.3
e
1.27 BSC
E
25.00 BSC
E1
8.075
E2
2.48
E3
7.43
A01 Corner Locator
B
A01 Corner
C
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
0.15 C
W
V
U
T
R
P
N
M
X-ray view of balls
L
K
from top of package
J
H
G
F
E
D
C
(18x)
B
A
e
There is no ball in the A01 position
(18x)
360X
b
0.3 C A B
0.15 C
A1
A
Not To Scale
Page 34
A2
A01 Corner
Note: All caps on the SCM are lower in height than the processor die.
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 17. 360 CBGA Decoupling Capacitors
C4
C3
GND
GND
0.51 (typical)
1.85 (typical)
VDD
0.83 (typical)
OVDD
3.45 typical
C5
GND
VDD
L2OVDD
GND
C2
GND
C1
CHIP
OVDD
C6
GND
VDD
L2OVDD
See note 1.
GND
GND
C7
C8
A0 Corner
Chip Carrier (pins down)
Notes:
1. For PID8 - 750 dd2.x, this capacitor is connected to Vdd. For dd3.x, this capacitor is connected to AVdd.
2. For dd3.x, AVdd is no longer brought to the BGA pin.
12/8/99
Version 1.02
Page 35
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
System Design Information
PLL Configuration
The 750 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation.
PLL Configuration
PLL_CFG
(0:3)
Processor to Bus Frequency Ratio
VCO Divider5
bin
dec
0000
0
Rsv1
n/a
0001
1
7.5x
2
0010
2
7x
2
0011
3
PLL Bypass3
n/a
0100
4
2x6
2
0101
5
6.5x
2
0110
6
10x
2
0111
7
4.5x
2
1000
8
3x
2
1001
9
5.5x
2
1010
10
4x
2
1011
11
5x
2
1100
12
8x
2
1101
13
6x
2
1110
14
3.5x
2
1111
15
4
Off
n/a
Note:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode
operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. In Clock-off mode, no clocking occurs inside the 750 regardless of the SYSCLK input.
5. The VCO to core clock ratio is 2x for 740/750. This simplifies clock frequency calculations so the user can disregard the VCO frequency. The VCO will
operate correctly when the core clock is within specification.
6. Not tested.
Page 36
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PLL Power Supply Filtering
The AVDD and L2AVdd are power signals provided on the 750 to provide power to the clock generation phaselocked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power
supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in Figure 18. The
circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much noise as possible.
For dd3.2, AVdd is filtered on the module from Vdd for the 750 only and can be connected or not, at the
designer’s convenience. The 740 requires AVdd to be supplied as usual.
Figure 18. PLL Power Supply Filter Circuit
10 Ω
VDD
AVDD (or L2AVDD)
10µF
0.1µF
GND
Decoupling Recommendations
Due to the dynamic power management of the 750, which features large address and data buses, as well as
high operating frequencies, the 750 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the 750 system, and the 750 itself requires a clean, tightly regulated source of power.
Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with
a low ESR (effective series resistance) rating at each VDD and OVDD pin (and L2OVDD for the 360 CBGA) of the
750. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD
and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should range in value from 220pF to 10µF to provide both high- and low-frequency filtering,
and should be placed as close as possible to their associated VDD or OVDD pins. Suggested values for the VDD
pins – 220pF (ceramic), 0.01µF (ceramic), and 0.1µf (ceramic). Suggested values for the OVDD pins – 0.01µF
(ceramic), 0.1µf (ceramic), and 10µF (tantalum). Only SMT (surface-mount technology) capacitors should be
used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100µF (AVX TPS tantalum) or 330µF (AVX TPS tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to VDD. Unused active high inputs should be connected to GND.
All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, and GND, pins of the 750.
12/8/99
Version 1.02
Page 37
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
External clock routing should ensure that the rising edge of the L2 clock is coincident at the CLK input of all
SRAMs and at the L2SYNC_IN input of the 750. The L2CLKOUTA network could be used only, or the
L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs.
Output Buffer DC Impedance
The 750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z0,
an external resistor is connected to the chip pad, either to OVDD or GND. Then the value of such resistor is
varied until the pad voltage is OVDD/2; see Figure 19, “Driver Impedance Measurement,” below.
The output impedance is actually the average of two components, the resistances of the pull-up and pulldown devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until Pad = OVDD/2. RN
then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open),
and RP is trimmed until Pad = OVDD/2. RP then becomes the resistance of the pull-up devices. With a properly
designed driver RP and RN are close to each other in value, then Z0 = (RP + RN)/2.
Figure 19. Driver Impedance Measurement
OVDD
RN
SW2
Pad
Data
SW1
RP
GND
The following table summarizes the impedance a board designer would design to for a typical process. These
values were derived by simulation at 65°C. As the process improves, the output impedance will be lower by
several ohms than this typical value.
Impedance Characteristics
VDD = 1.9VDC, L2OVDD=OVDD = 3.3VDC, TJ = 65°C
Process
60x
L2
Symbol
Unit
Typical
43
38
Z0
Ω
Page 38
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Pull-up Resistor Requirements
The 750 requires high-resistive (weak: 10KΩ) pull-up resistors on several control signals of the bus interface
to maintain the control signals in the negated state after they have been actively negated and released by the
750 or other bus masters. These signals are: TS, ABB, DBB, TBST, GBL, and ARTRY.
In addition, the 750 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7KΩ
- 1KΩ) if it is used by the system. This signal is: CKSTP_OUT.
If address or data parity is not used by the system, it should be disabled using HID0. This also disables the
parity input receivers. In most systems, the unused (and disabled) parity pins can be left unconnected; however, in some systems, these parity pins must be pulled up to OVdd by a weak (or stronger) pull-up.
No pull-up resistors are normally required for the L2 interface, the 60x bus address and AP lines, or the 60x
bus data and DP lines. The data bus input receivers are normally turned off when no read operation is in
progress and do not require pull-up resistors on the data bus.
HRESET and GBL must be actively driven.
Resistor Pull-up / Pull-down Requirements
Required or Recommended Actions
Signals
Strong pull-up required
CKSTP_OUT
Weak pull-up required
TLBISYNC, LSSD_MODE, L1_TSTCLK, L2TSTCLK, TS, ABB, DBB, ARTRY,
GBL, TBST
Weak pull-up or pull-down required
TCK
Weak pull-up recommended
SRESET, SMI, INT, MCP, CKSTP_IN
Weak pull-up recommended if pin not used
AP[0:3], DP[0:3]
Errata Summary
#
Problem
Description
Impact
Solution(s)
Applies to
Version 3.2
1
L2 cache invalidate may If DPM is enabled during Possible system failure Turn DPM off during a
fail with DPM enabled.
a global invalidate of the after L2 initialization and L2 tag invalidate.
L2 cache, the global
start-up.
invalidate may not invalidate all the L2’s tags.
Yes
3
dcbz that hits in L1
cache may not retry
snoop.
If a dcbz hits in the L1
cache, a snoop received
at the same time to that
address may not be serviced or get retried.
Stale data from system
memory may be read by
the other bus master,
and the line may
become valid in multiple
caches.
Limit use of dcbz to
data that is protected
through software synchronization.
Yes
5
Segment register
updates may corrupt
data translation.
mtsr<in> followed by an
instruction causing a
page data address translation can cause contention for the segment
registers.
Possible access to incorrect real address locations or false translation
and data access exceptions.
Insert isync, sc, or rfi
between andy mtsr<in>
and instructions that
cause a page data
address translation.
Yes
8
(Advisory)
12/8/99
Stfd of uninitialized FPR A stfd will hang the part if Any system using a stfd. Initialize all FPRs at
can hang part.
its source FPR has powPOR.
ered up in a certain
state.
Version 1.02
Yes
Page 39
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Thermal Management Information
This section provides thermal management information for the CBGA package for air cooled applications.
Proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, air
flow, and the thermal interface material. To reduce the die-junction temperature, heat sinks may be attached
to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, and
mounting clip and screw assembly, see Figure 20.
Figure 20. Package Exploded Cross-Sectional View with Several Heat Sink Options
Heat Sink
CBGA Package
Heat Sink clip
Adhesive
or
Thermal
Interface
Material
Printed
Circuit
Board
Option
Maximum Heatsink Weight Limit for the 360 CBGA
Force
Maximum (pounds)
Dynamic Compression
10.0
Dynamic Tensile
2.5
Static Constant (Spring Force)
8.2
Page 40
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
The board designer can choose between several types of heat sinks to place on the 750. There are several
commercially-available heat sinks for the 750 provided by the following vendors:
Chip Coolers, Inc.
333 Strawberry Field Rd.
Warwick, RI 02887-6979
800-227-0254 (USA/Canada)
401-739-7600
Thermalloy
2021 W. Valley View Lane
P.O. Box 810839
Dallas, TX 75731
214-243-4321
International Electronic Research Corporation (IERC) 818-842-7277
135 W. Magnolia Blvd.
Burbank, CA 91502
Aavid Engineering
One Kool Path
Laconic, NH 03247-0440
603-528-3400
Wakefield Engineering
60 Audubon Rd.
Wakefield, MA 01880
617-245-5900
Ultimately, the final selection of an appropriate heat sink for the 750 depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table “Package Thermal Characteristics1,” on page 10,
the intrinsic conduction thermal resistance paths are as follows.
• Die junction-to-case thermal resistance
• Die junction-to-ball thermal resistance
Figure 21 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
12/8/99
Version 1.02
Page 41
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 21. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Radiation
External Resistance
Convection
Heat Sink
Thermal Interface Material
Die/Package
Chip Junction
Internal Resistance
Package/Leads
Printed-Circuit Board
Radiation
External Resistance
Convection
(Note the internal versus external package resistance.)
Heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat
sink attach material (or thermal interface material), and finally to the heat sink; where it is removed by forcedair convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature
drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms.
Adhesives and Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by a spring clip mechanism,
Figure 22 shows the thermal performance of three thin-sheet thermal-interface materials (silicon, graphite/oil,
flouroether oil), a bare joint, and a joint with thermal grease, as a function of contact pressure. As shown, the
performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal
resistance approximately 7 times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 20). Therefore the synthetic grease offers the best thermal performance, considering the low interface
pressure. Of course, the selection of any thermal interface material depends on many factors – thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc.
Page 42
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 22. Thermal Performance of Select Thermal Interface Material
Silicone Sheet (0.006 inch)
Bare Joint
Floroether Oil Sheet (0.007 inch)
Graphite/Oil Sheet (0.005 inch)
Synthetic Grease
+
2
+
Specific Thermal Resistance (Kin2/W)
+
1.5
+
1
0.5
0
0
10
20
30
40
50
60
70
80
Contact Pressure (PSI)
The board designer can choose between several types of thermal interfaces. Heat sink adhesive materials
should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive
materials provided by the following vendors.
Dow-Corning Corporation
Dow-Corning Electronic Materials
P.O. Box 0997
Midland, MI 48686-0997
12/8/99
517-496-4000
Version 1.02
Page 43
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Chomerics, Inc.
77 Dragon Court
Woburn, MA 01888-4850
617-935-4850
Thermagon, Inc.
3256 West 25th Street
Cleveland, OH 44109-1668
216-741-7659
Loctite Corporation
1001 Trout Brook Crossing
Rocky Hill, CT 06067
860-571-5100
AI Technology (e.g. EG7655)
1425 Lower Ferry Road
Trent, NJ 08618
609-882-2332
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows.
TJ = TA + TR + (θJC + θINT + θSA) × PD
Where:
TJ is the die-junction temperature
TA is the inlet cabinet ambient temperature
TR is the air temperature rise within the system cabinet
θJC is the junction-to-case thermal resistance
θINT is the thermal resistance of the thermal interface material
θSA is the heat sink-to-ambient thermal resistance
PD is the power dissipated by the device
Typical die-junction temperatures (TJ) should be maintained less than the value specified in Table “Package
Thermal Characteristics1,” on page 10. The temperature of the air cooling the component greatly depends
upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. An electronic
cabinet inlet-air temperature (TA) may range from 30 to 40°C. The air temperature rise within a cabinet (TR)
may be in the range of 5 to 10°C. The thermal resistance of the interface material (θINT) is typically about 1°C/
W. Assuming a TA of 30°C, a TR of 5°C, a CBGA package θJC = 0.03, and a power dissipation (PD) of 5.0 watts,
the following expression for TJ is obtained.
Die-junction temperature: TJ = 30°C + 5°C + (0.03°C/W +1.0°C/W + θSA) × 5W
For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θSA) versus air flow velocity
is shown in Figure 23.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Figure 23. Thermalloy #2328B Pin-Fin Heat Sink-to-Ambient Thermal Resistance vs. Air flow Velocity
Thermalloy #2328B Pin-fin Heat Sink
(25 x 28 x 15 mm)
Heat Sink Thermal Resistance (×°C/W)
8
7
6
5
4
3
2
1
0
0.5
1
1.5
2
2.5
3
3.5
Approach Air Velocity (m/s)
Assuming an air velocity of 0.5m/s, we have an effective θSA of 7°C/W, thus
TJ = 30°C + 5°C + (.03°C/W +1.0°C/W + 7°C/W) × 4.5W,
resulting in a junction temperature of approximately 71°C which is well within the maximum operating temperature of the component.
Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Aavid, and Wakefield Engineering offer different
heat sink-to-ambient thermal resistances, and may or may not need air flow.
Though the junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-ofmerit used for comparing the thermal performance of various microelectronic packaging technologies, one
should exercise caution when only using this metric in determining thermal management because no single
parameter can adequately describe three-dimensional heat flow. The final chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power dissipation, a number of factors affect the final
operating die-junction temperature. These factors might include air flow, board population (local heat flux of
adjacent components), heat sink efficiency, heat sink attach, next-level interconnect technology, system air
temperature rise, etc.
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Ordering Information
This section provides the part numbering nomenclature for the 750. Note that the individual part numbers correspond to a maximum processor core frequency. For available devices contact your local IBM sales office.
Figure 24. Part Number Key
IBM25PPC750L-GBYYYA2T
Shipping Container
T=Tray
R=Tape and Reel
Reliability Grade (2=25 FIT)
Application Conditions:
A = 2.0 - 2.2V, -40 - 65°C
The CMOS 0.20 µm
Copper Technology,
PID-8p, Implementation
of the PowerPC 740
and PowerPC 750
RevisionLevels:
Levels:E=
G=3.2
Revision
2.2
Processor Frequency
Package (CBGA)
Revision Level
Letter
G
Page 46
Rev
dd 3.2
Processor Version Register
0008 8302
Version 1.02
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PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Page 47
Version 1.02
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© International Business Machines Corporation 1999
Printed in the United States of America
12/99
All Rights Reserved
The information contained in this document is subject to change without notice. The products described in this document
are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to
persons. The information contained in this document does not affect or change IBM’s product specifications or warranties.
Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of
IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as
illustration. The results obtained in other operating environments may vary.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied
upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable for any damages arising directly or indirectly from any use of the information contained in this document.
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