ETC IS24C64-2G

IS24C32-2/3
IS24C64-2/3
ISSI
®
65,536-bit/32,768-bit 2-WIRE SERIAL
CMOS EEPROM
PRELIMINARY INFORMATION
MARCH 2000
FEATURES
• 8-pin PDIP and 8-pin SOIC packages
• Low Power CMOS Technology
• Self time write cycle with auto clear
– Standby Current less than 2 µA (5.5V)
– Read Current (typical) less than 1 mA (5.5V)
– Write Current (typical) less than 3 mA (5.5V)
– 5 ms @ 2.5V
• Organization:
– IS24C64-2 and IS24C64-3: 8192x8
• Low Voltage Operation
– IS24C64-2 & IS24C32-2: Vcc = 1.8V to 5.5V
– IS24C32-2 and IS24C32-3: 4096x8
– IS24C64-3 & IS24C32-3: Vcc = 2.5V to 5.5V
• 32-Byte Page Write Buffer
• 100 KHz (1.8V) and 400 KHz (5V) Compatibility
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• Hardware Data Protection
• High Reliability
– Write Protect Pin
• Sequential Read Feature
– Endurance: 1,000,000 Cycles
• Filtered Inputs for Noise Suppression
– Data Retention: 100 Years
• Commercial and Industrial temperature ranges
PRODUCT OFFERING OVERVIEW
Part No
IS24C64-2
IS24C64-3
IS24C32-2
IS24C32-3
Voltage
1.8V-5.5V
2.5V-5.5V
1.8V-5.5V
2.5V-5.5V
Speed
100 KHz
400 KHz
100 KHz
400 KHz
Standby ICC
< 2 µA
< 2 µA
< 2 µA
< 2 µA
Read ICC
1 mA
1 mA
1 mA
1 mA
Write ICC
3 mA
3 mA
3 mA
3 mA
Temperature
C,I
C,I
C,I
C,I
DESCRIPTION
The IS24C64-2 is a 1.8V (1.8V-5.5V) 64K-bit (8192 x 8)
Electrically Erasable PROM, IS24C64-3 is a 2.5V (2.5V5.5V) 64K-bit (8192 x 8) Electrically Erasable PROM,
IS24C32-2 is a 1.8V (1.8V-5.5V) 32K-bit (4096 x 8)
Electrically Erasable PROM and the IS24C32-3 is a 2.5V
(2.5V-5.5V) 32K-bit (4096 x 8) Electrically Erasable
PROM.
The IS24CXX (IS24C64-2, IS24C64-3, IS24C32-2 and
IS24C32-3) family is a low-cost and low voltage 2-wire
Serial EEPROM. It is fabricated using ISSI’s advanced
CMOS EEPROM technology and provides a low power
and low voltage operation. The IS24CXX family features
a write protection feature, and is available in 8-pin DIP and
8-pin SOIC packages.
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/02/00
Rev. 00A
1
IS24C32-2/3
IS24C64-2/3
ISSI
®
FUNCTIONAL BLOCK DIAGRAM
8
SDA
5
SCL
6
WP
7
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
CONTROL
LOGIC
X
DECODER
Vcc
SLAVE ADDRESS
REGISTER &
COMPARATOR
EEPROM
ARRAY
WORD ADDRESS
COUNTER
GND
Y
DECODER
ACK
4
Clock
DI/O
>
nMOS
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
DATA
REGISTER
PIN CONFIGURATION
8-Pin DIP and SOIC
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
A0
1
8
VCC
A1
2
7
WP
A2
3
8
SCL
GND
4
5
SDA
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
2
with the 24C16. When pins are hardwired, as many as
eight 32K/64K devices may be addressed on a single bus
system. When the pins are not hardwired, the default A0,
A1,and A2 are zero..
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc
the upper half array becomes Write Protected (Read
only). When WP is tied to GND or left floating normal read/
write operations are allowed to the device.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/02/00
IS24C32-2/3
IS24C64-2/3
ISSI
®
DEVICE OPERATION
The IS24CXX family features a serial communication and
supports a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and a Serial
Clock Line (SCL). The protocol defines any device that sends data
onto the SDA bus as a transmitter, and the receiving devices as a
receiver. The bus is controlled by MASTER device which generates
the SCL, controls the bus access and generates the STOP and
START conditions. The IS24CXX is the SLAVE device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not busy
– During a data transfer, the data line must remain stable
whenever the clock line is high. Any changes in the
data line while the clock line is high will be interpreted
as a START or STOP condition.
The state of the data line represents valid data when after
a START condition, the data line is stable for the duration
of the HIGH period of the clock signal. The data on the
SDA line may be changed during the LOW period of the
clock signal. There is one clock pulse per bit of data. Each
data transfer is initiated with a START condition and
terminated with a STOP condition.
START Condition
The START condition precedes all commands to the device
and is defined as a HIGH to LOW transition of SDA when
SCL is HIGH. The IS24CXX monitors the SDA and SCL
lines and will not respond until the START condition is met.
STOP Condition
The STOP condition is defined as a LOW to HIGH
transition of SDA when SCL is HIGH. All operations must
end with a STOP condition.
ACKnowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line.
DEVICE ADDRESSING
The MASTER begins a transmission by sending a START
condition. The MASTER then sends the address of the particular
slave devices it is requesting. The SLAVE (Fig. 5) address is 8 bits.
The four most significant bits of the address are fixed as
1010 for the IS24CXX.
The 32K/64K uses the three device address bits A2, A1,
A0 to allow as many as eight devices on the same bus.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/02/00
Rev. 00A
These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal
proprietary circuit that biases them to a logic low condition
if the pins are allowed to float.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the MASTER sends a START condition and the
SLAVE address byte, the IS24CXX monitors the bus and
responds with an Acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
IS24CXX pulls down the SDA line during the ninth clock
cycle, signaling that it received the eight bits of data. The
IS24CXX then performs a Read or Write operation
depending on the state of the R/W bit.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the START
condition and the slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an acknowledge, the Master sends two byte addresses that
are to be written into the address pointer of the
IS24CXX. After receiving another acknowledge from the
Slave, the Master device transmits the data byte to be written
into the address memory location. The IS24CXX acknowledges
once more and the Master generates the STOP condition,
at which time the device begins its internal programming
cycle. While this internal cycle is in progress, the device
will not respond to any request from the Master device.
Page Write
The IS24CXX is capable of 32-byte page-WRITE operation.
A page-WRITE is initiated in the same manner as a byte
write, but instead of terminating the internal write cycle after
the first data word is transferred, the master device can
transmit up to 31 more bytes. After the receipt of each data
word, the IS24CXX responds immediately with an
ACKnowledge on SDA line, and the five lower order data
word address bits are internally incremented by one, while
the five higher order bits of the data word address remain
constant. If the master device should transmit more than
32 words, prior to issuing the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. Once all 32 bytes are received and the
STOP condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data
is written to the IS24CXX in a single write cycle. All inputs
are disabled until completion of the internal WRITE cycle.
3
IS24C32-2/3
IS24C64-2/3
ISSI
®
Acknowledge Polling
Sequential Read
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation, the
IS24CXX initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address for a write operation.
If the IS24CXX is still busy with the write operation, no
ACK will be returned. If the IS24CXX has completed the
write operation, an ACK will be returned and the host can
then proceed with the next read or write operation.
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24CXX sends initial byte sequence, the master device
now responds with an ACKnowledge indicating it requires
additional data from the IS24CXX. The IS24CXX continues
to output data for each ACKnowledge received. The
master device terminates the sequential READ operation
by pulling SDA HIGH (no ACKnowledge) indicating the
last data word to be read, followed by a STOP condition.
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
slave address is set to “1”. There are three READ
operation options: current address read, random address
read and sequential read.
Current Address Read
The IS24CXX contains an internal address counter which
maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a read or write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24CXX
receives the Device Addressing Byte with a READ
operation (read/write bit set to “1”), it will respond an
ACKnowledge and transmit the 8-bit data word stored at
address location n+1. The master will not acknowledge
the transfer but does generate a STOP condition and the
IS24CXX discontinues transmission. If 'n' is the last byte
of the memory, then the data from location '0' will be
transmitted. (Refer to Figure 8. Current Address Read
Diagram.)
The data output is sequential, with the data from address
n followed by the data from address n+1, ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential read operation. When the memory address
boundary (8191 for IS24C64-2 and IS24C64-3; 4095 for
IS24C32-2 and IS24C32-3) is reached, the address counter
“rolls over” to address 0, and the IS24CXX-2 continues to
output data for each ACKnowledge received. (Refer to
Figure 10. Sequential Read Operation Starting with a
Random Address READ Diagram.)
Random Access Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a 'dummy'
write operation by sending the START condition, slave
address and word address of the location it wishes to
read. After the IS24CXX acknowledge the word address,
the Master device resends the START condition and the
slave address, this time with the R/W bit set to one. The
IS24CXX then responds with its acknowledge and sends
the data requested. The master device does not send an
acknowledge but will generate a STOP condition. (Refer
to Figure 9. Random Address Read Diagram.)
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/02/00
IS24C32-2/3
IS24C64-2/3
ISSI
®
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24Cxx
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
tAA
Data Output
from
Receiver
tAA
ACK
STOP
Condition
SCL
START
Condition
Figure 3. START and STOP Conditions
SDA
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/02/00
Rev. 00A
5
IS24C32-2/3
IS24C64-2/3
ISSI
®
Figure 4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5. Slave Address
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 6. Byte Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
W
R
I
T
E
Word Address
A
C
K
M
S
B
Data
Word Address
A
C
K
S
T
O
P
A
C
K
A
C
K
L
M
S
S
B
B
R/W
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
Data (n)
Word Address (n)
Word Address (n)
A
C
K
M
S
B
6
W
R
I
T
E
A
C
K
A
C
K
Data (n+1)
A
C
K
S
T
O
P
Data (n+31)
A
C
K
A
C
K
L
S
B
R/W
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/02/00
IS24C32-2/3
IS24C64-2/3
ISSI
®
Figure 8. Current Access Read
S
T
A
R
T
R
E
A
D
Device
Address
SDA
Bus
Activity
S
T
O
P
Data
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Access Read
S
T
A
R
T
Device
Address
W
R
I
T
E
SDA
Bus
Activity
Word
Address (n)
A
C
K
M
S
B
S
T
A
R
T
Word
Address (n)
A
C
K
Device
Address
R
E
A
D
S
T
O
P
Data n
A
C
K
A
C
K
L
S
B
R/W
N
O
A
C
K
DUMMY WRITE
Figure 10. Sequential Read
Device
Address
R
E
A
D
SDA
Bus
Activity
Data Byte n
A
C
K
Data Byte n+1
A
C
K
Data Byte n+2
A
C
K
S
T
O
P
Data Byte n+X
A
C
K
N
O
R/W
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/02/00
Rev. 00A
A
C
K
7
IS24C32-2/3
IS24C64-2/3
ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
0.5 to +6.25
–0.5 to Vcc + 0.5
–40 to +85
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE (IS24C64-2 and IS24C32-2)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
1.8V to 5.5V
1.8V to 5.5V
OPERATING RANGE (IS24C64-3 and IS24C32-3)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
2.5V to 5.5V
2.5V to 5.5V
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/02/00
IS24C32-2/3
IS24C64-2/3
ISSI
®
DC ELECTRICAL CHARACTERISTICS
Symbol
VOL1
VOL2
VIH
VIL
ILI
ILO
Parameter
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = 1.8V, IOL = 0.15 mA
VCC = 2.5V, IOL = 1.0 mA
Min.
Max.
—
0.2
—
0.4
VCC X 0.7 VCC + 0.5
–1.0
VCC X 0.3
—
3
—
3
VIN = VCC max.
Unit
V
V
V
V
µA
µA
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
ICC1
ICC2
ISB1
ISB2
Parameter
Vcc Operating Current
Vcc Operating Current
Standby Current
Standby Current
Test Conditions
READ at 100 KHz (Vcc = 5V)
WRITE at 100 KHz (Vcc = 5V)
Vcc = 1.8V
Vcc = 5.5V
Min.
—
—
—
—
Max.
1.0
3.0
1.0
2.0
Unit
mA
mA
µA
µA
2.5V-5.5V
Min. Max.
0
400
—
50
1.2
—
0.6
—
1.2
—
0.6
—
0.6
—
0.6
—
0.6
—
100
—
0
—
50
—
0.1
0.9
—
300
—
300
—
5
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ms
AC ELECTRICAL CHARACTERISTICS
Symbol
f SCL
T
tLOW
tHIGH
tBUF
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
t DH
tAA
tR
tF
t WR
Parameter
Test Conditions
SCL Clock Frequency
Noise Suppression Time(1)
Clock LOW Period
Clock HIGH Period
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
Data In Hold Time
Data Out Hold Time
SCL LOW to SDA Data Out Change
Clock to Output
SCL LOW to SDA Data Out Valid
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
1.8V-5.5V
Min. Max.
0
100
—
100
4.7
—
4
—
4.7
—
4.7
—
4.7
—
4
—
4
—
200
—
0
—
100
—
0.1
4.5
—
1000
—
300
—
10
Note:
1. This parameter is characterized but not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/02/00
Rev. 00A
9
IS24C32-2/3
IS24C64-2/3
ISSI
®
AC WAVEFORMS
Figure 11. Bus Timing
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA
tBUF
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
tAA
tDH
SDAOUT
Figure 12. Write Cycle Timing
SCL
SDA
8th BIT
ACK
tWR
WORD n
STOP
Condition
10
START
Condition
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/02/00
IS24C32-2/3
IS24C64-2/3
ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Voltage
Frequency Range
Part Number
Package
100 KHz
1.8V
to 5.5V
IS24C32-2P
IS24C32-2G
300-mil Plastic DIP
Small Outline (JEDEC STD)
100 KHz
1.8V
to 5.5V
IS24C64-2P
IS24C64-2G
300-mil Plastic DIP
Small Outline (JEDEC STD)
400 KHz
2.5V
to 5.5V
IS24C32-3P
IS24C32-3G
300-mil Plastic DIP
Small Outline (JEDEC STD)
400 KHz
2.5V
to 5.5V
IS24C64-3P
IS24C64-3G
300-mil Plastic DIP
Small Outline (JEDEC STD)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Voltage
Frequency Range
Part Number
Package
100 KHz
1.8V
to 5.5V
IS24C32-2PI
IS24C32-2GI
300-mil Plastic DIP
Small Outline (JEDEC STD)
100 KHz
1.8V
to 5.5V
IS24C64-2PI
IS24C64-2GI
300-mil Plastic DIP
Small Outline (JEDEC STD)
400 KHz
2.5V
to 5.5V
IS24C32-3PI
IS24C32-3GI
300-mil Plastic DIP
Small Outline (JEDEC STD)
400 KHz
2.5V
to 5.5V
IS24C64-3PI
IS24C64-3GI
300-mil Plastic DIP
Small Outline (JEDEC STD)
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/02/00
Rev. 00A
11