ISSI ISSI® IS62C64 IS62C64 ® 8K x 8 LOW POWER CMOS STATIC RAM FEATURES • CMOS low power operation — 400 mW (max.) operating — 25 mW (max.) standby • Automatic power-down when chip is deselected • TTL compatible interface levels • Single 5V power supply • Fully static operation: no clock or refresh required • Three-state outputs • Two Chip Enables (CE1 and CE2) for simple memory expansion • Industrial temperature available DESCRIPTION The ISSI IS62C64 is a low power, 8,192-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation is reduced to 25 µW (typical) with CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C64 is packaged in the JEDEC standard 28-pin, 600-mil DIP and SOP surface mount packages. FUNCTIONAL BLOCK DIAGRAM A0-A12 DECODER 256 X 256 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE2 CE1 OE CONTROL CIRCUIT WE ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. SR013-1D 3/17/97 1 ISSI IS62C64 ® PIN CONFIGURATION 28-Pin DIP and SOJ PIN DESCRIPTIONS A0-A12 Address Inputs WE CE1 Chip Enable 1 Input 26 CE2 CE2 Chip Enable 2 Input 4 25 A8 OE Output Enable Input 5 24 A9 WE Write Enable Input A4 6 23 A11 A3 7 22 OE I/O0-I/O7 Input/Output A2 8 21 A10 Vcc Power A1 9 20 CE1 GND Ground A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 NC 1 28 VCC A12 2 27 A7 3 A6 A5 TRUTH TABLE Mode WE CE1 CE2 OE I/O Operation Vcc Current X X H H L H X L L L X L H H H X X H L X High-Z High-Z High-Z DOUT DIN ISB1, ISB2 ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 Not Selected (Power-down) Output Disabled Read Write ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –55 to +125 –65 to +150 1.0 20 Unit V °C °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial 2 Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Integrated Silicon Solution, Inc. SR013-1D 3/17/97 ISSI IS62C64 ® DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage(1) –0.5 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. –2 –10 2 10 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. –2 –10 2 10 µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -45 ns Min. Max. -70 ns Min. Max. -100 ns Min. Max. Symbol Parameter Test Conditions ICC1 Vcc Operating Supply Current VCC = Max., IOUT = 0 mA, f = 0 Com. Ind. — — 65 75 — — 65 75 — — 65 75 mA ICC2 Vcc Dynamic Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. — — 90 100 — — 80 90 — — 70 80 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE1 ≥ VIH or CE2 ≤ VIL, f = 0 Com. Ind. — — 20 30 — — 20 30 — — 20 30 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., Com. Ind. — — 5 10 — — 5 10 — — 5 10 mA CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Unit Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 5 pF VOUT = 0V 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Silicon Solution, Inc. SR013-1D 3/17/97 3 ISSI IS62C64 ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Commercial Operating Range) Symbol -45 ns Min. Max. Parameter -70 ns Min. Max. -100 ns Min. Max. Unit tRC Read Cycle Time 45 — 70 — 100 — ns tAA Address Access Time — 45 — 70 — 100 ns tOHA Output Hold Time 3 — 3 — 3 — ns tACE1 CE1 Access Time — 45 — 70 — 100 ns tACE2 CE2 Access Time — 45 — 70 — 100 ns tDOE OE Access Time — 25 — 35 — 50 ns OE to Low-Z Output 0 — 0 — 0 — ns OE to High-Z Output — 20 — 25 — 25 ns tLZCE1(2) CE1 to Low-Z Output 3 — 3 — 3 — ns tLZCE2 CE2 to Low-Z Output 3 — 3 — 3 — ns tHZCE CE1 or CE2 to High-Z Output — 20 — 25 — 25 ns CE1 or CE2 to Power-Up 0 — 0 — 0 — ns CE1 or CE2 to Power-Down — 30 — 50 — 50 ns tLZOE (2) tHZOE (2) (2) tPU (3) tPD(3) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 5 ns 1.5V See Figures 1a and 1b AC TEST LOADS 1838 Ω 5V OUTPUT OUTPUT 100 pF Including jig and scope Figure 1a. 4 1838 Ω 5V 994 Ω 5 pF Including jig and scope 994 Ω Figure 1b. Integrated Silicon Solution, Inc. SR013-1D 3/17/97 ISSI IS62C64 ® AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE1 tACE CE2 tLZCE DOUT tHZCE HIGH-Z DATA VALID tPU SUPPLY CURRENT tPD 50% ICC 50% ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Silicon Solution, Inc. SR013-1D 3/17/97 5 ISSI IS62C64 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Commercial Operating Range) Symbol -45 ns Min. Max. Parameter -70 ns Min. Max. -100 ns Min. Max. Unit tWC Write Cycle Time 45 — 70 — 100 — ns tSCE1 CE1 to Write End 35 — 60 — 80 — ns tSCE2 CE2 to Write End 35 — 60 — 80 — ns tAW Address Setup Time to Write End 35 — 60 — 80 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWE(4) WE Pulse Width 35 — 55 — 60 — ns tSD Data Setup to Write End 25 — 30 — 35 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 20 — 25 — 25 ns tLZWE(2) WE HIGH to Low-Z Output 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 6 tHD DATA-IN VALID Integrated Silicon Solution, Inc. SR013-1D 3/17/97 ISSI IS62C64 ® WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2) tWC ADDRESS tSA tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE WE tHZWE DOUT DATA UNDEFINED tLZWE HIGH-Z tHD tSD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package 45 45 IS62C64-45W IS62C64-45U 600-mil Plastic DIP 330-mil Plastic SOP 70 70 IS62C64-70W IS62C64-70U 600-mil Plastic DIP 330-mil Plastic SOP 100 100 IS62C64-100W IS62C64-100U 600-mil Plastic DIP 330-mil Plastic SOP Package 45 IS62C64-45UI 330-mil Plastic SOP 70 IS62C64-70UI 330-mil Plastic SOP 100 IS62C64-100UI 330-mil Plastic SOP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 e-mail: [email protected] http://www.issiusa.com Integrated Silicon Solution, Inc. SR013-1D 3/17/97 7