ISSI ® IS61C64B 8K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 10, 12, and 15 ns • Automatic power-down when chip is deselected • CMOS low power operation — 450 mW (typical) operating — 250 µW (typical) standby • TTL compatible interface levels • Single 5V power supply • Fully static operation: no clock or refresh required • Three state outputs • One Chip Enables (CE) for increased speed JULY 2001 DESCRIPTION The ISSI IS61C64B is a very high-speed, low power, 8192-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. Easy memory expansion is provided by using one Chip Enable input, CE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C64B is packaged in the JEDEC standard 28-pin, 300-mil DIP and SOJ, and TSOP. FUNCTIONAL BLOCK DIAGRAM A0-A12 DECODER 256 X 256 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 1 ISSI IS61C64B PIN CONFIGURATION PIN CONFIGURATION 28-Pin DIP and SOJ 28-Pin TSOP (Type 1) NC 1 28 VCC A12 2 27 WE A7 3 26 A6 4 25 *A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS OE A11 A9 A8 * WE VCC NC A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 ® A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE A0-A12 Address Inputs Mode CE Chip Enable 1 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Not Selected (Power-down) Output Disabled Read Write * Must be tied to either Vcc or GND Vcc Power GND Ground WE CE OE I/O Operation Vcc Current X X H H L H X L L L X X H L X High-Z High-Z High-Z DOUT DIN ISB1, ISB2 ISB1, ISB2 ICC ICC ICC OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C Speed 10 ns 12 ns 15 ns VCC 5V ± 5% 5V ± 10% 5V ± 10% ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –10 to +85 –65 to +150 1.0 20 Unit V °C °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 ISSI IS61C64B ® DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage(1) –0.5 0.8 V ILI Input Leakage GND - VIN - VCC –2 2 µA ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –2 2 µA 1 2 3 Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 4 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10ns Min. Max. -12 ns Min. Max. -15ns Min. Max. 5 Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX — 185 — 175 — 135 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE1 • VIH or CE2 - VIL, f = 0 — 30 — 30 — 30 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE1 • VCC – 0.2V, CE2 - 0.2V, VIN • VCC – 0.2V, or VIN - 0.2V, f = 0 — 10 — 10 — 10 mA 6 7 8 Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 9 10 CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 10 pF 11 Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 12 3 ISSI IS61C64B ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol –10ns Min. Max. Parameter -12ns Min. Max. -15ns Min. Max. Unit tRC Read Cycle Time 10 — 12 — 15 — ns tAA Address Access Time — 10 — 12 — 15 ns tOHA Output Hold Time 2 — 2 — 2 — ns tACE CE Access Time — 10 — 12 — 15 ns OE Access Time — 5 — 6 — 7 ns OE to Low-Z Output 0 — 0 — 0 — ns OE to High-Z Output — 5 — 6 — 6 ns CE to Low-Z Output 2 — 3 — 3 — ns tHZCE(2) CE to High-Z Output — 5 — 7 — 8 ns tDOE tLZOE (2) tHZOE (2) tLZCE1 (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b AC TEST LOADS 480 Ω 5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1a. 4 480 Ω 5V 255 Ω 5 pF Including jig and scope 255 Ω Figure 1b. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 ISSI IS61C64B ® AC WAVEFORMS READ CYCLE NO. 1(1,2) 1 tRC ADDRESS 2 tAA tOHA tOHA DOUT 3 DATA VALID PREVIOUS DATA VALID 4 READ CYCLE NO. 2(1,3) 5 tRC ADDRESS tAA tOHA 6 OE tDOE tHZOE 7 tLZOE CE tACE tLZCE DOUT HIGH-Z tHZCE 8 DATA VALID 9 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 5 ISSI IS61C64B ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol –10ns Min. Max. Parameter -12ns Min. Max. -15ns Min. Max. Unit tWC Write Cycle Time 10 — 12 — 15 — ns tSCE CE to Write End 9 — 10 — 12 — ns tAW Address Setup Time to Write End 9 — 10 — 12 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns Address Setup Time 0 — 0 — 0 — ns WE Pulse Width 8 — 8 — 10 — ns Data Setup to Write End 8 — 8 — 9 — ns tSA tPWE (4) tSD tHD Data Hold from Write End 0 — 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 6 — 6 — 7 ns (2) tLZWE WE HIGH to Low-Z Output 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tHA tSCE CE tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 6 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 ISSI IS61C64B ® WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2) tWC 1 ADDRESS tSA tHA tSCE CE 2 tAW tPWE WE tHZWE DOUT DATA UNDEFINED 3 tLZWE HIGH-Z tHD tSD DIN 4 DATA-IN VALID 5 Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = VIH. 6 7 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 10 IS61C64B-10N IS61C64B-10J IS61C64B-10T 300-mil Plastic DIP 300-mil Plastic SOJ Plastic TSOP 12 IS61C64B-12N IS61C64B-12J IS61C64B-12T 300-mil Plastic DIP 300-mil Plastic SOJ Plastic TSOP IS61C64B-15N IS61C64B-15J IS61C64B-15T 300-mil Plastic DIP 300-mil Plastic SOJ Plastic TSOP 15 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/17/01 7