a
FEATURES
256-Position, 2-Channel
Potentiometer Replacement
10 k, 50 k, 100 k
Power Shut-Down, Less than 5 A
2.7 V to 5.5 V Single Supply
2.7 V Dual Supply
3-Wire SPI-Compatible Serial Data Input
Midscale Preset During Power-On
2-Channel, 256-Position
Digital Potentiometer
AD5207
FUNCTIONAL BLOCK DIAGRAM
A1
W1
B1
A2
W2
B2
SHDN
VDD
RDAC1 REGISTER
R
RDAC2 REGISTER
R
VSS
APPLICATIONS
Mechanical Potentiometer Replacement
Stereo Channel Audio Level Control
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Automotive Electronics Adjustment
GENERAL DESCRIPTION
The AD5207 provides dual channel, 256-position, digitally
controlled variable resistor (VR) devices that perform the same
electronic adjustment function as a potentiometer or variable
resistor. Each channel of the AD5207 contains a fixed resistor with
a wiper contact that taps the fixed resistor value at a point
determined by a digital code loaded into the SPI-compatible
serial-input register. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. The variable resistor
offers a completely programmable value of resistance, between
the A Terminal and the wiper or the B Terminal and the wiper.
The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ or 100 kΩ
has a ± 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional switched
resistor designs and avoids any make-before-break or breakbefore-make operation.
Each VR has its own VR latch, which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register, which is loaded from a standard
3-wire serial-input digital interface. Ten bits, to make up the
data word, are required and clocked into the serial input register.
CS
POWERON
RESET
LOGIC
AD5207
8
CLK
SERIAL INPUT REGISTER
SDO
SDI
DGND
The first two bits are address bits. The following eight bits are
the data bits that represent the 256 steps of the resistance value.
The reason for two address bits instead of one is to be compatible
with similar products such as AD8402 so that drop-in replacement
is possible. The address bit determines the corresponding VR
latch to be loaded with the data bits during the returned positive
edge of CS strobe. A serial data output pin at the opposite end
of the serial register allows simple daisy chaining in multiple
VR applications without additional external decoding logic.
An internal reset block will force the wiper to the midscale position during every power-up condition. The SHDN pin forces an
open circuit on the A Terminal and at the same time shorts the
wiper to the B Terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface remains active during shutdown;
code changes can be made to produce new wiper positions when
the device is resumed from shutdown.
The AD5207 is available in 1.1 mm thin TSSOP-14 package,
which is suitable for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range
of –40°C to +125°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD5207–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10 k, 50 k, 100 k VERSION (V
DD
= 5 V, VSS = 0, VA = 5 V,
VB = 0, –40C < TA < +125C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
DC CHARACTERISTICS
RHEOSTAT MODE
Specifications Apply to All VRs
Resistor Differential Nonlinearity2
Resistor Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
Nominal Resistance Match
R-DNL
R-INL
∆R
RAB/∆T
RW
∆R/RO
RWB, VA = NC
RWB, VA = NC
–1
–1.5
–30
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Specifications Apply to All VRs
Resolution
Integral Nonlinearity4
Differential Nonlinearity4
Voltage Divider Temperature
Coefficient
Full-Scale Error
Zero-Scale Error
VAB = VDD, Wiper = No Connect
IW = 1 V/R, VDD = 5 V
Ch 1 to 2, VAB = VDD, TA = 25°C
Typ1
500
50
0.2
N
INL
DNL
∆VW/∆T
8
–1.5
–1
VDD = 5 V, VSS = 0 V
Code = 80H
VWFSE
VWZSE
Code = FFH
Code = 00H
–1.5
RESISTOR TERMINALS
Voltage Range5
Capacitance6 AX, BX
Capacitance6 WX
Shutdown Current7
Shutdown Wiper Resistance
Common-Mode Leakage
VA, B, W
CA,B
CW
IA_SD
RW_SD
ICM
|VDD| + |VSS| ≤5.5 V
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
VA = VB = VDD/2
VSS
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
VDD = 5 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
RL = 1 kΩ to VDD
IOL = 1.6 mA, VDD = 5 V
VIN = 0 V or 5 V
2.4
POWER SUPPLIES
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation8
Power Supply Sensitivity, VDD
Power Supply Sensitivity, VSS
VDD RANGE
VDD/SS RANGE
IDD
ISS
PDISS
PSS
PSS
VSS = 0 V
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3 dB
Bandwidth –3 dB
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk10
BW_10 kΩ
BW_50 kΩ
BW_100 kΩ
THDW
tS
eN_WB
CT
RAB = 10 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ
RAB = 10 kΩ/50 kΩ/100 kΩ, ± 1 LSB Error Band
RWB = 5 kΩ, f = 1 kHz, RS = 0
VA = 5 V, VB = 0 V
Max
Unit
+1
+1.5
+30
LSB
LSB
%
ppm/°C
Ω
%
100
1
+1.5
+1
15
+1.5
VDD
45
70
5
200
1
0.8
2.1
0.6
VDD – 0.1
0.4
± 10
10
2.7
± 2.2
5.5
± 2.7
40
40
0.2
0.01
0.03
VIH = VDD or VIL = GND, VSS = 0 V
VIH = VDD or VIL = GND VSS = –2.5 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
∆VDD = 5 V ± 10%, VSS = 0 V, Code = 80H
∆VSS = –2.5 V ± 10%, VDD = 2.5 V, Code = 80H
–2–
600
125
71
0.003
2/9/18
9
–65
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
nA
V
V
V
V
V
V
µA
pF
V
V
µA
µA
mW
%/%
%/%
kHz
kHz
kHz
%
µs
nV√Hz
dB
REV. 0
AD5207
Parameter
Symbol
Conditions
Min
INTERFACE TIMING
CHARACTERISTICS
Applies to All Parts6, 11
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay12
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tCSH0
tCSH1
tCS1
Clock Level High or Low
10
5
5
1
10
10
0
0
10
RL = 1 kΩ to 5 V, CL < 20 pF
Typ1
Max
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = 5 V,
VSS = 0 V.
3
VAB = VDD, Wiper (VW) = No connect.
4
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A X terminals. All A X terminals are open-circuited in shut-down mode.
8
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V DD = 5 V, VSS = 0 V.
10
Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change.
11
See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using V DD = 5 V.
12
Propagation delay depends on value of V DD, RL, and CL; see applications text.
The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.
Specifications subject to change without notice.
1
A1
SDI
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
CLK
0
1
RDAC REGISTER LOAD
CS
0
VOUT
Figure 1a. Timing Diagram
SDI
(DATA IN)
SDO
(DATA OUT)
1
Ax OR Dx
Ax OR Dx
0
tDS
tDH
1
A'x OR D'x
A'x OR D'x
0
tPD_MAX
tCH
tCS1
1
CLK
0
tCSH0
1
CS
tCL
tCSH1
tCSS
tCSW
0
tS
VDD
VOUT
ⴞ1LSB ERROR BAND
0V
ⴞ1LSB
Figure 1b. Detail Timing Diagram
REV. 0
–3–
AD5207
ABSOLUTE MAXIMUM RATINGS 1
PIN FUNCTION DESCRIPTIONS
(TA = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0, –3 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
IMAX2 (A, B, W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Inputs and Output Voltage to GND . . 0 V, VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Thermal Resistance3 θJA, TSSOP-14 . . . . . . . . . . . . . 206°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Max current is bounded by the maximum current handling of the switches,
maximum power dissipation of the package, and maximum applied voltage
across any two of the A, B, and W Terminals at a given resistance. Please refer to
TPC 22 for detail.
3
Package Power Dissipation = (T J Max–TA)/θJA.
PIN CONFIGURATION
VSS 1
14 B1
B2 2
13 A1
A2 3
AD5207
Pin Mnemonic Description
1
VSS
2
3
4
5
6
B2
A2
W2
DGND
SHDN
7
CS
8
9
SDI
SDO
10
11
CLK
VDD
12
13
14
W1
A1
B1
Negative Power Supply, specified for operation from 0 V to –2.7 V.
Terminal B of RDAC#2.
Terminal A of RDAC#2.
Wiper, RDAC#2, addr = 12
Digital Ground.
Active Low Input. Terminal A open-circuit
and Terminal B shorted to Wiper. Shutdown controls both RDACs #1 and #2.
Chip Select Input, Active Low. When CS
returns high, data in the serial input register
is decoded, based on the address bit, and
loaded into the corresponding RDAC register.
Serial Data Input. MSB is loaded first.
Serial Data Output. Open Drain transistor
requires pull-up resistor.
Serial Clock Input. Positive Edge Triggered.
Positive Power Supply. Specified for operation at 2.7 V to 5.5 V.
Wiper, RDAC #1, addr = 02.
Terminal A of RDAC #1.
Terminal B of RDAC #1.
Table I. Serial-Data Word Format
12 W1
W2 4 TOP VIEW 11 VDD
(Not to Scale) 10
DGND 5
CLK
ADDR
B9
B8
SHDN 6
9
SDO
A1
A0
CS 7
8
SDI
29
28
B7
B6
B5
D7 D6
MSB
27
D5
DATA
B4
B3
D4
D3
B2
B1
B0
D2
D1
D0
LSB
20
NOTES
ADDR(RDAC1) = 00; ADDR(RDAC2 = 01).
Data loads B9 first into SDI pin.
ORDERING GUIDE
Model
k
Temperature
Range
Package
Description
Package
Option
Qty Per
Container
Branding
Information*
AD5207BRU10-REEL7
AD5207BRU50-REEL7
AD5207BRU100-REEL7
10
50
100
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
TSSOP-14
TSSOP-14
TSSOP-14
RU-14
RU-14
RU-14
1,000
1,000
1,000
B10
B50
B100
*Three lines of information appear on the device. Line 1 lists the part number; Line 2 includes branding information and the ADI logo, and Line 3 contains the
date code YYWW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5207 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
Typical Performance Characteristics–AD5207
0.4
0.20
VDD = 5.5V, V SS = 0V
0.15
0.3
0.10
0.2
0.05
0.1
INL – LSB
RDNL – LSB
VDD = 5.5V, V SS = 0V
0.00
0.0
0.05
–0.1
0.10
–0.2
0.15
–0.3
0.20
–0.4
0
32
64
96
128
160
CODE – Decimal
192
224
256
0
TPC 1. 10 kΩ RDNL vs. Code
32
64
96
128
160
CODE – Decimal
192
224
256
TPC 4. 10 kΩ INL vs. Code
1.0
0.20
VDD = 5.5V, V SS = 0V
0.15
IDD @ VDD/V SS = 5V/0V
0.1
0.05
IDD/I SS – mA
RINL – LSB
0.10
0.00
–0.05
IDD @ VDD/V SS = 2.5V
0.01
–0.10
ISS @ VDD/V SS = 2.5V
–0.15
IDD @ V DD/V SS = 3V/0V
–0.20
0
32
64
96
128
160
CODE – Decimal
192
224
0.001
0.0
256
2.0
3.0
4.0
5.0
VIH – V
TPC 2. 10 kΩ RINL vs. Code
TPC 5. Supply Current vs. Logic Input Voltage
0.3
20
VDD = 5.5V, V SS = 0V
VIL = VSS
VIH = VDD
18
IDD SUPPLY CURRENT – A
0.2
0.1
DNL – LSB
1.0
0.0
–0.1
16
14
VDD = 5.5V
12
10
8
VDD = 2.7V
6
4
–0.2
2
0
–40
–0.3
0
32
64
96
128
160
CODE – Decimal
192
224
256
TPC 3. 10 kΩ DNL vs. Code
REV. 0
–20
0
20
40
TEMPERATURE – C
60
80
TPC 6. Supply Current vs. Temperature
–5–
100
AD5207
1000
45
VDD = 5.5V
700
30
IDD/I SS – A
IA_SD SHUTDOWN CURRENT – nA
800
35
25
20
15
ISS @ VDD/V SS = 2.5V
600
IDD @ VDD/V SS = 2.5V
500
400
300
10
IDD @ V DD/V SS = 5V/0V
200
5
0
–40
CODE 55H
900
40
IDD @ VDD/V SS = 3V/0V
100
–20
0
20
40
60
80
TEMPERATURE – C
100
0
10k
120
100k
1M
FREQUENCY – Hz
TPC 10. 10 kΩ Supply Current vs. Clock Frequency
TPC 7. Shutdown Current vs. Temperature
80
160
CODE = 80H, VA = VDD, VB = 0V
140
+PSRR @ VDD = 5V DC 10% p-p AC
120
60
80
PSRR – dB
100
RON – 10M
VDD = 3V
60
40
VDD = 5V
+PSRR @ VDD = 3V DC 10% p-p AC
40
20
–PSRR @ VDD = 3V DC 10% p-p AC
20
0
0
1
2
3
4
5
0
100
6
1k
10k
FREQUENCY – Hz
VSUPPLY – V
TPC 8. Wiper ON Resistance vs. VSUPPLY
0
CODE FFH
800
–12
700
–18
600
–24
300
ISS @ VDD/V SS = 2.5V
IDD @ VDD/V SS = 2.5V
DATA = 40 H
DATA = 20 H
DATA = 10 H
DATA = 08 H
–30
DATA = 04 H
–36
DATA = 02 H
–42
DATA = 01 H
IDD @ VDD/V SS = 5V/0V
–48
200
IDD @ VDD/V SS = 3V/0V
–54
100
0
10k
DATA = 80 H
–6
GAIN – dB
IDD/I SS – A
900
400
1M
TPC 11. Power Supply Rejection Ratio vs. Frequency
1000
500
100k
100k
1M
FREQUENCY – Hz
–60
1k
10M
TPC 9. 10 kΩ Supply Current vs. Clock Frequency
VDD = +2.7V
VA
VSS = –2.7V
VA = 100mV rms
TA = 25C
OP42
10k
100k
FREQUENCY – Hz
1M
TPC 12. 10 kΩ Gain vs. Frequency vs. Code
–6–
REV. 0
AD5207
0
–5.99
DATA = 80 H
–6
–6.01
DATA = 20 H
–18
–6.02
DATA = 10 H
–24
GAIN – dB
GAIN – dB
–6.00
DATA = 40 H
–12
DATA = 08 H
–30
DATA = 04 H
–36
10k
–6.03
VDD = +2.7V
VSS = –2.7V
VA = 100mV rms
DATA = 80 H
TA = 25C
–6.04
–6.05
DATA = 02 H
–42
–6.06
–54
–60
1k
–6.07
VDD = +2.7V
VA
VSS = –2.7V
VA = 100mV rms
TA = 25C
100k
VA
DATA = 01 H
–48
50k
VB = 0V
OP42
–6.08
OP42
10k
100k
FREQUENCY – Hz
–6.09
100
1M
TPC 13. 50 kΩ Gain vs. Frequency vs. Code
1k
10k
FREQUENCY – Hz
100k
TPC 16. Normalized Gain Flatness vs. Frequency
0
DATA = 80 H
–6
DATA = 40 H
–12
DATA = 20 H
DATA = 10 H
–24
DATA = 08 H
–30
DATA = 04 H
–36
DATA = 02 H
–42
–48
–54
–60
1k
VW (10mV/DIV)
GAIN – dB
–18
DATA = 01 H
VDD = +2.7V
VA
VSS = –2.7V
VA = 100mV rms
TA = 25C
OP42
10k
100k
FREQUENCY – Hz
1M
TPC 14. 100 kΩ Gain vs. Frequency vs. Code
TPC 17. One Position Step Change at Half Scale
VOUT (50mV/DIV)
6
4
2
10k
–2
–4
50k
–6
VIN (5mV/DIV)
GAIN – dB
0
–8
–10
–12
–14
1k
VDD = 2.7V
2.7V
VSS = 0V
6
VA = 100mV rms
DATA = 80 H
1.5V
TA = 25C
100k
OP42
10k
100k
FREQUENCY – Hz
1M
TPC 18. Large Signal Settling Time
TPC 15. –3 dB Bandwidth
REV. 0
–7–
AD5207
VW (10mV/DIV)
RHEOSTAT MODE TEMPCO – ppm/C
2500
2000
1500
1000
500
0
500
32
64
96
128
160
CODE – Decimal
192
224
256
TPC 21. ∆RWB/∆T Rheostat Mode Temperature Coefficient
TPC 19. Digital Feedthrough vs. Time
120
100.0
100
80
THEORETICAL IMAX – mA
POTENTIOMETER MODE TEMPCO – ppm/C
0
60
40
20
0
IWB_MAX
10.0
RAB = 10k
1.0
RAB = 50k
–20
40
0.1
0
32
64
96
128
160
CODE – Decimal
192
224
256
TPC 20. ∆VWB /∆T Potentiometer Mode
Temperature Coefficient
0
32
64
128
96
160
CODE – Decimal
192
224
256
TPC 22. IMAX vs. Code
–8–
REV. 0
AD5207
OPERATION
The AD5207 provides a dual channel, 256-position digitally
controlled variable resistor (VR) device. The terms VR, RDAC,
and digital potentiometer are sometimes used interchangeably.
Changing the programmable VR settings is accomplished by
clocking in a 10-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is two address Bits, A1
and A0. With A1 and A2 are first and second bits respectively,
followed by eight data bits B7–B0 with MSB first. Table I provides the serial register data word format. See Table III for the
AD5207 address assignments to decode the location of VR latch
receiving the serial register data in Bits B7 through B0. VR settings
can be changed one at a time in random sequence. The AD5207
presets to a midscale during power-on condition. AD5207 contains
a power shutdown SHDN pin. When activated in logic low.
Terminals A on both RDACs will be open-circuited while the
wiper terminals WX are shorted to BX. As a result, a minimum
amount of leakage current will be consumed in both RDACs,
and the power dissipation is negligible. During the shutdown
mode, the VR latch settings are maintained. Thus the previous resistance values remain when the devices are resumed
from the shutdown.
The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the VDD supply
of the AD5207 SDO output device, e.g., the AD5207 could
operate at VDD = 3.3 V and the pull-up for interface to the next
device could be set at 5 V. This allows for daisy chaining several
RDACs from a single processor serial-data line. The clock period
may need to be increased when using a pull-up resistor to the
SDI pin of the following devices in series. Capacitive loading at
the daisy chain node SDO–SDI between devices may add time
delay to subsequent devices. User should be aware of this potential problem in order to successfully achieve data transfer. See
Figure 3. When configuring devices for daisy-chaining, the CS
should be kept low until all the bits of every package are clocked
into their respective serial registers, ensuring that the address bit
and data bits are in the proper decoding location. This requires
20 bits of address and data complying with the data word in
Table I if two AD5207 RDACs are daisy chained. During shutdown SHDN, the SDO output pin is forced to OFF (logic high
state) to disable power dissipation in the pull-up resistor. See
Figure 4 for equivalent SDO output circuit schematic.
DIGITAL INTERFACING
+V
The AD5207 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), chip select (CS),
and serial data input (SDI). The positive edge-sensitive CLK
input requires clean transitions to avoid clocking incorrect data
into the serial input register. Standard logic families work well.
If mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Figure 2 shows more detail of the internal digital circuitry. When CS
is low, the clock loads data into the serial register on each positive clock edge; see Table II.
AD5207
C
SDI
SDO
CS
AD5207
RP
2k
SDI
SDO
CS
CLK
CLK
Figure 3. Daisy-Chain Configuration Using SDO
Table II. Input Logic Control Truth Table
AD5207
VDD
CLK
CS
SHDN
Register Activity
L
P
L
L
H
H
X
P
H
X
X
H
H
H
L
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin. MSB
first. The tenth previously entered bit
is shifted out of the SDO pin.
Load SR data into RDAC latch based
on A0 decode (Table III).
No Operation.
Open circuits all resistor A Terminals,
connects W to B, turns off SDO output transistor.
CS
A1
RDAC
LATCH
#1
CLK
W1
B1
EN
SDO
SDI
A0
SER
REG
ADDR
DEC
D7
D6
D5
D4
D3
D2
D1
D0
A2
RDAC
LATCH
#2
W2
B2
NOTE
P = positive edge, X = don’t care, SR = shift register.
VSS
POWER-ON RESET
Table III. Address Decode Table
SHDN
Figure 2. Block Diagram
REV. 0
–9–
A1
A0
Latch Loaded
0
0
0
1
RDAC #1
RDAC #2
AD5207
The data setup and data hold times in the specification table
determine the data valid time requirements. The last ten bits of
the data word entered into the serial register are held when CS
returns high and any extra bits are ignored. At the same time, when
CS goes high, it gates the address decoder enabling one of two
positive edge-triggered AD5207 RDAC latches; see Figure 5 detail.
RS
D7
D6
D5
D4
D3
D2
D1
D0
SHDN
CS
SDI
SDO
SERIAL
REGISTER
D
Ax
SHDN
RS
RS
Wx
Q
RDAC
LATCH
AND
DECODER R
S
CK RS
CLK
Bx
INTERNAL
RS
Figure 4. Detail SDO Output Schematic of the AD5207
The target RDAC latch is loaded with the last eight bits of the
data word to complete one RDAC update. For AD5207, it
cannot update both channels simultaneously and therefore, two
separate 10-bit data words must be clocked in to change both
VR settings.
AD5207
CS
RDAC1
ADDR
DECODE
RDAC2
CLK
SERIAL
REGISTER
SDI
Figure 5. Equivalent Input Control Logic
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figures 6 and 7. Applies
to digital input pins CS, SDI, SDO, SHDN, and CLK. Digital
input level for Logic 1 can be anywhere from 2.4 V to 5 V
regardless of whether it is in single or dual supplies.
340
LOGIC
DIGITAL PIN
VSS
Figure 6. ESD Protection of Digital Pins
Figure 8. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The last
few digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 50 kΩ = 50; and 100 kΩ = 100. The
nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B Terminal contact.
The 8-bit data in the RDAC latch is decoded to select one of
the 256 possible settings. Assume a 10 kΩ part is used, the
wiper’s first connection starts at the B Terminal for data 00H.
Since there is a 45 Ω wiper contact resistance, such connection
yields a minimum of 45 Ω resistance between Terminals W and
B. The second connection is the first tap point corresponds to
84 Ω (RWB = RAB/256 + RW = 39 Ω + 45 Ω) for data 01H. The
third connection is the next tap point representing 123 Ω (39 ×
2 + 45) for data 02H and so on. Each LSB value increase moves
the wiper up the resistor ladder until the last tap point is reached at
10006 Ω (RAB – 1 LSB + RW). Figure 8 shows a simplified diagram of the equivalent RDAC circuit.
The general equation determining the programmable output
resistance between W and B is:
RWB ( D ) =
D
(1)
× RAB + RW
256
where D is the data contained in the 8-bit RDAC latch, and RAB
is the nominal end-to-end resistance.
For example, RAB =10 kΩ, A Terminal can be open-circuit or
tied to W. The following output resistance RWB will be set for
the following RDAC latch codes.
A,B,W
VSS
Figure 7. ESD Protection of Resistor Terminals
–10–
REV. 0
AD5207
position of the potentiometer divider. Since AD5207 is capable
for dual supplies, the general equation defining the output voltage with respect to ground for any given input voltage applied to
terminals AB is:
Table IV.
D
(DEC)
RWB
()
Output State
255
128
1
0
10006
5045
84
45
Full-Scale (RAB – 1 LSB + RW)
Midscale
1 LSB
Zero-Scale (Wiper Contact Resistance)
VW ( D ) =
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than 5 mA. Otherwise, degradation or possibly destruction of
the internal switch contacts can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and Terminal A also produces a
digitally controlled resistance RWA. When these terminals are used,
the B Terminal should be let open or tied to the wiper terminal.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch is
increased in value. The general equation for this operation is:
RWA ( D ) =
256 – D
(2)
× RAB + RW
256
For example, when RAB = 10 kΩ, B terminal is either open or
tied to W, the following output resistance, RWA, will be set for
the following RDAC latch codes.
D
256 − D
VA +
VB
256
256
(3)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent on the ratio of
RWA and RWB and not the absolute values; therefore, the drift
reduces to 15 ppm/°C. There is no voltage polarity constraint
between Terminals A, B, and W as long as the terminal voltage
stays within VSS < VTERM < VDD.
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider the –3 dB bandwidth of the
AD5207BRU10 (10 kΩ resistor) measures 600 kHz at half
scale. TPC 16 provides the large signal BODE plot characteristics of the three available resistor versions 10 kΩ and 50 kΩ.
The gain flatness versus frequency graph, TPC 16, predicts
filter applications performance. A parasitic simulation model has
been developed and is shown in Figure 9. Listing I provides a
macro model net list for the 10 kΩ RDAC:
RDAC
10k
Table V.
A
D
(DEC)
RWA
()
Output State
255
128
1
0
84
5045
10006
10045
Full-Scale (RAB/256 + RW)
Midscale
1 LSB
Zero-Scale
The typical distribution of RAB from channel to channel matches
within ± 1%. Device-to-device matching is process-lot dependent and is possible to have ± 30% variation. The change in RAB
with temperature has a 500 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage. Let’s ignore the effect of
the wiper resistance for the moment. For example, when connecting A Terminal to 5 V and B Terminal to ground, it produces
a programmable output voltage at the wiper starting at zero
volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
REV. 0
B
CA
CW
70pF
CA = 45pF
CB
CB = 45pF
W
Figure 9. RDAC Circuit Simulation Model for RDAC = 10 kΩ
Listing I. Macro Model Net List for RDAC
.PARAM D=255, RDAC=10E3
*
.SUBCKT DPOT (A,W)
*
CA A 0 45E-12
RAW A W {(1-D/256)*RDAC+50}
CW W 0 70E-12
RBW W B {D/256*RDAC+50}
CB B 0 45E-12
*
.ENDS DPOT
–11–
AD5207
TEST CIRCUITS
5V
Figures 10 to 18 define the test conditions used in product
Specification table.
OP279
DUT
VIN
V+ = VDD
1 LSB = V+/2N
A
OFFSET
GND
W
V+
B
W
A
VMS
VOUT
DUT
B
OFFSET BIAS
Figure 10. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 15. Noninverting Gain Test Circuit
NO CONNECT
DUT
W
DUT
VIN
W
2.5V
VMS
0.1V
ISW
CODE = H
DUT
W
–15V
RSW =
DUT
VW
VOUT
Figure 16. Gain vs. Frequency Test Circuit
Figure 11. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
A
OP42
B
OFFSET
GND
B
VMS2
+15V
A
IW
A
IW = VDD/R NOMINAL
W
+
ISW
B
B
0.1V
–
VMS1
VSS TO VDD
RW = [VMS1 – V MS2]/IW
Figure 12. Wiper Resistance Test Circuit
Figure 17. Incremental ON Resistance Test Circuit
NC
VA
VDD
A
V+
VDD
DUT
V+ = VDD 10%
W
PSRR (dB) = 20 LOG
B
VMS
PSS (%/%) =
VMS%
VMS
VDD
VSS
VDD%
ICM
A
W
GND
B
VCM
NC
NC = NO CONNECT
Figure 13. Power Supply Sensitivity Test Circuit
(PSS, PSSR)
A
Figure 18. Common-Mode Leakage Current Test Circuit
DUT B
5V
W
VIN
OP279
OFFSET
GND
VOUT
OFFSET BIAS
Figure 14. Inverting Gain Test Circuit
–12–
REV. 0
AD5207
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE
Part
Number
Number
of VRs
per
Package
Terminal
Voltage
Range
Interface
Data
Control
Nominal
Resistance
(k⍀)
Resolution
(Number
of Wiper
Positions)
Power
Supply
Current
(IDD)
Packages
Comments
AD5201
1
± 3 V, +5.5 V
3-Wire
10, 50
33
40 µA
µSOIC-10
Full AC Specs, Dual Supply,
Pwr-On-Reset, Low Cost
AD5220
1
5.5 V
Up/Down
10, 50, 100
128
40 µA
PDIP, SO-8, µSOIC-8
No Rollover, Pwr-On-Reset
AD7376
1
± 15 V, +28 V
3-Wire
10, 50, 100, 1000
128
100 µA
PDIP-14, SOL-16,
TSSOP-14
Single +28 V or Dual ± 15 V
Supply Operation
AD5200
1
± 3 V, +5.5 V
3-Wire
10, 50
256
40 µA
µSOIC-10
Full AC Specs, Dual Supply,
Pwr-On-Reset
AD8400
1
5.5 V
3-Wire
1, 10, 50, 100
256
5 µA
SO-8
Full AC Specs
AD5260
1
± 5 V, +15 V
3-Wire
20, 50, 200
256
60 µA
TSSOP-14
15 V or ± 5 V,
TC < 50 ppm/°C
AD5241
1
± 3 V, +5.5 V
2-Wire
10, 100, 1000
256
50 µA
SO-14, TSSOP-14
I2C-Compatible, TC
< 50 ppm/°C
AD5231* 1
± 3 V, +5.5 V
3-Wire
10, 50, 100
1024
20 µA
TSSOP-16
Nonvolatile Memory, Direct
Program, I/D, ± 6 dB Settability
AD5222
2
± 3 V, +5.5 V
Up/Down
10, 50, 100, 1000
128
80 µA
SO-14, TSSOP-14
No Rollover, Stereo, Pwr-OnReset, TC < 50 ppm/°C
AD8402
2
5.5 V
3-Wire
1, 10, 50, 100
256
5 µA
PDIP, SO-14,
TSSOP-14
Full AC Specs, nA
Shutdown Current
AD5207
2
± 3 V, +5.5 V
3-Wire
10, 50, 100
256
40 µA
TSSOP-14
Full AC specs, Dual Supply,
Pwr-On-Reset, SDO
AD5232* 2
± 3 V, +5.5 V
3-Wire
10, 50, 100
256
20 µA
TSSOP-16
Nonvolatile Memory, Direct
Program, I/D, ± 6 dB Settability
AD5235* 2
± 3 V, +5.5 V
3-Wire
25, 250
1024
20 µA
TSSOP-16
Nonvolatile Memory, Direct
Program, TC < 50 ppm/°C
AD5242
2
± 3 V, +5.5 V
2-Wire
10, 100, 1000
256
50 µA
SO-16, TSSOP-16
I2C-Compatible, TC
< 50 ppm/°C
AD5262* 2
± 5 V, +15 V
3-Wire
20, 50, 200
256
60 µA
TSSOP-16
± 15 V or ± 5 V, Pwr-OnReset, TC < 50 ppm/°C
AD5203
5.5 V
3-Wire
10, 100
64
5 µA
PDIP, SOL-24,
TSSOP-24
Full AC Specs, nA
Shutdown Current
AD5233* 4
± 3 V, +5.5 V
3-Wire
10, 50, 100
64
20 µA
TSSOP-16
Nonvolatile Memory, Direct
Program, I/D, ± 6 dB Settability
AD5204
4
± 3 V, +5.5 V
3-Wire
10, 50, 100
256
60 µA
PDIP, SOL-24,
TSSOP-24
Full AC Specs, Dual Supply,
Pwr-On-Reset
AD8403
4
5.5 V
3-Wire
1, 10, 50, 100
256
5 µA
PDIP, SOL-24,
TSSOP-24
Full AC Specs, nA
Shutdown Current
AD5206
6
± 3 V, +5.5 V
3-Wire
10, 50, 100
256
60 µA
PDIP, SOL-24,
TSSOP-24
Full AC Specs, Dual Supply,
Pwr-On-Reset
4
*Future product, consult factory for latest status.
Latest Digital Potentiometer Information available at www.analog.com/support/standard_linear/selection_guides/dig_pot.html
REV. 0
–13–
AD5207
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
14-Lead TSSOP
(RU-14)
0.201 (5.10)
0.193 (4.90)
14
8
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
7
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0256
(0.65)
BSC
0.0433 (1.10)
MAX
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–14–
8
0
0.028 (0.70)
0.020 (0.50)
REV. 0
–15–
–16–
PRINTED IN U.S.A.
C01885–1.5–4/01(0)