256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer AD5165 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD A CS SDI 3-WIRE INTERFACE W CLK WIPER REGISTER B 04749-0-001 Ultralow standby power IDD = 50 nA typical 256-position End-to-end resistance 100 kΩ Logic high voltage 1.8 V Power supply 2.7 V to 5.5 V Low temperature coefficient 35 ppm/°C Compact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package Simple 3-wire digital interface Wide operating temperature −40°C to +125°C Pin-to-pin compatible to AD5160 with CS inverted GND APPLICATIONS Figure 1. Battery-operated electronics adjustment Remote utilities meter adjustment Mechanical potentiometer replacement Transducer circuit adjustment Automotive electronics adjustment Gain control and offset adjustment System calibration VCXO adjustment PIN CONFIGURATION 8 AD5165 B TOP VIEW GND 3 (Not to Scale) 6 CS 5 SDI CLK 4 Figure 2. GENERAL OVERVIEW TYPICAL APPLICATION 5V VOH = 1.8V MIN VDD 3.3V DIGITAL CONTROL Wiper settings are controlled through a simple 3-wire interface. The interface is similar to the SPI® digital interface except for the inverted chip-select function that minimizes logic power consumption in the idling state. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the wiper register. Operating from a 2.7 V to 5.5 V power supply and consuming less than 50 nA typical standby power allows use in batteryoperated portable or remote utility device applications. LOGIC OR MICRO AD5165 VA VW WIDE TERMINAL VOLTAGE RANGE: VB 0V < VA,VB,VW < 5V CS CLK SDI GND 04749-0-003 The AD5165 provides a compact 2.9 mm × 2.8 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The AD5165’s supply voltage requirement is 2.7 V to 5.5 V, but its logic voltage requirement is 1.8 V to VDD. The AD5165 consumes very low quiescent power during standby mode and is ideal for battery-operated applications. A 7 04749-0-002 W 1 VDD 2 Figure 3. Note: The terms digital potentiometer, RDAC, and VR are used interchangeably. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD5165 TABLE OF CONTENTS Electrical Characteristics—100 kΩ Version .................................. 3 3-Wire Serial Bus Digital Interface .......................................... 14 Absolute Maximum Ratings............................................................ 5 ESD Protection ........................................................................... 14 Pin Configuration and Functional Descriptions.......................... 6 Terminal Voltage Operating Range.......................................... 14 Typical Performance Characteristics ............................................. 7 Power-Up Sequence ................................................................... 14 Test Circuits..................................................................................... 11 Layout and Power Supply Bypassing ....................................... 15 3-Wire Digital Interface................................................................. 12 Evaluation Board ........................................................................ 15 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 16 Programming the Variable Resistor ......................................... 13 Ordering Guide .......................................................................... 16 Programming the Potentiometer Divider ............................... 14 REVISION HISTORY 4/04—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD5165 ELECTRICAL CHARACTERISTICS—100 kΩ VERSION VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted. Table 1. Parameter Symbol DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL Resistor Integral Nonlinearity2 R-INL Nominal Resistor Tolerance3 ∆RAB/RAB Resistance Temperature Coefficient (∆RAB/RAB)/∆Tx106 Wiper Resistance RW DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N Differential Nonlinearity4 DNL Integral Nonlinearity4 INL (∆VW/VW )/∆Tx106 Voltage Divider Temperature Coefficient Full-Scale Error VWFSE Zero-Scale Error VWZSE RESISTOR TERMINALS Voltage Range5 VA,B,W Capacitance6 A, B CA,B Capacitance6 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 8 Bandwidth −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density CW ICM VIH VIL CIL VDD RANGE IDD PDISS PSS BW THDW tS eN_WB Conditions Min Typ1 Max Unit RWB, VA = no connect RWB, VA = no connect TA = 25°C VAB = VDD, wiper = no connect VDD = 2.7 V/5.5 V −1 −2 −20 ±0.1 ±0.25 +1 +2 +20 LSB LSB % ppm/°C Ω 35 85/50 Code = 0xFF Code = 0x00 8 +1 +1 Bits LSB LSB ppm/°C 0 0.5 LSB LSB VDD 90 V pF 95 pF 1 nA −1 −1 ±0.1 ±0.3 15 −0.5 0 −0.3 0.1 Code = 0x80 GND f = 1 MHz, measured to GND, Code = 0x80 f = 1 MHz, measured to GND, Code = 0x80 VA = VB = VDD/2 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V 150/120 1.8 0.6 5 2.7 Digital inputs = 0 V or VDD VDD = 2.7 V, digital inputs = 1.8 V VDD = 5 V, digital inputs = 1.8 V Digital inputs = 0 V or VDD VDD = +5 V ± 10%, Code = Midscale Code = 0x80 VA =1 V rms, VB = 0 V, f = 1 kHz, VA = 5 V, VB = 0 V, ±1 LSB error band RWB = 50 kΩ 1 0.05 10 500 ±0.001 5.5 1 5.5 ±0.005 Rev. 0 | Page 3 of 16 V µA µA µA µW %/% 55 0.05 2 kHz % µs 28 nV/√Hz Typical specifications represent average readings at +25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. 5 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 2 V V pF AD5165 TIMING CHARACTERISTICS—100 kΩ VERSION VDD = +5 V ± 10%, or +3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 2. Parameter Symbol Conditions 3-WIRE INTERFACE TIMING CHARACTERISTICS2, 3, 4 (specifications apply to all parts) Clock Frequency fCLK= 1/( tCH+ tCL) Input Clock Pulse Width tCH, tCL Clock level high or low Data Setup Time tDS Data Hold Time tDH CS Setup Time tCSS CS Low Pulse Width tCSW CLK Fall to CS Rise Hold Time tCSH0 CLK Fall to CS Fall Hold Time tCSH1 CS Fall to Clock Rise Setup tCS1 1 Min 20 5 5 15 40 0 0 10 Typ1 Max Unit 25 MHz ns ns ns ns ns ns ns ns Typical specifications represent average readings at +25°C and VDD = 5 V. Guaranteed by design and not subject to production test. 3 All dynamic characteristics use VDD = 5 V. 4 See Figure 34 and Figure 35 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 2 Rev. 0 | Page 4 of 16 AD5165 ABSOLUTE MAXIMUM RATINGS TA = +25°C, unless otherwise noted.1, 2 Table 3. Parameter VDD to GND VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB ≤ 1 kΩ, A open)2 IWA Continuous (RWA ≤ 1 kΩ, B open)2 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 – 30 sec) Thermal Resistance2 θJA: TSOT-8 Value –0.3 V to +7 V VDD ±20 mA ±5 mA ±5 mA 0 V to +7 V –40°C to +125°C 150°C –65°C to +150°C 245°C 200°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX − TA)/θJA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 AD5165 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS 8 AD5165 A B TOP VIEW GND 3 (Not to Scale) 6 CS 5 SDI CLK 4 7 04749-0-002 W 1 VDD 2 Figure 4. Table 4. Pin 1 2 3 4 5 6 7 8 Name W VDD GND CLK SDI CS B A Description Wiper terminal. GND ≤ VA ≤ VDD. Positive Power Supply. Digital Ground. Serial Clock Input. Positive-edge triggered. Serial Data Input (data loads MSB first). Chip Select Input, active high. When CS returns low, data is loaded into the wiper register. B terminal. GND ≤ VA ≤ VDD. A terminal. GND ≤ VA ≤ VDD. Rev. 0 | Page 6 of 16 AD5165 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 5.5V 2.7V –40°C +25°C +85°C +125°C 0.4 POTENTIOMETER MODE DNL (LSB) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 32 64 96 128 160 192 224 256 CODE (Decimal) –0.5 04749-0-011 –0.5 0 96 128 160 192 224 256 Figure 8. DNL vs. Code vs. Temperature, VDD = 5 V Figure 5. R-INL vs. Code vs. Supply Voltages 0.5 5.5V 2.7V 0.4 POTENTIOMETER MODE INL (LSB) 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 5.5V 2.7V 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 32 64 96 128 160 192 224 256 CODE (Decimal) –0.5 04749-0-013 –0.5 0 32 64 96 128 160 192 224 256 CODE (Decimal) Figure 6. R-DNL vs. Code vs. Supply Voltages 04749-0-007 –0.4 Figure 9. INL vs. Code vs. Supply Voltages 0.5 0.5 –40°C +25°C +85°C +125°C 0.3 5.5V 2.7V 0.4 POTENTIOMETER MODE DNL (LSB) 0.4 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 32 64 96 128 160 192 224 CODE (Decimal) 256 04749-0-006 POTENTIOMETER MODE INL (LSB) 64 CODE (Decimal) 0.5 REHOSTAT MODE DNL (LSB) 32 04749-0-008 –0.4 0.3 Figure 7. INL vs. Code vs. Temperature , VDD = 5 V –0.5 0 32 64 96 128 160 192 224 CODE (Decimal) Figure 10. DNL vs. Code vs. Supply Voltages Rev. 0 | Page 7 of 16 256 04749-0-009 RHEOSTAT MODE INL (LSB) 0.4 AD5165 0.5 0.5 –40°C +25°C +85°C +125°C 0.3 0.2 0.1 0.1 ZSE (LSB) 0.2 0 –0.1 0 –0.2 –0.3 –0.3 –0.4 –0.4 0 32 64 96 128 160 192 224 256 CODE (Decimal) ZSE @ VDD = 2.7V –0.1 –0.2 –0.5 ZSE @ VDD = 5.5V –0.5 –40 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 11. R-INL vs. Code vs. Temperature, VDD = 5 V Figure 14. Zero-Scale Error vs. Temperature 0.5 0.5 –40°C +25°C +85°C +125°C 0.3 SUPPLY CURRENT (µA) 0.3 0.4 0.2 0.1 0 –0.1 –0.2 0.2 0 –0.1 IDD @ VDD = 2.7V –0.2 –0.3 –0.3 –0.4 –0.4 0 32 64 96 128 160 192 224 256 CODE (Decimal) –0.5 –40 04749-0-012 –0.5 IDD @ VDD = 5.5V 0.1 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 12. R-DNL vs. Code vs. Temperature, VDD = 5 V 04749-0-020 0.4 RHEOSTAT MODE DNL (LSB) –20 04749-0-022 0.3 0.4 04749-0-010 RHEOSTAT MODE INL (LSB) 0.4 Figure 15. Supply Current vs. Temperature 0.5 10000 0.4 1000 0.3 FSE @ VDD = 5.5V 100 0.1 IDD (µA) VDD = VA = 5V 0 –0.1 FSE @ VDD = 2.7V –0.2 10 VDD = VA = 2.7V 1 –0.3 –0.5 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 Figure 13. Full-Scale Error vs. Temperature 0.01 0 1 2 3 4 VIH (0) (V) Figure 16. Supply Current vs. Digital Input Voltage Rev. 0 | Page 8 of 16 5 04749-0-025 0.1 –0.4 04749-0-023 FSE (LSB) 0.2 AD5165 REF LEVEL 0.000dB 0 1000 VDD = VA = 5V –6 0x80 –12 0x40 –18 0x20 –24 0x10 –30 0x08 –36 0x04 –42 0x02 10 1 0.1 0x01 –48 0 1 2 3 4 5 VIH (1MHz) (V) –54 04749-0-026 0.01 –60 1k START 1 000.000Hz Figure 17. Supply Current vs. Digital Input Voltage 100k 1M STOP 1 000 000.000Hz Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ REF LEVEL –5.000dB 20 /DIV 0.500dB –5.5 15 100kΩ – 54kHz –6.0 10 –6.5 5 –7.0 0 –7.5 –5 –8.0 –8.5 –10 –9.0 R = 100kΩ –15 –9.5 –20 0 32 64 96 128 160 192 224 256 CODE (Decimal) –10.0 04749-0-015 RHEOSTAT MODE TEMCO (ppm/°C) 10k –10.5 10k 10M START 1 000.000Hz STOP 1 000 000.000Hz 04749-0-047 IDD (µA) VDD = VA = 2.7V MARKER 54 089.173Hz MAG (A/R) –9.052dB 04749-0-048 100 /DIV 6.000dB Figure 21. –3 dB Bandwidth @ Code = 0x80 Figure 18. Rheostat Mode Tempco ∆RWB/∆T vs. Code 80 CODE = 80H, VA = VDD, VB = 0V 6 60 4 PSRR (–dB) PSRR @ VDD = 5V DC ± 10% p-p AC 2 0 PSRR @ VDD = 3V DC ± 10% p-p AC 40 –2 20 –4 –8 0 32 64 96 128 160 192 224 256 CODE (Decimal) 0 100 1k 10k 100k FREQUENCY (Hz) Figure 22. PSRR vs. Frequency Figure 19. Potentiometer Mode Tempco ∆VWB/∆T vs. Code Rev. 0 | Page 9 of 16 1M 04749-0-019 –6 04749-0-014 POTENTIOMETER MODE TEMPCO (ppm/°C) 8 AD5165 800 VDD = 5V VA = 5V VB = 0V 700 500 1 VW 400 2 300 Ch 1 CODE FFH 100 100mV BW Ch 2 5.00 V BW M 200ns A CH1 152mV 100k 1M 04749-0-018 Figure 26. Midscale Glitch, Code 0x80–0x7F 0 10k 10M FREQUENCY (Hz) Figure 23. IDD vs. Frequency 1 VW 2 Ch 1 200mV BW Ch 2 5.00 V BW M 100ns A CH2 3.00 V 04749-0-030 CS Figure 24. Large Signal Settling Time, Code 0xFF–0x00 1 VW CLK 2 Ch 1 200mV BW Ch 2 5.00 V BW M 100ns A CH2 3.00 V Figure 25. Digital Feedthrough Rev. 0 | Page 10 of 16 04749-0-028 CS CODE 55H 200 04749-0-030 IDD (µA) 600 AD5165 TEST CIRCUITS Figure 27 to Figure 33 illustrate the test circuits that define the test conditions used in the product specification tables. V+ = VDD 1LSB = V+/2N DUT W VIN AD8610 VMS OFFSET GND –15V 2.5V Figure 31. Test Circuit for Gain vs. Frequency Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) NO CONNECT W B GND TO VDD Figure 32. Test Circuit for Incremental ON Resistance Figure 28. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) NC DUT IW = VDD/RNOMINAL DUT VW A RW = [VMS1 – VMS2]/IW VMS1 04749-0-033 VDD B W GND VA V+ = VDD 10% B W PSS (%/%) = VMS ∆VMS% ∆V (∆V MS ) DD ∆VDD % 04749-0-034 A V+ VCM NC = NO CONNECT Figure 33. Test Circuit for Common-Mode Leakage Current Figure 29. Test Circuit for Wiper Resistance PSRR (dB) = 20 LOG ICM B NC VDD 0.1V ISW 04749-0-032 VMS W 0.1V ISW CODE = 0x00 IW B VMS2 RSW = DUT DUT A W VOUT 04749-0-035 04749-0-031 B B A +15V W 04749-0-037 V+ DUT A 04749-0-036 A Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Rev. 0 | Page 11 of 16 AD5165 3-WIRE DIGITAL INTERFACE Note that in the AD5165 data is loaded MSB first. Table 5. AD5165 Serial Data-Word Format B6 D6 B5 D5 B4 D4 1 SDI CLK CS VOUT D7 0 1 B3 D3 D6 D5 D4 D3 B2 D2 D2 D1 B1 D1 B0 D0 LSB 20 D0 0 1 RDAC REGISTER LOAD 0 1 04749-0-004 0 Figure 34. 3-Wire Digital Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) Dx Dx 0 tCH 1 tDS tDH tCS1 CLK 0 tCL tCSHO tCSH1 tCSS 1 CS tCSW 0 tS VDD VOUT ±1LSB 0 Figure 35. 3-Wire Digital Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) Rev. 0 | Page 12 of 16 04749-0-005 B7 D7 MSB 27 AD5165 THEORY OF OPERATION The AD5165 is a 256-position digitally controlled variable resistor (VR) device. where: PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available in 100 kΩ. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 100 kΩ and the A terminal is open circuited, the following output resistance RWB is set for the indicated RDAC latch codes. Table 6. Codes and Corresponding RWB Resistance A A A W B B W 04749-0-038 W D (Dec.) 255 128 1 0 B Figure 36. Rheostat Mode Configuration Assuming that a 100 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 490 Ω (RWB = RAB/256 + 2 × RW = 390 Ω + 2 × 50 Ω) for data 0x01. The third connection is the next tap point, representing 880 Ω (2 × 390 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 100,100 Ω (RAB + 2 × RW). A RWB (Ω) 99,710 50,100 490 100 Note that, in the zero-scale condition, a finite wiper resistance of 100 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RS RWA (D ) = D7 D6 D5 D4 D3 D2 D1 D0 Output State Full scale (RAB – 1 LSB + RW) Midscale 1 LSB Zero scale (wiper contact resistance) RS 256 − D × RAB + 2 × RW 256 (2) For RAB = 100 kΩ with the B terminal open circuited, the following output resistance RWA is set for the indicated RDAC latch codes. RS W Table 7. Codes and Corresponding RWA Resistance RS LATCH AND DECODER B 04749-0-039 RDAC D (Dec.) 255 128 1 0 Figure 37. AD5165 Equivalent RDAC Circuit The general equation determining the digitally programmed output resistance between W and B is RWB (D ) = D × RAB + 2 × RW 256 RWA (Ω) 490 50,100 99, 710 100,100 Output State Full scale Midscale 1 LSB Zero scale Typical device-to-device matching is process-lot dependent and may vary by up to ±20%. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 35 ppm/°C temperature coefficient. (1) Rev. 0 | Page 13 of 16 AD5165 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. VI A VO All digital inputs are protected with a series of input resistors and parallel Zener ESD structures, shown in Figure 39 and Figure 40. This applies to the digital input pins SDI, CLK, and CS. 340Ω Figure 38. Potentiometer Mode Configuration GND If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminals A and B divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is 256 − D D VA + VB 256 256 R (D ) RWB (D ) VA + WA VB RAB RAB A, B, W GND Figure 40. ESD Protection of Resistor Terminals (3) TERMINAL VOLTAGE OPERATING RANGE A more accurate calculation, which includes the effect of wiper resistance, VW, is VW (D ) = Figure 39. ESD Protection of Digital Pins (4) The AD5165 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or GND are clamped by the internal forward-biased diodes, as shown in Figure 41. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C. VDD 3-WIRE SERIAL BUS DIGITAL INTERFACE GND The AD5165 contains a 3-wire digital interface (SDI, CS, and CLK). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table 5. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When CS is high, the clock loads data into the serial register on each positive clock edge, as shown in Figure 34. A W B 04749-0-043 VW (D ) = 04749-0-041 LOGIC 04749-0-042 B ESD PROTECTION 04749-0-040 W The data setup and data hold times in the specifications table determine the valid timing requirements. The AD5165 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic low. Extra MSB bits are ignored. Figure 41. Maximum Terminal Voltages Set by VDD and GND POWER-UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 41), it is important to power VDD/GND before applying any voltage to terminals A, B, and W; otherwise, the diode is forward biased such that VDD is powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA, VB, and VW. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. Rev. 0 | Page 14 of 16 AD5165 LAYOUT AND POWER SUPPLY BYPASSING EVALUATION BOARD It is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. An evaluation board, along with all necessary software, is available to program the AD5165 from any PC running Windows® 98/2000/XP. The graphical user interface, as shown in Figure 43, is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board. VDD C3 10µF + 04749-0-046 Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disk or chip ceramic capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 42). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. VDD C1 0.1µF Figure 43. AD5165 Evaluation Board Software AD5165 04749-0-044 GND The AD5165 starts at midscale upon power-up. To increment or decrement the resistance, the user may move the scroll bars on the left. To write any specific value, the user should use the bit pattern in the upper screen and click the Run button. The format of writing data to the device is shown in Figure 32. Figure 42. Power Supply Bypassing Rev. 0 | Page 15 of 16 AD5165 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 INDICATOR 0.65 BSC 1.95 BSC 0.90 0.87 0.84 1.00 MAX 0.10 MAX 0.38 0.22 0.20 0.08 SEATING PLANE 8° 4° 0° 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-193BA Figure 44. 8-Lead Thin Small Outline Transistor Package [Thin SOT-23] (UJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD5165BUJZ100-R21 AD5165BUJZ100-R71 AD5165EVAL 1 RAB (Ω) 100 k 100 k Temperature –40°C to +125°C –40°C to +125°C Package Description Thin SOT-23 Thin SOT-23 Evaluation Board Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04749–0–4/04(0) Rev. 0 | Page 16 of 16 Package Option UJ-8 UJ-8 Quantity on Reel 250 3,000 Branding D3N D3N