ETC LXT363PE

LXT363
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Datasheet
The LXT363 is a fully integrated, combination transceiver for T1 ISDN Primary Rate Interface
and general T1 long and short haul applications. The device operates over 22 AWG twisted-pair
cables from 0 to 6 kft and offers Line Build Outs and pulse equalization settings for all T1 Line
Interface Unit (LIU) applications.
The LXT363 features an Intel or Motorola compatible parallel port for microprocessor control.
The LXT363 incorporates advanced crystal-less digital jitter attenuation in either the transmit or
receive data path starting at 3 Hz. B8ZS encoding/decoding and unipolar or bipolar data I/O are
available. The LIU provides loss of signal monitoring and a variety of diagnostic loopback
modes.
The parallel port is ideal for applications with multiple T1 interfaces.
Applications
■
■
■
ISDN Primary Rate Interface (ISDN PRI)
CSU/NTU interface to T1 Service
T1 LAN/WAN bridge/routers
■
■
T1 Mux; Channel Banks
Digital Loop Carrier - Subscriber Carrier
Systems
Product Features
■
■
■
■
■
■
Fully integrated transceiver for Long or
Short-Haul T1 interfaces
Crystal-less digital jitter attenuation
— Select either transmit or receive path
— No crystal or high speed external clock
required
Meets or exceeds specifications in ANSI
T1.102, T1.403 and T1.408; and AT&T
Pub 62411
Supports 100 Ω (T1 twisted-pair)
applications
Selectable receiver sensitivity – fully
restores the received signal after
transmission through a cable with
attenuation of either 0 to 26 dB, or 0 to
36 dB @ 772 kHz
Five Pulse Equalization Settings for T1
Short-Haul applications
■
■
■
■
■
■
■
■
Four Line Build-Outs for T1 long-haul
applications from 0 dB to -22.5 dB
Transmit/receive performance monitors
with Driver Fail Monitor Open and Loss of
Signal outputs
Selectable unipolar or bipolar data I/O and
B8ZS encoding/decoding
Line attenuation indication output in 2.9 dB
steps
QRSS generator/detector for testing or
monitoring
Local, remote, and analog loopback, plus
in-band network loopback code generation
and detection
Intel/Motorola compatible 8-bit parallel
interface for microprocessor control
Available in 28-pin PLCC, 44-pin PQFP
and 44-pin LQFP packages
As of January 15, 2001, this document replaces the Level One document
Order Number: 249034-001
known as LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications.
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT363 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Contents
1.0
Pin Assignments and Signal Descriptions ...................................................... 8
1.1
2.0
Mode Dependent Signals ...................................................................................... 9
Functional Description...........................................................................................13
2.1
2.2
2.3
2.4
2.5
2.6
Initialization..........................................................................................................13
2.1.1 Reset Operation .....................................................................................13
Transmitter ..........................................................................................................13
2.2.1 Transmit Digital Data Interface...............................................................13
2.2.2 Transmit Monitoring................................................................................13
2.2.3 Transmit Drivers .....................................................................................14
2.2.4 Transmit Idle Mode.................................................................................14
2.2.5 Transmit Pulse Shape ............................................................................14
Receiver ..............................................................................................................14
2.3.1 Receive Equalizer ..................................................................................14
2.3.2 Receive Data Recovery..........................................................................15
2.3.3 Receiver Monitor Mode ..........................................................................15
Jitter Attenuation .................................................................................................15
Diagnostic Mode Operation.................................................................................16
2.5.1 Loopback Modes ....................................................................................16
2.5.1.1 Local Loopback .........................................................................16
2.5.1.2 Analog Loopback.......................................................................18
2.5.1.3 Remote Loopback .....................................................................18
2.5.1.4 Network Loopback.....................................................................19
2.5.1.5 Dual Loopback ..........................................................................19
2.5.2 Internal Pattern Generation and Detection.............................................20
2.5.2.1 Transmit All Ones ......................................................................20
2.5.2.2 Quasi-Random Signal Source (QRSS) .....................................20
2.5.2.3 In-Band Network Loop Up or Down Code Generator ................21
2.5.3 Error Insertion and Detection .................................................................21
2.5.3.1 Bipolar Violation Insertion (INSBPV) .........................................21
2.5.3.2 Logic Error Insertion (INSLER)..................................................22
2.5.3.3 Bipolar Violation Detection (BPV)..............................................22
2.5.4 Alarm Condition Monitoring ....................................................................22
2.5.4.1 Loss of Signal ............................................................................22
2.5.4.2 Alarm Indication Signal Detection .............................................22
2.5.4.3 Driver Failure Open Mode .........................................................22
2.5.4.4 Elastic Store Overflow/Underflow ..............................................23
2.5.5 Other Diagnostic Reports .......................................................................23
2.5.5.1 Receive Line Attenuation Indication ..........................................23
2.5.5.2 Built-In Self Test ........................................................................23
Parallel Microprocessor Interface........................................................................23
2.6.1 Interrupt Handling...................................................................................24
3.0
Register Definitions.................................................................................................25
4.0
Application Information .........................................................................................30
4.1
4.2
Datasheet
Transmit Return Loss ..........................................................................................30
Transformer Data ................................................................................................30
3
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
4.3
Application Circuits.............................................................................................. 30
5.0
Test Specifications .................................................................................................. 33
6.0
Mechanical Specifications ................................................................................... 41
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
4
LXT363 Block Diagram ......................................................................................... 7
LXT363 Pin Assignments...................................................................................... 8
50% Duty Cycle Coding ...................................................................................... 14
TAOS with LLOOP .............................................................................................. 17
Local Loopback ................................................................................................... 17
Analog Loopback ................................................................................................ 18
Remote Loopback ............................................................................................... 19
Dual Loopback .................................................................................................... 19
TAOS Data Path ................................................................................................. 20
QRSS Mode ........................................................................................................ 20
Typical LXT363 Application................................................................................. 32
1.544 MHz T1 Pulse (DS1 and DSX-1) (See Table 23) ...................................... 35
Transmit Clock Timing ........................................................................................ 36
Receive Clock Timing ......................................................................................... 37
LXT363 I/O Timing Diagram for Intel Address/Data Bus .................................... 38
LXT363 I/O Timing Diagram for Motorola Address/Data Bus ............................. 39
Typical T1 Jitter Tolerance at 36 dB ................................................................... 39
T1 Jitter Attenuation ............................................................................................ 40
Plastic Leaded Chip Carrier Package Specifications .......................................... 41
Plastic Quad Flat Package Specifications........................................................... 42
Low-Profile Quad Flat Package Specifications ................................................... 43
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Datasheet
LXT363 Clock and Data Pin Assignments by Mode1............................................ 9
LXT363 Processor Interface Pins.......................................................................... 9
LXT363 Signal Descriptions ................................................................................10
Diagnostic Mode Summary .................................................................................16
Register Addresses .............................................................................................25
Register and Bit Summary ..................................................................................25
Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................26
Equalizer Control Bit Settings..............................................................................26
Control Register #2 Read/Write, Address (A7-A0) = x010001x ..........................27
Control Register #3 Read/Write, Address (A7-A0) = x010010x ..........................27
Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x....................28
Transition Status Register Read Only, Address (A7-A0) = x010100x.................28
Performance Status Register Read Only, Address (A7-A0) = x010101x ............29
Equalizer Status Register Read Only, Address (A7-A0) = x010110x .................29
Control Register #4 Read/Write, Address (A7-A0) = x010111x ..........................29
Transmit Return Loss ..........................................................................................30
Transformer Specifications for LXT363...............................................................30
Recommended Transformers for LXT363...........................................................31
Absolute Maximum Ratings.................................................................................33
Recommended Operating Conditions .................................................................33
Digital Characteristics..........................................................................................34
Analog Characteristics ........................................................................................34
1.544 MHz T1 Pulse Mask Corner Point Specifications......................................35
Master and Transmit Clock Timing Characteristics (See Figure 13)...................35
Receive Timing Characteristics (See Figure 14).................................................36
LXT363 20 MHz Intel Bus Parallel I/O Timing Characteristics
(See Figure 15) ...................................................................................................37
LXT363 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics
(See Figure 16) ...................................................................................................38
5
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Revision History
Revision
6
Date
Description
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Figure 1. LXT363 Block Diagram
Datasheet
7
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
1.0
Pin Assignments and Signal Descriptions
ALE / AS
AD3
2
AD4
TCLK
3
MCLK
TPOS / TDATA / INSLER
4
AD5
TNEG / INSBPV
Figure 2. LXT363 Pin Assignments and Markings
1
28
27
26
5
25
AD2
RNEG / BPV
6
24
AD1
RPOS / RDATA
7
23
AD0
22
GND
21
VCC
20
RRING
19
RTIP
n/c
AD2
CS
18
INT
16 17
AD3
15
AD4
14
TRING
13
AD5
TNEG / INSBPV
n/c
WR / R/W
12
MCLK
11
TVCC
10
AD7
n/c
AD6
TTIP
9
TGND
RD / DS
TCLK
8
LXT363PE
XX
LXT363PE
XXXXXX
XXXXXXXX
TPOS / TDATA / INSLER
RCLK
44 43 42 41 40 39 38 37 36 35 34
n/c
1
33
n/c
ALE / AS
RNEG /
BPV
RPOS / RDATA
2
32
AD1
3
31
AD0
4
30
n/c
RCLK
5
n/c
6
RD / DS
7
n/c
LXT363QE XX
LXT363QE
LXT363LE
XX
XXXXXX
LXT363LE
XXXXXXXX
29
GND
28
n/c
27
VCC
8
26
n/c
AD6
9
25
RRING
AD7
10
24
RTIP
n/c
11
23
n/c
n/c
INT
CS
TVCC
TRING
n/c
TGND
n/c
TTIP
n/c
8
WR / R/W
12 13 14 15 16 17 18 19 20 21 22
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
1.1
Mode Dependent Signals
As shown in Figure 2, the LXT363 has several pins that change function (and signal name)
according to the selected mode(s) of operation. These pins, associated signal names, and operating
modes are summarized in Table 1 and Table 2. LXT363 signals are described in Table 3.
LXT363 Clock and Data Pin Assignments by Mode1
Table 1.
Pin #
External Data Modes
Bipolar Mode
QRSS Modes
PLCC
QFP
Unipolar Mode
Bipolar Mode
Unipolar Mode
1
39
2
41
3
42
TPOS
TDATA
INSLER
4
43
TNEG
INSBPV
INSBPV
6
3
RNEG
BPV
7
4
RPOS
RDATA
8
5
RCLK
13
15
TTIP
16
19
TRING
19
24
RTIP
20
25
RRING
MCLK
TCLK
RNEG
BPV
RPOS
RDATA
1. Data pins change based on whether external data or internal QRSS mode is active.
Table 2.
LXT363 Processor Interface Pins
Pin #
Address/Data Bus Type
Pin #
Address/Data Bus Type
PLCC
QFP
Intel
Motorola
PLCC
QFP
Intel
Motorola
5
2
ALE
AS
25
35
AD2
9
7
RD
DS
26
36
AD3
12
13
WR
R/W
27
37
AD4
17
20
CS
28
38
AD5
18
21
INT
10
9
AD6
23
31
AD0
11
10
AD7
24
32
AD1
-
-
-
Datasheet
9
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 3.
LXT363 Signal Descriptions
Pin #
Symbol
PLCC
I/O1
Description
QFP
1
39
MCLK
DI
Master Clock. External, independent 1.544 MHz clock signal required to
generate internal clocks. MCLK must be jitter-free and have an accuracy
better than ± 50 ppm with a typical duty cycle of 50%. Upon Loss of Signal
(LOS), RCLK is derived from MCLK.
2
41
TCLK
DI
Transmit Clock. A 1.544 MHz clock is required. The transceiver samples
TPOS and TNEG on the falling edge of TCLK (or MCLK, if TCLK is not
present).
BIPOLAR MODES:
Transmit – Positive and Negative. TPOS and TNEG are the positive and
negative sides of a bipolar input pair. Data to be transmitted onto the
twisted-pair line is input at these pins. TPOS/TNEG are sampled on the
falling edge of TCLK (or MCLK, if TCLK is not present).
UNIPOLAR MODES:
3
42
TPOS / TDATA /
INSLER
DI
4
43
TNEG / INSBPV
DI
Transmit Data. TDATA carries unipolar data to be transmitted onto the
twisted-pair line and is sampled on the falling edge of TCLK.
Transmit Insert Logic Error. In QRSS mode, a Low-to-High transition on
INSLER inserts a logic error into the transmitted QRSS data pattern. The
error follows the data flow of the active loopback mode. The LXT363
samples this pin on the falling edge of TCLK (or MCLK, if TCLK is not
present).
Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge
of TCLK (or MCLK, if TCLK is not present) to control Bipolar Violation
(BPV) insertions in the transmit data stream. A Low-to-High transition is
required to insert each BPV. In QRSS mode, the BPV is inserted into the
transmitted QRSS pattern.
Address Latch Enable. Connect to ALE signal of Intel microprocessor
5
2
ALE / AS
DI
Address Strobe Connect to AS signal of Motorola microprocessor.
Note that leaving this pin floating forces all output pins to a high impedance
state.
BIPOLAR MODES:
6
3
RNEG / BPV
DO
Receive – Negative and Positive. RPOS and RNEG are the positive and
negative sides of a bipolar output pair. Data recovered from the line
interface is output on these pins. A signal on RNEG corresponds to receipt
of a negative pulse on RTIP/RRING. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. RNEG/RPOS are Non-Returnto-Zero (NRZ). The PLCKE bit in register CR3 selects the RCLK clock
edge when RPOS /RNEG are stable and valid.
7
4
RPOS / RDATA
DO
UNIPOLAR MODES:
Receive Bipolar Violation. BPV goes High to indicate detection of a
bipolar violation from the line. This is an NRZ output, valid on the rising
edge of RCLK.
Receive Data. RDATA is the unipolar NRZ output of data recovered from
the line interface. The PLCKE bit in register CR3 selects the RCLK clock
edge when RDATA is stable and valid.
8
5
RCLK
DO
Receive Recovered Clock. The clock recovered from the line input signal
is output on this pin. Under LOS conditions, there is a smooth transition
from the RCLK signal (derived from the recovered data) to the MCLK
signal at the RCLK pin.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
10
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Table 3.
LXT363 Signal Descriptions (Continued)
Pin #
Symbol
PLCC
I/O1
Description
QFP
9
7
RD / DS
10
9
AD6
11
10
AD7
DI
DI/O
Read. On an Intel bus, driving RD Low commands a LXT363 register read
operation.
Data Strobe. On a Motorola bus, DS goes Low when data is being driven
on the address/data bus. Data is valid on the rising edge of DS.
Address/Data Bus 6 and 7. Used with AD0 - AD5 to form the address/
data bus. Conforms to Intel and Motorola multiplexed address/data bus
specifications.
Write. On an Intel bus, driving WR Low commands a LXT363 register write
operation.
12
13
WR / R/W
13
15
TTIP
16
19
TRING
14
16
TGND
-
Ground return for the transmit driver power supply TVCC.
15
18
TVCC
-
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from
VCC by more than ± 0.3 V.
17
20
CS
18
21
INT
19
24
RTIP
20
25
RRING
21
27
VCC
DI
AO
DI
Read/Write. On a Motorola bus, driving R/W High commands a LXT363
register read operation; driving it Low commands a write operation.
Transmit Tip and Ring. Differential driver output pair designed to drive a
50 - 200 Ω load. The transformer and line matching resistors should be
selected to give the desired pulse height and return loss performance. See
“Application Information” on page 30.
Chip Select. During a read or write operation, CS must remain Low. See
Figure 15 and Figure 16 for timing requirements.
In the case of a single processor controlling several chips, this line is used
to select a specific transceiver.
DO
Interrupt. INT goes Low to flag the host when LOS, AIS, NLOOP, QRSS,
DFMS or DFMO bits changes state, or when an elastic store overflow or
underflow occurs. To identify the specific interrupt, read the Performance
Status Register (PSR). To clear or mask an interrupt, write a one to the
appropriate bit in the Interrupt Clear Register (ICR). To re-enable the
interrupt, write a zero. INT is an open drain output that must be
connected to VCC through a pull-up resistor.
AI
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data
and clock recovered from RTIP/RRING are output on the RPOS/RNEG (or
RDATA in Unipolar mode), and RCLK pins.
-
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
Datasheet
11
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 3.
LXT363 Signal Descriptions (Continued)
Pin #
Symbol
I/O1
29
GND
-
23
31
AD0
24
32
AD1
25
35
AD2
26
36
AD3
27
37
AD4
28
38
AD5
-
8, 11,
12, 14,
17, 22,
23, 26,
28, 30,
33, 34,
40, 44
n/c
PLCC
QFP
22
DI/O
-
Description
Ground return for VCC.
Address/Data Bus 0 - 5. Used with AD6 and AD7 to form the address/
data bus. Conforms to Intel and Motorola multiplexed address/data bus
specifications.
Not Connected
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
12
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
2.0
Functional Description
The LXT363 is a fully integrated, PCM transceiver for 1.544 Mbps (T1) long- or short-haul
applications allowing full-duplex transmission of digital data over existing twisted-pair
installations. The device interfaces with two twisted-pair lines (one pair each for transmit and
receive) through standard pulse transformers and appropriate resistors.
The figure on the front page of this data sheet shows a block diagram of the LXT363. Control of
the chip is via the 8-bit parallel microprocessor port. Stand-alone operation is not supported.
The LXT363 provides a high-precision, crystal-less jitter attenuator (JA). The user may place the
JA in the transmit or receive path, or bypass it completely.
The transceiver meets or exceeds FCC, ANSI, and AT&T specifications for CSU and DSX-1
applications.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the Phase Lock
Loops (PLL). The transceiver uses a reference clock to calibrate the PLLs: the transmitter reference
is TCLK, and the receiver reference clock is MCLK. MCLK is mandatory for chip operation and
must be independent, free running, and jitter free.
2.1.1
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS, NLOOP, and QRSS
blocks. Writing a 1 to the bit CR2.RESET commands a reset which clears all registers to 0. Allow
32 ms for the device to settle.
2.2
Transmitter
2.2.1
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS
and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts unipolar data.
Input data may pass through either the Jitter Attenuator or B8ZS encoder or both. Setting
CR1.ENCENB = 1 enables B8ZS encoding.
TCLK supplies input synchronization. See the Figure 13 on page 36 for the transmit timing
requirements for TCLK and the Master Clock (MCLK).
2.2.2
Transmit Monitoring
The Performance Status Register (PSR) flags open circuits in bit PSR.DFMO. A transition of
DFMO can provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
Datasheet
13
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
Figure 3. 50% Duty Cycle Coding
Bit
Cell
1
2.2.4
0
1
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote loopback, Dual loopback, TAOS, or detection
of Network Loop Up code in the receive direction, temporarily disable the high impedance state.
2.2.5
Transmit Pulse Shape
As shown in Table 8 on page 26, the transmitted pulse shape is established by bits EC1 through
EC4 of Control Register #1 (CR1).
Shaped pulses meeting the various T1, DS1, and DSX-1 specifications are applied to the AMI line
driver for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1 pulses
for short-haul T1 applications (settings from 0 dB to +6.0 dB of cable), and DS1 pulses for
long-haul T1 applications (settings from 0 dB to -22.5 dB). Refer to the Test Specifications section
for pulse mask specifications.
2.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line. Recovered data is output at RPOS/
RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK. Refer to Table 25
on page 36 for receiver timing specifications.
2.3.1
Receive Equalizer
The receive equalizer processes the signal received at RTIP and RRING. The equalizer gain is up
to 36 dB. In long-haul applications, bits EC1 through EC4 in Control Register #1 determine the
maximum gain applied at the equalizer. When EC1 = 0, up to 36 dB of gain may be applied. When
EC1 = 1, 26 dB is the gain limit to provide an increased noise margin in shorter loop operations.
14
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
2.3.2
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS decoder (if selected) and to the receive monitor. The data and timing
recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411. See “Test Specifications” on page 33 for details.
Recovered data is routed to the Loss of Signal (LOS) Monitor and through the Alarm Indication
Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled or disabled in the
receive data path or the transmit path. Received data may be routed to either the B8ZS or HDB3
decoder or neither. Finally, the device may send the digital data to the framer as either unipolar or
bipolar data.
When transmitting unipolar data to the framer, the device reports reception of bipolar violations by
driving the BPV pin High.
2.3.3
Receiver Monitor Mode
The LXT363 receive equalizer can be used in Monitor mode applications. Monitor mode
applications require 20 dB to 30 dB resistive attenuation of the signal, plus a small amount of cable
attenuation (less than 6 dB). Setting bit CR3.EQZMON = 1 configures the device to operate in
Monitor mode. The device must be in T1 long-haul receiver mode (set bits CR1.EC4:1 = 0xx0 or
1001 or 1010) for Monitor mode.
2.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides jitter attenuation as shown in
the Test Specifications section. The JAL requires no special circuitry, such as an external quartz
crystal or high-frequency clock (higher than the line rate). Its timing reference is MCLK.
Bit CR1.JASEL0 enables or disables the JA circuit. With bit CR1.JASEL0 = 1, bit CR1.JASEL1
controls the JA circuit placement (see Table 7 on page 26). The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see Table 10 on page 27.)
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average
delay of 16 bits (or 32 bits, with the 64-bit ES option selected) in the associated data path. When
the Jitter Attenuator is in the receive path, the output RCLK transitions smoothly to MCLK in the
event of a LOS condition.
The Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store
overflow or underflow, respectively. Note that these are sticky bits that once set to 1, remain set
until the host reads the register. The ES can also provide a maskable interrupt on either overflow or
underflow.
Datasheet
15
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.5
Diagnostic Mode Operation
The LXT363 offers multiple diagnostic modes as listed in Table 4. The diagnostic modes are
selected by setting the appropriate register bits as described in the following paragraphs.
2.5.1
Loopback Modes
2.5.1.1
Local Loopback
See Figure 4 and Figure 5. Local loopback is selected by setting CR2.ELLOOP to 1. LLOOP
inhibits the receiver circuits. The transmit clock and data inputs (TCLK and TPOS/TNEG or
TDATA) loop back through the jitter attenuator (if enabled) and show up at RCLK and RPOS/
RNEG or RDATA. Note that during LLOOP, the JASEL input is strictly an Enable/Disable control;
it does not affect the placement of the JAL. If JA is enabled, it is active in the loopback circuit. If
JA is bypassed, it is not active in the loopback circuit.
The transmitter circuits are unaffected by LLOOP. LXT363 transmits the TPOS/TNEG or TDATA
inputs (or a stream of 1s if TAOS is asserted) normally. When used in this mode, the transceiver
can function as a stand-alone jitter attenuator.
Table 4.
Diagnostic Mode Summary
Diagnostic Mode
Interrupt
Maskable
Loopback Modes
Local Loopback (LLOOP)
No
Analog Loopback (ALOOP)
No
Remote Loopback (RLOOP)
No
In-band Network Loopback (NLOOP)
Yes
Dual Loopback (DLOOP)
No
Internal Data Pattern Generation and Detection
Transmit All Ones (TAOS)
No
Quasi-Random Signal Source (QRSS)
Yes
In-band Loop Up/Down Code Generator
No
Error Insertion and Detection
Bipolar Violation Insertion (INSBPV)
No
Logic Error Insertion (INSLER)
No
Bipolar Violation Detection (BPV)
No
Alarm Condition Monitoring
16
Receive Loss of Signal (LOS) Monitoring
Yes
Receive Alarm Indication Signal (AIS)
Monitoring
Yes
Transmit Driver Failure Monitoring Open
(DFMO)
Yes
Elastic Store Overflow and Underflow
Monitoring
Yes
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Table 4.
Diagnostic Mode Summary
Interrupt
Maskable
Diagnostic Mode
Other Diagnostic Reports
Receive Line Attenuation Indicator (LATN)
No
Built-In Self Test (BIST)
Yes
Figure 4. TAOS with LLOOP
Figure 5. Local Loopback
RCLK
RPOS
RNEG
DECODER*
TCLK
TPOS
TNEG
ENCODER*
Local Loopback with JA in Receive Path
Timing &
Control
TTIP
TRING
* If Enabled
JA*
Timing
Recovery
RTIP
RRING
RCLK
RPOS
RNEG
Datasheet
DECODER*
TCLK
TPOS
TNEG
ENCODER*
Local Loopback with JA in Transmit Path
JA*
Timing &
Control
TTIP
TRING
* If Enabled
Timing
Recovery
RTIP
RRING
17
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.5.1.2
Analog Loopback
See Figure 6. Analog loopback (ALOOP) exercises the maximum number of functional blocks.
ALOOP operation disconnects the RTIP/RRING inputs from the line and routes the transmit
outputs back into the receive inputs. This tests the encoders/decoders, jitter attenuator, transmitter,
receiver and timing recovery sections. Writing a 1 to bit CR2.EALOOP enables the ALOOP mode.
Note that ALOOP will override all other loopback modes.
Figure 6. Analog Loopback
RCLK
RPOS
RNEG
DECODER*
TCLK
TPOS
TNEG
ENCODER*
Analog Loopback with JA in Receive Path
TTIP
TRING
* If Enabled
JA*
Timing
Recovery
RTIP
RRING
RCLK
RPOS
RNEG
2.5.1.3
DECODER*
TCLK
TPOS
TNEG
ENCODER*
Analog Loopback with JA in Transmit Path
TTIP
JA*
TRING
* If Enabled
Timing
Recovery
RTIP
RRING
Remote Loopback
See Figure 7. In Remote loopback (RLOOP) mode, the device ignores the transmit data and clock
inputs (TCLK and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The
RPOS/RNEG or RDATA outputs loop back through the transmit circuits to TTIP and TRING at the
RCLK frequency. The RLOOP command does not affect the receiver circuits which continue to
output the RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line.
RLOOP is selected by writing a 1 to bit CR2.ERLOOP.
18
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Figure 7. Remote Loopback
Remote Loopback with JA in Receive Path
TCLK
TPOS
TNEG
Timing &
Control
* If Enabled
RCLK
RPOS
RNEG
JA*
Timing
Recovery
TTIP
TRING
RTIP
RRING
Remote Loopback with JA in Transmit Path
TCLK
TPOS
TNEG
JA*
* If Enabled
Timing
Recovery
RCLK
RPOS
RNEG
2.5.1.4
Timing &
Control
TTIP
TRING
RTIP
RRING
Network Loopback
Network loopback (NLOOP) can be initiated only when the Network loopback detect function is
enabled. Writing a 1 to CR2.ENLOOP enables NLOOP detection.
With NLOOP detection enabled, the receiver looks for the NLOOP data patterns (00001 = enable,
001 = disable) in the input data stream. When the receiver detects an NLOOP enable data pattern
repeated for a minimum of five seconds, the device enables RLOOP. The device responds to both
framed and unframed NLOOP patterns. Once NLOOP detection is enabled at the chip and
activated by the appropriate data pattern, it is identical to Remote loopback (RLOOP). NLOOP is
disabled by receiving the 001 pattern for five seconds, or by activating RLOOP or ALOOP, or by
disabling NLOOP detection. The device goes into Dual loopback mode (DLOOP) in the case
where it detects both the NLOOP and LLOOP functions.
2.5.1.5
Dual Loopback
See Figure 8. To select Dual loopback (DLOOP) set bits CR2.ERLOOP and CR2.ELLOOP to 1. In
DLOOP mode, the transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back
through the Jitter Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data
and clock recovered from the twisted-pair line loop back through the transmit circuits to TTIP and
TRING without jitter attenuation.
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
Datasheet
DECODER* ENCODER*
Figure 8. Dual Loopback
Timing &
Control
JA*
TTIP
TRING
* If Enabled
Timing
Recovery
RTIP
RRING
19
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.5.2
Internal Pattern Generation and Detection
2.5.2.1
Transmit All Ones
See Figure 9. In Transmit All Ones (TAOS) mode the transceiver ignores the TPOS and TNEG
inputs and transmits a continuous stream of 1s at the TCLK frequency. (With no TCLK, the TAOS
output clock is MCLK.) This can be used as the Alarm Indication Signal (AIS–also called the Blue
Alarm). TAOS is commanded by writing a 1 to bit CR2.ETAOS. Both TAOS and Local loopback
can occur simultaneously as shown in Figure 4, however, Remote loopback inhibits TAOS. When
both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to RCLK and RPOS/RNEG
through the jitter attenuator (if enabled), and an all ones pattern goes to TTIP/TRING.
Figure 9. TAOS Data Path
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
2.5.2.2
DECODER* ENCODER*
TAOS
Timing &
Control
TTIP
TRING
* If Enabled
Timing
Recovery
RTIP
RRING
Quasi-Random Signal Source (QRSS)
See Figure 10. The Quasi-Random Signal Source (QRSS) is a 220-1 pseudo-random bit sequence
(PRBS) with no more than 14 consecutive zeros. Setting bits CR2.EPAT0 = 0 and CR2.EPAT1 = 1
enables this function.
The QRSS pattern is normally locked to TCLK; but if there is no TCLK, MCLK is the clock
source. Bellcore Pub 62411 defines the T1 QRSS transmit format.
Figure 10. QRSS Mode
INT*
20
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on INSLER. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is “jammed”. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
Furthermore, a bipolar violation in the QRSS pattern is possible by causing a Low-to-High
transition on the INSBPV pin, regardless of whether the device is in Bipolar or Unipolar mode.
Choosing QRSS mode also enables the QRSS Pattern Detection in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. The PSR.QRSS bit
provides an indication of QRSS pattern synchronization. This bit goes Low when no QRSS pattern
detected (i.e., when there are more than four errors in 128 bits). The TQRSS bit in the Transition
Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear
command.
The LXT363 can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0.
2.5.2.3
In-Band Network Loop Up or Down Code Generator
The LXT363 can transmit in-band Network Loop Up or Loop Down code. The Loop Up code is
00001; Loop Down code is 001. A Loop Up code transmission occurs when Control Register #2
bits EPAT0 = 1 and EPAT1 = 0. A Loop Down code transmission requires that both EPAT0 and
EPAT1 = 1.
With this mode enabled, logic errors and bipolar violations can be inserted into the transmit data
stream. Inserting a logic error requires a Low-to-High transition in INSLER (pin 3). If no logic or
bit errors are to be inserted, INSLER must remain Low. Inserting a bipolar violation requires a
Low-to-High transition on the INSBPV pin, regardless of unipolar or bipolar operation.
2.5.3
Error Insertion and Detection
2.5.3.1
Bipolar Violation Insertion (INSBPV)
Bipolar violation insertion is available In Unipolar mode. Choosing Unipolar mode configures the
INSBPV pin. To insert bipolar violation (BPV), a Low-to-High transition on the INSBPV is
required. Sampling occurs on the falling edge of TCLK. When INSBPV goes High a BPV is
inserted on the next available mark except in the four following situations:
• Zero suppression (B8ZS) is not violated
• If LLOOP and TAOS are both active, the BPV is looped back to RNEG/BPV indicator and the
line driver transmits all ones with no violation
• BPV insertion is disabled with RLOOP active
• BPV insertion is disabled when NLOOP is active
With the LXT363 configured to transmit internally generated data patterns (QRSS or NLOOP), a
BPV can be inserted into the transmit pattern regardless of whether the device is in the Unipolar or
Bipolar mode of operation.
Datasheet
21
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.5.3.2
Logic Error Insertion (INSLER)
When configured to transmit internally generated data patterns (QRSS or NLOOP Up/Down
codes), a logic error is inserted into the transmit data pattern when the INSLER pin transitions
Low-to-High. Note that in QRSS mode, there is no logic error insertion on a jammed bit (i.e., a bit
forced to one to suppress transmission of more than 14 consecutive zeros). The transceiver routes
data patterns the same way it routes data applied to TPOS/TNEG. Therefore, the inserted logic
error will follow the data flow path of the active loopback mode.
2.5.3.3
Bipolar Violation Detection (BPV)
When the internal encoders/decoders are disabled or when configured in Unipolar mode, bipolar
violations are reported at the BPV pin. BPV goes High for a full clock cycle to indicate receipt of a
BPV. When the encoders/decoders are enabled, the LXT363 does not report bipolar violations due
to the line coding scheme.
2.5.4
Alarm Condition Monitoring
2.5.4.1
Loss of Signal
The receiver LOS monitor loads a digital counter at the RCLK frequency. The count increments
with each received 0 and the counter resets to 0 on receipt of a 1. When the count reaches “n” 0s,
bit PSR.LOS is set to ‘1’, and the MCLK replaces the recovered clock at the RCLK output in a
smooth transition. “n” can be set to either 175 or 2048 with bit CR4.LOS2048.
When the received signal has 12.5% 1s (16 marks in a sliding 128-bit period, with fewer than 100
consecutive 0s), bit PSR.LOS = 0 and the recovered clock replaces MCLK at the RCLK output in
another smooth transition.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). Bit PSR.LOS = 1 indicates a LOS condition, and can generate an interrupt if enabled.
2.5.4.2
Alarm Indication Signal Detection
The receiver detects an AIS pattern when it receives fewer than three 0s in any string of 2048 bits.
The device clears the AIS condition when it receives three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
2.5.4.3
Driver Failure Open Mode
The DFM Open (DFMO) bit is available in the Performance Status Register to indicate an open
condition on the lines. DFMO can generate an INT to the host controller. The Transition Status
Register bit TDFMO indicates a transition in the status of the bit. Writing a 1 to ICR.CDFMO will
clear or mask the interrupt.
22
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
2.5.4.4
Elastic Store Overflow/Underflow
When the bit count in the Elastic Store (ES) is within two bits of overflowing or underflowing the
ES adjusts the output clock by 1/8 of a bit period. The ES provides an indication of overflow and
underflow via bits TRS.ESOVR and TSR.ESUNF. These are sticky bits and will stay set to 1 until
the host controller reads the register. These interrupts can be cleared or masked by writing a 1 to the
bits ICR.CESO and ICR.CESU, respectively.
2.5.5
Other Diagnostic Reports
2.5.5.1
Receive Line Attenuation Indication
The Equalizer Status Register (ESR) provides an approximation of the line attenuation encountered
by the device. The four most significant bits of the register (ESR.LATN7:4) indicate line
attenuation in approximately 2.9 dB steps of the receive equalizer. For instance, if ESR.LATN7:4 is
10 (decimal), then the receiver is seeing a signal attenuated by approximately 29 dB (2.9 dB x 10)
of cable loss.
2.5.5.2
Built-In Self Test
LXT363 provides a Built-In Self Test (BIST) capability. The BIST exercises the internal circuits by
providing an internal QRSS pattern, running it through the encoders and the transmit drivers then
looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern
detection circuitry. If all the blocks in this data path function correctly, the receive pattern detector
locks onto the pattern. It then pulls INT Low and sets the following bits:
• TSR.TQRSS = 1
• PSR.QRSS = 1
• PSR.BIST = 1
The most reliable test will result when a separate TCLK and MCLK are applied and the Line
Build-Out (LBO) is set to -22.5 dB (CR1.EC4:1 = 011x).
2.6
Parallel Microprocessor Interface
The LXT363 multiplexed address/data bus and timing/control signals are compatible with both the
Intel and Motorola microprocessors. See Figure 15 and Figure 16 for the I/O timing diagram for
each bus. The LXT363 detects and distinguishes between Intel and Motorola timing and then
automatically selects the appropriate bus timing. The maximum recommended processor speed for
an Intel device is 20 MHz; for a Motorola device, 16.78 MHz. See “Test Specifications” on
page 33 for microprocessor interface timing details.
The LXT363 contains five read/write and three read-only registers for control and status purposes.
Table 6 on page 25 is a summary of the registers. Table 7 through Table 15 identify and explain the
function of the register bits.
Datasheet
23
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.6.1
Interrupt Handling
The LXT363 provides a latched interrupt output pin (INT). When enabled, a change in any of the
Performance Status Register bits will generate an interrupt. An interrupt can also be generated
when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an interrupt
occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has internal
pull-down only. Therefore, each device that shares the INT line requires an external pull-up
resistor.
The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes
a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in
any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
24
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
3.0
Register Definitions
The LXT363 contains five read/write and three read-only registers. Table 5 lists the LXT363
register addresses. Note that only bits A6 through A1 of the address byte are valid; the address
decoder ignores bits A7 and A0. Table 6 identifies the name of each register bit. Table 7 through
Table 15 describe the function of the bits in each register.
Note that upon power-up or reset, all registers are cleared to 0.
Table 5.
Register Addresses
Register
Address1
A7 - A0
Name
Abbr
Control #1
CR1
x010000x
Control #2
CR2
x010001x
Control #3
CR3
x010010x
Interrupt Clear
ICR
x010011x
Transition Status
TSR
x010100x
Performance Status
PSR
x010101x
Equalizer Status
ESR
x010110x
Control #4
CR4
x010111x
1. x = don’t care
Table 6.
Register and Bit Summary
Register
Name
Bit
Type
7
6
5
4
3
2
1
0
EC3
EC2
EC1
EALOOP
ELLOOP
ERLOOP
Control #1
CR1
R/W
JASEL1
JASEL0
ENCENB
UNIENB
EC4
Control #2
CR2
R/W
RESET
EPAT1
EPAT0
ETAOS
ENLOOP
1
Control #3
CR3
R/W
JA6HZ
PCLKE
SBIST
EQZMON
reserved
ES64
ESCEN
ESJAM
Interrupt Clear
ICR
R/W
CESU
CESO
CDFMO
reserved2
CQRSS
CAIS
CNLOOP
CLOS
Transition
Status
TSR
R
ESUNF
ESOVR
TDFMO
reserved1
TQRSS
TAIS
TNLOOP
TLOS
Performance
Status
PSR
R
reserved1
BIST
DFMO
reserved1
QRSS
AIS
NLOOP
LOS
Equalizer
Status
ESR
R
LATN7
LATN6
LATN5
LATN4
reserved1
reserved1
reserved1
reserved1
Control #4
CR4
R/W
reserved1
reserved1
reserved1
reserved1
reserved1
LOS2048
reserved1
reserved1
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
Datasheet
25
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 7.
Control Register #1 Read/Write, Address (A7-A0) = x010000x
Jitter Attenuator
Bit
Name
Function
0
EC1
1
EC2
2
EC3
3
EC4
4
UNIENB
5
ENCENB
6
JASEL0
7
JASEL1
Table 8.
JASEL0
JASEL1
Position
1
0
Transmit
1
1
Receive
0
X
Disabled
Sets T1 mode and equalizer
(see Table 8 below for control codes).
1 = Enable Unipolar I/O mode and allow insertion/detection of BPVs.
0 = Enable Bipolar I/O mode
1 = Enable B8ZS encoders/decoders and force Unipolar I/O mode.
0 = Disable B8ZS encoders/decoders
Select jitter attenuation circuitry position in data path or disables the JA.
See right hand section of table for codes.
Ñ
Equalizer Control Bit Settings
Control Register #1
Function
Pulse
Cable
Gain
Coding2
0
T1 Long Haul
0.0 dB pulse
100 Ω TP
36 dB
B8ZS
1
0
T1 Long Haul
-7.5 dB pulse
100 Ω TP
36 dB
B8ZS
0
0
T1 Long Haul
-15.0 dB pulse
100 Ω TP
36 dB
B8ZS
EC4
EC3
EC2
EC11
0
0
0
0
0
0
1
0
1
1
0
T1 Long Haul
-22.5 dB pulse
100 Ω TP
36 dB
B8ZS
0
0
0
1
T1 Long Haul
0.0 dB pulse
100 Ω TP
26 dB
B8ZS
0
0
1
1
T1 Long Haul
-7.5 dB pulse
100 Ω TP
26 dB
B8ZS
0
1
0
1
T1 Long Haul
-15.0 dB pulse
100 Ω TP
26 dB
B8ZS
0
1
1
1
T1 Long Haul
-22.5 dB pulse
100 Ω TP
26 dB
B8ZS
1
0
0
1
D4 Short Haul
6 V pulse
100 Ω TP
12 dB
B8ZS
1
0
1
1
T1 Short Haul
0-133 ft / 0.6 dB
100 Ω TP
12 dB
B8ZS
1
1
0
0
T1 Short Haul
133-266 ft / 1.2 dB
100 Ω TP
12 dB
B8ZS
1
1
0
1
T1 Short Haul
266-399 ft / 1.8 dB
100 Ω TP
12 dB
B8ZS
1
1
1
0
T1 Short Haul
399-533 ft / 2.4 dB
100 Ω TP
12 dB
B8ZS
1
1
1
1
T1 Short Haul
533-655 ft / 3.0 dB
100 Ω TP
12 dB
B8ZS
1. EC1 sets the receive equalizer gain (EGL) during T1 long-haul operation.
2. When enabled.
26
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Table 9.
Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
0
ERLOOP1
1
ELLOOP1
2
EALOOP
3
ENLOOP
4
ETAOS
5
EPAT0
6
EPAT1
7
RESET
Function
EPAT0
EPAT1
Selected
0
0
Transmit TPOS/TNEG
0
1
Detect and transmit QRSS
1
0
In-band Loop Up Code
00001
1
1
In-band Loop Down Code
001
1 = Enable Remote loopback mode
0 = Disable Remote loopback mode
1 = Enable Local loopback mode
0 = Disable Local loopback mode
1 = Enable Analog loopback mode
0 = Disable Analog loopback mode
1 = Enable Network loopback detection
0 = Disable Network loopback detection
1 = Enable Transmit All Ones
0 = Disable Transmit All Ones
Selects internal data pattern transmission. See right
hand section of table for codes.
Ñ
1 = Reset device states and clear all registers.
0 = Reset complete.
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Table 10. Control Register #3 Read/Write, Address (A7-A0) = x010010x
Bit
Name
0
ESJAM
1
ESCEN
2
ES64
3
-
4
EQZMON
5
SBIST
6
PLCKE
7
JA6HZ
Datasheet
Description
1 = Disable jamming of Elastic Store read out clock (1/8 bit-time adjustment for over/underflow).
0 = Enable jamming of Elastic Store read out clock
1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically).
0 = Centering completed
1 = Set elastic store depth to 64 bits.
0 = Set elastic store depth to 32 bits.
reserved–set to 0 for normal operation.
1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor).
0 = Configure receiver equalizer for normal mode application
1 = Start Built-In Self Test.
0 = Built-In Self Test complete.
0 = RPOS/RNEG valid on the rising edge of RCLK.
1 = RPOS/RNEG valid on the falling edge of RCLK.
1 = Set bandwidth of jitter attenuation loop to 6 Hz.
0 = Set bandwidth of jitter attenuation loop to 3 Hz.
27
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
0
CLOS
1
CNLOOP
2
CAIS
3
CQRSS
4
-
5
CDFMO
6
CESO
7
CESU
Function1
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
1 = Clear/Mask Network loopback interrupt.
0 = Enable Network loopback interrupt.
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
reserved–set to 1 for normal operation.
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit
Name
0
TLOS
1
TNLOOP
2
TAIS
3
TQRSS
4
-
5
TDFMO
6
ESOVR
7
ESUNF
Function
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
1 = NLOOP has changed since last clear NLOOP interrupt occurred.
0 = No change in status.
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
1 = QRSS has changed since last clear QRSS interrupt occurred1.
0 = No change in status.
reserved-ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
1 = ES overflow status sticky bit2.
0 = No change in status.
1 = ES underflow status sticky bit2.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
28
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
0
LOS
1
NLOOP
2
AIS
3
QRSS
4
-
5
DFMO
6
BIST
7
-
Function
1 = Loss of Signal occurred.
0 = Loss of Signal did not occur.
1 = Network loopback active.
0 = Network loopback not active.
1 = Alarm Indicator Signal detected.
0 = Alarm Indicator Signal not detected.
1 = Quasi-Random Signal Source pattern detected.
0 = Quasi-Random Signal Source pattern not detected.
reserved–ignore.
1 = Driver Failure Monitor Open detected.
0 = Driver Failure Monitor Open not detected.
1 = Built-In Self Test passed.
0 = Built-In Self Test did not pass (or was not run).
reserved–ignore.
Table 14. Equalizer Status Register Read Only, Address (A7-A0) = x010110x
Bit
Name
0
-
Function
reserved–ignore (Least Significant Bit)
1
-
reserved–ignore
2
-
reserved–ignore
3
-
reserved–ignore
4
LATN4
5
LATN5
6
LATN6
7
LATN7
Receive Line Attenuation Indicators. Convert this binary output to a decimal number and multiply
by 2.9 dB to determine the approximate cable attenuation as seen by the receiver.
For example, if LATN7-4 = 1010 BIN (= 10 DEC), then the receiver is seeing a signal attenuated by
approximately 29 dB (2.9 dB x 10) of cable. This approximation assumes that a 3 V pulse was
transmitted.
Table 15. Control Register #4 Read/Write, Address (A7-A0) = x010111x
Bit
Name
0
-
reserved–set to 0 for normal operation; ignore when reading.
1
-
reserved–set to 0 for normal operation; ignore when reading.
2
LOS2048
3
-
reserved–set to 0 for normal operation; ignore when reading.
4
-
reserved–set to 0 for normal operation; ignore when reading.
5
-
reserved–set to 0 for normal operation; ignore when reading.
6
-
reserved–set to 0 for normal operation; ignore when reading.
7
-
reserved–set to 0 for normal operation; ignore when reading.
Datasheet
Function
1 = Set LOS detection threshold to 2048 consecutive zeros.
0 = Set LOS detection threshold to 175 consecutive zeros.
29
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
4.0
Application Information
4.1
Transmit Return Loss
Table 16 shows the transmit return loss values for T1 applications. Table 22 on page 34 specifies
the receive return loss values.
4.2
Transformer Data
Specifications for transformers are listed in Table 17. A list of transformers recommended for use
with the LXT363 are specified in Table 18.
4.3
Application Circuits
Figure 11 shows a typical LXT363 applications for Hardware and Host modes of operation.
Table 16. Transmit Return Loss
Xfrmr/Rt
RL
(Ω )
1:2 / 9.1 Ω
100
1:1.151 / 0 Ω
100
1:22 / 0 Ω
100
EC4:1
Refer to
Table 8
1001
(D4 Mode)
CL
(pF)
Return
Loss (dB)
0
16
470
17
0
2
470
2
0
1
470
1
1. A 1:1.15 transmit transformer keeps the total transceiver
power dissipation at a low level, a 0.47 µF DC blocking
capacitor must be placed on TTIP or TRING.
2. A 0.47 µF DC blocking capacitor must be placed on TTIP or
TRING.
Table 17. Transformer Specifications for LXT363
Tx/Rx
Frequency
MHz
Turns
Ratio
Primary
Inductance
µH (minimum)
Leakage
Inductance
µH
(max)
Interwinding
Capacitance
pF
(max)
DCR
Ω
(maximum)
Dielectric
Breakdown
V
(minimum)
1.544
1:1.15
600
0.80
60
0.90 pri, 1.70 sec
1500 VRMS1
1.544
1:2
600
0.80
60
0.70 pri, 1.20 sec
1500 VRMS1
1.544
1:1
600
1.10
60
1.10 pri, 1.10 sec
1500 VRMS1
Tx
Rx
1. Some applications require transformers with a center tap (Long-Haul applications with DC current in the T1 loop).
30
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Table 18. Recommended Transformers for LXT363
Tx/Rx
Turns Ratio
Part Number
Manufacturer
PE-65388
Pulse Engineering
1:1.15
PE-65770
16Z5952
Vitec
PE-65351
Pulse Engineering
PE-65771
0553-5006-IC
Bell-Fuse
66Z-1308
Fil-Mag
671-5832
Midcom
Tx
1:2
67127370
Schott Corp
67130850
TD61-1205D
HALO (combination Tx/Rx set)
TG26-1205NI
HALO (surface mount dual transformer 1CT:2CT & 1CT:2CT)
TG48-1205NI
16Z5946
HALO (surface mount dual transformer 1CT:2CT & 1:1)
Vitec
FE 8006-155
Fil-Mag
671-5792
Midcom
PE-64936
Pulse Engineering
PE-65778
Rx
1:1
67130840
Schott Corp
67109510
TD61-1205D
HALO (combination Tx/Rx set)
16Z5936
Vitec
16Z5934
Figure 11 shows a typical LXT363 application. See Table 16 through Table 18 to select the
transformers (T1 and T2), resistors (Rt) and capacitor (CL).
Note that if the application includes surge protection, such as a varistor or sidactor on the TTIP/
TRING lines, it may be necessary to reduce the value of the capacitor CL or eliminate it
completely. Excessive capacitance at CL will distort the transmitted signals.
Datasheet
31
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 11. Typical LXT363 Application
VCC
22 kΩ
1.544 MHz
MCLK
INT
ALE/AS
T1
Framer
TCLK
TCLK
TPOS
TPOS
TNEG
TNEG
RCLK
RCLK
RPOS
RPOS
RNEG
RNEG
µP
(Intel or
Motorola)
RD/DS
WR/R/W
CS
AD0-7
LXT363
0.47 µF2
T11
TTIP
Rt1
CL1
(0 TO 470 PF
TVCC
VCC
0.1 µF
68 µF
Rt1
TRING
RTIP
TGND
100 Ω
GND
RRING
1:1
NOTES:
1. See Table 16 through Table 18 for CL, Rt, and transformer selection.
2. Optional for power savings.
32
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
5.0
Test Specifications
Note:
Table 19 through Table 27 and Figure 12 through Figure 18 represent the performance
specifications of the LXT363 and are guaranteed by test except, where noted, by design. The
minimum and maximum values listed in Table 21 through Table 27 are guaranteed over the
recommended operating conditions specified in Table 20.
Table 19. Absolute Maximum Ratings
Parameter
DC supply (reference to GND)
Sym
Min
Max
Unit
VCC, TVCC
–
6.0
V
Input voltage, any pin
1
VIN
GND - 0.3 V
VCC + 0.3 V
V
Input current, any pin
2
IIN
- 10
10
mA
TSTG
-65
150
°C
Storage Temperature
Caution: Exceeding these values may cause permanent damage.
Caution: Functional operation under these conditions is not implied.
Caution: Exposure to maximum rating conditions for extended periods may affect device reliability.
1. TVCC and VCC must not differ by more than 0.3 V during operation. TGND and GND must not differ by more than 0.3 V
during operation.
2. Transient currents of up to 100 mA will not cause SCR latch-up. TTIP, TRING, TVCC, and TGND can withstand continuous
currents of up to 100 mA.
Table 20. Recommended Operating Conditions
Sym
Min
Typ1
Max
Unit
DC Supply 2
VCC, TVCC
4.75
5.0
5.25
V
Ambient
Operating
Temperature
TA
-40
–
85
°C
PD
–
450
540
mW
100% mark density
PD
–
300
360
mW
50% mark density
PD
–
350
425
mW
100% mark density
PD
–
250
300
mW
50% mark density
PD
–
400
485
mW
100% mark density
PD
–
275
330
mW
50% mark density
Parameter
Test Conditions
Short Haul
Total
Power
Dissipation3
Long Haul
D4
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. TVCC and VCC must not differ by more than 0.3 V.
3. Power dissipation while driving 100 Ω load over operating range. Includes power dissipation on device and load. Digital levels
are within 10% of the supply rails and digital outputs driving a 50 pF capacity load, RL=9.1, T1=1:2.
Datasheet
33
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 21. Digital Characteristics
Parameter
Sym
Min
High level input voltage (pins 1-5, 9-12, 17, 23-28)2
VIH
2.0
–
–
V
Low level input voltage (pins 1-5, 9-12, 17, 23-28)2
VIL
–
–
0.8
V
High level output voltage1 (pins 6-8, 10, 11,23, 28)2
VOH
2.4
–
–
V
IOUT = 400 µA
Low level output voltage (pins 6-8, 10, 11,23, 28)
VOL
–
–
0.4
V
IOUT = 1.6 mA
Input leakage current
ILL
–
–
±50
µA
1
2
Typ
Max
Unit
Test Conditions
1. Output drivers will output CMOS logic levels into CMOS loads.
2. Referenced pin numbers are for the PLCC package. Refer to Figure 2 on page 8 for the corresponding QFP pins.
Table 22. Analog Characteristics
Parameter
Min
Typ1
Max
Unit
Recommended output load on TTIP/TRING
50
–
200
Ω
AMI Output Pulse Amplitudes
2.4
3.0
3.6
V
DSX-1, DS1
10 Hz - 8 kHz
Jitter added by the transmitter2
3
–
–
0.02
UI
–
–
0.025
UI
3
10 Hz - 40 kHz
–
–
0.025
UI
Broad Band
–
–
0.05
UI
0
–
26
dB
0
–
36
dB
0
–
13.6
dB
160
175
190
–
0.4
–
–
UI
138
–
–
UI
0 dB line
AT&T Pub 62411
–
3
–
Hz
selectable in data port
8 kHz - 40 kHz
(Long-Haul)
Mode 2 (EC1 = 0)
(Long-Haul)
Mode 3 (EC4 = 1)
(Short-Haul)
Allowable consecutive zeros before LOS
10 kHz - 100 kHz
Input jitter tolerance
1 Hz
3
Jitter attenuation curve corner frequency 4
1.
2.
3.
4.
34
RL = 100 Ω
3
Mode 1 (EC1 = 1)
Receiver sensitivity
@ 772 kHz
Test Conditions
See Table 8 on page 26
for Gain Setting
Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
Guaranteed by characterization; not subject to production testing.
Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Figure 12. 1.544 MHz T1 Pulse (DS1 and DSX-1) (See Table 23)
1.5
1.5
Normalized Amplitude
1.0
1.0
0.5
0.5
0.5
-0.5
0.0
1.0
Normalized Amplitude
0.5
-0.5
1.5
0.0
Time
1.0
1.5
Time
(in Unit Intervals)
(in Unit Intervals)
-0.5
-0.5
Table 23. 1.544 MHz T1 Pulse Mask Corner Point Specifications
DS1 Template (per ANSI T1. 403-1995)
Minimum Curve
DSX-1 Template (per ANSI T1. 102-1993)
Maximum Curve
Minimum Curve
Maximum Curve
Time (UI)
Amplitude
Time (UI)
Amplitude
Time (UI)
Amplitude
Time (UI)
Amplitude
-0.77
-0.05
-0.77
0.05
-0.77
-0.05
-0.77
0.05
-0.23
-0.05
-0.39
0.05
-0.23
-0.05
-0.39
0.05
-0.23
0.50
-0.27
0.80
-0.23
0.50
-0.27
0.80
-0.15
0.90
-0.27
1.20
-0.15
0.95
-0.27
1.15
0.0
0.95
-0.12
1.20
0.0
0.95
-0.12
1.15
0.15
0.90
0.0
1.05
0.15
0.90
0.0
1.05
0.23
0.50
0.27
1.05
0.23
0.50
0.27
1.05
0.23
-0.45
0.34
-0.05
0.23
-0.45
0.35
-0.07
0.46
-0.45
0.77
0.05
0.46
-0.45
0.93
0.05
0.61
-0.26
1.16
0.05
0.66
-0.20
1.16
0.05
0.93
-0.05
0.93
-0.05
1.16
-0.05
1.16
-0.05
Table 24. Master and Transmit Clock Timing Characteristics (See Figure 13)
Sym
Min
Typ1
Max
Unit
Notes
Master clock frequency
MCLK
–
1.544
–
MHz
must be supplied
Master clock tolerance
MCLKt
–
±50
–
ppm
Master clock duty cycle
MCLKd
40
–
60
%
Parameter
Transmit clock frequency
TCLK
–
1.544
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
35
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 24. Master and Transmit Clock Timing Characteristics (See Figure 13)
Parameter
Transmit clock duty cycle
Sym
Min
Typ1
Max
Unit
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
tSUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
tHT
50
–
–
ns
Notes
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 13. Transmit Clock Timing
Table 25. Receive Timing Characteristics (See Figure 14)
Parameter
Receive clock duty cycle
2, 3
2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
40
50
60
%
tPW
–
648
–
ns
tPWH
–
324
–
ns
tPWL
260
324
388
ns
RPOS/RNEG to RCLK rising time
tSUR
–
274
–
ns
RCLK rising to RPOS/RNEG hold time
tHR
–
274
–
ns
Receive clock pulse width
Receive clock pulse width high
Receive clock pulse width low
1,3
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
36
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Figure 14. Receive Clock Timing
Table 26. LXT363 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 15)
Parameter
Sym
Min
Max
Unit
ALE pulse width
TLHLL
35
–
ns
Address valid to ALE falling edge
TAVLL
10
–
ns
ALE falling edge to address hold time
TLLAX
10
–
ns
ALE falling edge to RD falling edge
TLLRL
10
–
ns
ALE falling edge to WR falling edge
TLLWL
10
–
ns
CS falling edge to RD falling edge
TCLRL
10
–
ns
CS falling edge to WR falling edge
TCLWL
10
–
ns
RD low pulse width
TRLRH
95
–
ns
RD falling edge to data valid
TRLDV
10
55
ns
Data hold time after RD rising edge
TRHDX
5
35
ns
RD rising edge to ALE rising edge
TRHLH
15
–
ns
RD rising edge to address valid
TRHAV
35
–
ns
CS low hold time after RD rising edge
TRHCH
0
–
ns
WR low pulse width
TWLWH
95
–
ns
Data setup time before WR rising edge
TDVWH
40
–
ns
Data hold time after WR rising edge
TWHDX
30
–
ns
WR rising edge to ALE rising edge
TWHLH
15
–
ns
CS low hold time after WR rising edge
TWHCH
15
–
ns
Datasheet
Test Conditions
37
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 15. LXT363 I/O Timing Diagram for Intel Address/Data Bus
TCLWL
TCLRL
CS
TWHCH
TRHCH
TLLRL
TLLWL
TLHLL
TLLAX
TRHLH
TWHLH
ALE
TAVLL
TRLRH
RD
TRHAV
TRLDV
AD0-7_R
TRHDX
TWLWH
TDVWH
WR
TWHDX
AD0-7_W
Table 27. LXT363 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 16)
Parameter
Symbol
Min
Max
Units
DS rising edge to AS rising edge
TDSHASH
15
–
ns
AS high pulse width
TASHASL
35
–
ns
Address valid setup time at AS falling edge
TAVASL
10
–
ns
AS falling edge to Address valid hold time
Taslax
10
–
ns
TASLDSL
20
–
ns
CS falling edge to DS falling edge
TCSLDSL
10
–
ns
DS low pulse width
TDSLDSH
95
–
ns
DS falling edge to data valid
TDSLDV
10
55
ns
Data hold time after DS rising edge
TDSHDX
5
35
ns
R/W falling edge to DS falling edge
TRWLDSL
10
–
ns
Data setup time before DS rising edge
TDVDSH
40
–
ns
Data hold time after DS rising edge
Tdxdsh
30
–
ns
R/W low hold time after DS rising edge
TDSHRWH
15
–
ns
CS low hold time after DS rising edge
TDSHCSH
15
–
ns
AS falling edge to DS falling edge
38
Test Conditions
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Figure 16. LXT363 I/O Timing Diagram for Motorola Address/Data Bus
TCSLDSL
CS
TASHASL
TAVASL
AS
TDSHCSH
TASLDSL
TASLAX
TDSHASH
TDXDSH
TDSLDSH
TRWLDSL
DS
TDVDSH
TDSHRWH
R/W_Read
TDSHDX
TDSLDV
AD0-7_Read
R/W_Write
AD0-7_Write
Figure 17. Typical T1 Jitter Tolerance at 36 dB
1000 UI
Jitter
500 UI
@ 10 Hz
LXT363 Device
Typical Jitter Tolerance
Loop Mode
138 UI
100 UI
Pub 62411
28 UI
Dec 1990
10 UI
0.6 UI
@ 10 kHz
1 UI
0.4 UI
.1 UI
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
Datasheet
39
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 18. T1 Jitter Attenuation
40
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
6.0
Mechanical Specifications
Figure 19. Plastic Leaded Chip Carrier Package Specifications
28-Pin PLCC
• Part Number LXT363PE
• Extended Temperature Range (-40 °C to 85 °C)
CL
C
B
D1
D
D
A2
A
A1
F
Inches
Millimeters
Dim
Min
Max
Min
Max
A
0.165
0.180
4.191
4.572
A1
0.090
0.120
2.286
3.048
A2
0.062
0.083
1.575
1
2.108
1
B
.050 BSC (nominal)
1.27 BSC (nominal)
C
0.026
0.032
0.660
0.813
D
0.485
0.495
12.319
12.573
D1
0.450
0.456
11.430
11.582
F
0.013
0.021
0.330
0.533
1. BSC—Basic Spacing between Centers.
Datasheet
41
LXT363 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 20. Plastic Quad Flat Package Specifications
44-Pin PQFP
• Part Number LXT363QE
• Extended Temperature Range (-40 °C to 85 °C)
D
D1
D3
e
E1
E3
E
θ3
L1
A2
A
θ
A1
θ3
B
L
Inches
Millimeters
Dim
Min
Max
Min
Max
A
–
0.096
–
2.45
A1
0.010
–
0.25
–
A2
0.077
0.083
1.95
2.10
B
0.012
0.018
0.30
0.45
D
0.510
0.530
12.95
13.45
D1
0.390
0.398
9.90
10.10
D3
0.315 BSC1 (nominal)
8.00 BSC1 (nominal)
0.510
0.530
12.95
13.45
E1
0.390
0.398
9.90
10.10
E3
0.315 BSC1 (nominal)
8.00 BSC1 (nominal)
e
0.031 BSC1 (nominal)
0.80 BSC1 (nominal)
L
0.029
0.73
E
L1
0.041
1
0.063 BSC (nominal)
1.03
1
1.60 BSC (nominal)
q3
5°
16°
5°
16°
q
0°
7°
0°
7°
1. BSC—Basic Spacing between Centers.
42
Datasheet
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT363
Figure 21. Low-Profile Quad Flat Package Specifications
44-Pin LQFP
• Part Number LXT363LE
• Extended Temperature Range (-40 °C to 85 °C)
D
NOTE: All dimensions in millimeters.
D/2
b
E/2
e
E1/2
e/2
E1
E
M
0 DEG. MIN.
A2
0.08 / 0.20 R.
D1/2
A1
D1
0.08 R. MIN.
A
L
0.20 MIN.
1.00
REF.
0 - 7 DEG.
Millimeters
Dimension1
Minimum
Nominal
Maximum
A
-
-
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
D
12.00 (basic spacing between centers)
D1
10.00 (basic spacing between centers)
E
12.00 (basic spacing between centers)
E1
10.00 (basic spacing between centers)
e
0.80 (basic spacing between centers)
L
0.45
0.60
0.75
M
0.15
-
-
1. See JEDEC Publication for additional specifications.
Datasheet
43