ETC LXT350PE

LXT350
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Datasheet
The LXT350 is a full-featured, fully-integrated transceiver for T1 and E1 short-haul
applications. The LXT350 is software switchable between T1 and E1 operation, and offers pulse
equalization settings for all short-haul T1 and E1 line interface (LIU) applications.
LXT350 provides both a serial port for microprocessor control (Host mode) as well as standalone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter
attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS/HDB3 encoding/
decoding and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety
of diagnostic loopback modes can also be selected.
Applications
■
■
SONET/SDH tributary interfaces
Digital cross connects
■
■
Public/private switching trunk line
interfaces
Microwave transmission systems
Product Features
■
■
■
■
■
■
Fully integrated transceivers for Short-Haul
T1 or E1 interfaces
Crystal-less digital jitter attenuation
— Select either transmit or receive path
— No crystal or high speed external clock
required
Meet or exceed specifications in ANSI
T1.403 and T1.408; ITU I.431, G.703,
G.736, G.775 and G.823; ETSI 300-166
and 300-233; and AT&T Pub 62411
Supports 75 Ω (E1 coax), 100 Ω (T1
twisted-pair) and 120 Ω (E1 twisted-pair)
applications
Fully restores the received signal after
transmission through a cable with
attenuation of 18dB, at 1024 kHz
Five pulse equalization settings for T1
short-haul applications
■
■
■
■
■
■
■
■
Transmit/receive performance monitors
with Driver Fail Monitor Open (DFM) and
Loss of Signal (LOS) outputs
Selectable unipolar or bipolar data I/O and
B8ZS/HDB3 encoding/decoding
QRSS generator/detector for testing or
monitoring
Output short circuit current limit protection
Local, remote and analog loopback
capability
Compatible with Intel’s LXT360/361 T1/
E1 long haul/short haul transceiver
(Universal LIU)
Multiple register serial interface for
microprocessor control
Available in 28-pin PLCC and 44-pin
PQFP packages
As of January 15, 2001, this document replaces the Level One document
Order Number: 249029-001
LXT350 — Integrated T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation.
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT350 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Contents
1.0
Pin Assignments and Signal Descriptions ...................................................... 8
1.1
2.0
Mode Dependent Signals ...................................................................................... 9
Functional Description...........................................................................................14
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Initialization..........................................................................................................14
2.1.1 Reset Operation .....................................................................................14
Transmitter ..........................................................................................................14
2.2.1 Transmit Digital Data Interface...............................................................14
2.2.2 Transmit Monitoring................................................................................15
2.2.3 Transmit Drivers .....................................................................................15
2.2.4 Transmit Idle Mode.................................................................................15
2.2.5 Transmit Pulse Shape ............................................................................15
Receiver ..............................................................................................................16
2.3.1 Receive Data Recovery..........................................................................16
2.3.2 Receive Digital Data Interface................................................................16
Jitter Attenuation .................................................................................................16
Hardware Mode...................................................................................................17
Host Mode ...........................................................................................................17
2.6.1 Interrupt Handling...................................................................................17
Diagnostic Mode Operation.................................................................................19
2.7.1 Loopback Modes ....................................................................................20
2.7.1.1 Local Loopback (LLOOP) ..........................................................20
2.7.1.2 Analog Loopback (ALOOP) .......................................................21
2.7.1.3 Remote Loopback (RLOOP) .....................................................22
2.7.1.4 Dual Loopback (DLOOP) ..........................................................23
2.7.2 Internal Pattern Generation ....................................................................23
2.7.2.1 Transmit All Ones (TAOS).........................................................23
2.7.2.2 Quasi-Random Signal Source (QRSS) .....................................23
2.7.3 Error Insertion and Detection .................................................................25
2.7.3.1 Bipolar Violation Insertion (INSBPV) .........................................25
2.7.3.2 Logic Error Insertion (INSLER)..................................................25
2.7.3.3 Logic Error Detection (QPD) .....................................................25
2.7.3.4 Bipolar Violation Detection (BPV)..............................................25
2.7.3.5 HDB3 Code Violation Detection (CODEV) ................................25
2.7.3.6 HDB3 Zero Substitution Violation Detection (ZEROV) ..............26
2.7.4 Alarm Condition Monitoring ....................................................................26
2.7.4.1 Loss of Signal (LOS) .................................................................26
2.7.4.2 Alarm Indication Signal Detection (AIS) ....................................26
2.7.4.3 Driver Failure Monitor Open (DFMO) ........................................27
2.7.4.4 Elastic Store Overflow/Underflow (ESOVR and ESUNF)..........27
2.7.4.5 Built-In Self Test (BIST).............................................................27
3.0
Register Definitions.................................................................................................28
4.0
Application Information .........................................................................................33
4.1
4.2
4.3
Datasheet
Transmit Return Loss ..........................................................................................33
Transformer Data ................................................................................................33
Application Circuits..............................................................................................33
3
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
4.4
Line Protection .................................................................................................... 33
4.4.1 Hardware Mode Application ................................................................... 35
4.4.2 Host Mode Application ........................................................................... 36
5.0
Test Specifications .................................................................................................. 38
6.0
Mechanical Specifications ................................................................................... 49
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
4
LXT350 Block Diagram ......................................................................................... 7
LXT350 Pin Assignments...................................................................................... 8
50% Duty Cycle Coding ...................................................................................... 15
Serial Port Data Structure ................................................................................... 18
TAOS with LLOOP .............................................................................................. 21
Local Loopback ................................................................................................... 21
Analog Loopback ................................................................................................ 22
Remote Loopback ............................................................................................... 22
Dual Loopback .................................................................................................... 23
TAOS Data Path ................................................................................................. 23
QRSS Mode ........................................................................................................ 24
Typical T1/E1 LXT350 Hardware Mode Application ........................................... 36
Typical T1/E1 LXT350 Host Mode Application.................................................... 37
2.048 MHz E1 Pulse (See Table 26) ................................................................... 41
1.544 Mbps T1 Pulse, DSX-1 (See Table 27) ..................................................... 42
Transmit Clock Timing ........................................................................................ 43
Receive Clock Timing ......................................................................................... 44
Serial Data Input Timing Diagram ....................................................................... 45
Serial Data Output Timing Diagram .................................................................... 46
Typical T1 Jitter Tolerance at 36 dB ................................................................... 46
Typical E1 Jitter Tolerance at 43 dB ................................................................... 47
Typical E1 Jitter Attenuation ............................................................................... 48
Typical T1 Jitter Attenuation................................................................................ 48
Plastic Leaded Chip Carrier Package Specifications .......................................... 49
Plastic Quad Flat Package Specifications........................................................... 50
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Datasheet
LXT350 Clock and Data Pins by Mode1 ............................................................... 9
LXT350 Control Pins by Mode ..............................................................................9
LXT350 Signal Descriptions ................................................................................10
CLKE Pin Settings1.............................................................................................18
Control and Operational Mode Selection ............................................................19
Diagnostic Mode Availability................................................................................19
Register Addresses .............................................................................................28
Register and Bit Summary ..................................................................................28
Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................29
Equalizer Control Input Settings.........................................................................29
Control Register #2 Read/Write, Address (A7-A0) = x010001x ..........................29
Control Register #3 Read/Write, Address (A7-A0) = x010010x ..........................30
Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x....................30
Transition Status Register Read Only, Address (A7-A0) = x010100x.................31
Performance Status Register Read Only, Address (A7-A0) = x010101x ............31
Control Register #4 Read/Write, Address (A7-A0) = x010111x ..........................32
E1 Transmit Return Loss Requirements .............................................................33
Transmit Return Loss (2.048 Mbps)....................................................................34
Transmit Return Loss (1.544 Mbps)....................................................................34
Transformer Specifications..................................................................................34
Recommended Transformers..............................................................................35
Absolute Maximum Ratings.................................................................................38
Recommended Operating Conditions .................................................................38
DC Electrical Characteristics...............................................................................39
Analog Characteristics ........................................................................................39
2.048 MHz E1 Pulse Mask Specifications...........................................................41
1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications........................42
T1 Operation Master and Transmit Clock Timing Characteristics
(See Figure 16) ...................................................................................................43
E1 Operation Master and Transmit Clock Timing Characteristics
(See Figure 16) ...................................................................................................43
Receive Timing Characteristics for T1 Operation (See Figure 17)......................44
Receive Timing Characteristics for E1 Operation (See Figure 17) .....................44
Serial I/O Timing Characteristics (See Figure 18 and Figure 19)........................45
5
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Revision History
Revision
6
Date
Description
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Figure 1. LXT350 Block Diagram
Datasheet
7
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
1.0
Pin Assignments and Signal Descriptions
TNEG / INSBPV
TPOS / TDATA / INSLER
TCLK
MCLK
TAOS / CLKE / QRSS
LLOOP / SCLK
RLOOP / CS
Figure 2. LXT350 Pin Assignments
4
3
2
1
28
27
26
MODE
5
25
EC3 / SDO
RNEG / BPV
6
24
EC2 / SDI
RPOS / RDATA
7
EC1 / INT
22
GND
21
VCC
20
RRING
19
RTIP
n/c
n/c
23
EC3 / SDO
RLOOP / CS
18
GND
TVCC
17
TRING
TGND
n/c
16
LLOOP / SCLK
14
TAOS / CLKE / QRSS
13
MCLK
15
12
TCLK
11
TNEG / INSBPV
JASEL
n/c
10
TTIP
9
n/c
LOS / QPD
8
TRSTE
LXT350PE
XX
LXT350PE
XXXXXX
XXXXXXXX
TPOS / TDAT /INSLER
RCLK
44 43 42 41 40 39 38 37 36 35 34
n/c
1
33
n/c
MODE
2
32
EC2 / SDI
RNEG / BPV
3
31
EC1 / INT
RPOS / RDATA
4
30
n/c
RCLK
5
n/c
6
TRSTE
7
29
GND
28
n/c
27
VCC
26
n/c
9
25
RRING
JASEL
10
24
RTIP
n/c
11
23
n/c
n/c
n/c
LXT350QE
LXT350QE XX Rev
XXXXXX
XXXXXXXX
Part #
LOT #
8
FPO #
n/c
n/c
GND
TRING
TVCC
n/c
TGND
TTIP
n/c
n/c
8
LOS / QPD
12 13 14 15 16 17 18 19 20 21 22
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
1.1
Mode Dependent Signals
As shown in Figure 2, the LXT350 has various signal pins that change function (and name)
according to the selected mode(s) of operation. These pins, associated signal names and operating
modes are summarized in Table 1 and Table 2. LXT350 signals are described in Table 3.
LXT350 Clock and Data Pins by Mode1
Table 1.
Pin #
External Data Modes
Bipolar Mode
QRSS Modes
PLCC
QFP
Unipolar Mode
Bipolar Mode
Unipolar Mode
1
39
2
41
3
42
TPOS
TDATA
INSLER
4
43
TNEG
INSBPV
INSBPV
6
3
RNEG
BPV
7
4
RPOS
RDATA
8
5
RCLK
13
15
TTIP
16
19
TRING
19
24
RTIP
20
25
RRING
MCLK
TCLK
RNEG
BPV
RPOS
RDATA
1. Data pins change based on whether external data or internal QRSS mode is active. Clock pins remain the same in both
Hardware and Host modes.
Table 2.
Pin #
LXT350 Control Pins by Mode
Hardware Modes
Unipolar/
Bipolar
PLCC
QFP
5
2
MODE
9
7
11
10
12
13
23
31
Datasheet
QRSS
Host Modes
Unipolar/
Bipolar
Hardware Modes
Unipolar/
Bipolar
Unipolar/
Bipolar
QFP
MODE
24
32
EC2
SDI
TRSTE
TRSTE
25
35
EC3
SDO
JASEL
Low
26
36
RLOOP
CS
27
37
LLOOP
SCLK
28
38
LOS/
QPD
EC1
LOS/
QPD
LOS
INT
TAOS
QRSS
Host Modes
PLCC
LOS
QRSS
Pin #
QRSS
QRSS
CLKE
9
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 3.
LXT350 Signal Descriptions
Pin #
Symbol
PLCC
I/O1
Description
QFP
1
39
MCLK
DI
Master Clock. External, independent clock signal required to generate internal
clocks. For T1 applications, a 1.544 MHz clock is required; for E1, a 2.048 MHz
clock. MCLK must be jitter-free and have an accuracy better than ± 50 ppm
with a typical duty cycle of 50%. Upon Loss of Signal (LOS), RCLK is derived
from MCLK.
2
41
TCLK
DI
Transmit Clock. For T1 applications, a 1.544 MHz clock is required; for E1, a
2.048 MHz clock. The transceiver samples TPOS and TNEG on the falling
edge of TCLK (or MCLK, if TCLK is not present).
BIPOLAR MODES:
Transmit – Positive and Negative. TPOS and TNEG are the positive and
negative sides of a bipolar input pair. Data to be transmitted onto the twistedpair line is input at these pins. TPOS/TNEG are sampled on the falling edge of
TCLK (or MCLK, if TCLK is not present).
UNIPOLAR MODES:
3
42
TPOS / TDATA /
INSLER
DI
4
43
TNEG / INSBPV
DI
Transmit Data. TDATA carries unipolar data to be transmitted onto the twistedpair line and is sampled on the falling edge of TCLK.
Transmit Insert Logic Error. In QRSS mode, a Low-to-High transition on
INSLER inserts a logic error into the transmitted QRSS data pattern. The
inserted error follows the data flow of the active loopback mode. The LXT350
samples this pin on the falling edge of TCLK (or MCLK, if TCLK is not present).
Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of
TCLK (or MCLK, if TCLK is not present) to control Bipolar Violation (BPV)
insertions in the transmit data stream. A Low-to-High transition is required to
insert each BPV. In QRSS mode, the BPV is inserted into the transmitted
QRSS pattern.
5
2
MODE
DI
Mode Select. Connect Low to select Hardware mode. Connect High to select
Host mode. See Table 5 on page 19 for a complete list of operating modes.
BIPOLAR MODES:
6
3
RNEG / BPV
DO
Receive – Negative and Positive. RPOS and RNEG are the positive and
negative sides of a bipolar output pair. Data recovered from the line interface is
output on these pins. A signal on RNEG corresponds to receipt of a negative
pulse on RTIP/RRING. A signal on RPOS corresponds to receipt of a positive
pulse on RTIP/RRING. RNEG/RPOS are Non-Return-to-Zero (NRZ). In
Hardware mode, RPOS/RNEG are stable and valid on the rising edge of
RCLK. In Host mode, the CLKE pin selects the RCLK clock edge when RPOS
/RNEG are stable and valid as described in Table 4 on page 18.
7
4
RPOS / RDATA
DO
UNIPOLAR MODES:
Receive Bipolar Violation. BPV goes High to indicate detection of a bipolar
violation from the line. This is an NRZ output and is valid on the rising edge of
RCLK.
Receive Data. RDATA is the unipolar NRZ output of data recovered from the
line interface. In Hardware mode, RDATA is stable and valid on the rising
edge of RCLK. In Host mode, the CLKE pin selects the RCLK clock edge
when RDATA is stable and valid as described in Table 4 on page 18.
8
5
RCLK
DO
Receive Recovered Clock. The clock recovered from the line input signal is
output on this pin. Under LOS conditions, there is a smooth transition from the
RCLK signal (derived from the recovered data) to the MCLK signal, which
appears at the RCLK pin.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
10
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 3.
LXT350 Signal Descriptions (Continued)
Pin #
Symbol
PLCC
I/O1
Description
QFP
Tristate.
HARDWARE MODES:
9
7
TRSTE
DI
Connect TRSTE High to force all output pins to the high impedance state.
TRSTE, in conjunction with the MODE pin, selects the operating modes listed
in Table 5 on page 19.
HOST MODES:
Connect TRSTE High to force all output pins to the high-impedance state.
Connect this pin Low for normal operation.
HARDWARE MODES:
Jitter Attenuation Select. Selects jitter attenuation location:
11
10
JASEL
DI
Setting JASEL High activates the jitter attenuator in the receive path.
Setting JASEL Low activates the jitter attenuator in the transmit path.
Setting JASEL to Midrange2 disables jitter attenuation.
HOST MODES:
Connect Low in Host mode.
Loss of Signal Indicator. LOS goes High upon receipt of 175 consecutive
spaces and returns Low when the received signal reaches a mark density of
12.5% (determined by receipt of 16 marks within a sliding window of 128 bits
with fewer than 100 consecutive zeros). Note that the transceiver outputs
received marks on RPOS and RNEG even when LOS is High.
12
13
LOS / QPD
13
15
TTIP
16
19
TRING
14
16
TGND
-
Ground return for the transmit driver power supply TVCC.
15
18
TVCC
-
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from VCC
by more than ± 0.3 V.
17
20
GND
-
Tie to Ground.
19
24
RTIP
20
25
RRING
21
27
VCC
-
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
22
29
GND
-
Ground return for power supply VCC.
DO
AO
AI
QRSS Pattern Detect. In QRSS mode, QPD stays High until the transceiver
detects a QRSS pattern. When a QRSS pattern is detected, the pin goes Low.
Any bit errors cause QPD to go High for half a clock cycle. This output can be
used to trigger an external error counter. Note that a LOS condition will cause
QPD to remain High. See Figure 11.
Transmit Tip and Ring. Differential driver output pair designed to drive a 50 200 Ω load. The transformer and line matching resistors should be selected to
give the desired pulse height and return loss performance. See “Application
Information” on page 33.
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data and
clock recovered from RTIP/RRING are output on the RPOS/RNEG (or RDATA
in Unipolar mode), and RCLK pins.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
Datasheet
11
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 3.
LXT350 Signal Descriptions (Continued)
Pin #
Symbol
PLCC
I/O1
Description
QFP
HARDWARE MODES:
Equalization Control 1-3. EC1, EC2, and EC3 specify the pulse equalization,
line build out and equalizer gain limit settings. See Table 10 on page 29 for
details.
HOST MODES:
23
31
EC1 / INT
24
32
EC2 / SDI
DI
25
35
EC3 / SDO
DI/O
DI
Interrupt. INT goes Low to flag the host when LOS, AIS, QRSS, DFMS or
DFMO bits changes state, or when an elastic store overflow or underflow
occurs. To identify the specific interrupt, read the Performance Status Register
(PSR). To clear or mask an interrupt, write a one to the appropriate bit in the
Interrupt Clear Register (ICR). To re-enable the interrupt, write a zero. INT is an
open drain output that must be connected to VCC through a pull-up resistor.
Serial Data Input. SDI inputs the 16-bit serial address/command and data
word. SDI is sampled on the rising edge of SCLK. Timing is shown in Figure 18
on page 45.
Serial Data Output. SDO outputs the 8-bit serial data read from the selected
LXT350 register. When the CLKE pin is High, SDO is valid on the rising edge of
SCLK. When CLKE is Low, SDO is valid on the falling edge of SCLK. SDO
goes to a high-impedance state when the serial port is being written to or when
CS is High. Timing is shown in Figure 19 on page 46.
HARDWARE MODES:
26
36
RLOOP / CS
DI
Remote Loopback. When held High, the clock and data inputs from the
framer (TPOS/TNEG or TDATA) are ignored and the data received from the
twisted-pair line is transmitted back onto the line at the RCLK frequency.
HOST MODES:
Chip Select. CS is used to access the serial interface. For each read or write
operation, CS must transition from High to Low, and remain Low.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
12
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 3.
LXT350 Signal Descriptions (Continued)
Pin #
Symbol
PLCC
I/O1
Description
QFP
HARDWARE MODES:
27
37
LLOOP / SCLK
DI
Local Loopback. When held High, the data on TPOS and TNEG loops back
digitally to the RPOS and RNEG outputs (through the JA if enabled).
Connecting this pin to Midrange2 enables Analog loopback (TTIP and TRING
are looped back to RTIP and RRING).
HOST MODES:
Serial Clock. SCLK synchronizes serial port read/write operations. The clock
frequency can be any rate up to 2.048 MHz.
HARDWARE MODES:
Transmit All Ones. When held High, the transmit data inputs are ignored and
the LXT350 transmits a stream of 1’s at the TCLK frequency. If TCLK is not
supplied, MCLK becomes the transmit clock reference. Note that TAOS is
inhibited during Remote loopback.
28
38
TAOS / QRSS /
CLKE
DI
QRSS. In QRSS mode, setting this pin to Midrange2, enables QRSS pattern
generation and detection. The transceiver transmits the QRSS pattern at the
TCLK rate (or MCLK, if TCLK is not present).
HOST MODES:
Clock Edge Select. When CLKE is High, RPOS/RNEG or RDATA are valid on
the falling edge of RCLK, and SDO is valid on the rising edge of SCLK.
When CLKE is Low, RPOS/RNEG or RDATA are valid on the rising edge of
RCLK, and SDO is valid on the falling edge of SCLK. The operation of CLKE is
summarized in Table 4 on page 18.
10, 18
1, 6, 8,
9, 11,
12, 14,
17, 21,
22, 23,
26, 28,
30, 33,
34, 40,
44
n/c
-
Not Connected. Let float
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
Datasheet
13
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.0
Functional Description
The LXT350 is a fully integrated, PCM transceiver for short-haul, 1.544 Mbps (T1) or 2.048 Mbps
(E1) applications allowing full-duplex transmission of digital data over existing twisted-pair
installations. It interfaces with two twisted-pair lines (one pair each for transmit and receive)
through standard pulse transformers and appropriate resistors.
The figure on the front page of this data sheet shows a block diagram of the LXT350. The designer
can configure the device for either Host or Hardware control. In Host mode, control is via the serial
microprocessor port. In Hardware mode, individual pin settings allow stand-alone operation.
The transceiver provides a high-precision, crystal-less jitter attenuator. The user may place it in the
transmit or receive path, or bypass it completely.
The LXT350 meets or exceeds FCC, ANSI T1 and AT&T specifications for CSU and DSX-1
applications, as well as ITU and ETSI requirements for E1 ISDN PRI applications.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the Phase Lock
Loops (PLL). The transceiver uses a reference clock to calibrate the PLLs: the transmitter reference
is TCLK, and the receiver reference clock is MCLK. MCLK is mandatory for chip operation and
must be an independent free running jitter free reference clock.
2.1.1
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS, and QRSS blocks. In
Hardware mode, holding pins RLOOP, LLOOP and TAOS High for at least one clock cycle resets
the device. In Host mode, writing a 1 to the bit CR2.RESET commands a reset which clears all
registers to 0. Allow 32 ms for the device to settle after removing all reset conditions.
2.2
Transmitter
2.2.1
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS
and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts unipolar data.
Input data may pass through either the Jitter Attenuator or B8ZS/HDB3 encoder or both. In Host
mode, setting CR1.ENCENB = 1 enables B8ZS/HDB3 encoding. In Hardware mode, connecting
the MODE pin to Midrange selects zero suppression coding. With zero suppression enabled, the
EC1 through EC3 inputs determine the coding scheme as listed in Table 10 on page 29.
TCLK supplies input synchronization. See the Figure 16 on page 43 for the transmit timing
requirements for TCLK and the Master Clock (MCLK).
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
2.2.2
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low impedance
load. The limiter automatically resets when the load current drops below the limit. The current is
determined by the interface circuitry (total resistance on transmit side).
In Host mode, the Performance Status Register flags open circuits in bit PSR.DFMO. A transition
on DFMO will provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
2.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
Figure 3. 50% Duty Cycle Coding
Bit Cell
1
2.2.4
0
1
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote or Dual Loopback, TAOS or any internal
transmit patterns temporarily disable the high impedance state.
2.2.5
Transmit Pulse Shape
As shown in Table 10 on page 29, Equalizer Control inputs (EC1 through EC3) determine the
transmitted pulse shape. In Host mode, EC1 through 3 are established by bits 0 through 2 of
Control Register #1 (CR1), respectively. In Hardware mode, pins EC1, EC2 and EC3 specify pulse
shape.
The transceiver produces DSX-1 pulses for short-haul T1 applications (settings from 0 dB to +6.0
dB of cable) or G.703 pulses for E1 applications. Shaped pulses are applied to the AMI line driver
for transmission onto the line at TTIP and TRING. Refer to the Test Specifications section for
pulse mask specifications.
Datasheet
15
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line (RTIP/RING). Recovered data is
output at RPOS/RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK.
Refer to Table 30 on page 44 for receiver timing specifications.
2.3.1
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and
timing recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411 and ITU G.823. See “Test Specifications” on page 38 for details.
2.3.2
Receive Digital Data Interface
Recovered data is routed to the Loss of Signal (LOS) Monitor. In Host mode, it also goes through
the Alarm Indication Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled
or disabled in the receive data path or the transmit path. Received data may be routed to either the
B8ZS or HDB3 decoder or neither. Finally, the device may send the digital data to the framer as
either unipolar or bipolar data.
When decoding unipolar data to the framer, the LXT350 reports reception of bipolar violations by
driving the BPV pin High. During E1 operation in Host mode, the device can be programmed to
report HDB3 code violations and Zero Substitution Violations on the BPV pin. See “Diagnostic
Mode Operation” on page 19 for details.
2.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides the jitter attenuation function.
The JAL requires no special circuitry, such as an external quartz crystal or high-frequency clock
(higher than the line rate). Rather, its timing reference is MCLK.
In Hardware mode, the ES is a 32 x 2-bit register. Setting the JASEL pin High places the JA
circuitry in the receive data path; setting JASEL Low places the JA in the transmit data path;
setting it to Midrange disables the JA.
In Host mode, bit CR1.JASEL0 enables or disables the JA circuit while bit CR1.JASEL1 controls
the JA circuit placement as specified in Table 9 on page 29. The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see Table 12).
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average
delay of 16 bits in the data path. An average delay of 32 bits occurs when the 64-bit ES option
selected (Host mode only). In the event of a LOS condition, with the Jitter Attenuator in the receive
path, RCLK will be derived from MCLK.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store overflow or
underflow, respectively. Note that these are “sticky bits”, that is, once set to 1, they remain set until
the host reads the register. An ES overflow or underflow condition will generate a maskable
interrupt.
2.5
Hardware Mode
The LXT350 operates in Hardware mode when the MODE pin is set to Low or Midrange. In
Hardware mode individual pins are used to access and control the transceiver. In Hardware mode,
RPOS/RNEG or RDATA are valid on the rising edge of RCLK.
Note: Some functions, such as interrupt (INT), clock edge selection (CLKE), and various
diagnostic modes, are provided only in Host mode.
2.6
Host Mode
The LXT350 operates in Host mode when the MODE pin is set High. In Host mode a
microprocessor controls the LXT350 and reads its status via the serial port which provides access
to the LXT350’s internal registers.
The host microprocessor can completely configure the device, as well as get a full diagnostic/status
report, via the serial port. However, in Unipolar mode, bipolar violation (BPV) insertions and logic
error insertions are controlled by the BPV and INSLER pins, respectively. Similarly, the recovered
clock, data, and BPV detection are available only at output pins. All other mode settings and
diagnostic information are available via the serial port. See “Register Definitions” on page 28 for
details.
Figure 4 shows the serial port data structure. The registers are accessible through a 16-bit word
composed of an 8-bit Command/Address byte (bits R/W and A1-A7) and a subsequent 8-bit data
byte (bits D0-7). The R/W bit commands a read or a write operation, i.e., the direction of the
following byte. Bits A1 through A6, of the command/address byte, point to a specific register. Note
that the LXT350 address decoder ignores bits A0 and A7. Refer to Table 32 on page 45 for timing
specifications.
Host mode also allows control of data output timing. The CLKE pin determines when SDO is
valid, relative to the Serial Clock (SCLK) as shown in Table 4.
2.6.1
Interrupt Handling
In Host mode, the LXT350 provides a latched interrupt output pin (INT). When enabled, a change
in any of the Performance Status Register bits will generate an interrupt. An interrupt can also be
generated when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an
interrupt occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has
internal pull-down only. Therefore, each device that shares the INT line requires an external
pull-up resistor.
The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes
a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in
any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
Datasheet
17
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 4.
CLKE Pin Settings1
CLKE
Pin
Valid Clock
Edge
Output
RPOS
RNEG
Rising RCLK
Low
RDATA
SDO
Falling SCLK
RPOS
RNEG
Falling RCLK
High
RDATA
SDO
Rising SCLK
1. The clock edge selection feature is not available in Hardware
mode.
Figure 4. Serial Port Data Structure
CS
SCLK
Address / Command Byte
Input (Write) Data Byte
A7
SDI
SDO
R/W
A1
A2
A3
A4
High Impedance
A5
A6
(don’t
care)
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
R/W = 1: Read operation
R/W = 0: Write operation (SDO remains high impedance)
18
Output (Read) Data Byte
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
.
Table 5.
Control and Operational Mode Selection
Input to Pin1
Mode of Operation
Mode
TRSTE
Hardware
Host2
Unipolar
Bipolar
AMI Enc/Dec
B8ZS/HDB3
Encoder/Decoder
Low
Low
On
Off
Off
On
Off3
Off
No
Low
High
On
Off
Off
On
Off3
Off
Yes
Low
Open
On
Off
On
Off
On
Off
No
High
Low
Off
On
x
x
x
x
No
High
High
Off
On
x
x
x
x
Yes
High
Open
Off
On
x
x
x
x
No
Open
Low
On
Off
On
Off
Off
On
No
Open
High
On
Off
On
Off
Off
On
Yes
Open
Open
On
Off
On
Off
Off
On
No
All Outputs Tristated
1. Open is either a midrange voltage or the pin is floating.
2. In Host mode, the contents of register CR1 determine the operation mode.
3. Encoding is done externally.
2.7
Diagnostic Mode Operation
The LXT350 offers multiple diagnostic modes as listed in Table 6. Note that various diagnostic
modes are only available in Host mode. In Hardware mode, the diagnostic modes are selected by a
combination of pin settings. In Host mode, the diagnostic modes are selected by writing
appropriate register bits. The following paragraphs provide details of the diagnostic modes.
Table 6.
Diagnostic Mode Availability
Availability1
Diagnostic Mode
Host Mode
Maskable2
Hardware
Host
Local Loopback (LLOOP)
Yes
Yes
No
Analog Loopback (ALOOP)
Yes
Yes
No
Loopback Modes
Remote Loopback (RLOOP)
Yes
Yes
No
Dual Loopback (DLOOP)
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
Bipolar Violation Insertion (INSBPV)
Yes
Yes
No
Logic Error Insertion (INSLER)
Yes
Yes
No
Internal Data Pattern Generation
Transmit All Ones (TAOS)
Quasi-Random Signal Source (QRSS)
Error Insertion and Detection
1. In Hardware mode, a combination of pin settings selects the Diagnostics Modes. In Host mode, writing appropriate bits in the
Control Registers selects the Diagnostic Modes.
2. Host mode allows interrupt masking by writing a “1” to the corresponding bit in the Interrupt Clear Register.
Datasheet
19
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 6.
Diagnostic Mode Availability
Availability1
Diagnostic Mode
Host Mode
Maskable2
Hardware
Host
Bipolar Violation Detection (BPV)
Yes
Yes
No
Logic Error Detection, QRSS (QPD)
Yes
Yes
No
HDB3 Code Violation Detection (CODEV)
No
Yes
No
No
Yes
No
Receive Loss of Signal (LOS) Monitoring
Yes
Yes
Yes
Receive Alarm Indication Signal (AIS) Monitoring
No
Yes
Yes
Transmit Driver Failure Monitoring—Open (DFMO)
No
Yes
Yes
Elastic Store Overflow and Underflow Monitoring
No
Yes
Yes
Built-In Self Test (BIST)
No
Yes
Yes
HDB3 Zero violation Detection (ZEROV)
Alarm Condition Monitoring
1. In Hardware mode, a combination of pin settings selects the Diagnostics Modes. In Host mode, writing appropriate bits in the
Control Registers selects the Diagnostic Modes.
2. Host mode allows interrupt masking by writing a “1” to the corresponding bit in the Interrupt Clear Register.
2.7.1
Loopback Modes
2.7.1.1
Local Loopback (LLOOP)
See Figure 5 and Figure 6. LLOOP inhibits the receiver circuits. The transmit clock and data inputs
(TCLK and TPOS/TNEG or TDATA) loop back through the jitter attenuator (if enabled) and
appear at RCLK and RPOS/RNEG or RDATA. Note that during LLOOP, the JASEL input is
strictly an enable/disable control, i.e. it does not affect the placement of the JA. If the JA is enabled,
it is active in the loopback circuit. If the JA is bypassed, it is not active in the loopback circuit.
The transmitter circuits are unaffected by LLOOP and the LXT350 continues to transmit the
TPOS/TNEG or TDATA inputs (or a stream of 1’s if TAOS is asserted). When used in this mode,
the transceiver can function as a stand-alone jitter attenuator.
In Hardware mode, Local loopback (LLOOP) is selected by setting LLOOP High; in Host mode,
by setting bit CR2.ELLOOP = 1.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Figure 5. TAOS with LLOOP
Figure 6. Local Loopback
2.7.1.2
Analog Loopback (ALOOP)
See Figure 7. Analog loopback (ALOOP) exercises the maximum number of functional blocks.
ALOOP operation disconnects the RTIP/RRING inputs from the line and routes the transmit
outputs back into the receive inputs. This tests the encoders/decoders, jitter attenuator, transmitter,
receiver and timing recovery sections.
Datasheet
21
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
In Hardware mode, ALOOP becomes active when the LLOOP pin is floating (i.e. Midrange). In
Host mode, setting bit CR2.EALOOP = 1 commands ALOOP. Note that ALOOP overrides all
other loopback modes.
Figure 7. Analog Loopback
2.7.1.3
Remote Loopback (RLOOP)
See Figure 8. When RLOOP is active, the device ignores the transmit data and clock inputs (TCLK
and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The RPOS/RNEG or
RDATA outputs loop back through the transmit circuits to TTIP and TRING at the RCLK
frequency. The RLOOP command does not affect the receiver circuits which continue to output the
RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line.
In Host mode, command RLOOP by writing a 1 to bit CR2.ERLOOP. In Hardware mode, RLOOP
is commanded by setting the RLOOP pin High.
Figure 8. Remote Loopback
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
2.7.1.4
Dual Loopback (DLOOP)
See Figure 9. In Hardware mode, DLOOP is selected by setting both the RLOOP and LLOOP pins
High. In Host mode set bits CR2.ERLOOP = 1 and CR2.ELLOOP = 1. In DLOOP mode, the
transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the Jitter
Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data and clock recovered
from the twisted-pair line loop back through the transmit circuits to TTIP and TRING without jitter
attenuation.
Figure 9. Dual Loopback
2.7.2
Internal Pattern Generation
2.7.2.1
Transmit All Ones (TAOS)
See Figure 10. When TAOS is active, the transceiver ignores the TPOS and TNEG inputs and
transmits a continuous stream of 1’s at the TCLK frequency. When TCLK is not supplied, TAOS
timing is derived from MCLK. This can be used as the Alarm Indication Signal (AIS–also called
the Blue Alarm).
Both TAOS and LLOOP can operate simultaneously as shown in Figure 5, however, RLOOP
inhibits TAOS. When both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to
RCLK and RPOS/RNEG (through the jitter attenuator if enabled), and the all ones pattern is also
routed to TTIP/TRING.
In Host mode, TAOS is activated when bit CR2.ETAOS = 1. In Hardware mode, setting the TAOS
pin High activates TAOS.
Figure 10. TAOS Data Path
2.7.2.2
Quasi-Random Signal Source (QRSS)
See Figure 11. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 220-1 pseudorandom bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is
215-1 PRBS with inverted output.
Datasheet
23
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Both Hardware and Host Modes allow QRSS mode. The QRSS pattern is normally locked to
TCLK, however, if there is no TCLK, MCLK is the clock source. Bellcore Pub 62411 defines the
T1 QRSS transmit format and ITU G.703 defines the E1 format.
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on the INSLER pin. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is “jammed”. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
A Low-to-High transition on the INSBPV pin will insert a bipolar violation in the QRSS pattern.
Note that the BPV insertion occurs regardless of whether the device is in Bipolar or Unipolar
operating mode.
In Hardware mode, connecting the TAOS pin to Midrange enables QRSS transmission. In Host
mode, setting bits CR2.EPAT0 = 0 and CR2.EPAT1=1 enables QRSS.
Figure 11. QRSS Mode
Selecting QRSS mode also enables QRSS Pattern Detection (QPD) in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. After achieving
synchronization the device drives the QPD pin Low. In the QRSS mode, any subsequent bit error in
the QRSS pattern causes QPD to go High for half an RCLK clock cycle. Note that in Host mode,
the precise relationship between QPD and RCLK depends on the CLKE pin. When CLKE is Low,
QPD goes High while RCLK is High; when CLKE is High, QPD goes High while RCLK is Low.
The edge of QPD can serve as a trigger for an external bit-error counter. A LOS condition or a loss
of QRSS synchronization will cause QPD to go High continuously. In this case, and with either
Unipolar mode or the encoders/decoders enabled, the BPV pin indicates BPVs, CODEVs or
ZEROVs.
Host mode can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. This interrupt is enabled when bit ICR.CQRSS = 0. If the QPD signal is
used to trigger a bit error counter, the interrupt could be used to start or reset the error counter.
The PSR.QRSS bit provides an indication of QRSS pattern synchronization. This bit goes to 0
when the QRSS pattern is not detected (i.e., when there are more than four errors in 128 bits). The
TQRSS bit in the Transition Status Register indicates that QRSS status has changed since the last
QRSS Interrupt Clear command.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
2.7.3
Error Insertion and Detection
2.7.3.1
Bipolar Violation Insertion (INSBPV)
The INSBPV function is available in Unipolar mode. Sampling occurs on the falling edge of
TCLK. A Low-to-High transition on the INSBPV pin inserts a BPV on the next available mark,
except in the four following situations:
• When zero suppression (B8ZS) is not violated
• When LLOOP and TAOS are both active. In this case, the BPV is looped back to the BPV pin
and the line driver transmits all ones with no violation.
• When RLOOP is active
Note that when the LXT350 is configured to transmit internally generated data patterns, a BPV can
be inserted on the transmit pattern regardless of whether the device is in the Unipolar or Bipolar
mode of operation.
2.7.3.2
Logic Error Insertion (INSLER)
When transmission of QRSS is active, a logic error is inserted into the transmit data pattern when a
Low-to-High transition occurs on the INSLER pin. Note that in QRSS mode, logic error insertion
is inhibited on a jammed bit (i.e. a bit forced to one to suppress transmission of more than 14
consecutive zeros).
The transceiver treats data patterns the same way it treats data applied to TPOS/TNEG. Therefore,
the inserted logic error will follow the data flow path as defined by the active loopback mode
2.7.3.3
Logic Error Detection (QPD)
After pattern synchronization is detected in QRSS mode, subsequent logic errors are reported on
the QPD pin. If a logic error occurs, the QPD pin goes High for half an RCLK cycle. Note that in
Host mode, the precise relationship between QPD and RCLK depends on the value of the CLKE
pin. When CLKE is Low, QPD goes High while RCLK is High; when CLKE is High, QPD goes
High while RCLK is Low. To tally logic errors, connect an error counter to QPD. A continuous
High on this pin indicates loss of either the QRSS pattern lock or a LOS condition. “Quasi-Random
Signal Source (QRSS)” on page 23 provides additional details on QRSS pattern lock criteria.
2.7.3.4
Bipolar Violation Detection (BPV)
When the internal encoders/decoders are disabled or when configured in Unipolar mode, bipolar
violations are reported at the BPV pin. BPV goes High for a full clock cycle to indicate receipt of a
BPV. When the encoders/decoders are enabled, the LXT350 does not report bipolar violations due
to the line coding scheme.
2.7.3.5
HDB3 Code Violation Detection (CODEV)
An HDB3 code violation (CODEV) occurs when two consecutive bipolar violations of the same
polarity are received (refer to ITU O.161). When CODEV detection is enabled, the BPV pin goes
High for a full RCLK cycle to report a CODEV violation. Note that bipolar violations and zero
substitution violations will also be reported on the BPV pin if these options are enabled.
Datasheet
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LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
CODEV detection is not available in Hardware mode. In Host mode, HDB3 code violation
detection is enabled when the HDB3 encoders/decoders are enabled. This requires that
CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select CODEV
detection, set bit CR4.CODEV = 1.
2.7.3.6
HDB3 Zero Substitution Violation Detection (ZEROV)
An HDB3 ZEROV is the receipt of four or more consecutive zeros. This does not occur with
correctly encoded HDB3 data unless there are transmission errors. The BPV pin goes High for a
full RCLK cycle to report a ZEROV. Note that when ZEROV detection enabled, the BPV pin will
also indicate received BPVs and CODEVs, if these detection options are enabled.
ZEROV detection is not available in Hardware mode. In Host mode, HDB3 zero substitution
violation (ZEROV) detection is enabled when the HDB3 encoders/decoders are enabled. This
requires CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select
ZEROV detection, set bit CR4.ZEROV = 1.
2.7.4
Alarm Condition Monitoring
2.7.4.1
Loss of Signal (LOS)
The Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI 300233. The
receiver LOS monitor loads a digital counter at the RCLK frequency. The count increments with
each received 0 and the counter resets to 0 on receipt of a 1. When the count reaches “n” 0s, the
LOS flag goes High, and the MCLK replaces the recovered clock at the RCLK output in a smooth
transition. For Hardware mode T1 operations, the number of 0s, n = 175, and for Hardware mode
E1 operations, n = 32. In Host mode, either number can be changed to 2048 by setting bit
CR4.LOS2048 to 1.
For T1 operation, when the received signal has 12.5% 1’s density (16 marks in a sliding 128-bit
period, with fewer than 100 consecutive 0s), the LOS flag returns Low and the recovered clock
replaces MCLK at the RCLK output in another smooth transition.
For E1 operation, the LOS condition is cleared when the received signal has 12.5% 1’s density
(four 1s in a sliding 32-bit window with fewer than 16 consecutive 0s). In E1 Host mode operation,
the out-of-LOS criterion can be modified from 12.5% marks density to 32 consecutive marks by
setting bit CR4.COL32CM = 1.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). In Hardware and Host modes, the LOS pin goes High when a LOS condition occurs. In
Host mode, bit PSR.LOS =1 indicates a LOS condition, and will generate an interrupt if so
programmed.
2.7.4.2
Alarm Indication Signal Detection (AIS)
This function is only available in Host mode. The receiver detects an AIS pattern when it receives
fewer than three 0s in any string of 2048 bits. The device clears the AIS condition when it receives
three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
2.7.4.3
Driver Failure Monitor Open (DFMO)
This function is only available in Host mode. The DFMO bit is available in the Performance Status
Register to indicate an open condition on the lines. DFMO can generate an interrupt to the host
controller. The Transition Status Register bit TDFMO indicates a transition in the status of the bit.
Writing a 1 to ICR.CDFMO will clear or mask the interrupt.
2.7.4.4
Elastic Store Overflow/Underflow (ESOVR and ESUNF)
This function is only available in Host mode. When the bit count in the Elastic Store (ES) is within
two bits of overflowing or underflowing the ES adjusts the output clock by 1/8 of a bit period. The
ES provides an indication of overflow and underflow via bits TRS.ESOVR and TSR.ESUNF.
These are “sticky bits” and will stay set to 1 until the host controller reads the register. These
interrupts can be cleared or masked by writing a 1 to the bits ICR.CESO and ICR.CESU,
respectively.
2.7.4.5
Built-In Self Test (BIST)
The BIST function in only available in Host mode. The BIST exercises the internal circuits by
providing an internal QRSS pattern, running it through the encoders and the transmit drivers then
looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern
detection circuitry. The BIST is initiated by setting bit CR3.SBIST = 1. If all the blocks in this data
path operate correctly, the receive pattern detector locks onto the pattern. It then pulls INT Low and
sets the following bits:
• TSR.TQRSS = 1
• PSR.QRSS = 1
• PSR.BIST = 1
The QPD pin also indicates completion status of the test. Initiating the BIST forces QPD High.
During the test, it remains High until the test finishes successfully, at which time it goes Low. Note
that during BIST, the TPOS/TNEG inputs must remain at logic level = 0
The most reliable test will result when a separate TCLK and MCLK are applied.
Datasheet
27
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
3.0
Register Definitions
The LXT350 contains five read/write and two read-only registers that are accessible in Host mode
via the serial I/O port. Table 7 lists the LXT350 register addresses. Only bits A6 through A1 of the
address byte are valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/
write (R/W) bit. Table 8 identifies the name of each register bit. Table 9 through Table 16 describe
the function of the bits in each register.
Note that upon power-up or reset, all registers are cleared to 0.
Table 7.
Register Addresses
Register
Address1, 2
A7 - A1
Name
Abbr
Control #1
CR1
x010000
Control #2
CR2
x010001
Control #3
CR3
x010010
Interrupt Clear
ICR
x010011
Transition Status
TSR
x010100
Performance Status
PSR
x010101
Control #4
CR4
x010111
1. x = don’t care
2. Address A0 is the read/write (R/W) bit.
Table 8.
Register and Bit Summary
Register
Name
Control #1
Control #2
Control #3
CR1
CR2
CR3
Bit
Type
7
6
5
4
3
R/W
JASEL1
JASEL0
ENCENB
UNIENB
reserved1
R/W
R/W
RESET
JA6HZ
EPAT1
reserved
EPAT0
1
SBIST
ETAOS
EQZMON
2
1
0
EC3
EC2
EC1
reserved
1
EALOOP
ELLOOP
ERLOOP
reserved
1
ES64
ESCEN
ESJAM
2
CQRSS
CAIS
reserved
2
CLOS
Interrupt Clear
ICR
R/W
CESU
CESO
CDFMO
reserved
Transition
Status
TSR
R
ESUNF
ESOVR
TDFMO
reserved1
TQRSS
TAIS
reserved1
TLOS
Performance
Status
PSR
R
reserved1
BIST
DFMO
reserved1
QRSS
AIS
reserved1
LOS
Control #4
CR4
R/W
reserved1
reserved1
reserved1
reserved1
COL32CM
LOS2048
ZEROV
CODEV
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
28
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 9.
Control Register #1 Read/Write, Address (A7-A0) = x010000x
Jitter Attenuator
Bit
Name
0
Function
JASEL0
JASEL1
Position
1
0
Transmit
1
1
Receive
0
X
Disabled
EC1
1
EC2
2
EC3
3
-
4
UNIENB
5
ENCEN
B
6
JASEL0
7
JASEL1
Sets mode (T1 or E1) and equalizer
(see Table 10 below for control codes).
Reserved, set this bit to 0, ignore when reading.
1 = Enable Unipolar I/O mode and allow insertion/detection of BPVs.
0 = Enable Bipolar I/O mode
1 = Enable B8ZS/HDB3 encoders/decoders and force Unipolar I/O
mode.
0 = Disable B8ZS/HDB3 encoders/decoders
Select jitter attenuation circuitry position in data path or disables the
JA. See right hand section of table for codes.
Ñ
Table 10. Equalizer Control Input Settings
EC3
EC2
EC1
Function
Pulse
Cable
Coding1
0
0
0
E1
ITU Rec G.703
75 Ω Coax/120 Ω TP
HDB3
0
1
1
T1
0-133 ft / 0.6 dB
100 Ω TP
B8ZS
1
0
0
T1
133-266 ft / 1.2 dB
100 Ω TP
B8ZS
1
0
1
T1
266-399 ft / 1.8 dB
100 Ω TP
B8ZS
1
1
0
T1
399-533 ft / 2.4 dB
100 Ω TP
B8ZS
1
1
1
T1
533-655 ft / 3.0 dB
100 Ω TP
B8ZS
1. When enabled.
Table 11. Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
0
ERLOOP1
1
ELLOOP1
2
EALOOP
3
-
Function
1 = Enable Remote loopback mode
0 = Disable Remote loopback mode
1 = Enable Local loopback mode
0 = Disable Local loopback mode
1 = Enable Analog loopback mode
0 = Disable Analog loopback mode
Reserved, set to 0, ignore when reading.
EPAT0
EPAT1
Selected
0
0
Transmit TPOS/TNEG
0
1
Detect and transmit QRSS
1
0
In-band Loop Up Code
00001
1
1
In-band Loop Down Code
001
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Datasheet
29
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 11. Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
Function
EPAT0
4
ETAOS
5
EPAT0
6
EPAT1
7
RESET
EPAT1
Selected
1 = Enable Transmit All Ones
0 = Disable Transmit All Ones
Selects internal data pattern transmission. See right
hand section of table for codes.
Ñ
1 = Reset device states and clear all registers.
0 = Reset complete.
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Table 12. Control Register #3 Read/Write, Address (A7-A0) = x010010x
Bit
Name
0
ESJAM
1
ESCEN
2
ES64
3
-
4
EQZMON
5
SBIST
6
-
7
JA6HZ
Description
1 = Disable jamming of Elastic Store read out clock (1/8 bit-time adjustment for over/underflow).
0 = Enable jamming of Elastic Store read out clock
1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically).
0 = Centering completed
1 = Set elastic store depth to 64 bits.
0 = Set elastic store depth to 32 bits.
Reserved. Set to 0 for normal operation.
1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor).
0 = Configure receiver equalizer for normal mode application
1 = Start Built-In Self Test.
0 = Built-In Self Test complete.
Reserved. Set to 0 for normal operation.
1 = Set bandwidth of jitter attenuation loop to 6 Hz.
0 = Set bandwidth of jitter attenuation loop to 3 Hz.
Table 13. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
0
CLOS
1
-
2
CAIS
3
CQRSS
4
-
Function1
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
Reserved. Set to 1 for normal operation.
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
Reserved. Set to 1 for normal operation.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
30
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 13. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
5
CDFMO
6
CESO
7
CESU
Function1
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 14. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit
Name
0
TLOS
1
-
2
TAIS
3
TQRSS
4
-
5
TDFMO
6
ESOVR
7
ESUNF
Function
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
Reserved. Ignore.
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
1 = QRSS has changed since last clear QRSS interrupt occurred1.
0 = No change in status.
Reserved. Ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
1 = ES overflow status sticky bit2.
0 = No change in status.
1 = ES underflow status sticky bit2.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
Table 15. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
0
LOS
1
-
2
AIS
3
QRSS
4
-
Datasheet
Function
1 = Loss of Signal occurred.
0 = Loss of Signal did not occur.
Reserved. Ignore.
1 = Alarm Indicator Signal detected.
0 = Alarm Indicator Signal not detected.
1 = Quasi-Random Signal Source pattern detected.
0 = Quasi-Random Signal Source pattern not detected.
Reserved. Ignore.
31
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 15. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
5
DFMO
6
BIST
7
-
Function
1 = Driver Failure Monitor Open detected.
0 = Driver Failure Monitor Open not detected.
1 = Built-In Self Test passed.
0 = Built-In Self Test did not pass (or was not run).
Reserved. Ignore.
Table 16. Control Register #4 Read/Write, Address (A7-A0) = x010111x
Bit
Name
Function
0
CODEV
1 = Enable detection of HDB3 code violations at the BPV pin along with bipolar violations and Zero
Substitution Violations (if enabled).
0 = Disable detection of HDB3 code violations
1
ZEROV
1 = Enable detection of HDB3 Zero Substitution Violations (four consecutive zeros). Note that Zero
Substitution Violations are reported at the BPV pin.
0 = Disable detection of HDB3 Zero Substitution Violations.
1 = Set LOS detection threshold to 2048 consecutive zeros.
32
2
LOS2048
3
COL32CM
4
-
Reserved. Set to 0 for normal operation, ignore when reading
5
-
Reserved. Set to 0 for normal operation, ignore when reading
6
-
Reserved. Set to 0 for normal operation, ignore when reading
7
-
Reserved. Set to 0 for normal operation, ignore when reading
0 = Set LOS detection threshold to 32 consecutive zeros (for E1 operation) or to 175 consecutive
zeros (for T1 operation).
1 = Set LOS clear condition criterion to receipt of 32 consecutive marks (E1 operation).
0 = Set LOS clear condition criterion to 12.5% mark density (E1 operation).
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
4.0
Application Information
4.1
Transmit Return Loss
Table 17 shows the specification for transmit return loss in E1 applications. The G.703/CH PTT
specification is a Swiss Telecommunications Ministry specification.
Table 18 and Table 19 show the transmit return loss values for E1 and T1 applications.
4.2
Transformer Data
Specifications for transformers are listed in Table 20. A list of transformers recommended for use
with the LXT350 are specified in Table 21.
4.3
Application Circuits
Figure 12 and Figure 13 show typical LXT350 applications for Hardware and Host modes of
operation.
4.4
Line Protection
On the receive side, 1 kΩ series resistors protect the receiver against current surges coupled into
the device. Due to the high receiver impedance (40 kΩ typical) the resistors do not affect the
receiver sensitivity. On the transmit side, Schottky diodes D1-D4 protect the output driver. While
not mandatory for normal operation, these protection elements are strongly recommended to
improve the design robustness.
Table 17. E1 Transmit Return Loss Requirements
Return Loss
Frequency Band
ETS 300 166
Datasheet
G.703/CH PTT
51-102 kHz
6 dB
8 dB
102-2048 kHz
8 dB
14 dB
2048 - 3072 kHz
8 dB
10 dB
33
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 18. Transmit Return Loss (2.048 Mbps)
EC3-1
Xfrmr/Rt
R L (Ω )
CL (pF)
Return Loss
(dB)
0
14
470
16
0
12
470
13
0
13
470
16
75
1:2/
9.1 Ω
000
120
1:2.3/9.1
Ω
120
Table 19. Transmit Return Loss (1.544 Mbps)
EC3-1
Xfrmr/Rt
RL ( Ω)
1:2/
9.1 Ω
100
0112
1
1:1.15 /
0.0 Ω
CL (pF)
Return Loss
(dB)
0
16
470
17
0
2
470
2
100
1. A 1:1.15 transmit transformer keeps the total transceiver
power dissipation at a low level, a 0.47 µF DC blocking
capacitor must be placed on TTIP or TRING.
2. Refer to Table 10.
Table 20. Transformer Specifications
Tx/Rx
Tx
Rx
Turns Ratio
Primary
Inductance
µH
(minimum)
Leakage
Inductance
µH
(max)
Interwinding
Capacitance
pF
(max)
1.544
1:1.15
600
0.80
60
2.048
1:2.3
600
0.80
60
1.544/2.048
1:2
600
0.80
1.544/2.048
1:1
600
1.10
Frequency
MHz
DCR
Ω
(maximum)
0.90 pri
1.70 sec
Dielectric1
Breakdown
V
(minimum)
1500 VRMS
1.20 sec
1500 VRMS2
(3000 VRMS)
60
1.0 pri
1.70 sec
1500 VRMS2
(3000 VRMS)
60
1.10 pri
1.10 sec
1500 VRMS2
(3000 VRMS)
0.70 pri
1. Some ETSI applications may require a 2.3 kV dielectric breakdown voltage.
2. Some applications require transformers to guarantee performance in extended temperature range (-40° to +85° C) ETSI
applications require a dielectric breakdown voltage of 3000 VRMS.
34
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 21. Recommended Transformers
Tx/Rx
Turns Ratio
Part Number
Manufacturer
PE-65388
Pulse Engineering
1:1.15
PE-65770
16Z5952
Vitec
PE-65351
Pulse Engineering
PE-65771
0553-5006-IC
Tx
Bell-Fuse
66Z-1308
Fil-Mag
671-5832
Midcom
67127370
1:2
Schott Corp
67130850
TD61-1205D
HALO (combination Tx/Rx set)
TG26-1205NI
HALO (surface mount dual transformer 1CT:2CT
& 1CT:2CT)
TG48-1205NI
HALO (surface mount dual transformer 1CT:2CT
& 1:1)
16Z5946
1:2.3
PE-65558
Vitec
Pulse Engineering
FE 8006-155
Fil-Mag
671-5792
Midcom
PE-64936
Pulse Engineering
Rx
1:1
PE-65778
67130840
Schott Corp
67109510
TD61-1205D
4.4.1
HALO (combination Tx/Rx set)
Hardware Mode Application
Figure 12 shows a typical LXT350 application in either a T1 or E1 environment. See Table 18
through Table 19 to select the transformers (T1 and T2), resistors (Rt and RL) and capacitors (CL)
needed for this application.
Note:
Datasheet
If the application includes surge protection, such as a varistor or sidactor on the TTIP/TRING lines,
it may also require reducing the value of the capacitor CL, or eliminating it completely. Excessive
capacitance at CL will distort the transmitted signals.
35
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 12. Typical T1/E1 LXT350 Hardware Mode Application
2.048 MHz/
1.544 MHz
TAOS
MCLK
LLOOP
RLOOP
TCLK
TCLK
TPOS
TPOS
TNEG
TNEG
From
CMOS
Control
Logic
EC1
EC2
EC3
MODE
T1/E1
Framer
TRSTE
RCLK
JASEL
1:21
RCLK
TTIP
RPOS
RPOS
RNEG
RNEG
LXT350
CL1
TRING
LOS
Rt1
Rt1
RTIP
NLOOP
TVCC
RL2
VCC
0.1 µF
RRING
68 µF
TGND
1:1
GND
NOTES:
1. See Table 18 and Table 19 for CL, Rt and Transformer selection.
2. RL = 100 Ω for T1
RL = 120 Ω for E1/120 Ω twisted pair
RL = 75 Ω for E1/75 Ω coax
4.4.2
Host Mode Application
Figure 13 shows a typical application using the LXT350 in Host mode. See Table 18 through Table
19 to select the transformers (T1 and T2), resistors (Rt and RL) and capacitors (CL) needed for this
application.
Note:
36
If the application includes surge protection, such as a varistor or sidactor on the TTIP/TRING lines,
it may also require reducing the value of the capacitor CL, or eliminating it completely. Excessive
capacitance at CL will distort the transmitted signals.
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Figure 13. Typical T1/E1 LXT350 Host Mode Application
VCC
2.048 MHz/
1.544 MHz
22 kΩ
MCLK
INT
CLKE
TCLK
TCLK
TPOS
TPOS
TNEG
TNEG
SDO
MODE
TRSTE
SDI
CS
SCLK
+5 V
T1/E1
Framer
RCLK
RCLK
RPOS
RPOS
RNEG
RNEG
Host
11
LXT350
17
1:21
TTIP
Rt1
CL1
LOS
NLOOP
TVCC
TRING
Rt1
RTIP
VCC
0.1 µF
RL2
68 µF
TGND
GND
RRING
1:1
NOTES:
1. See Table 18 and Table 19 for CL, Rt and Transformer
selection.
2. RL = 100 Ω for T1
RL = 120 Ω for E1/120 Ω twisted pair
RL = 75 Ω for E1/75 Ω coax
Datasheet
37
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
5.0
Test Specifications
Note:
Table 22 through Table 32 and Figure 14 through Figure 23 represent the performance
specifications of the LXT350 and are guaranteed by test except, where noted, by design. The
minimum and maximum values listed in Table 24 through Table 32 are guaranteed over the
recommended operating conditions specified in Table 23.
Table 22. Absolute Maximum Ratings
Parameter
DC supply (reference to GND)
Sym
Min
Max
Unit
VCC, TVCC
–
6.0
V
Input voltage, any pin
1
VIN
GND - 0.3 V
VCC + 0.3 V
V
Input current, any pin
2
IIN
- 10
10
mA
TSTG
-65
150
°C
Storage Temperature
Caution: Exceeding these values may cause permanent damage.
Caution: Functional operation under these conditions is not implied.
Caution: Exposure to maximum rating conditions for extended periods may affect device reliability.
1. TVCC and VCC must not differ by more than 0.3 V during operation. TGND and GND must not differ by more than 0.3 V
during operation.
2. Transient currents of up to 100 mA will not cause SCR latch-up. TTIP, TRING, TVCC, and TGND can withstand continuous
currents of up to 100 mA.
Table 23. Recommended Operating Conditions
Parameter
DC supply 2
Ambient operating temperature
Sym
Min
Typ1
Max
Unit
VCC,TVCC
4.75
5.0
5.25
V
TA
- 40
25
85
°C
PD
–
310
380
mW
100% mark density
PD
–
225
295
mW
50% mark density
PD
–
275
330
mW
100% mark density
PD
–
215
270
mW
50% mark density
Test Conditions
T1
Total power dissipation3
E1
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. TVCC and VCC must not differ by more than 0.3 V.
3. Power dissipation while driving 75 Ω load over operating range for T1 operation or 60 Ω load for E1 operation. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacitive load.
38
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 24. DC Electrical Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions
VIH
2.0
–
–
V
VIL
–
–
0.8
V
–
V
IOUT = -400 µA
IOUT = 1.6 mA
Digital I/O pins
High level input voltage 1,2 (pins 1-4, 23-25)4
Low level input voltage
1,2
4
(pins 1-4, 23-25)
High level output voltage
1,2
4
(pins 6-8, 12, 23, 25)
VOH
2.4
–
Low level output voltage
1,2
4
VOL
–
–
0.4
V
I 3L
0
–
±10
µA
VIH
3.5
–
–
V
(pins 6-8, 12, 23, 25)
Tri-state leakage current 1 (all outputs)
Mode input pins
3
High level input voltage (pins 5, 9, 11, 26-28)
4
3
Midrange output voltage (pins 5, 9, 11, 26-28)
4
VOM
2.3
–
2.7
V
Host Mode
VIL
–
–
0.8
V
H/W Mode
VIL
–
–
1.5
V
ILL
0
–
±50
µA
Tri-state leakage current (all outputs)
I3L
0
–
±10
µA
TTIP/TRING leakage current
ITR
–
–
1.2
mA
Low level input voltage 3 (pins 5, 9, 11, 26-28)4
4
Input leakage current (pins 5, 9, 11, 26-28)
1
1.
2.
3.
4.
In power down
and tristate
Functionality of pin 23 and 25 depends on mode. See Host mode and Hardware mode description.
Output drivers will output CMOS logic levels into CMOS loads.
As an alternative to supplying 2.3 - 2.7 V to these pins, they may be left open.
Listed pins are for the PLCC package. Refer to “Pin Assignments and Signal Descriptions” on page 8 for the 44-pin QFP
package.
Table 25. Analog Characteristics
Parameter
Min
Recommended output load on TTIP/TRING
T1
Typ1
Max
Unit
50
–
200
Ω
2.4
3.0
3.6
V
RL = 100 Ω
2.7
3.0
3.3
V
RL = 120 Ω
AMI output pulse amplitudes
E1
10 Hz - 8 kHz
3
–
–
0.02
UI
3
–
–
0.025
UI
10 Hz - 40 kHz3
–
–
0.025
UI
Broad Band
–
–
0.05
UI
0
–
18
dB
Allowable consecutive zeros before LOS (T1)
160
175
190
–
Allowable consecutive zeros before LOS (E1)
–
32
–
–
0.4
–
–
UI
138
–
–
UI
Jitter added by the
transmitter2
8 kHz - 40 kHz
Receiver sensitivity
10 kHz - 100 kHz
Input jitter tolerance (T1)
3
1 Hz
1.
2.
3.
4.
Test Conditions
@ 1024 kHz
1.431
0 dB line
AT&T Pub 62411
Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
Guaranteed by characterization; not subject to production testing.
Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Datasheet
39
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 25. Analog Characteristics
Min
Typ1
Max
Unit
10 kHz - 100 kHz
0.2
–
–
UI
1 Hz3
37
–
–
UI
0 dB line
ITU (G.823)
Jitter attenuation curve corner frequency 4
–
3
–
Hz
selectable in data port
Driver output impedance
–
3
–
Ω
Parameter
Input jitter tolerance (E1)
Receiver input impedance
51 kHz - 102 kHz3
Receive return loss (E1)
102 kHz - 2.048 MHz3
3
2.048 MHz - 3.072 MHz
1.
2.
3.
4.
40
–
40
–
kΩ
20
22
–
dB
20
28
–
dB
25
30
–
dB
Test Conditions
RTIP to RRING
Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
Guaranteed by characterization; not subject to production testing.
Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Figure 14. 2.048 MHz E1 Pulse (See Table 26)
20%
345 ns
20%
V = 100%
10% 10%
478 ns
NOMINAL PULSE
50%
434 ns
10% 10%
0%
10% 10%
390 ns
20%
870 ns
Table 26. 2.048 MHz E1 Pulse Mask Specifications
Parameter
TWP
Coax
Unit
Test load impedance
120
75
Ω
Nominal peak mark voltage
3.0
2.37
V
Nominal peak space voltage
0 ±0.30
0 ±0.237
V
Nominal pulse width
244
244
ns
Ratio of positive and negative pulse amplitudes at center of pulse
95-105
95-105
%
Ratio of positive and negative pulse amplitudes at nominal half amplitude
95-105
95-105
%
Datasheet
41
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 15. 1.544 Mbps T1 Pulse, DSX-1 (See Table 27)
1.5
Normalized Amplitude
1.0
0.5
0.5
-0.5
0.0
1.0
1.5
Time
(in Unit Intervals)
-0.5
0
Table 27. 1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications
DSX-1 Template (per ANSI T1. 102-1993)
Minimum Curve
42
Maximum Curve
Time (UI)
Amplitude
Time (UI)
Amplitude
-0.77
-0.05
-0.77
0.05
-0.23
-0.05
-0.39
0.05
-0.23
0.50
-0.27
0.80
-0.15
0.95
-0.27
1.15
0.0
0.95
-0.12
1.15
0.15
0.90
0.0
1.05
0.23
0.50
0.27
1.05
0.23
-0.45
0.35
-0.07
0.46
-0.45
0.93
0.05
0.66
-0.20
1.16
0.05
0.93
-0.05
-
-
1.16
-0.05
-
-
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 28. T1 Operation Master and Transmit Clock Timing Characteristics
(See Figure 16)
Sym
Min
Typ1
Max
Unit
Notes
Master clock frequency
MCLK
–
1.544
–
MHz
must be supplied
Master clock tolerance
MCLKt
–
±50
–
ppm
Master clock duty cycle
MCLKd
40
–
60
%
Parameter
Transmit clock frequency
TCLK
–
1.544
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
Transmit clock duty cycle
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
tSUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
tHT
50
–
–
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 29. E1 Operation Master and Transmit Clock Timing Characteristics
(See Figure 16)
Sym
Min
Typ1
Max
Unit
Notes
Master clock frequency
MCLK
–
2.048
–
MHz
must be supplied
Master clock tolerance
MCLKt
–
±50
–
ppm
Master clock duty cycle
Parameter
MCLKd
40
–
60
%
Transmit clock frequency
TCLK
–
2.048
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
Transmit clock duty cycle
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
tSUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
tHT
50
–
–
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 16. Transmit Clock Timing
Datasheet
43
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 30. Receive Timing Characteristics for T1 Operation (See Figure 17)
Parameter
Typ1
Max
40
50
60
%
–
648
–
ns
Sym
Min
Receive clock duty cycle 2, 3
RLCKd
Receive clock pulse width 2, 3
tPW
Unit
tPWH
–
324
–
ns
2, 3
tPWL
260
324
388
ns
RPOS/RNEG to RCLK rising time
tSUR
–
274
–
ns
RCLK rising to RPOS/RNEG hold time
tHR
–
274
–
ns
Receive clock pulse width high
Receive clock pulse width low
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 31. Receive Timing Characteristics for E1 Operation (See Figure 17)
Parameter
Receive clock duty cycle
2, 3
2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
40
50
60
%
tPW
–
488
–
ns
tPWH
–
244
–
ns
2, 3
tPWL
195
244
293
ns
RPOS/RNEG to RCLK rising time
tSUR
–
194
–
ns
RCLK rising to RPOS/RNEG hold time
tHR
–
194
–
ns
Receive clock pulse width
Receive clock pulse width high
Receive clock pulse width low
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz.)
3. Worst case conditions guaranteed by design only.
Figure 17. Receive Clock Timing
,
,
44
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 32. Serial I/O Timing Characteristics (See Figure 18 and Figure 19)
Parameter
Sym
Min
Typ1
Max
Unit
Parameter
Load 1.6 mA, 50 pF
Rise/fall time—any digital output
tRF
–
–
100
ns
SDI to SCLK setup time
tDC
50
–
–
ns
SCLK to SDI hold time
tCDH
50
–
–
ns
tCL
240
–
–
ns
SCLK low time
tCH
240
–
–
ns
tR, tF
–
–
50
ns
CS falling edge to SCLK rising edge
tCC
50
–
–
ns
Last SCLK edge to CS rising edge
tCCH
50
–
–
ns
CS inactive time
tCWH
250
–
–
ns
SCLK to SDO valid time
tCDV
–
–
200
ns
SCLK falling edge or CS rising edge to SDO high-Z
tCDZ
–
100
–
ns
SCLK high time
SCLK rise and fall time
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 18. Serial Data Input Timing Diagram
Datasheet
45
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 19. Serial Data Output Timing Diagram
CLKE = 0
2
1
3
4
5
6
7
8
9
10
11
1
2
12
13
14
15
5
6
16
SCLK
CS
tCCH
tCDZ
SDO
0
4
3
7
CLKE = 1
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS
0
SDO
1
2
3
4
5
tCDZ
6
tCCH
7
Figure 20. Typical T1 Jitter Tolerance at 36 dB
1000 UI
Jitter
500 UI
@ 10 Hz
LXT350 Device
Typical Jitter Tolerance
Loop Mode
138 UI
100 UI
Pub 62411
28 UI
Dec 1990
10 UI
0.6 UI
@ 10 kHz
1 UI
0.4 UI
.1 UI
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
46
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Figure 21. Typical E1 Jitter Tolerance at 43 dB
Datasheet
47
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 22. Typical E1 Jitter Attenuation
Figure 23. Typical T1 Jitter Attenuation
48
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
6.0
Mechanical Specifications
Figure 24. Plastic Leaded Chip Carrier Package Specifications
28-Pin PLCC
• Part Number LXT350PE
• Extended Temperature Range (-40 °C to 85 °C)
CL
C
B
D1
D
D
A2
A
A1
F
Inches
Millimeters
Dim
Min
Max
Min
Max
A
0.165
0.180
4.191
4.572
A1
0.090
0.120
2.286
3.048
A2
0.062
0.083
1.575
1
2.108
1
B
.050 BSC (nominal)
1.27 BSC (nominal)
C
0.026
0.032
0.660
0.813
D
0.485
0.495
12.319
12.573
D1
0.450
0.456
11.430
11.582
F
0.013
0.021
0.330
0.533
1. BSC—Basic Spacing between Centers.
Datasheet
49
LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 25. Plastic Quad Flat Package Specifications
44-Pin PQFP
• Part Number LXT350QE
• Extended Temperature Range (-40 °C to 85 °C)
D
D1
D3
e
E1
E3
E
θ3
L1
A2
A
θ
A1
θ3
B
L
Inches
Millimeters
Dim
Min
Max
Min
Max
A
–
0.096
–
2.45
A1
0.010
–
0.25
–
A2
0.077
0.083
1.95
2.10
B
0.012
0.018
0.30
0.45
D
0.510
0.530
12.95
13.45
D1
0.390
0.398
9.90
1
10.10
1
0.315 BSC (nominal)
8.00 BSC (nominal)
E
0.510
0.530
12.95
E1
0.390
0.398
9.90
D3
13.45
10.10
E3
1
0.315 BSC (nominal)
8.00 BSC (nominal)
e
1
0.031 BSC (nominal)
0.80 BSC1 (nominal)
L
0.029
0.73
L1
0.041
1
0.063 BSC (nominal)
1
1.03
1
1.60 BSC (nominal)
q3
5°
16°
5°
16°
q
0°
7°
0°
7°
1. BSC—Basic Spacing between Centers.
50
Datasheet