CAT-5 Receiver with Adjustable Line Equalization AD8128 FUNCTIONAL BLOCK DIAGRAM FEATURES AD8128 HPF VIN+ VOUT HPF VIN– LPF VPEAK VGAIN VOFFSET 05699-001 Tuned to compensate for Category-5 (CAT-5) cable losses Up to 100 meters @ 120 MHz 2 voltage-controlled frequency response adjustment pins High frequency peaking adjustment Broadband gain adjustment 2700 V/μs slew rate Low output noise 1.5 mV rms integrated noise (1 GHz) @ 100 meters equalized bandwidth DC output offset adjust Low offset voltage error: 7 mV typ Equalized pass-band ripple ±1 dB to 70 MHz Input: differential or single ended Supply current: 24 mA on ±5 V Small 8-lead 3 mm × 3 mm LFCSP Figure 1. APPLICATIONS Keyboard-video-mouse (KVM) RGB video over unshielded twisted pair (UTP) cable receivers Professional video projection and distribution Security video GENERAL DESCRIPTION The AD8128 is a high speed, differential receiver/equalizer that compensates for the transmission losses of unshielded twisted pair (UTP) CAT-5 cables. Various frequency dependent gain stages are summed together to best approximate the inverse frequency response of CAT-5/CAT-5e cable. An equalized bandwidth of 120 MHz can be achieved for 100 meters of cable. The AD8128 can be used as a standalone receiver/equalizer or in conjunction with the AD8143, triple differential receiver, to provide a complete low cost solution for receiving RGB over UTP cable in such applications as KVM. Low integrated output noise and offset voltage adjust make the AD8128 an excellent choice for dc-coupled wideband RGBover-CAT-5 applications. For systems where the UTP cable is longer than 100 meters, two AD8128s can be cascaded to compensate for up to 200 meters of CAT-5/CAT-5e. The AD8128 is available in a 3 mm × 3 mm 8-lead LFCSP and is rated to operate over the extended temperature range of −40°C to +85°C. The AD8128 has three control pins for optimal CAT-5/CAT-5e compensation. The equalized cable length is directly proportional to the voltage applied to the VPEAK pin, which controls the amount of high frequency peaking. VGAIN adjusts the broadband gain from 0 dB to 3 dB, compensating for the resistive cable loss. VOFFSET allows the output to be shifted by ±2.5 V, adding flexibility for dc-coupled systems. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD8128 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................9 Applications....................................................................................... 1 Input Common-Mode Voltage Range Considerations ............9 Functional Block Diagram .............................................................. 1 Applications..................................................................................... 10 General Description ......................................................................... 1 KVM Applications ..................................................................... 10 Revision History ............................................................................... 2 DC Control Pins......................................................................... 10 Specifications..................................................................................... 3 Cascaded Applications............................................................... 11 Absolute Maximum Ratings............................................................ 4 Exposed Pad (EP)....................................................................... 11 Thermal Resistance ...................................................................... 4 Layout and Power Supply Decoupling Considerations......... 11 ESD Caution.................................................................................. 4 Evaluation Boards ...................................................................... 11 Pin Configuration and Function Descriptions............................. 5 Outline Dimensions ....................................................................... 12 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 12 Test Circuit .................................................................................... 8 REVISION HISTORY 10/05—Revision 0: Initial Version Rev. 0 | Page 2 of 12 AD8128 SPECIFICATIONS TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable, VOFFSET = 0 V, VGAIN and VPEAK set to optimized settings (see Figure 4), unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE –3 dB Large Signal Bandwidth ±1 dB Equalized Bandwidth Flatness Rise/Fall Time Rise/Fall Time Settling Time to 2% Settling Time to 2% Integrated Output Voltage Noise DC PERFORMANCE Input Bias Current VOFFSET Pin Current VGAIN Pin Current VPEAK Pin Current INPUT CHARACTERISTICS Input Differential Voltage Input Common-Mode Voltage Input Resistance Input Capacitance Common-Mode Rejection Ratio (CMRR) ADJUSTMENT PINS VPEAK Input Voltage Maximum Peak Gain VGAIN Input Maximum Broadband Gain VOFFSET Input Range VOFFSET to VOUT Gain OUTPUT CHARACTERISTICS Output Voltage Swing Output Offset Voltage Output Offset Voltage Drift Short-Circuit Output Current POWER SUPPLY Operating Voltage Range Quiescent Supply Current, ICC/IEE Supply Current Drift, ICC/IEE +Power Supply Rejection Ratio (PSRR) −Power Supply Rejection Ratio (PSRR) TEMPERATURE RANGE Conditions Min VOUT = 2 V p-p, 100 meter CAT-5 VOUT = 2 V p-p VOUT = 2 V step, 50 meter CAT-5 VOUT = 2 V step, 100 meter CAT-5 VOUT = 2 V step, 50 meter CAT-5 VOUT = 2 V step, 100 meter CAT-5 VPEAK = 0.9 V, VGAIN = 225 mV, BW = 1 GHz Typ 120 70 2 3.6 26 36.4 1.5 15.5 1.7 2 4.2 Common mode Differential 200 kHz, ΔVOUT/ΔVIN, cm −63 Relative to ground @ 120 MHz, VPEAK = 1 V Relative to ground VGAIN = 1 V Relative to ground 0 VOFFSET = 0 V, RTO 1 3 ±2.5 1 −2.55 −10.9 +7 −5.5 100 −48 −48 −40 +24/−21 +86/−77 −59 −61 μA μA μA μA V V kΩ kΩ pF dB 1 ±4.5 Rev. 0 | Page 3 of 12 24 8.2 3.4 6.8 ±2.8 ±3.0 380 675 1.7 −74 0 Unit MHz MHz ns ns ns ns mV rms 20 @ ±5 V RTO RTO Max V dB V dB V V/V +2.7 +18.7 V mV μV/°C mA ±5.5 +31/−27 V mA μA/°C dB dB °C +85 AD8128 ABSOLUTE MAXIMUM RATINGS Table 2. Rating ±5.5 V ±VS −3 V to +VS ±VS −40°C to +85°C −65°C to +125°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface, which is thermally connected to a copper plane to achieve the specified θJA. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead LFCSP (48.5°C/W) on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a PCB plane. Extra thermal relief is required for operation at high supply voltages. 3.0 Package Type 8-Lead LFCSP θJA 77 θJC 14 Unit °C/W Maximum Power Dissipation The maximum safe power dissipation in the AD8128 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8128. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices potentially causing failure. 2.5 2.0 1.5 1.0 0.5 0 –40 –30 –20 –10 05699-020 Table 3. Thermal Resistance MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Input Voltage VPEAK and VGAIN Control Pins VOFFSET Control Pins Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the 0 10 20 30 40 50 70 80 90 100 110 120 130 Figure 2. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 12 60 AMBIENT TEMPERATURE (°C) AD8128 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN– 2 VGAIN 3 VPEAK 4 PIN 1 INDICATOR AD8128 TOP VIEW (Not to Scale) 8 VS+ 7 VOFFSET 6 VOUT 5 VS– 05699-002 VIN+ 1 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 EP Mnemonic VIN+ VIN− VGAIN VPEAK VS− VOUT VOFFSET VS+ GND Description Positive Equalizer Input Negative Equalizer Input 0 V to 1 V Broadband Gain Control 0 V to 1 V High Frequency Gain Control Negative Power Supply Equalizer Output DC Offset Adjust Positive Power Supply Ground Reference and Thermal Pad (see Exposed Pad (EP) section). Rev. 0 | Page 5 of 12 AD8128 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable, VOFFSET = 0 V, unless otherwise noted. 1.0 2 VOUT = 2V p-p RL = 150Ω 1 0 0.8 –1 MAGNITUDE (dB) 0.7 VPEAK 0.5 0.4 0.3 –4 –5 –6 –8 0.1 0 –3 –7 VGAIN 0.2 –2 0 10 20 30 40 50 60 70 80 90 –9 –10 0.1 100 VPEAK AND V GAIN SETTINGS ARE CONSISTENT WITH OPTIMIZED SETTINGS IN FIGURE 4 VOUT = 2V p-p RL = 150Ω 1 CABLE LENGTH (M) 05699-012 0.6 05699-003 OPTIMIZED VPEAK AND VGAIN (V) 0.9 10 100 300 FREQUENCY (MHz) Figure 4. VPEAK and VGAIN Settings vs. Cable Length Figure 7. Equalized Frequency Response for 50 M Cable 2 30 VPEAK = 1V 20 1 0 10 –1 –10 MAGNITUDE (dB) MAGNITUDE (dB) 0 VPEAK = 0.5V –20 VPEAK = 0V –30 –40 –2 –3 –4 –5 –6 –7 05699-014 –8 –60 –70 0.1 1 10 100 1k –9 –10 0.1 3k VPEAK AND VGAIN SETTINGS ARE CONSISTENT WITH OPTIMIZED SETTINGS IN FIGURE 4 VOUT = 2V p-p RL = 150Ω 1 FREQUENCY (MHz) VGAIN = 1V 100 300 FREQUENCY (MHz) Figure 5. Frequency Response for Various VPEAK Settings Without Cable 10 10 05699-011 –50 Figure 8. Equalized Frequency Response for 100 M Cable 1.5 VGAIN = 0.5V 0 1.0 VGAIN = 0V VPEAK AND VGAIN SETTINGS ARE CONSISTENT WITH OPTIMIZED SETTINGS IN FIGURE 4 0.5 –20 OUTPUT (V) MAGNITUDE (dB) –10 –30 –40 0 –0.5 –50 05699-013 –70 0.1 1 10 100 1k 3k FREQUENCY (MHz) –1.5 05699-010 –1.0 –60 0 20 40 60 80 100 120 140 160 180 TIME (ns) Figure 6. Frequency Response for Various VGAIN Settings Without Cable Rev. 0 | Page 6 of 12 Figure 9. Equalized Pulse Response for 50 M of Cable 200 1.0 VPEAK AND VGAIN SETTINGS ARE CONSISTENT WITH OPTIMIZED SETTINGS IN FIGURE 4 OUTPUT (V) 0.5 0 –0.5 –1.5 05699-009 –1.0 0 20 40 60 80 100 120 140 160 180 200 1.8 1.6 1.4 1.2 1.0 0.8 0.6 VGAIN SETTINGS ARE CONSISTENT WITH OPTIMIZED SETTINGS IN FIGURE 4 0.4 0.2 0 05699-006 1.5 INTEGRATED VOLTAGE NOISE FROM 100kHz TO 1GHz (mV) AD8128 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 450 500 VPEAK (V) TIME (ns) Figure 13. Integrated Voltage Noise vs. VPEAK Figure 10. Equalized Pulse Response for 100 M of Cable 6 40 VPEAK = 0V VGAIN = 0V 30 4 20 VOLTAGE (V) 0 –10 0 –2 OUTPUT –20 –4 –40 –4 05699-008 –30 –3 –2 –1 0 1 2 3 –6 4 INPUT 0 50 100 150 200 250 05699-005 VOUT (mV) 2 10 300 350 400 TIME (ns) VIN, CM (V) Figure 14. Overdrive Recovery Time Figure 11. Output Voltage vs. Common-Mode Input Voltage 20 100 VOLTAGE NOISE (nV/ Hz) VPEAK = 0.9V VGAIN = 0.225V 10 0.1 05699-007 VPEAK = 0V VGAIN = 0V 1 10 100 1k 0 –10 –20 VGAIN = 1V VPEAK = 1V –30 –40 VGAIN = 0V VPEAK = 0V –50 –60 05699-004 COMMON-MODE REJECTION (dB) 10 –70 –80 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Common-Mode Rejection vs. Frequency Figure 12. Voltage Noise vs. Frequency Rev. 0 | Page 7 of 12 1k AD8128 10 POWER SUPPLY REJECTION (dB) 0 VOS = 0V VPEAK = 0V VGAIN = 0V +PSR –10 –20 –PSR –30 –40 –50 –70 0.001 05699-015 –60 0.01 0.1 1 10 1k 100 FREQUENCY (MHz) Figure 16. Power Supply Rejection vs. Frequency TEST CIRCUIT VS+ 1µF VS+ 0.01µF 10µF AD8128 VS+ + VS– 10µF + HPF VIN+ CAT-5 50Ω VOUT HPF 50Ω VIN– VS– VS– VPEAK LPF VGAIN VOFFSET VGAIN VOFFSET 0.01µF 0.01µF 0.01µF Figure 17. Rev. 0 | Page 8 of 12 0.01µF 05699-021 1µF VPEAK AD8128 THEORY OF OPERATION The AD8128 is a high speed, low noise analog line equalizer that compensates for losses in CAT-5/CAT-5e cables up to 100 meters with ±1 dB flatness in the pass band out to 70 MHz (see Figure 8). Two continuously adjustable control voltages alter the frequency response to add flexibility to the system by allowing for the compensation of various cable lengths as well as for variations in the cable itself. The dc control voltage pin VGAIN adjusts ac broadband gain from 0 dB to 3 dB (see Figure 6) to account for dc resistive losses present in the cable. A second dc control voltage pin VPEAK adjusts the amount of high frequency peaking (see Figure 5) from 0 dB to 20 dB. This compensates for the high frequency loss due to the skin effect of the cable. The AD8128 has a high impedance differential input that allows it to receive dc-coupled signals directly from the cable. For systems with very high CMRR specifications, the AD8128 can also be used with a dedicated receiver, such as the AD8130 or AD8143, placed in front of it. The output of the AD8128 is low impedance and is capable of driving a 150 Ω load resistor and up to 20 pF of load capacitance at its output. For systems with high parasitic capacitances at the output, it is recommended that a small series resistor be placed between the output and capacitive load to reduce ringing in the pulse response. The AD8128 is designed to be used in medium-length systems that have stringent low noise requirements as well as longerlength systems that can tolerate more noise. For the mediumlength requirements, a single AD8128 is able to compensate up to 100 meters of cable with only 1.5 mV rms of output noise. For longer-length applications that require equalization of up to 200 meters of cable, two AD8128s can be cascaded together to achieve the desired equalization, while keeping approximately the same pass-band bandwidth, but with a slight degradation in settling time and slew rate. The AD8128 approximates the magnitude response of Equation 1 by summing multiple zero-poles pairs offset at different frequencies. Equalization adjustment due to varying line lengths is done by changing the weighting factors of each of the zero-pole pairs. INPUT COMMON-MODE VOLTAGE RANGE CONSIDERATIONS When using the AD8128 as a receiver, it is important to ensure that the input common-mode (CM) voltage range of the AD8128 stays within the specified range. The input CM level can be easily calculated by adding the CM level of the driver, the amplitude of any sync pulses, and the other possible induced common-mode signals from power lines and fluorescent lights. VICM = VCM + VSYNC + VOTHER For example, when using a single 5 V supply on the drive side, the CM voltage of the line typically becomes the midsupply voltage, VCM = 2.5 V. Furthermore, an addition of a sync signal, VSYNC = 0.5 V, on to the common mode puts the peak CM voltage at 3 V. Assuming that both the driver and receiver have exactly the same ground potential, the signal is marginally below the upper end of the common-mode input range of 3.1 V. Other CM signals that can be picked up by the CAT-5 cable result in exceeding the CM input range of the AD8128. The most effective way of not exceeding the CM level of the AD8128 is to lower the CM level on the driver. In the previous example, this was the primary contributor to the CM input level. If this is not possible, a dedicated receiver with a wider CM input range, such as the AD8130 or AD8143, should be used. The frequency response of the AD8128 approximates the inverse frequency response of a lossy transmission line, which is given by H ( f ) = e kl (1+ j ) f (2) (1) where: f is the frequency. l is the length. k is the line constant. Rev. 0 | Page 9 of 12 AD8128 APPLICATIONS KVM APPLICATIONS In KVM applications, cable equalization typically occurs at the root of the KVM network. In a star configuration, a driver is located at each of the end nodes and a receiver/equalizer is located at the single root node. In a daisy-chain configuration, each of the end nodes are connected to one another, and one of them is connected to the root. Similarly, the drivers are placed on the nodes, and the receivers/equalizers are placed at the root. In both of these aforementioned configurations, three AD8128 receiver/equalizers can be used at the root node to equalize the transmitted red (R), green (G), and blue (B) channels for up to 100 meters of cable. Since the skew between two pairs of cables in CAT-5 is less than 1%, the control pins can be tied together and used as a single set of controls. While these equations give a close approximation of the desired value for each pin, to achieve optimal performance, it may be necessary to adjust these values slightly. Figure 19 and Figure 20 illustrate circuits used to adjust the control pins on the AD8128. In Figure 19, a 1 kΩ potentiometer is used to adjust the control pin voltage between the specified range of 0 V to 1 V. In Figure 20, a 2 kΩ potentiometer is used to control the offset pin from −2.5 V to +2.5 V. For both of these configurations, a ±5V supply is assumed. +5V 4kΩ CONTROL PIN VGAIN OR VPEAK 1kΩ Figure 19. Circuit to Control VGAIN and VPEAK (0 V to 1 V) +5V 1kΩ AD8128 1kΩ VCM VIN+ 50Ω VCM CAT-5 50Ω VCM –5V VOUT HPF VIN– VPEAK VGAIN VOFFSET 05699-016 LPF VDIFF Figure 18. Single Receiver Configuration for CAT-5 Equalizer DC CONTROL PINS The AD8128 uses two control pins (VGAIN and VPEAK) to adjust the equalization based on the length of the cable and one pin (VOFFSET) to adjust the dc output offset. VGAIN is a user-adjustable 0 V to 1 V broadband gain control pin, and VPEAK is a 0 V to 1 V adjustable high frequency gain pin to equalize for the skin effect in CAT-5 cable. The values of both VPEAK and VGAIN are linearly correlated to the length of the cable to be equalized. A simple formula can be used to approximate the desired values for both of these pins. VGAIN = length(m) 425m/V (3) VPEAK = length(m) 110m/V (4) Rev. 0 | Page 10 of 12 OFFSET 0.01µF 05699-018 2kΩ HPF VDIFF 05699-017 0.01µF If the common-mode levels of the inputs permit using the AD8128 as a receiver (see the Input Common-Mode Voltage Range Considerations section), the input signal should be terminated by a 100 Ω shunt resistor between the pairs, or by two 50 Ω shunt resistors with a common-mode tap in the middle. This CM tap can be used to extract the sync information from the signal if sync-on-common-mode is used. Figure 20. Circuit to Control VOFFSET (±2.5 V) AD8128 VS+ VS+ VS+ 1µF 0.01µF 1µF 0.01µF AD8128 VS+ AD8128 VS+ HPF VS– + + HPF VIN+ VIN+ VOUT HPF VIN– VOUT HPF VIN– LPF VGAIN VS– VOFFSET VPEAK LPF VGAIN VS– VOFFSET VPEAK VS– VS– 0.01µF 1µF VOFFSET VGAIN VPEAK 0.01µF 05699-019 1µF Figure 21. Cascaded AD8128 Configuration CASCADED APPLICATIONS To equalize distances longer than the specified 100 meters, the AD8128 can be cascaded to provide equalization for longer distances. When combining two AD8128s in series, it is possible to link the control pins together and use them like a single control pin for up to 200 meters of equalization. In this configuration, it is important to note that some key video specifications can be slightly degraded. By combining two equalizers in series, specifications such as rise time and settling time both increase while 3 dB bandwidth decreases slightly. Also, integrated noise is increased because the second equalizer adds gain. Subjective testing should be done to determine the appropriate setting for the three control pins for optimum equalization. EXPOSED PAD (EP) The 8-lead LFCSP has an exposed paddle on the underside of its body. To achieve the specified thermal resistance, it must have a good thermal connection to one of the PCB planes. The exposed paddle must be soldered to a pad on top of the board connected to an inner plane with several thermal vias. For the AD8128, this pad must also be electrically connected to ground to provide a ground reference to the part. LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS Standard high speed PCB layout practices should be adhered to when designing with the AD8128. A solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins and control pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. EVALUATION BOARDS There are two evaluation boards available for easy characterization of the AD8128. A general-purpose evaluation board consisting of a single AD8128, with an option of also using a dedicated receiver, is available for simple characterization of the part. Additionally, a KVM application specific evaluation board is available. This evaluation board consists of six AD8128s to equalize each of the RGB channels up to 200 meters, a 16-pin 26C32 comparator for sync-on-common-mode extract and a triple op amp to provide additional gain if necessary. Rev. 0 | Page 11 of 12 AD8128 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 1 8 PIN 1 INDICATOR 0.90 MAX 0.85 NOM TOP VIEW 0.50 BSC 1.50 REF 5 1.89 1.74 1.59 4 1.60 1.45 1.30 0.70 MAX 0.65 TYP 12° MAX SEATING PLANE 2.75 BSC SQ PIN 1 INDICATOR 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF Figure 22. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model AD8128ACPZ-R2 1 AD8128ACPZ-RL1 AD8128ACPZ-R71 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05699-0-10/05(0) Rev. 0 | Page 12 of 12 Package Option CP-8-2 CP-8-2 CP-8-2 Branding HZB HZB HZB