MCP651/2/4/5/9
50 MHz, 6 mA Op Amps with mCal
Features
Description
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The Microchip Technology, Inc. MCP651/2/4/5/9 family
of operational amplifiers features low offset. At power
up, these op amps are self-calibrated using mCal.
Some package options also provide a calibration/chip
select pin (CAL/CS) that supports a low power mode of
operation, with offset calibration at the time normal
operation is re-started. These amplifiers are optimized
for high speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
Gain Bandwidth Product: 50 MHz (typical)
Short Circuit Current: 100 mA (typical)
Noise: 7.5 nV/√Hz (typical, at 1 MHz)
Calibrated Input Offset: ±200 µV (maximum)
Rail-to-Rail Output
Slew Rate: 30 V/µs (typical)
Supply Current: 6.0 mA (typical)
Power Supply: 2.5V to 5.5V
Extended Temperature Range: -40°C to +125°C
This family is offered in single with CAL/CS pin
(MCP651), dual (MCP652), dual with CAL/CS pins
(MCP655), quad (MCP654) and quad with CAL/CS
pins (MCP659). All devices are fully specified from
-40°C to +125°C.
Typical Applications
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Driving A/D Converters
Power Amplifier Control Loops
Barcode Scanners
Optical Detector Amplifier
Typical Application Circuit
Design Aids
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R1
VDD/2
SPICE Macro Models
FilterLab® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
R2
R3
VOUT
RL
MCP65X
VIN
Power Driver with High Gain
Package Types
MCP651
SOIC
MCP652
3×3 DFN *
VIN+ 3
6 VOUT
VINA+ 3
VSS 4
5 VCAL
VSS 4
VOUTA
MCP659
4x4 QFN*
8 VDD
EP
9
16 15 14 13
12 VIND+
VINA- 1
VINA+ 2
5
6
7
8
VINB-
VOUTB
CALBC/CSBC
VOUTC
VINB+ 4
© 2011 Microchip Technology Inc.
VOUTA 1
8 VDD
VOUTA 1
VINA– 2
7 VOUTB
6 VINB–
VINA+ 3
5 VINB+
VSS 4
6 VINB–
5 VINB+
VINA- 2
VINA+ 3
VDD 4
MCP655
3×3 DFN *
14 VOUTD
13 VIND12 VIND+
11 VSS
VINB+ 5
VINB- 6
10 VINC+
VOUTB 7
8 VOUTC
9 VINC-
MCP655
MSOP
11 VSS
EP
17
VDD 3
MCP654
SOIC, TSSOP
7 VOUTB
VIND–
VINA– 2
VOUTD
VOUTA 1
7 VDD
NC 1
CALAD/CSAD
8 CAL/CS
VIN– 2
MCP652
SOIC
10 VINC+
VOUTA 1
10 VDD
9 VINC-
VINA– 2
9 VOUTB
VINA+ 3
VSS 4
CALA/CSA 5
EP
11
8 VINB–
7 VINB+
6 CALB/CSB
VOUTA 1
VINA– 2
VINA+ 3
VSS 4
CALA/CSA 5
10 VDD
9 VOUTB
8 VINB–
7 VINB+
6 CALB/CSB
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS22146B-page 1
MCP651/2/4/5/9
NOTES:
DS22146B-page 2
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings †
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Difference Input voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V
1.2
†† See Section 4.2.2 “Input Voltage and Current Limits”.
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
Input Offset Voltage Trim Step
Input Offset Voltage Drift
Power Supply Rejection Ratio
VOS
-200
—
+200
µV
VOSTRM
—
37
200
µV
After calibration (Note 1)
ΔVOS/ΔTA
—
±2.5
—
PSRR
61
76
—
IB
—
6
—
pA
IB
—
130
—
pA
TA= +85°C
TA= +125°C
µV/°C TA= -40°C to +125°C
dB
Input Current and Impedance
Input Bias Current
Across Temperature
IB
—
1700
5,000
pA
Input Offset Current
IOS
—
±1
—
pA
Common Mode Input Impedance
ZCM
—
1013||9
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
Ω||pF
Common-Mode Input Voltage Range
VCMR
VSS − 0.3
—
VDD − 1.3
V
(Note 2)
Common-Mode Rejection Ratio
CMRR
65
81
—
dB
VDD = 2.5V, VCM = -0.3 to 1.2V
CMRR
68
84
—
dB
VDD = 5.5V, VCM = -0.3 to 4.2V
AOL
88
114
—
dB
VDD = 2.5V, VOUT = 0.3V to 2.2V
AOL
94
123
—
dB
VDD = 5.5V, VOUT = 0.3V to 5.2V
VOL, VOH
VSS + 25
—
VDD − 25
mV
VDD = 2.5V, G = +2,
0.5V Input Overdrive
VOL, VOH
VSS + 50
—
VDD − 50
mV
VDD = 5.5V, G = +2,
0.5V Input Overdrive
ISC
±50
±95
±145
mA
VDD = 2.5V (Note 3)
ISC
±50
±100
±150
mA
VDD = 5.5V (Note 3)
Across Temperature
Common Mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Note 1:
2:
3:
Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
See Figure 2-6 and Figure 2-7 for temperature effects.
The ISC specifications are for design guidance only; they are not tested.
© 2011 Microchip Technology Inc.
DS22146B-page 3
MCP651/2/4/5/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
mV
Conditions
Calibration Input
VCALRNG
VSS + 0.1
—
VDD – 1.4
Internal Calibration Voltage
VCAL
0.31VDD
0.33VDD
0.35VDD
Input Impedance
ZCAL
—
100 || 5
—
VDD
2.5
—
5.5
V
IQ
3
6
9
mA
POR Input Threshold, Low
VPRL
1.15
1.40
—
V
POR Input Threshold, High
VPRH
—
1.40
1.65
V
Calibration Input Voltage Range
VCAL pin externally driven
VCAL pin open
kΩ||pF
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
3:
IO = 0
Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
See Figure 2-6 and Figure 2-7 for temperature effects.
The ISC specifications are for design guidance only; they are not tested.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
GBWP
—
50
—
MHz
PM
—
65
—
°
ROUT
—
20
—
Ω
THD+N
—
0.0012
—
%
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
Open-Loop Output Impedance
G = +1
AC Distortion
Total Harmonic Distortion plus Noise
G = +1, VOUT = 4VP-P, f = 1 kHz,
VDD = 5.5V, BW = 80 kHz
Step Response
tr
—
6
—
ns
SR
—
30
—
V/µs
G = +1
Input Noise Voltage
Eni
—
17
—
µVP-P
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
eni
—
7.5
—
nV/√Hz f = 1 MHz
Input Noise Current Density
ini
4
—
fA/√Hz
Rise Time, 10% to 90%
Slew Rate
G = +1, VOUT = 100 mVP-P
Noise
DS22146B-page 4
f = 1 kHz
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
Conditions
CAL/CS Logic Threshold, Low
VIL
VSS
—
0.2VDD
V
CAL/CS Input Current, Low
ICSL
—
0
—
nA
CAL/CS Logic Threshold, High
VIH
0.8VDD
VDD
V
CAL/CS Input Current, High
ICSH
—
0.7
—
µA
CAL/CS = VDD
ISS
-3.5
-1.8
—
µA
Single, CAL/CS = VDD = 2.5V
ISS
-8
-4
—
µA
Single, CAL/CS = VDD = 5.5V
ISS
-5
-2.5
—
µA
Dual, CAL/CS = VDD = 2.5V
Dual, CAL/CS = VDD = 5.5V
CAL/CS Low Specifications
CAL/CS = 0V
CAL/CS High Specifications
GND Current
ISS
-10
-5
—
µA
RPD
—
5
—
MΩ
IO(LEAK)
—
50
—
nA
CAL/CS = VDD
VDD Low to Amplifier Off Time
(output goes High-Z)
tPOFF
—
200
—
ns
G = +1 V/V, VL = VSS,
VDD = 2.5V to 0V step to VOUT = 0.1 (2.5V)
VDD High to Amplifier On Time
(including calibration)
tPON
100
200
300
ms
G = +1 V/V, VL = VSS,
VDD = 0V to 2.5V step to VOUT = 0.9 (2.5V)
CAL/CS Input Hysteresis
VHYST
—
0.25
—
V
CAL/CS Setup Time
(between CAL/CS edges)
tCSU
1
—
—
µs
G = +1 V/V, VL = VSS (Notes 2, 3, 4)
CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2)
CAL/CS High to Amplifier Off Time
(output goes High-Z)
tCOFF
—
200
—
ns
G = +1 V/V, VL = VSS,
CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2)
CAL/CS Low to Amplifier On Time
(including calibration)
tCON
—
3
4
ms
G = +1 V/V, VL = VSS, MCP651 and MCP655,
CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)
tCON
—
6
8
ms
G = +1 V/V, VL = VSS, MCP659,
CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)
CAL/CS Internal Pull Down Resistor
Amplifier Output Leakage
POR Dynamic Specifications
CAL/CS Dynamic Specifications
Note 1:
2:
3:
4:
The MCP652 single, MCP655 dual and MCP659 quad have their CAL/CS inputs internally pulled down to VSS (0V).
This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to low power mode.
For the MCP655 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously
(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in
calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.
For the MCP659 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously (within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and
the maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD
(CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in calibration mode; allow
more than the maximum tCON time (8 ms) before the other side is toggled.
© 2011 Microchip Technology Inc.
DS22146B-page 5
MCP651/2/4/5/9
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Specified Temperature Range
(Note 1)
Thermal Package Resistances
Thermal Resistance, 8L-3×3 DFN
θJA
—
63
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 10L-3×3 DFN
θJA
—
71
—
°C/W
Thermal Resistance, 10L-MSOP
θJA
—
202
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Thermal Resistance, 16L-4x4-QFN
θJA
—
46
—
°C/W
(Note 2)
(Note 2)
Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).
Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
Note 1:
2:
1.3
(Note 2)
Timing Diagram
CAL/CS
VDD
VPRH
tPON
tCSU
tCOFF
VOUT High-Z
On
ISS -3 µA (typical)
-6 mA (typical)
ICS 0 nA (typical)
Note:
VIL
VIH
High-Z
-3 µA (typical)
0.7 µA (typical)
VPRL
tCON
tPOFF
High-Z
On
-6 mA (typical)
-3 µA (typical)
0 nA (typical)
For the MCP655 dual and the MCP659 quad, there is an additional constraint on toggling the two CAL/CS pins close
together; see the TCON specification in Table 1-3.
FIGURE 1-1:
DS22146B-page 6
Timing Diagram.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
1.4
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-2. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
10 kΩ
VP
EQUATION 1-1:
VIN+
G DM = R F ⁄ R G
MCP65X
V CM = ( VP + VDD ⁄ 2 ) ⁄ 2
V OUT = ( V DD ⁄ 2 ) + ( V P – V M ) + V OST ( 1 + G DM )
Where:
GDM = Differential Mode Gain
(V/V)
VCM = Op Amp’s Common Mode
Input Voltage
(V)
© 2011 Microchip Technology Inc.
VDD
CB1
100 nF
VDD/2
CB2
2.2 µF
VIN–
V OST = V IN– – V IN+
VOST = Op Amp’s Total Input Offset
Voltage
RF
10 kΩ
(mV)
VM
RG
10 kΩ
RL
1 kΩ
RF
10 kΩ
CF
6.8 pF
VOUT
CL
20 pF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
DS22146B-page 7
MCP651/2/4/5/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
DC Signal Inputs
Percentage of Occurrences
35%
30%
25%
700
80 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Calibrated at +25°C
Input Offset Voltage (µV)
2.1
20%
15%
10%
5%
0%
FIGURE 2-1:
400
300
Input Offset Voltage.
100
0
-8
-6
-4
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage.
80 Samples
VDD = 2.5V and 5.5V
TA = -40°C to +125°C
Calibrated at +25°C
-10
-2
0
2
4
6
8
50
40
30
20
10
0
-10
-20
-30
-40
-50
10
Input Offset Voltage Drift.
VDD = 5.5V
0.0
80 Samples
TA = +25°C
VDD = 2.5V and 5.5V
No Change
(includes noise)
Calibration
Changed
VDD = 2.5V
FIGURE 2-5:
Output Voltage.
Calibration
Changed
Low Input Common
Mode Headroom (V)
Percentage of Occurrences
FIGURE 2-2:
Representative Part
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage Drift (µV/°C)
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
+125°C
+85°C
+25°C
-40°C
200
80 100
Input Offset Voltage (µV)
Percentage of Occurrences
500
-100
-100 -80 -60 -40 -20 0 20 40 60
Input Offset Voltage (µV)
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Representative Part
Calibrated at VDD = 6.5V
600
-0.1
Input Offset Voltage vs.
1 Lot
Low (VCMR_L – VSS)
-0.2
VDD = 2.5V
-0.3
VDD = 5.5V
-0.4
-0.5
-100 -80 -60 -40 -20 0 20 40 60 80 100
Input Offset Voltage Repeatability (µV)
FIGURE 2-3:
Input Offset Voltage
Repeatability (repeated calibration).
DS22146B-page 8
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
125
FIGURE 2-6:
Low Input Common Mode
Voltage Headroom vs. Ambient Temperature.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
1 Lot
High (VDD – VCMR_H)
CMRR, PSRR (dB)
High Input Common
Mode Headroom (V)
1.4
1.3
VDD = 2.5V
1.2
1.1
VDD = 5.5V
1.0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
125
CMRR, VDD = 5.5V
CMRR, VDD = 2.5V
-50
-25
120
115
VDD = 2.5V
110
105
100
95
-50
10,000
Input Bias, Offset Currents
(pA)
Input Common Mode Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 5.5V.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-40°C
+25°C
+85°C
+125°C
0.0
125
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-11:
DC Open-Loop Gain vs.
Ambient Temperature.
VDD = 5.5V
Representative Part
-0.5
Input Offset Voltage (µV)
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 2.5V.
© 2011 Microchip Technology Inc.
100
VDD = 5.5V
125
Input Common Mode Voltage (V)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-10:
CMRR and PSRR vs.
Ambient Temperature.
DC Open-Loop Gain (dB)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-40°C
+25°C
+85°C
+125°C
-0.4
PSRR
130
VDD = 2.5V
Representative Part
-0.6
Input Offset Voltage (µV)
FIGURE 2-7:
High Input Common Mode
Voltage Headroom vs. Ambient Temperature.
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
110
105
100
95
90
85
80
75
70
65
60
VDD = 5.5V
VCM = VCMR_H
1,000
IB
100
10
-IOS
1
25
45
65
85
105
Ambient Temperature (°C)
125
FIGURE 2-12:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = +5.5V.
DS22146B-page 9
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
160
140
120
100
80
60
40
20
0
-20
-40
-60
1.E-03
1m
TA = +85°C
VDD = 5.5V
100µ
1.E-04
10µ
1.E-05
IB
1µ
1.E-06
100n
1.E-07
10n
1.E-08
IOS
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
2000
Input Bias, Offset Currents
(pA)
Input Current Magnitude (A)
Input Bias, Offset Currents
(pA)
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
1500
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-15:
Input Bias Current vs. Input
Voltage (below VSS).
TA = +125°C
VDD = 5.5V
IB
1000
500
0
IOS
-500
-1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
DS22146B-page 10
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
Other DC Voltages and Currents
14
8
VDD = 5.5V
12
7
VOL – VSS
-IOUT
10
Supply Current
(mA/amplifier)
8
6
4
VDD – VOH
IOUT
VDD = 2.5V
2
2
RL = 1 kΩ
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
FIGURE 2-19:
Supply Voltage.
Supply Current vs. Power
9
VOL – VSS
8
8
6
VDD – VOH
VDD = 2.5V
1.5
Power Supply Voltage (V)
VDD = 5.5V
10
1.0
100
Supply Current
(mA/amplifier)
2
7
VDD = 5.5V
6
5
VDD = 2.5V
4
3
2
1
5.5
5.0
4.5
4.0
3.5
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
vs. Ambient Temperature.
100
80
60
40
20
0
-20
-40
-60
-80
-100
3.0
125
2.5
100
2.0
0
25
50
75
Ambient Temperature (°C)
1.5
-25
0.0
-50
1.0
0
0
0.5
Output Headroom (mV)
+125°C
+85°C
+25°C
-40°C
3
0.5
10
Output Current Magnitude (mA)
12
FIGURE 2-20:
Supply Current vs. Common
Mode Input Voltage.
POR Trip Voltages (V)
1.8
+125°C
+85°C
+25°C
-40°C
1.6
1.4
VPRH
1.2
1.0
VPRL
0.8
0.6
0.4
0.2
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
Output Short Circuit Current
(mA)
4
0
0
FIGURE 2-16:
Ratio of Output Voltage
Headroom to Output Current.
4
5
1
1
14
6
0.0
Ratio of Output Headroom to
Output Current (mV/mA)
2.2
Power Supply Voltage (V)
FIGURE 2-18:
Output Short Circuit Current
vs. Power Supply Voltage.
© 2011 Microchip Technology Inc.
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-21:
Power On Reset Voltages
vs. Ambient Temperature.
DS22146B-page 11
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
25%
144 Samples
VDD = 2.5V and 5.5V
20%
15%
10%
5%
Normalized Internal Calibration Voltage;
VCAL/VDD
FIGURE 2-22:
Normalized Internal
Calibration Voltage.
DS22146B-page 12
33.52%
33.48%
33.44%
33.40%
33.36%
33.32%
33.28%
33.24%
0%
Internal V CAL Resistance (kΩ)
30%
33.20%
Percentage of Occurrences
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
140
120
100
80
60
40
20
0
-50
-25
FIGURE 2-23:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
VCAL Input Resistance vs.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
Frequency Response
0
100
-30
80
-60
∠AOL
-90
-120
| AOL |
20
-150
0
-180
-20
-210
50
40
40
50
30
40
20
30
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
10
125
FIGURE 2-26:
Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
© 2011 Microchip Technology Inc.
Open-Loop Output Impedance (Ω)
GBWP
VDD = 5.5V
VDD = 2.5V
Phase Margin (°)
Gain Bandwidth Product
(MHz)
50
60
70
GBWP
30
60
VDD = 2.5V
20
10
PM
50
40
30
FIGURE 2-28:
Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
60
70
80
VDD = 5.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Open-Loop Gain vs.
PM
90
0
70
80
6.0
60
Frequency (Hz)
90
5.5
FIGURE 2-27:
Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
1.E+1
1.E+5 1.E+6
1.E+7 100M
1.E+8 1.E+9
10 1.E+2
100 1.E+3
1k 1.E+4
10k 100k
1M 10M
1G
FIGURE 2-25:
Frequency.
5.0
10
4.5
30
Common Mode Input Voltage (V)
120
40
20
10M
1.E+7
CMRR and PSRR vs.
60
40
4.0
1M
1.E+6
30
GBWP
Phase Margin (°)
Open-Loop Gain (dB)
FIGURE 2-24:
Frequency.
10k
100k
1.E+4
1.E+5
Frequency (Hz)
50
3.5
1k
1.E+3
Open-Loop Phase (°)
0
100
1.E+2
50
40
3.0
10
60
2.5
20
VDD = 5.5V
VDD = 2.5V
1.5
30
70
1.0
40
60
0.5
50
80
0.0
60
70
PM
-0.5
PSRR+
PSRR-
CMRR
Gain Bandwidth Product
(MHz)
CMRR, PSRR (dB)
70
Gain Bandwidth Product
(MHz)
90
80
Phase Margin (°)
90
2.0
2.3
1000
100
10
G = 101 V/V
G = 11 V/V
G = 1 V/V
1
0.1
1k
10k
100k 1.0E+06
1M
10M 1.0E+08
100M
1.0E+03
1.0E+04
1.0E+05
1.0E+07
Frequency (Hz)
FIGURE 2-29:
Closed-Loop Output
Impedance vs. Frequency.
DS22146B-page 13
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
10
9
8
7
6
5 G = 1 V/V
G = 2 V/V
4 G 4 V/V
3
2
1
0
10p
100p 1.0E-10
1n
10n
1.0E-11
1.0E-09
Normalized Capacitive Load; CL/G (F)
FIGURE 2-30:
Gain Peaking vs.
Normalized Capacitive Load.
DS22146B-page 14
Channel-to-Channel
Separation (dB)
Gain Peaking (dB)
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
150
140
130
120
110
100
90
80
RS = 0Ω
RS = 1 kΩ
70
RS = 10 kΩ
60 RS = 100 kΩ
50
1k
10k
1.E+03
1.E+04
RTI
VCM = VDD/2
G = +1 V/V
100k
1M
1.E+05
1.E+06
Frequency (Hz)
10M
1.E+07
FIGURE 2-31:
Channel-to-Channel
Separation vs. Frequency.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
Input Noise and Distortion
1.E+4
10μ
Input Offset + Noise;
VOS + e ni(t) (µV)
20
1.E+3
1μ
1.E+2
100n
1.E+1
10n
15
Representative Part
NPBW = 0.1 Hz
10
5
0
-5
-10
-15
-20
1n
1.E+0
0.1
1.E-1
1
1.E+0
10
1.E+1
160
Input Noise Voltage Density
THD + Noise (%)
100
VDD = 5.5V
80
60
40
20 25 30
Time (min)
35
40
45
50
VDD = 5.0V
0.1
BW = 22 Hz to > 500 kHz
G = 1 V/V
G = 11 V/V
0.01
0.001
BW = 22 Hz to 80 kHz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.0
0.5
0.0
0.0001
1.E+2
100
Common Mode Input Voltage (V)
FIGURE 2-33:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 100 Hz.
FIGURE 2-36:
1.E+3
1k
1.E+4
10k
Frequency (Hz)
1.E+5
100k
THD+N vs. Frequency.
VDD = 2.5V
VDD = 5.5V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
f = 1 MHz
-0.5
Input Noise Voltage Density
(nV/Hz)
15
f = 100 Hz
0
12
11
10
9
8
7
6
5
4
3
2
1
0
10
1
120
20
5
FIGURE 2-35:
Input Noise plus Offset vs.
Time with 0.1 Hz Filter.
VDD = 2.5V
140
-0.5
Input Noise Voltage Density
(nV/√Hz)
FIGURE 2-32:
vs. Frequency.
0
100 1.E+3
1k 1.E+4
10k 100k
1M 1.E+7
10M
1.E+2
1.E+5 1.E+6
Frequency (Hz)
1.5
Input Noise Voltage Density (nV/Hz)
2.4
Common Mode Input Voltage (V)
FIGURE 2-34:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 1 MHz.
© 2011 Microchip Technology Inc.
DS22146B-page 15
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
2.5
Time Response
VIN
0
Output Voltage (V)
Output Voltage (10 mV/div)
VDD = 5.5V
G=1
VOUT
20
40
60
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
80 100 120 140 160 180 200
Time (ns)
Non-inverting Small Signal
VIN
VOUT
100
200
FIGURE 2-40:
Response.
300 400 500
Time (ns)
600
700
Input, Output Voltages (V)
VIN
VOUT
800
Inverting Large Signal Step
7
VDD = 5.5V
G=1
VDD = 5.5V
G=2
VIN
6
5
VOUT
4
3
2
1
0
-1
0
100
200
Output Voltage (10 mV/div)
FIGURE 2-38:
Step Response.
300 400 500
Time (ns)
600
700
0
800
Non-inverting Large Signal
VDD = 5.5V
G = -1
RF = 499Ω
VOUT
50
100
FIGURE 2-39:
Response.
DS22146B-page 16
150
200 250
Time (ns)
300
350
400
Inverting Small Signal Step
1
2
3
4
5
6
Time (ms)
7
8
9
10
FIGURE 2-41:
The MCP651/2/4/5/9 family
shows no input phase reversal with overdrive.
VIN
0
VDD = 5.5V
G = -1
RF = 499Ω
0
Slew Rate (V/µs)
Output Voltage (V)
FIGURE 2-37:
Step Response.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
60
55
50
45
40
35
30
25
20
15
10
5
0
Falling Edge
VDD = 5.5V
VDD = 2.5V
Rising Edge
-50
-25
FIGURE 2-42:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
Maximum Output Voltage
Swing (VP-P)
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1.E+05
1M
10M
1.E+06
1.E+07
Frequency (Hz)
100M
1.E+08
FIGURE 2-43:
Maximum Output Voltage
Swing vs. Frequency.
© 2011 Microchip Technology Inc.
DS22146B-page 17
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
Calibration and Chip Select Response
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
CAL/CS = VDD
CAL/CS Hysteresis (V)
CAL/CS Current (µA)
2.6
0.35
0.30
0.20
0.10
0.05
0.00
-50
IDD
Op Amp
turns off
Op Amp
turns on
Calibration
starts
CAL/CS
VOUT
0
1
2
3
4 5 6
Time (ms)
7
8
9
8
6
4
2
0
-2
-4
-6
-8
-10
-12
Calibration
starts
Op Amp
turns off
Op Amp
turns on
CAL/CS
VOUT
0
1
2
3
4 5 6
Time (ms)
7
8
9
Power Supply Current;
IDD (mA)
IDD
10
FIGURE 2-46:
CAL/CS Voltage, Output
Voltage and Supply Current (for Side A) vs. Time
with VDD = 5.5V.
DS22146B-page 18
100
125
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
VDD = 5.5V
G=1
VL = 0V
0
25
50
75
Ambient Temperature (°C)
4.0
10
FIGURE 2-45:
CAL/CS Voltage, Output
Voltage and Supply Current (for Side A) vs. Time
with VDD = 2.5V.
11
10
9
8
7
6
5
4
3
2
1
0
-1
CAL/CS Turn On Time (ms)
VDD = 2.5V
G=1
VL = 0V
-25
FIGURE 2-47:
CAL/CS Hysteresis vs.
Ambient Temperature.
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-48:
CAL/CS Turn On Time vs.
Ambient Temperature.
8
CAL/CS Pull-down Resistor
(MΩ)
9
8
7
6
5
4
3
2
1
0
-1
CAL/CS Current vs. Power
Power Supply Current;
IDD (mA)
FIGURE 2-44:
Supply Voltage.
CAL/CS, V OUT (V)
VDD = 2.5V
0.15
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
CAL/CS, V OUT (V)
VDD = 5.5V
0.25
Representative Part
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-49:
CAL/CS’s Pull-down
Resistor (RPD) vs. Ambient Temperature.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS.
1.E-06
CAL/CS = VDD
-1
Output Leakage Current (A)
Negative Power Supply
Current; ISS (µA)
0
-2
-3
-4
+125°C
+85°C
+25°C
-40°C
-5
-6
Power Supply Voltage (V)
FIGURE 2-50:
Quiescent Current in
Shutdown vs. Power Supply Voltage.
© 2011 Microchip Technology Inc.
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-7
CAL/CS = VDD = 5.5V
1.E-07
+125°C
1.E-08
+85°C
1.E-09
1.E-10
+25°C
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
FIGURE 2-51:
Output Voltage.
Output Leakage Current vs.
DS22146B-page 19
MCP651/2/4/5/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP651
SOIC
3.1
PIN FUNCTION TABLE
MCP652
MCP654
MCP655
SOIC DFN SOIC TSSOP MSOP DFN
MCP659
Symbol
QFN
Description
6
2
3
4
1
2
3
4
1
2
3
4
1
2
3
11
1
2
3
11
1
2
3
4
1
2
3
4
16
1
2
11
VOUT, VOUTA
VIN–, VINA–
VIN+, VINA+
VSS
Output (op amp A)
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Negative Power Supply
8
—
—
—
—
5
5
—
CAL/CS,
CALA/CSA
Calibrate/Chip Select Digital Input
(op amp A)
—
—
—
—
—
6
6
—
CALB/CSB
—
—
—
—
—
—
—
15
CALAD/CSAD
—
—
—
—
—
—
—
7
CALBC/CSBC
—
—
—
—
—
—
—
—
—
7
5
5
6
7
—
—
—
—
—
—
8
—
5
6
7
—
—
—
—
—
—
8
—
5
6
7
10
9
8
12
13
14
4
—
5
6
7
10
9
8
12
13
14
4
—
7
8
9
—
—
—
—
—
—
10
—
7
8
9
—
—
—
—
—
—
10
—
4
5
6
10
9
8
12
13
14
3
—
VINB+
VINB–
VOUTB
VINC+
VINCVOUTC
VIND+
VINDVOUTD
VDD
VCAL
1
—
—
—
—
9
—
—
—
—
—
—
—
11
—
17
NC
EP
Calibrate/Chip Select Digital Input
(op amp B)
Calibrate/Chip Select Digital Input
(op amps A and D)
Calibrate/Chip Select Digital Input
(op amps B and C)
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Output (op amp B)
Non-inverting input (op amp C)
Inverting Input (op amp C)
Output (op amp C)
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Output (op amp D)
Positive Power Supply
Calibration Common Mode Voltage
Input
No Internal Connection
Exposed Thermal Pad (EP);
must be connected to VSS
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.2
3.4
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
DS22146B-page 20
Calibration Common Mode
Voltage Input
A low impedance voltage placed at this input (VCAL)
analog input will set the op amps’ common mode input
voltage during calibration. If this pin is left open, the
common mode input voltage during calibration is
approximately VDD/3. The internal resistor divider is
disconnected from the supplies whenever the part is
not in calibration.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
3.5
Calibrate/Chip Select Digital Input
This input (CAL/CS, …) is a CMOS, Schmitt-triggered
input that affects the calibration and low power modes
of operation. When this pin goes high, the part is placed
into a low power mode and the output is high-Z. When
this pin goes low, a calibration sequence is started
(which corrects VOS). At the end of the calibration
sequence, the output becomes low impedance and the
part resumes normal operation.
3.6
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
An internal POR triggers a calibration event when the
part is powered on, or when the supply voltage drops
too low. Thus, the MCP652 parts are calibrated, even
though they do not have a CAL/CS pin.
© 2011 Microchip Technology Inc.
DS22146B-page 21
MCP651/2/4/5/9
NOTES:
DS22146B-page 22
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
4.0
APPLICATIONS
The MCP651/2/4/5/9 family of self-zeroed op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for low cost, low power and high
precision applications. Its low supply voltage, low
quiescent current and wide bandwidth makes the
MCP651/2/4/5/9 ideal for battery-powered applications.
4.1
Calibration and Chip Select
These op amps include circuitry for dynamic calibration
of the offset voltage (VOS).
4.1.1
mCal CALIBRATION CIRCUITRY
The internal mCal circuitry, when activated, starts a
delay timer (to wait for the op amp to settle to its new
bias point), then calibrates the input offset voltage
(VOS). The mCal circuitry is triggered at power-up (and
after some power brown out events) by the internal
POR, and by the memory’s Parity Detector. The power
up time, when the mCal circuitry triggers the calibration
sequence, is 200 ms (typical).
4.1.2
CAL/CS PIN
The CAL/CS pin gives the user a means to externally
demand a low power mode of operation, then to
calibrate VOS. Using the CAL/CS pin makes it possible
to correct VOS as it drifts over time (1/f noise and aging;
see Figure 2-35) and across temperature.
The CAL/CS pin performs two functions: it places the
op amp(s) in a low power mode when it is held high,
and starts a calibration event (correction of VOS) after a
rising edge.
While in the low power mode, the quiescent current is
quite small (ISS = -3 µA, typical). The output is also is in
a High-Z state.
During the calibration event, the quiescent current is
near, but smaller than, the specified quiescent current
(6 mA, typical). The output continues in the High-Z
state, and the inputs are disconnected from the
external circuit, to prevent internal signals from
affecting circuit operation. The op amp inputs are internally connected to a common mode voltage buffer and
feedback resistors. The offset is corrected (using a
digital state machine, logic and memory), and the
calibration constants are stored in memory.
Once the calibration event is completed, the amplifier is
reconnected to the external circuitry. The turn on time,
when calibration is started with the CAL/CS pin, is 3 ms
(typical).
There is an internal 5 MΩ pull-down resistor tied to the
CAL/CS pin. If the CAL/CS pin is left floating, the amplifier operates normally.
© 2011 Microchip Technology Inc.
For the MCP655 dual and the MCP659 quad, there is
an additional constraint on toggling the two CAL/CS
pins close together; see the tCON specification in
Table 1-3. If the two pins are toggled simultaneously, or
if they are toggled separately with an adequate delay
between them (greater than tCON), then the CAL/CS
inputs are accepted as valid. If one of the two pins
toggles while the other pin’s claibration routine is in
progress, then an invalid input occurs and the result is
unpredictable.
4.1.3
INTERNAL POR
This part includes an internal Power On Reset (POR)
to protect the internal calibration memory cells. The
POR monitors the power supply voltage (VDD). When
the POR detects a low VDD event, it places the part into
the low power mode of operation. When the POR
detects a normal VDD event, it starts a delay counter,
then triggers an calibration event. The additional delay
gives a total POR turn on time of 200 ms (typical); this
is also the power up time (since the POR is triggered at
power up).
4.1.4
PARITY DETECTOR
A parity error detector monitors the memory contents
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
POR event is automatically triggered. This will cause
the input offset voltage to be re-corrected, and the op
amp will not return to normal operation for a period of
time (the POR turn on time, tPON).
4.1.5
CALIBRATION INPUT PIN
A VCAL pin is available in some options (e.g., the single
MCP651) for those applications that need the calibration to occur at an internally driven common mode
voltage other than VDD/3.
Figure 4-1 shows the reference circuit that internally
sets the op amp’s common mode reference voltage
(VCM_INT) during calibration (the resistors are disconnected from the supplies at other times). The 5 kΩ
resistor provides over-current protection for the buffer.
To op amp during
calibration
VDD
300 kΩ
VCAL
150 kΩ
VCM_INT
5 kΩ
BUFFER
VSS
FIGURE 4-1:
Input Circuitry.
Common-Mode Reference’s
DS22146B-page 23
MCP651/2/4/5/9
When the VCAL pin is left open, the internal resistor
divider generates a VCM_INT of approximately VDD/3,
which is near the center of the input common mode
voltage range. It is recommended that an external
capacitor from VCAL to ground be added to improve
noise immunity.
When the VCAL pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that common mode input voltage. Make sure that VCAL is within
its specified range.
It is possible to use an external resistor voltage divider
to modify VCM_INT; see Figure 4-2. The internal circuitry
at the VCAL pin looks like 100 kΩ tied to VDD/3. The
parallel equivalent of R1 and R2 should be much
smaller than 100 kΩ to minimize differences in matching and temperature drift between the internal and
external resistors. Again, make sure that VCAL is within
its specified range.
VDD
MCP65X
R1
VCAL
C1
R2
VSS
FIGURE 4-2:
Resistors.
4.2.1
Input
PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
DS22146B-page 24
VDD Bond
Pad
VIN+
Bond
Pad
Bond
VIN–
Pad
Input
Stage
VSS Bond
Pad
FIGURE 4-3:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-4 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
Setting VCM with External
For instance, a design goal to set VCM_INT = 0.1V when
VDD = 2.5V could be met with: R1 = 24.3 kΩ,
R2 = 1.00 kΩ and C1 = 100 nF. This will keep VCAL
within its range for any VDD, and should be close
enough to 0V for ground based applications.
4.2
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VDD
D1
V1
V2
R1
D2
MCP65X
VOUT
R2
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-4:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
© 2011 Microchip Technology Inc.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-5
+I SC Limited
RL = 100Ω
RL = 10Ω
FIGURE 4-6:
120
80
100
60
40
20
0
-20
-40
-60
VOL Limited
-80
The input stage of the MCP651/2/4/5/9 op amps uses
a differential PMOS input stage. It operates at low common mode input voltage (VCM), with VCM up to VDD –
1.3V and down to VSS – 0.3V. The input offset voltage
(VOS) is measured at VCM = VSS – 0.3V and VDD –
1.3V to ensure proper operation. See Figure 2-6 and
Figure 2-7 for temperature effects.
RL = 1 kΩ
-ISC Limited
NORMAL OPERATION
VOH Limited
(VDD = 5.5V)
-100
4.2.3
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-120
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-15. Applications that are high impedance may
need to limit the usable voltage range.
VOUT (V)
MCP651/2/4/5/9
IOUT (mA)
Output Current.
VDD
VIN
MCP65X
VOUT
V SS < V IN, V OUT ≤ VDD – 1.3V
FIGURE 4-5:
Unity Gain Voltage
Limitations for Linear Operation.
4.3
4.3.0.1
Rail-to-Rail Output
Maximum Output Voltage
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
15 mV of the negative rail with a 1 kΩ load tied to
VDD/2.
4.3.0.2
Output Current
Figure 4-6 shows the possible combinations of output
voltage (VOUT) and output current (IOUT). IOUT is
positive when it flows out of the op amp into the
external circuit.
© 2011 Microchip Technology Inc.
DS22146B-page 25
MCP651/2/4/5/9
4.3.0.3
Power Dissipation
Since the output short circuit current (ISC) is specified
at ±100 mA (typical), these op amps are capable of
both delivering and dissipating significant power. Two
common loads, and their impact on the op amp’s power
dissipation, will be discussed.
Figure 4-7 shows a capacitive load (CL), which is
driven by a sine wave with DC offset. The capacitive
load causes the op amp to output higher currents at
higher frequencies. Because the output rectifies IOUT,
the op amp’s dissipated power increases (even though
the capacitor does not dissipate power).
Figure 4-7 shows a resistive load (RL) with a DC output
voltage (VOUT). VL is RL’s ground point, VSS is usually
ground (0V) and IOUT is the output current. The input
currents are assumed to be negligible.
VDD
IDD
IOUT
VOUT
MCP65X
VDD
IDD
ISS
IOUT
VSS
VOUT
MCP65X
RL
ISS
FIGURE 4-8:
Diagram for Capacitive Load
Power Calculations.
The output voltage is assumed to be:
VSS
VL
FIGURE 4-7:
Diagram for Resistive Load
Power Calculations.
The DC currents are:
EQUATION 4-4:
V OUT = V DC + V AC sin ( ω t )
Where:
VDC = DC offset (V)
VAC = Peak output swing (VPK)
EQUATION 4-1:
VOUT – VL
IOUT = -------------------------RL
IDD ≈ IQ + max ( 0, I OUT )
ISS ≈ – I Q + min ( 0, I OUT )
Where:
IQ = Quiescent supply current for one
op amp (mA/amplifier)
VOUT = A DC value (V)
ω = Radian frequency (2π f) (rad/s)
The op amp’s currents are:
EQUATION 4-5:
dVOUT
I OUT = C L ⋅ ----------------- = V AC ω C L cos ( ω t )
dt
I DD ≈ I Q + max ( 0, I OUT )
I SS ≈ – I Q + min ( 0, I OUT )
Where:
The DC op amp power is:
IQ = Quiescent supply current for one
op amp (mA/amplifier)
EQUATION 4-2:
P OA = I DD ( VDD – V OUT ) + I SS ( V SS – V OUT )
The maximum op amp power, for resistive loads at DC,
occurs when VOUT is halfway between VDD and VL or
halfway between VSS and VL:
The op amp’s instantaneous power, average power
and peak power are:
EQUATION 4-6:
P OA = I DD ( V DD – V OUT ) + I SS ( V SS – V OUT )
EQUATION 4-3:
max ( P OA ) = I DD ( VDD – V SS )
2
max ( V DD – V L, VL – VSS )
+ -----------------------------------------------------------------4R L
DS22146B-page 26
CL
4VAC fCL
ave ( POA ) = ( V DD – V SS ) ⎛ IQ + ------------------------⎞
⎝
⎠
π
max ( P OA ) = ( V DD – V SS ) ( IQ + 2V AC fC L )
The power dissipated in a package depends on the
powers dissipated by each op amp in that package:
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
EQUATION 4-7:
n
PPKG =
∑ POA
k=1
Where:
n = Number of op amps in package (1 or 2)
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-9) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
The maximum ambient to junction temperature rise
(ΔTJA) and junction temperature (TJ) can be calculated
using the maximum expected package power (PPKG),
ambient temperature (TA) and the package thermal
resistance (θJA) found in Table 1-4:
EQUATION 4-8:
ΔT JA = PPKG θ JA
T J = T A + ΔT JA
The worst case power de-rating for the op amps in a
particular package can be easily calculated:
EQUATION 4-9:
RG
VOUT
RN
TA = Ambient temperature (°C)
Several techniques are available to reduce ΔTJA for a
given package:
• Reduce θJA
- Use another package
- Improve the PCB layout (ground plane, etc.)
- Add heat sinks and air flow
• Reduce max(PPKG)
- Increase RL
- Decrease CL
- Limit IOUT using RISO (see Figure 4-9)
- Decrease VDD
4.4
4.4.1
Improving Stability
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. See Figure 2-30. A unity gain buffer (G = +1)
is the most sensitive to capacitive loads, though all
gains show the same general behavior.
© 2011 Microchip Technology Inc.
MCP65X
FIGURE 4-9:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-10 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
100
Recommended R ISO (Ω)
TJmax = Absolute maximum junction
temperature (°C)
RISO
CL
T Jmax – T A
P PKG ≤ -------------------------θ JA
Where:
RF
10
GN = +1
GN ≥ +2
1
10p
1.E-11
100p
1n
1.E-10
1.E-09
Normalized Capacitance; CL/GN (F)
10n
1.E-08
FIGURE 4-10:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP651/2/4/5/9 SPICE macro
model are helpful.
4.4.2
GAIN PEAKING
Figure 4-11 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
DS22146B-page 27
MCP651/2/4/5/9
EQUATION 4-10:
RN
VP
Given:
G N1 = 1 + R F ⁄ R G
CN
MCP65X
G N2 = 1 + C G ⁄ C F
VOUT
VM
RG
FIGURE 4-11:
Capacitance.
CG
f F = 1 ⁄ ( 2 π RF C F )
f Z = f F ( G N1 ⁄ G N2 )
We need:
f F ≤ fGBWP ⁄ ( 2G N2 ) , G N1 < GN2
RF
f F ≤ fGBWP ⁄ ( 4G N1 ) , G N1 > GN2
Amplifier with Parasitic
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.4.1 “Capacitive
Loads”) and CG. Figure 4-12 shows the maximum
recommended RF for several CG values.
Maximum Recommended RF
(Ω)
1.E+05
100k
4.5
Power Supply
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
GN > +1 V/V
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
1.E+04
10k
4.6
1k
1.E+03
1.E+02
100
1
FIGURE 4-12:
RF vs. Gain.
10
Noise Gain; GN (V/V)
100
Maximum Recommended
Figure 2-37 and Figure 2-38 show the small signal and
large signal step responses at G = +1 V/V. The unity
gain buffer usually has RF = 0Ω and RG open.
Figure 2-39 and Figure 2-40 show the small signal and
large signal step responses at G = -1 V/V. Since the
noise gain is 2 V/V and CG ≈ 10 pF, the resistors were
chosen to be RF = RG = 499Ω and RN = 249Ω.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the de-stabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in
Equation 4-10.
DS22146B-page 28
High Speed PCB Layout
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PC board
layout techniques will help you achieve the
performance shown in the specifications and Typical
Performance Curves; it will also help you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low speed from high
speed, and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect guard traces
to ground plane at both ends, and in the middle for long
traces.
Use coax cables, or low inductance wiring, to route
signal and power to and from the PCB. Mutual and self
inductance of power wires is often a cause of crosstalk
and unusual behavior.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
4.7
Typical Applications
4.7.1
4.7.3
POWER DRIVER WITH HIGH GAIN
Figure 4-13 shows a power driver with high gain
(1 + R2/R1). The MCP651/2/4/5/9 op amp’s short circuit current makes it possible to drive significant loads.
The calibrated input offset voltage supports accurate
response at high gains. R3 should be small, and equal
to R1||R2, in order to minimize the bias current induced
offset.
R1
VDD/2
R2
H-BRIDGE DRIVER
Figure 4-15 shows the MCP652 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
½ MCP652
VIN
RF
RL
RGT
VOUT
RGB
RL
R3
VOT
RF
RF
VOB
VIN
MCP65X
FIGURE 4-13:
4.7.2
VDD/2
OPTICAL DETECTOR AMPLIFIER
Figure 4-14 shows a transimpedance amplifier, using
the MCP651 op amp, in a photo detector circuit. The
photo detector is a capacitive current source. The op
amp’s input common mode capacitance (5 pF, typical)
acts in parallel with CD. RF provides enough gain to
produce 10 mV at VOUT. CF stabilizes the gain and limits the transimpedance bandwidth to about 1.1 MHz.
RF’s parasitic capacitance (e.g., 0.2 pF for a 0805
SMD) acts in parallel with CF.
CF
1.5 pF
Photo
Detector
ID
100 nA
½ MCP652
Power Driver.
RF
100 kΩ
CD
30pF
H-Bridge Driver.
This circuit automatically makes the noise gains (GN)
equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in
phase). Equation 4-11 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
EQUATION 4-11:
VOT – V OB
G DM ≡ -------------------------------- ≥ 2 V/V
VIN – V DD ⁄ 2
RF
RGT = --------------------------------( G DM ⁄ 2 ) – 1
RF
RGB = ------------------G DM ⁄ 2
VOUT
MCP651
VDD/2
FIGURE 4-14:
Transimpedance Amplifier
for an Optical Detector.
© 2011 Microchip Technology Inc.
FIGURE 4-15:
Equation 4-12 gives the resulting common mode and
differential mode output voltages.
EQUATION 4-12:
VOT + V OB
VDD
--------------------------- = ----------2
2
VDD
V OT – VOB = GDM ⎛ V IN – -----------⎞
⎝
2 ⎠
DS22146B-page 29
MCP651/2/4/5/9
NOTES:
DS22146B-page 30
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP651/2/4/5/9 family of op amps.
5.1
SPICE Macro Model
•
•
•
•
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
The latest SPICE macro model for the MCP651/2/4/5/9
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
5.5
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
Filter-Lab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals”, DS01332
5.3
Some of these application notes, and others, are listed
in the design guide:
5.2
FilterLab® Software
Microchip Advanced Part Selector
(MAPS)
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• “Signal Chain Design Guide”, DS21825
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data sheets, Purchase and Sampling of
Microchip parts.
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their corresponding user’s guides and technical information, visit the
Microchip web site at www.microchip.com/analog
tools.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
© 2011 Microchip Technology Inc.
DS22146B-page 31
MCP651/2/4/5/9
NOTES:
DS22146B-page 32
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
8-Lead DFN (3x3) (MCP652)
Device
XXXX
YYWW
NNN
MCP652
Note: Applies to 8-Lead
3x3 DFN
8-Lead SOIC (150 mil) (MCP651, MCP652)
XXXXXXXX
XXXXYYWW
NNN
XXXX
YYWW
NNN
e3
*
Note:
Example:
Example:
BAFC
1105
256
10-Lead MSOP (MCP655)
Legend: XX...X
Y
YY
WW
NNN
DABP
1105
256
MCP651E
SN e3 1105
256
10-Lead DFN (3x3) (MCP655)
XXXXXX
YWWNNN
Code
DABP
Example:
655EUN
105256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2011 Microchip Technology Inc.
DS22146B-page 33
MCP651/2/4/5/9
6.2
Package Marking Information
14-Lead SOIC (MCP654)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP654)
XXXXXXXX
YYWW
NNN
Example:
MCP654
E/SL
1105256
e3
Example:
654E/ST
1105
256
16-Lead QFN (4x4) (MCP659)
Example:
659
XXXXXXX
XXXXXXX
YWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS22146B-page 34
E/ML e3
1105256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc.
DS22146B-page 35
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22146B-page 36
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
%
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© 2011 Microchip Technology Inc.
DS22146B-page 37
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22146B-page 38
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc.
DS22146B-page 39
MCP651/2/4/5/9
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© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
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1
2
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TOP VIEW
A
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© 2011 Microchip Technology Inc.
DS22146B-page 41
MCP651/2/4/5/9
-
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DS22146B-page 42
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
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c
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© 2011 Microchip Technology Inc.
DS22146B-page 43
MCP651/2/4/5/9
-/
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1
2
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h
b
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c
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1=
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N
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DS22146B-page 44
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
%
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'#(
$
)**%%% *#
© 2011 Microchip Technology Inc.
DS22146B-page 45
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22146B-page 46
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc.
DS22146B-page 47
MCP651/2/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22146B-page 48
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
-0
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EXPOSED
PAD
e
E2
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2
2
1
1
b
TOP VIEW
K
N
N
NOTE 1
L
BOTTOM VIEW
A3
A
A1
@!
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E" 7
('!
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© 2011 Microchip Technology Inc.
DS22146B-page 49
MCP651/2/4/5/9
20-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4 mm Body [QFN]
With 0.40 mm Contact Length
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DS22146B-page 50
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
APPENDIX A:
REVISION HISTORY
Revision B (March 2011)
The following is a list of modifications:
1.
2.
Added the MCP654 and MCP659 amplifiers to
the product family and the related information
throughout the document.
Added the corresponding SOIC (14L), TSSOP
(14L) and QFN (16L) package options and
related information.
Revision A (April 2009)
• Original Release of this Document.
© 2011 Microchip Technology Inc.
DS22146B-page 51
MCP651/2/4/5/9
NOTES:
DS22146B-page 52
© 2011 Microchip Technology Inc.
MCP651/2/4/5/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Device:
Examples:
a) MCP651T-E/SN:
b) MCP652T-E/MF:
MCP651:
MCP651T:
MCP652:
MCP652T:
MCP654:
MCP654T:
MCP655:
MCP655T:
MCP659:
MCP659T:
Single Op Amp
Single Op Amp (Tape and Reel)
(DFN and SOIC)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and SOIC)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(TSSOP and SOIC)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and MSOP)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(QFN)
c) MCP652T-E/SN:
d) MCP654T-E/SL:
e) MCP654T-E/ST:
f) MCP655T-E/MF:
g) MCP655T-E/UN:
h) MCP659T-E/ML:
Temperature Range:
E
Package:
MF
SN
UN
ST
SL
ML
= -40°C to +125°C
Tape and Reel,
Extended Temperature,
8LD SOIC package.
Tape and Reel,
Extended Temperature,
8LD DFN package.
Tape and Reel,
Extended Temperature,
8LD SOIC package.
Tape and Reel,
Extended Temperature,
14LD SOIC package.
Tape and Reel,
Extended Temperature,
14LD TSSOP package.
Tape and Reel,
Extended Temperature,
10LD DFN package.
Tape and Reel,
Extended Temperature,
10LD MSOP package.
Tape and Reel,
Extended Temperature,
16LD QFN package.
=Plastic Dual Flat, No Lead (3x3 DFN),
8-lead, 10-lead
=Plastic Small Outline, (3.90 mm), 8-lead
=Plastic Micro Small Outline, (MSOP), 10-lead
=Plastic Thin Shrink Small Outline, (4.4 mm), 14lead
=Plastic Small Outline, Narrow, (3.90 mm), 14lead
=Plastic Quad Flat, No Lead Package,
(4x4x0.9 mm), 16-lead
© 2011 Microchip Technology Inc.
DS22146B-page 53
MCP651/2/4/5/9
NOTES:
DS22146B-page 54
© 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-024-0
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2011 Microchip Technology Inc.
DS22146B-page 55
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
02/18/11
DS22146B-page 56
© 2011 Microchip Technology Inc.