I2C®-Compatible, Wide Bandwidth, Hex 2:1 Multiplexer ADG796A FEATURES FUNCTIONAL BLOCK DIAGRAM Bandwidth: 325 MHz Low insertion loss and on resistance: 2.6 Ω typical On resistance flatness: 0.3 Ω typical Single 3 V/5 V supply operation 3.3 V analog signal range (5 V supply, 75 Ω load) Low quiescent supply current: 1 nA typical Fast switching times: tON = 186 ns, tOFF = 177 ns I2C-compatible interface Compact 24-lead LFCSP ESD protection 4 kV human body model 200 V machine model 1 kV field-induced charged device model VDD GND ADG796A S1A D1 S1B S2A D2 S2B S3A D3 S3B S4A D4 S4B S5A D5 APPLICATIONS S5B S-Video RGB/YPbPr video switches HDTV Projection TV DVD-R/RW AV receivers S6A D6 S6B A0 A1 SDA SCL 06036-001 I2C SERIAL INTERFACE Figure 1. GENERAL DESCRIPTION The ADG796A is a monolithic CMOS device comprising six 2:1 multiplexer/demultiplexers controlled by a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet offers high switching speed and low on resistance. The ADG796A operates from a single 3 V or 5 V supply voltage and is available in a compact 4 mm × 4 mm body, 24-lead, Pb-free LFCSP. The on resistance profile is very flat over the full analog input range, and wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG796A the ideal switching solution for a wide range of TV applications including S-Video, YPbPr, and RGB video switches. PRODUCT HIGHLIGHTS The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The ADG796A switches exhibit break-before-make switching action. The integrated I2C interface provides a large degree of flexibility in the system design. It has two user adjustable I2C address pins that allow up to four devices on the same bus. This allows the user to expand the capability of the device by increasing the size of the switching array. 1. Wide bandwidth: 325 MHz. 2. Ultralow power dissipation. 3. Extended input signal range. 4. Integrated I2C serial interface. 5. Compact 4 mm × 4 mm, 24-lead, Pb-free LFCSP. 6. ESD protection tested as per ESD Association standards: • • • 4 kV HBM (ANSI/ESD STM5.1-2001) 200 V MM (ANSI/ESD STM5.2-1999) 1 kV FICDM (ANSI/ESD STM5.3.1-1999) Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADG796A TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 16 Applications....................................................................................... 1 Theory of Operation ...................................................................... 17 Functional Block Diagram .............................................................. 1 I2C Serial Interface ..................................................................... 17 General Description ......................................................................... 1 I2C Address.................................................................................. 17 Product Highlights ........................................................................... 1 Write Operation.......................................................................... 17 Revision History ............................................................................... 2 LDSW Bit..................................................................................... 19 Specifications..................................................................................... 3 Power On/Software Reset.......................................................... 19 I2C Timing Specifications............................................................ 7 Read Operation........................................................................... 19 Absolute Maximum Ratings............................................................ 9 Evaluation Board ............................................................................ 20 ESD Caution.................................................................................. 9 Using the ADG796A Evaluation Board .................................. 20 Pin Configuration and Function Descriptions........................... 10 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 23 Test Circuits..................................................................................... 14 REVISION HISTORY 7/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADG796A SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage (IS(OFF)) Drain Off Leakage (ID(OFF)) Channel On Leakage (ID(ON), IS(ON)) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer −3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS (A0, A1, A2)3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN LOGIC INPUTS (SCL, SDA)3 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUTS3 SDA Pin Output Low Voltage, VOL Conditions Min VS = VDD, RL = 1 MΩ VS = VDD, RL = 75 Ω VD = 0 V, IDS = −10 mA, see Figure 18 VD = 0 V to 1 V, IDS = −10 mA, see Figure 18 VD = 0 V IDS = −10 mA VD = 1 V IDS = −10 mA VD = 0 V to 1 V, IDS = −10 mA 0 0 Typ 1 2.2 0.15 0.3 VD = 4 V/1 V, VS = 1 V/4 V, see Figure 19 VD = 4 V/1 V, VS = 1 V/4 V, see Figure 19 VD = VS = 4 V/1 V, see Figure 20 ±0.25 ±0.25 ±0.25 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 25 f = 10 MHz, RL = 50 Ω, see Figure 22 f = 10 MHz, RL = 50 Ω, see Figure 23 186 177 3 1 RL = 50 Ω, see Figure 21 RL = 100 Ω CL = 1 nF, VS = 0 V, see Figure 26 f = 20 kHz CCIR330 test signal CCIR330 test signal Max Unit 4 3.3 3.5 4 0.5 0.6 0.55 V V Ω Ω Ω Ω Ω nA nA nA 250 240 −60 dB −55 −70 325 0.14 5 10 13 27 70 0.32 0.44 dB dB MHz % pC pF pF pF dB % Degrees 2.0 VIN = 0 V to VDD 0.005 3 0.7 × VDD −0.3 VIN = 0 V to VDD ISINK = 3 mA ISINK = 6 mA Floating State Leakage Current Floating State Output Capacitance Rev. 0 | Page 3 of 24 ns ns ns +0.005 0.05 × VDD 3 0.8 ±1 V V μA pF VDD + 0.3 +0.3 × VDD ±1 V V μA V pF 0.4 0.6 ±1 10 V V μA pF ADG796A Parameter POWER REQUIREMENTS IDD Conditions Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400 kHz I2C interface active, fSCL = 3.4 MHz 1 All typical values are at TA = +25°C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. 3 Guaranteed by design, not subject to production test. 2 Rev. 0 | Page 4 of 24 Min Typ 1 Max Unit 0.001 1 μA 0.2 0.7 mA mA ADG796A VDD = 3 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage (IS(OFF)) Drain Off Leakage (ID(OFF)) Channel On Leakage (ID(ON), IS(ON)) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer −3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS (A0, A1, A2)3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN LOGIC INPUTS (SCL, SDA)3 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUTS 3 SDA Pin Output Low Voltage, VOL Conditions Min VS = VDD, RL = 1 MΩ VS = VDD, RL = 75 Ω VD = 0 V, IDS = −10 mA, see Figure 18 VD = 0 V to 1 V, IDS = −10 mA, see Figure 18 VD = 0 V IDS = −10 mA VD = 1 V IDS = −10 mA VD = 0 V to 1 V, IDS = −10 mA 0 0 Typ 1 2.2 0.15 0.3 VD = 2 V/1 V, VS = 1 V/2 V, see Figure 19 VD = 2 V/1 V, VS = 1 V/2 V, see Figure 19 VD = VS = 2 V/1 V, see Figure 20 ±0.25 ±0.25 ±0.25 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 25 f = 10 MHz, RL = 50 Ω, see Figure 22 f = 10 MHz, RL = 50 Ω, see Figure 23 198 195 3 1 RL = 50 Ω, see Figure 21 RL = 100 Ω CL = 1 nF, VS = 0 V, see Figure 26 f = 20 kHz CCIR330 test signal CCIR330 test signal Max Unit 2.2 1.7 4 6 0.6 1.1 2.8 V V Ω Ω Ω Ω Ω nA nA nA 270 260 −60 dB −55 −70 310 0.14 2.5 10 13 27 70 0.28 0.28 dB dB MHz % pC pF pF pF dB % Degrees 2.0 VIN = 0 V to VDD 0.005 3 0.7 × VDD −0.3 VIN = 0 V to VDD +0.005 0.05 × VDD 3 ISINK = 3 mA ISINK = 6 mA Floating State Leakage Current Floating State Output Capacitance 3 Rev. 0 | Page 5 of 24 ns ns ns 0.8 ±1 V V μA pF VDD + 0.3 +0.3 × VDD ±1 V V μA V pF 0.4 0.6 ±1 V V μA pF ADG796A Parameter POWER REQUIREMENTS IDD Conditions Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400kHz I2C interface active, fSCL = 3.4MHz 1 All typical values are at TA = +25°C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. 3 Guaranteed by design, not subject to production test. 2 Rev. 0 | Page 6 of 24 Min Typ 1 Max Unit 0.001 1 μA 0.1 0.2 mA mA ADG796A I2C TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; GND = 0 V; TA = −40°C to +85°C, unless otherwise noted (see Figure 2 for timing diagram). Table 3. Parameter 1 fSCL t1 t2 t3 t4 2 t5 t6 t7 t8 t9 t10 t11 Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Min Max 100 400 Unit kHz kHz 3.4 1.7 4 0.6 MHz MHz μs μs 60 120 4.7 1.3 ns ns μs μs 160 320 250 100 10 0 0 ns ns ns ns ns μs μs 0 0 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 3.45 0.9 1000 300 ns ns μs μs ns μs μs ns μs μs μs μs ns ns ns 80 160 300 300 ns ns ns ns 20 + 0.1 CB 80 160 1000 300 ns ns ns ns 10 20 40 80 ns ns 20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 703 150 Description Serial clock frequency tHIGH, SCL high time tLOW, SCL low time tSU;DAT, data setup time tHD;DAT, data hold time tSU;STA, setup time for a repeated start condition tHD;STA, hold time (repeated) start condition tBUF, bus free time between a stop and a start condition tSU;STO, setup time for stop condition tRDA, rise time of SDA signal tFDA, fall time of SDA signal tRCL, rise time of SCL signal Rev. 0 | Page 7 of 24 ADG796A Parameter 1 t11A t12 tSP 1 2 Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Fast mode High speed mode Min Max 1000 300 Unit ns ns 20 + 0.1 CB 80 160 300 300 ns ns ns ns 10 20 0 0 40 80 50 10 ns ns ns ns 20 + 0.1 CB 10 20 Description tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit tFCL, fall time of SCL signal Pulse width of suppressed spike Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD. A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. Timing Diagram t11 t12 t6 t2 SCL t1 t6 t4 t5 t3 t8 t10 t9 t7 P S S Figure 2. Timing Diagram for 2-Wire Serial Interface Rev. 0 | Page 8 of 24 P 06036-002 SDA ADG796A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Analog, Digital Inputs Continuous Current, S or D Pins Peak Current, S or D Pins Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance 24-Lead LFCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA 300 mA (pulsed at 1 ms, 10% duty cycle max) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. −40°C to +85°C −65°C to +150°C 150°C 30°C/W 300°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 24 ADG796A 24 23 22 21 20 19 GND VDD SDA SCL A0 A1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADG796A TOP VIEW (Not to Scale) 18 17 16 15 14 13 S6A S6B D6 D5 S5B S5A NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 06036-012 S3A S3B D3 D4 S4B S4A 7 8 9 10 11 12 S1A S1B D1 D2 S2B S2A Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mnemonic S1A S1B D1 D2 S2B S2A S3A S3B D3 D4 S4B S4A S5A S5B D5 D6 S6B S6A A1 A0 SCL 22 23 24 SDA VDD GND Function A-Side Source Terminal for Mux 1. Can be an input or output. B-Side Source Terminal for Mux 1. Can be an input or output. Drain Terminal for Mux 1. Can be an input or output. Drain Terminal for Mux 2. Can be an input or output. B-Side Source Terminal for Mux 2. Can be an input or output. A-Side Source Terminal for Mux 2. Can be an input or output. A-Side Source Terminal for Mux 3. Can be an input or output. B-Side Source Terminal for Mux 3. Can be an input or output. Drain Terminal for Mux 3. Can be an input or output. Drain Terminal for Mux 4. Can be an input or output. B-Side Source Terminal for Mux 4. Can be an input or output. A-Side Source Terminal for Mux 4. Can be an input or output. A-Side Source Terminal for Mux 5. Can be an input or output. B-Side Source Terminal for Mux 5. Can be an input or output. Drain Terminal for Mux 5. Can be an input or output. Drain Terminal for Mux 6. Can be an input or output. B-Side Source Terminal for Mux 6. Can be an input or output. A-Side Source Terminal for Mux 6. Can be an input or output. Logic Input. Sets Bit A1 from the least significant bits of the 7-bit slave address. Logic Input. Sets Bit A0 from the least significant bits of the 7-bit slave address. Digital Input, Serial Clock Line. Open drain input used in conjunction with SDA to clock data into the device. External pull-up resistor required. Digital I/O. Bidirectional open drain data line. External pull-up resistor required. Positive Power Supply Input. Ground (0 V) Reference. Rev. 0 | Page 10 of 24 ADG796A TYPICAL PERFORMANCE CHARACTERISTICS 3.0 4.0 VDD = 3.3V, RL = 1MΩ TA = 25°C 1 CHANNEL VDD = 3V, RL = 1MΩ 2.5 VDD = 5.0V VDD = 4.5V VDD = 5.5V 3.0 VDD = 3.3V, RL = 75Ω 2.5 RON (Ω) OUTPUT SIGNAL (V) VDD = 2.7V, RL = 1MΩ 2.0 TA = 25°C 1 CHANNEL 3.5 VDD = 3V, RL = 75Ω 1.5 VDD = 2.7V, RL = 75Ω 2.0 1.5 1.0 1.0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 INPUT SIGNAL (V) 0 0 2.0 2.5 3.0 1.6 7 TA = 25°C 1 CHANNEL 6 VDD = 3V TA = +85°C 5 3.5 VDD = 5V, RL = 75Ω 3.0 RON (Ω) OUTPUT SIGNAL (V) 4.0 1.5 Figure 7. On Resistance vs. VD (VS) with 5 V Supply VDD = 5.5V, RL = 1MΩ VDD = 5V, RL = 1MΩ VDD = 5.5V, RL = 75Ω VDD = 4.5V, RL = 1MΩ 4.5 1.0 VD (VS) (V) Figure 4. Analog Signal Range with 3 V Supply 5.0 0.5 06036-021 0.5 06036-022 0 06038-018 0 0.5 VDD = 4.5V, RL = 75Ω 2.5 2.0 4 TA = –40°C 3 TA = +25°C 1.5 2 1.0 1 0.5 0 1 2 3 4 6 5 INPUT SIGNAL (V) 0.2 0.4 0.6 0.8 1.0 VDD = 3.0V TA = +25°C 1 CHANNEL VDD = 5V 4.0 VDD = 2.7V 1.4 TA = +85°C TA = +25°C 3.5 4 1.2 VD (VS) (V) 4.5 TA = 25°C 1 CHANNEL 5 TA = –40°C 3.0 RON (Ω) VDD = 3.3V 3 2.5 2.0 1.5 2 1.0 1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VD (VS) (V) Figure 6. On Resistance vs. VD (VS) with 3 V Supply 1.8 0 0 0.5 1.0 1.5 VD (VS) (V) 2.0 2.5 3.0 06036-023 0.5 06036-020 RON (Ω) 0 Figure 8. On Resistance vs. VD (VS) for Various Temperatures with 3 V Supply Figure 5. Analog Signal Range with 5 V Supply 6 0 06038-019 0 TA = 25°C 1 CHANNEL Figure 9. On Resistance vs. VD (VS) for Various Temperatures with 5 V Supply Rev. 0 | Page 11 of 24 ADG796A 0 0 TA = 25°C –0.5 VDD = 3V –20 –1.0 VDD = 5V –1.5 CROSSTALK (dB) CHARGE INJECTION (pC) TA = 25°C VDD = 3V/5V –2.0 –2.5 –3.0 –3.5 –4.0 SAME MULTIPLEXER –40 –60 DIFFERENT MULTIPLEXER –80 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SOURCE VOLTAGE (V) –120 0.01 06036-029 –5.0 0.1 1 10 100 1000 100 1000 FREQUENCY (MHz) 06036-032 –4.5 Figure 13. Crosstalk vs. Frequency Figure 10. Charge Injection vs. Source Voltage 220 –1 210 –3 TA = 25°C VDD = 5V tOFF (3V) 190 tON (5V) 160 –40 –20 –7 –9 –11 tOFF (5V) 170 –5 0 –13 20 40 60 80 TEMPERATURE (°C) –15 0.01 0.1 0 TA = 25°C –10 1 CHANNEL VDD = 3V/5V –20 NO DECOUPLING CAPACITORS USED TA = 25°C VDD = 3V/5V –20 –30 PSRR (dB) –40 –60 –80 –40 –50 –60 –70 –80 –100 –120 0.01 0.1 1 10 100 FREQUENCY (MHz) 1000 Figure 12. Off Isolation vs. Frequency –100 0.0001 0.001 0.01 0.1 1 10 FREQUENCY (MHz) Figure 15. PSRR vs. Frequency Rev. 0 | Page 12 of 24 100 1000 06036-024 –90 06036-031 OFF ISOLATION (dB) 10 Figure 14. Bandwidth Figure 11. tON/tOFF vs. Temperature 0 1 FREQUENCY (MHz) 06036-033 180 06036-030 tON/tOFF (ns) ATTENUATION (dB) tON (3V) 200 ADG796A 0.40 1.4 TA = 25°C 0.35 1.2 0.30 1.0 TA = 25°C VDD = 5V VDD = 5V IDD (mA) 0.8 0.20 0.15 0.6 0.4 VDD = 3V 0.2 0.05 0 0 0.1 0.6 1.1 1.6 2.1 2.6 FREQUENCY (MHz) 3.1 –0.2 VDD = 3V 0 1 2 3 4 5 I2C LOGIC INPUT VOLTAGE (V) Figure 17 IDD vs. I2C Logic Input Voltage (SDA, SCL) Figure 16. IDD vs. fCLK Frequency Rev. 0 | Page 13 of 24 6 06036-026 0.10 06036-025 IDD (mA) 0.25 ADG796A TEST CIRCUITS VDD 0.1µF IDS NETWORK ANALYZER V1 50Ω SA S VS D 50Ω SB 06036-003 RON = V1/IDS VS 50Ω VOUT D 50Ω 06036-008 GND Figure 21. Bandwidth Figure 18. On Resistance VDD 0.1µF A S D NETWORK ANALYZER ID (OFF) A VS VD 50Ω S 50Ω 50Ω 06036-004 IS (OFF) VS 50Ω D VOUT 50Ω 06036-009 GND Figure 19. Off Leakage Figure 22. Off Isolation VDD 0.1µF NETWORK ANALYZER S D ID (ON) VD NC = NO CONNECT SX 50Ω A 50Ω VS 06036-005 SY 50Ω VOUT RL 50Ω DY DX GND 50Ω 50Ω Figure 23. Channel-to-Channel Crosstalk Figure 20. On Leakage Rev. 0 | Page 14 of 24 06036-010 NC ADG796A 5V CLOCK PULSES CORRESPONDING TO THE LDSW BITS 0.1µF CLOCK PULSES CORRESPONDING TO THE LDSW BITS VDD VOUT D SCL CL 35pF RL 50Ω VS I2C INTERFACE SDA 50% SCL 50% 90% VOUT tON 50% 90% VGPO 10% SCL 50% 10% tOFF tH tL GND Figure 24. Switching Times 5V CLOCK PULSES CORRESPONDING TO THE LDSW BIT 0.1µF VDD SA SB RL 50Ω CL 35pF VOUT 80% VS I2C INTERFACE SCL 06036-007 SDA tD GND Figure 25. Break-Before-Make Time Delay 5V VDD RS S SWITCH ON D VOUT CL 1nF VS ΔVOUT SWITCH OFF GND Figure 26. Charge Injection Rev. 0 | Page 15 of 24 QINJ = CL × ΔVOUT 06036-011 VS SCL VOUT D 06036-006 S ADG796A TERMINOLOGY On Resistance (RON) The series on-channel resistance measured between the S pin and D pin. On Resistance Match (ΔRON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. On Resistance Flatness (RFLAT(ON)) The variation of on resistance over the specified range produced by the specified analog input voltage change with a constant load current. Channel Off Leakage (IOFF) The sum of leakage currents into or out of an off channel input. Channel On Leakage (ION) The current loss/gain through an on-channel resistance, creating a voltage offset across the device. Input Leakage Current (IIN, IINL, IINH) The current flowing into a digital input when a specified low level or high level voltage is applied to that input. Input/Output Off Capacitance (COFF) The capacitance between an analog input and ground when the switch channel is off. Input/Output On Capacitance (CON) The capacitance between the inputs or outputs and ground when the switch channel is on. Output Off Switching Time (tOFF) The time required for the switch to open. The time is measured from 50% of the falling edge of the LDSW bit to the time the output reaches 10% of the final value. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. Off Isolation The measure of unwanted signal coupling through an off switch. Crosstalk The measure of unwanted signal that is coupled through from one channel to another because of parasitic capacitance. Charge Injection The measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Differential Gain Error The measure of how much color saturation shift occurs when the luminance level changes. Both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified and expressed in %. Differential Phase Error The measure of how much hue shift occurs when the luminance level changes. It can be a negative or positive value and is expressed in degrees of subcarrier phase. Digital Input Capacitance (CIN) The capacitance between a digital input and ground. Output On Switching Time (tON) The time required for the switch channel to close. The time is measured from 50% of the falling edge of the LDSW bit to the time the output reaches 90% of the final value. Input High Voltage (VINH) The minimum input voltage for Logic 1. Input Low Voltage (VINL) The maximum input voltage for Logic 0. Output Low Voltage (VOL) The maximum output voltage for Logic 0. IDD Positive supply current. Rev. 0 | Page 16 of 24 ADG796A THEORY OF OPERATION The ADG796A is a monolithic CMOS device comprising six 2:1 multiplexer/demultiplexers controllable via a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet offers high switching speed and low on resistance. read from, its serial register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. 3. Data transmits over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of the clock signal (SCL) and remain stable during the high period (SCL). This is because a low-tohigh transition when the clock signal is high can be interpreted as a stop event, which ends the communication between the master and the addressed slave device. 4. After transferring all data bytes, the master establishes a stop condition, defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. The on resistance profile is very flat over the full analog input range, and wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG796A the ideal switching solution for a wide range of TV applications. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The integrated serial I2C interface controls the operation of the multiplexers. The ADG796A has many attractive features, such as the ability to individually control each multiplexer and the option of reading back the status of any switch through the I2C interface. The following sections describe these features in more detail. I2C SERIAL INTERFACE The ADG796A is controlled via an I2C-compatible serial bus interface (refer to the I2C-Bus Specification available from Philips Semiconductor) that allows the part to operate as a slave device (no clock is generated by the ADG796A). The communication protocol between the I2C master and the device operates as follows: 1. The master initiates data transfer by establishing a start condition defined as a high-to-low transition on the SDA line while SCL is high. This indicates that an address/data stream follows. All slave devices connected to the bus respond to the start condition and shift in the next eight bits, consisting of a seven bit address (MSB first) plus an R/W bit. This bit determines the direction of the data flow during the communication between the master and the addressed slave device. 2. The slave device whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or I2C ADDRESS The ADG796A has a seven-bit I2C address. The five most significant bits are internally hardwired while the last two bits, A0 and A1, are user adjustable. This allows the user to connect up to four ADG796As to the same bus. The I2C bit map shows the configuration of the seven-bit address. Seven-Bit I2C Address Bit Configuration MSB 1 0 1 0 0 LSB A0 A1 WRITE OPERATION When writing to the ADG796A, the user must begin with an address byte and R/W bit. Next, the switch acknowledges that it is prepared to receive data by pulling SDA low. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCL. Figure 27 illustrates the entire write sequence for the ADG796A. The first data byte (AX7 to AX0) controls the status of the switches, while the LDSW and RESETB bits from the second byte control the operation mode of the device. SCL START CONDITION BY MASTER A0 R/W AX7 AX6 AX5 AX4 AX3 AX2 AX1 AX0 X ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH NOTES 1. X = LOGIC STATE DOES NOT MATTER. Figure 27. Write Operation Rev. 0 | Page 17 of 24 X X X X X RESETB LDSW STOP CONDITION BY MASTER ACKNOWLEDGE BY SWITCH 06036-014 A1 SDA ADG796A Table 6 shows a list of all commands supported by the ADG796A with the corresponding byte that needs to be loaded during a write operation. • Only one switch from a given multiplexer can be on at any given time. • When a sequence of successive commands affects the same switch, only the last command is executed. To achieve the desired configuration, one or more commands can be loaded into the device. Any combination of the commands listed in Table 6 can be used with the following restrictions: Table 6. ADG796A Command List AX7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 X1 X1 X1 X1 X1 X1 0 1 1 AX6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 AX3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 AX2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 AX1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1 AX0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 Addressed Switch S1A/D1, S2A/D2, S3A/D3, S4A/D4, S5A/D5, S6A/D6 off S1A/D1, S2A/D2, S3A/D3, S4A/D4, S5A/D5, S6A/D6 on S1B/D1, S2B/D2, S3B/D3, S4B/D4, S5B/D5, S6B/D6 off S1B/D1, S2B/D2, S3B/D3, S4B/D4, S5B/D5, S6B/D6 on S1A/D1 off S1A/D1 on S1B/D1 off S1B/D1 on S2A/D2 off S2A/D2 on S2B/D2 off S2B/D2 on S3A/D3 off S3A/D3 on S3B/D3 off S3B/D3 on S4A/D4 off S4A/D4 on S4B/D4 off S4B/D4 on S5A/D5 off S5A/D5 on S5B/D5 off S5B/D5 on S6A/D6 off S6A/D6 on S6B/D6 off S6B/D6 on Mux 1 disabled (All switches connected to D1 are off ) Mux 2 disabled (All switches connected to D2 are off ) Mux 3 disabled (All switches connected to D3 are off ) Mux 4 disabled (All switches connected to D4 are off ) Mux 5 disabled (All switches connected to D5 are off ) Mux 6 disabled (All switches connected to D6 are off ) Reserved All muxes disabled Reserved X= Logic state does not matter. Rev. 0 | Page 18 of 24 ADG796A LDSW BIT POWER ON/SOFTWARE RESET The LDSW bit allows the user to control the way the device executes the commands loaded during write operations. The ADG796A executes all commands loaded between two successive write operations that have set the LDSW bit high. The ADG796A has a software reset function implemented by the RESETB bit from the second data byte loaded into the device during a write operation. For normal operation of the multiplexers, this bit should be set high. When RESETB = low or after power-up, the switches from all multiplexers are turned off (open). Setting the LDSW high for every write cycle ensures that the device executes the command immediately after the LDSW bit is loaded into the device. This setting can be used when the desired configuration is achieved by sending a single command or when the switches are not required to be updated at the same time. When the desired configuration requires multiple commands with simultaneous updates, the LDSW bit should be set low while loading the commands, except for the last one when the LDSW bit should be set high. Once the last command with LDSW = high is loaded, the device simultaneously executes all commands received since the last update. READ OPERATION When reading data back from the ADG796A, the user must begin with an address byte and R/W bit. Then, the switch acknowledges that it is prepared to transmit data by pulling SDA low. Following this acknowledgement, the ADG796A transmits two bytes on the next clock edges. These bytes contain the status of the switches, and each byte is followed by an acknowledge bit. A logic high bit represents a switch in the on (close) state while a low represents a switch in the off (open) state. Figure 28 illustrates the entire read sequence. The bit map accompanying Figure 28 shows the relationship between the elements of the ADG796A and the bits that represent their status after a completed read operation. ADG796 Bit Map RB15 S1A/D1 RB14 S1B/D1 RB13 S2A/D2 RB12 S2B/D2 RB11 S3A/D3 RB10 S3B/D3 RB9 S4A/D4 RB8 S4B/D4 RB7 S5A/D5 RB6 S5B/D5 RB5 S6A/D6 RB4 S6B/D6 RB3 - RB2 - RB1 - RB0 - A1 SDA START CONDITION BY MASTER A0 R/W RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH Figure 28. Read Operation Rev. 0 | Page 19 of 24 STOP CONDITION BY MASTER ACKNOWLEDGE BY SWITCH 06036-015 SCL ADG796A EVALUATION BOARD The EVAL-ADG796AEB allows designers to evaluate the high performance of the device with a minimum of effort. This evaluation kit includes a printed circuit board populated with the ADG796A. The evaluation board interfaces to the USB port of a PC or can be used as a standalone evaluation board. Software is available with the evaluation board that allows the user to easily program the ADG796A through the USB port. Schematics of the evaluation board are shown in Figure 29 and Figure 30. The software runs on any PC that has Microsoft® Windows® 2000 or Windows XP installed with a minimum screen resolution of 1200 × 768. USING THE ADG796A EVALUATION BOARD The ADG796A evaluation kit is a test system designed to simplify the evaluation of the device. Each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. A data sheet is also available with the evaluation board offering full information on how to operate the evaluation board. Rev. 0 | Page 20 of 24 Rev. 0 | Page 21 of 24 C13 10µF Figure 29. EVAL-ADG796AEB Schematic, USB Controller Section T4 J5 C3 0.1µF A B AGND C6 0.1µF GND 7 5 8 AGND AGND C7 0.1µF 1 AGND IN1 OUT1 2 OUT2 IN2 6 SD ERROR 3 NR GND 4 U5 C16 0.1µF C8 0.1µF C19 0.1µF T26 AGND C14 10µF C20 0.1µF C21 0.1µF AGND C15 0.1µF 33 34 35 36 37 38 39 40 4 3.3V AGND AGND AGND 3.3V D4 R11 1kΩ 3.3V 6 AGND 8 AGND R1 2.2kΩ SCL_EN C17 22pF AGND AGND U4 S G GND IN2 D1 S1 S2 D2 IN1 VDD 5 6 7 8 Q2 3.3V S G Q1 D 3.3V ADG821 AGND 4 3 1 5 R2 2.2kΩ 2 C10 22pF T28 R32 10kΩ T27 XTAL1 24MHz AGND R31 10kΩ U2 A0 VCC 7 WP 6 A1 A2 SCL 5 VSS SDA 24LC64 C22 0.1µF 4 15 16 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52 29 30 31 1 2 3 4 AGND 3.3V AGND PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 RESET PB4/FD4 *WAKEUP PB5/FD5 PB6/FD6 CLKOUT PB7/FD7 U3 PD0/FD8 CY7C68013-CSP PD1/FD9 D– PD2/FD10 PD3/FD11 D+ PD4/FD12 PA0/INT0 PD5/FD13 PA1/INT1 PD6/FD14 PA2/*SLOE PD7/FD15 PA3/*WU2 CTL0/*FLAGA PA4/FIFOADR0 CTL1/*FLAGB PA5/FIFOADR1 PA6/*PKTEND CTL2/*FLAGC PA7/*FLD/SLCS SDA RDY0/*SLRD SCL RDY1/*SLWR IFCLK XTALOUT RSVD XTALIN R10 10kΩ 13 14 1 2 8 5 9 54 44 42 C23 2.2µF R7 OR C18 0.1µF * DENOTES PROGRAMMABLE POLARITY. AGND C9 0.1µF R6 75Ω 3.3V 3 AGND AGND C4 10µF R5 75Ω 3.3V 2 1 ADP3303-3.3 C5 0.1µF 3.3V D+ AGND IO D– VBUS J1 USB-MINI-B T1 SHIELD AGND J2-2 AGND VDD AGND J2-1 3 7 11 17 27 32 43 55 AVCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND 10 12 26 28 41 53 56 3.3V SCL_EN C2 0.1µF D R12 2.2kΩ AGND R9 2.2kΩ SCL SDA VDD 06036-016 3.3V ADG796A GPO2 PHONO_DUAL GND 2 BOTTOM 3 CASE TOP 5 CASE 4 1 K6 PHONO_DUAL K5 GND 2 BOTTOM 4 3 CASE TOP 5 CASE 1 PHONO_DUAL GND 2 BOTTOM 3 CASE TOP 5 CASE 4 1 K4 R24 R23 R22 R21 R20 R19 1 K7 T16 T17 T15 T14 T13 T12 R25 T11 GND 2 BOTTOM 3 CASE TOP CASE PHONO_DUAL T10 4 5 Rev. 0 | Page 22 of 24 Figure 30. EVAL-ADG796AEB Schematic, Chip Section R13 PHONO_DUAL 5 CASE 3 TOP 4 CASE BOTTOM 1 GND R26 2 T18 K8 R27 T19 12 11 10 9 8 7 T20 25 PADDLE ADG796A 13 14 15 16 17 18 K3 R14 R15 T22 T23 6 5 4 3 2 1 R29 PHONO_DUAL 5 CASE 3 TOP 4 CASE BOTTOM 1 GND 2 R36 0Ω 19 20 21 22 23 24 T21 U1 R34 0Ω K2 R16 R35 0Ω R17 A GPO1 CASE A CASE R28 K9 GND 2 BOTTOM 3 CASE TOP T3 GND 2 BOTTOM 3 CASE TOP T2 1 4 5 PHONO_DUAL 1 4 5 PHONO_DUAL R30 PHONO_DUAL 5 CASE 3 TOP 4 CASE BOTTOM 1 GND T24 2 T7 K1 T8 T25 R18 T9 R3 10kΩ J3 R4 10kΩ J7 J6-2 GPO2 T5 J6-1 J8 GPO1 R8 10kΩ T6 J4-1 J4-3 SCL SDA SCL C1 0.1µF SDA J6-3 J4-2 SCL SDA VDD 06036-017 ADG796A ADG796A OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ PIN 1 INDICATOR 0.60 MAX TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE PIN 1 INDICATOR 19 18 24 1 *2.45 EXPOSED PAD 2.30 SQ 2.15 (BOTTOMVIEW) 13 12 7 6 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 31. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters ORDERING GUIDE Model ADG796ABCPZ-REEL 1 ADG796ABCPZ-500RL71 ADG796ACCPZ-REEL1 ADG796ACCPZ-500RL71 EVAL-ADG796AEB 2 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C I2C Speed 100 kHz, 400 kHz 100 kHz, 400 kHz 100 kHz, 400 kHz, 3.4 MHz 100 kHz, 400 kHz, 3.4 MHz Z = Pb-free part. Evaluation board is RoHS compliant. Rev. 0 | Page 23 of 24 Package Description 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Evaluation Board Package Option CP-24-2 CP-24-2 CP-24-2 CP-24-2 ADG796A NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06036-0-7/06(0) Rev. 0 | Page 24 of 24