DS1776 PI-Bus Transceiver General Description The DS1776 is an octal PI-bus Transceiver. The A to B path is latched. B outputs are open collector with series Schottky diode, ensuring minimum B output loading. B outputs also have ramped rise and fall times (2.5 ns typical), ensuring minimum PI-bus ringing. B inputs have glitch rejection circuitry, 4 ns typical. Designed using National’s Bi-CMOS process for both low operating and disabled power. AC performance is optimized for the PI-Bus inter-operability requirements. The DS1776 is an octal latched transceiver and is intended to provide the electrical interface to a high performance wired-or bus. This bus has a loaded characteristic impedance range of 20Ω to 50Ω and is terminated on each end with a 30Ω to 40Ω resistor. The DS1776 is an octal bidirectional transceiver with open collector B and TRI-STATE ® A port output drivers. A latch function is provided for the A port signals. The B port output Pin Configurations driver is designed to sink 100 mA from 2V and features a controlled linear ramp to minimize crosstalk and ringing on the bus. A separate high level control voltage (VX) is provided to prevent the A side output high level from exceeding future high density processor supply voltage levels. For 5V systems, VX is tied to VCC. Features n n n n n n n Mil-Std-883C qualified Similar to BTL Low power ICCL = 41 mA max B output controlled ramp rate B input noise immunity, typically 4 ns Available in 28-pin DIP, Flatpak and CLCC Pin and function compatible with Signetics 54F776 Pin Configuration Pin Configuration DS010875-2 Logic Symbol DS010875-1 Order Number DS1776E/883 or DS1776J/883 See NS Package E28A or J28B DS010875-3 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS010875 www.national.com DS1776 PI-Bus Transceiver January 1996 MIL-STD-883C DEVICE SPECIFICATIONS Absolute Maximum Ratings (Notes 1, 2) in Low Output State (IO) B0–B7 Current Applied to Output in Low Output State (IO) Storage Temperature Range (TSTG) Lead Temperature (Soldering 10 Sec.) ESD Tolerance: CZAP = 120 pF, RZAP = 1500Ω The 883 specifications are written to reflect the Rel Electrical Test Specifications (RETS) established by National Semiconductor for this product. For a copy of the latest RETS please contact your local National Semiconductor sales office or distributor. Supply Voltage (VCC) VX, VOH Output Level Control Voltage (A Outputs) OEB n, OEA, LE Input Voltage (VI) A0–A7, B0–B7 Input Voltage (VI) Input Current (II) Voltage Applied to Output in High Output State (VO) A0–A7 Current Applied to Output −0.5V to +7.0V −0.5V to +7.0V −0.5V to +7.0V −0.5V to +5.5V −40 mA to +5 mA 40 mA 200 mA −65˚C to +150˚C 260˚C 0.5 kV Operating Conditions Min 4.5 −55 Supply Voltage (VCC) Operating Temp. Range (TA) Input Rise or Fall Times (tr, tf) −0.5V to +VCCV Max 5.5 +125 50 Units V ˚C ns PI Bus Transceiver DS1776 DC Electrical Characteristics VCC = 5V ± 10% (Unless Otherwise Specified) DC testing temp. groups: 1 = +25˚C, 2 = +125˚C, 3 = −55˚C Symbol VIH VIL IOH Parameter High Level Input Except Bn Voltage Bn Low Level Input Except Bn Voltage Bn High Level Output An Low Level Output 1, 2, 3 Bn VOL = 0.5V VOL = 1.15V Current IIK Input Clamp Current IOZ TRI-STATE Output An Leakage Current Bn High Level Output An Min 2 V V 1, 2, 3 VOL Low Output An VCC = Min, VIL = 1.2V Bn VIK Input Clamp www.national.com An VCC = Min, VIL = 0.8V VCC = Min, II = −40 mA 2 −3 mA 100 µA 20 mA mA −18 mA −40 mA ± 70 µA 2.5 VCC V 2.5 VX V 0.5 V 1.15 V −0.5 V 1, 2, 3 Level Voltage V V 100 1, 2, 3 VCC = Min, VIH = 1.9V 0.8 1.45 1, 2, 3 Except An Voltage Max Units 1.6 An VOH Typ (Note 4) 1, 2, 3 An Bn Current IOL Temp. Group VIN = VIH VOH = VCC − 2.0V VCC = Max, OEA = LE VIH = 2.0V, VOH = 2.1V VIN = VIL Current High Level Output Conditions (Notes 3, 5) IOH = − 3 mA VX = VCC IOH = −0.4 mA VX = 3.13V to 3.47V IOL = 20 mA, VX = VCC IOL = 100 mA IOL = 4 mA 1, 2, 3 1, 2, 3 0.4 1, 2, 3 DC Electrical Characteristics (Continued) VCC = 5V ± 10% (Unless Otherwise Specified) DC testing temp. groups: 1 = +25˚C, 2 = +125˚C, 3 = −55˚C Symbol IIH2 IIH1 Parameter Conditions Temp. (Notes 3, 5) Group (Note 4) −1.2 V 1, 2, 3 1 100 µA 0.01 1 mA 0.01 1 mA 20 µA 100 µA Voltage Except An VCC = Min, II = −18 mA Input Current OEBn, OEA, LE VCC = Min, VI = 7.0V at Max An Input Voltage Bn Input Current OEB, OEA, LE VCC = Min, VI = 5.5V VCC = Min, VI = 5.5V VCC = Max, VI = 2.7V at Max B0–B7 VCC = Max, VI = 2.1V OEB, OEA, LE VCC = Max, VI = 0.5V Min Typ Max Units Input Voltage IIL Low Level Input Current Bn IOZH TRI-STATE +IIH Output Current, An VCC = Max, VI = 0.3V VCC = Max, VO = 2.7V 2, 3 −40 µA 1 −20 µA 1, 2, 3 −100 µA 1, 2, 3 70 µA High Level Voltage Applied IOZH TRI-STATE +IIL Output Current, An VCC = Max, VO = 0.5V 1, 2, 3 −70 µA Low Level Voltage Applied IX High Level VCC = Max, VX = VCC, Control Current LE = OEA = OEBn = 2.7V An = 2.7V, Bn = 2.0V VCC = Max, VX = 3.14V & 3.47V, LE = OEA = OEBn = 2.7V, IOS Short-Circuit An An = 2.7V, Bn = 2.0V VCC = Max, Bn = 1.9V, 1, 2, 3 −100 100 µA −10 10 mA −150 mA 1, 2 37 mA 1, 2, 3 1, 2, 3 OEA = 2.0V, OEBn = 2.7V Output Current −60 −75 (Note 6) ICC Supply Current ICCH VCC = Max, VIH (A) = 5.0V ICCH Power Off VCC = Max, VIL(A) = 0.3V VCC = Max, VIL(A) = 0.3V Bn = 2.1V, VCC = 0.0V, Output Current VIL = Max or VIH = Min ICCL ICCZ IOFF 3 41 mA 1, 2, 3 38 mA 1, 2, 3 35 mA 1, 2, 3 100 µA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Unless otherwise specified, VX = VCC for all test conditions. Note 4: All typical values are at VCC = 5V, TA = 25˚C. Note 5: Due to test equipment limitations, actual test conditions are for VIH = 1.9V and for VIL = 1.2V, however the specified test limits and conditions are guaranteed. Note 6: Not more than one output should be shorted at a time. For testing [<i]nfOS the use of high speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature above normal and thereby cause invalid readings in other parameter tests. In any squence of parameter test [<i]nfOStest should be performed last. Note 7: Not more than one output should be shorted at a time. For testing IOS, the use of high speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature above normal and thereby cause invalid readings in other parameter tests. In any squence of parameter test, IOS tests should be performed last. 3 www.national.com AC Electrical Characteristics VCC = 5V ± 10% (Unless otherwise specified) AC testing temp. groups: 1 = +25˚C, 2 = +125˚C, 3 = −55˚C Path Parameter Conditions Temp. Min Max Units Group B-TO-A PATH Propagation Delay B to A tPLH Waveform 1, 2 1, 2, 3 tPHL tPZH Output Enable OEA to A Waveform 3, 4 1, 2, 3 tPZL tPHZ Output Disable OEA to A Waveform 3, 4 1, 2, 3 4.5 17 ns 6 17 ns 4 17 ns 4 17 ns 2 12 ns 2 13 ns 1, 3 2 13 ns 2 2 17 ns 1, 2, 3 2.5 13 ns 1, 3 2 16 ns 2 2 22 ns 1, 2, 3 2 16 ns 1, 3 2 13 ns 2 2 16 ns 1 3.5 14 ns 2 3.5 13 ns 3 3.5 16 ns 1, 3 0.5 5.5 ns 2 0.5 10 ns tPLZ A-TO-B PATH tPLH Propagation Delay A to B Waveform 1, 2 tPHL tPLH Propagation Delay LE to B Waveform 1, 2 tPHL tPLH Enable/Disable OEBn to B Waveform 1, 2 tPHL tTLH Transition Time, B Side tTHL 1.3V to 1.7V 1.7V to 1.3V 1 0.5 5.5 ns 2 0.5 7 ns 3 0.5 10 ns SETUP/HOLD/PULSE WIDTH SPECS tS A to LE Setup Waveform 5 1, 2, 3 7 ns tH A to LE Hold Waveform 5 1, 2, 3 0 ns tW LE Pulse Width Low Waveform 5 1, 2, 3 12 ns Description PIN DESCRIPTION TABLE 1. Pin Description Symbol Pins Type A0 3 I/O A1 5 I/O A2 6 I/O A3 7 I/O A4 9 I/O A5 10 I/O A6 12 I/O A7 13 I/O www.national.com Name and Function TTL Level, latched input/TRI-STATE output (with VX control option) 4 Description (Continued) TABLE 1. Pin Description (Continued) Symbol Pins Type B0 27 I/O Name and Function B1 26 I/O B2 24 I/O B3 23 I/O B4 21 I/O B5 20 I/O B6 19 I/O B7 17 I/O OEB 0 15 I OEB 1 16 I OEA 2 I Enables the A outputs when High LE 28 I VX 14 I Latched when High (a special delay feature is built in for proper enabling times) Clamping voltage keeping VOH from rising above VX (VX = VCC for normal use) Data input with special threshold circuitry to reject noise/Open Collector output, High current drive Enables the B outputs when both pins are low 5 www.national.com Description (Continued) FUNCTION DESCRIPTION DS010875-4 VCC = Pin 1 VX = Pin 14 GND = Pins 4, 8, 11, 18, 22, 25 FIGURE 1. Functional Logic Diagram www.national.com 6 Description (Continued) TABLE 2. Function Table Inputs Latch OEB 0 OEB 1 State L L L L L L H L L L — L H L H H H L — L H H — — H H X L X X An Bn (Note 8) LE OEA H X L L X L X X — — Outputs Mode An Bn H Z H L Z L Qn Z Qn L (Note 10) (Note 8) (Note 8) L H (Note 9) H off (Note 9) L L H (Note 9) L off (Note 9) H L L Qn Qn Qn L L H X H Z off L L H X L Z off X H L H X Qn Z off — H L H H X H H off — L L H H X L L off — H H H H X Qn H off — L H H H X Qn L off H X L L X H H Z off L X L L X H L Z off X X H L X H Qn Z off — H L H X H H H off — L L H X H L L off — H H H X H Qn H off — L H H X H Qn L off A TRI-STATE, Data from A to B A TRI-STATE, Latched Data to B Feedback: A to B, B to A Preconditioned Latch Enabling Data Transfer from B to A Latch State to A and B B off and A TRI-STATE B off, Data from B to A B off and A TRI-STATE B off, Data from B to A H = High Voltage Level L = Low Voltage Level X = Don’t Care — = Input not externally driven Z = High Impedance (off) state Qn = High or Low voltage level one setup time prior to the Low-to-High LE transition Note 8: Condition will cause a feedback loop path; A to B and B to A. Note 9: The latch must be preconditioned such that B inputs may assume a High or Low level while OEB 0 and OEB 1, are Low and LE is high. Note 10: Precaution should be taken to ensure that the B inputs do not float. If they do, they are equal to a Low state. Note 11: off = Applies to “B” (OC) outputs only. Indicates that the outputs are turned off. CONTROLLER POWER SEQUENCING OPERATION The DS1776 has a design feature which controls the output transitions during power up (or down). There are two possible conditions that occur. 1. When LE = Low and OEB n = Low, the B outputs are disabled until the LE circuit can take control. This feature ensures that the B outputs will follow the A inputs and allow only one transition during power up (or down). 2. If LE = High or OEB n = High, then the B outputs still remain disabled during power up (or down). 7 www.national.com Switching Characteristics AC WAVEFORMS DS010875-5 DS010875-6 Waveform 1: Propagation Delay for Data to Output Waveform 2: Propagation Delay for Data to Output DS010875-7 Waveform 3: TRI-STATE Output Enable Time to High Level and Output Disable Time from High Level DS010875-8 Waveform 4: TRI-STATE Output Enable Time to Low Level and Output Disable Time from Low Level DS010875-9 The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 5: Data Setup and Hold Times and LE Pulse Widths TEST CIRCUIT AND WAVEFORMS Test Circuit for TRI-STATE Outputs on A Side DS010875-10 Switch Position Test www.national.com Switch tPLZ, tPZL Closed All Other Open 8 Switching Characteristics (Continued) Test Circuit for TRI-STATE Outputs on B Side Input Pulse Definition DS010875-11 DS010875-12 DEFINITIONS RL = Load resistor 500Ω CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. RU = Pull up resistor Input Pulse Characteristics Amplitude Low V Rep. Rate tW tTLH tTHL A Side 3.0V 0.0V 1 MHz 500 ns 2 ns 2 ns B Side 2.0V 1.0V 1 MHz 500 ns 2 ns 2 ns 9 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Leadless Chip Carrier (E) Order Number DS1776E/883 NS Package Number E28A 28-Lead Ceramic Dual-In-Line Package (J) Order Number DS1776J/883 NS Package Number J28B www.national.com 10 DS1776 PI-Bus Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Ceramic Flatpak (F) Order Number DS1776W/883 NS Package Number WA28D LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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