54ABT543 Octal Registered Transceiver with TRI-STATE ® Outputs General Description The ’ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Features n Back-to-back registers for storage n Bidirectional data path n A and B outputs have current sourcing capability of 24 mA and current sinking capability of 48 mA n Separate controls for data flow in each direction n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Military Drawing (SMD) 5962-9231401 Ordering Code: Military Package Package Description Number 54ABT543J-QML J24A 24-Lead Ceramic Dual-In-Line 54ABT543W-QML W24C 24-Lead Cerpack 54ABT543E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100218-2 DS100218-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100218 www.national.com 54ABT543 Octal Registered Transceiver with TRI-STATE Outputs August 1998 Pin Descriptions Pin Names Description OEAB , OEBA Output Enable Inputs LEAB , LEBA Latch Enable Inputs CEAB , CEBA Chip Enable Inputs A0–A7 Side A Inputs or TRI-STATE Outputs B0–B7 Side B Inputs or TRI-STATE Outputs Functional Description Data I/O Control Table The ’ABT543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB ) input must be low in order to enter data from the A port or take data from the B port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB ) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA , LEBA and OEBA . Inputs Latch Status Output Buffers X Latched High Z X Latched — L X Transparent — X X H — High Z L X L — Driving LEAB OEAB H X X H L CEAB H = High Voltage Level L = Low Voltage Level X = Immaterial Logic Diagram DS100218-3 www.national.com 2 Absolute Maximum Ratings (Note 1) in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output twice the rated IOL (mA) −500 mA 10V Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to +5.5V −0.5V to VCC −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns DC Electrical Characteristics Symbol Parameter ABT543 Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VID Input Leakage Test Typ Units 2.0 54ABT 2.5 54ABT 2.0 54ABT Input HIGH Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Conditions V Recognized HIGH Signal 0.8 V −1.2 V Min Recognized LOW Signal IIN = −18 mA (Non I/O Pins) V Min V Min V 0.0 IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 3) VIN = VCC (Non-I/O Pins) 0.55 4.75 IIH VCC Max 5 µA Max 7 µA Max 100 µA Max −5 µA Max IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) Breakdown Test (I/O) IIL Input LOW Current IIH + IOZH Output Leakage Current 50 µA 0V–5.5V VIN = 0.5V (Non-I/O Pins)(Note 3) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); IIL + IOZL Output Leakage Current −50 µA 0V–5.5V OEAB or CEAB = 2V VOUT = 0.5V (An, Bn); IOS Output Short-Circuit Current −275 mA Max OEAB or CEAB = 2V VOUT = 0V (An, Bn) ICEX Output HIGH Leakage Current 50 µA Max IZZ Bus Drainage Test 100 µA 0.0V ICCLH Power Supply Current 50 µA Max ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max Outputs TRI-STATE ICCT Additional ICC/Input 2.5 mA Max All Others at VCC or GND VI = VCC − 2.1V ICCD Dynamic ICC −100 VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Others at VCC or GND No Load Outputs Open, CEAB 3 www.national.com DC Electrical Characteristics Symbol (Continued) Parameter ABT543 Min Typ Units VCC mA/MHz Max Conditions Max (Note 3) 0.18 and OEAB = GND,CEBA = VCC, One Bit Toggling, 50% Duty Cycle, (Note 4) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Note 3: Guaranteed but not tested. Note 4: For 8-bit toggling. ICCD < 1.4 mA/MHz. DC Electrical Characteristics Symbol Parameter Min Max Units Conditions CL = 50 pF, RL = 500Ω VCC VOLP Quiet Output Maximum Dynamic VOL 1.1 V 5.0 VOLV Quiet Output Minimum Dynamic VOL -0.45 V 5.0 TA = 25˚C (Note 5) TA = 25˚C(Note 5) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Fig. Units No. ns Figure 4 ns Figure 4 ns Figure 6 ns Figure 6 CL = 50 pF Min Max tPLH Propagation Delay 1.6 6.4 1.6 6.2 tPHL An to Bn or Bn to An tPLH Propagation Delay tPHL LEAB to Bn, LEBA to An 1.6 6.6 OEBA or OEAB to An or Bn 1.6 6.4 tPZH Enable Time tPZL LEAB to Bn, LEBA to An 1.3 6.4 OEBA or OEAB to An or Bn 1.8 7.4 tPHZ Disable Time 2.0 7.2 tPLZ CEBA or CEAB to An or Bn 1.5 7.0 www.national.com 4 AC Operating Requirements Symbol 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Parameter Fig. Units No. CL = 50 pF Min tS(H) Setup Time, HIGH or LOW 3.5 tS(L) An or Bn to LEBA or LEAB 3.0 tH(H) Hold Time, HIGH or LOW 2.0 tH(L) An or Bn to LEBA or LEAB 2.0 tS(H) Setup Time, HIGH or LOW 3.3 tS(L) An or Bn to CEAB or CEBA 2.5 tH(H) Hold Time, HIGH or LOW 2.0 tH(L) An or Bn to CEAB or CEBA 2.0 tW(L) Pulse Width, LOW 3.5 Max ns Figure 7 ns Figure 7 ns Figure 7 ns Figure 7 Figure 5 ns Capacitance Typ Units CIN Symbol Input Capacitance Parameter 5.0 pF CI/O(Note 6) Output Capacitance 11.0 pF Conditions: TA = 25˚C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Note 6: CI/O is measured at frequency, f = 1 MHz, PER MIL-STD-883, METHOD 3012. AC Loading DS100218-6 DS100218-4 FIGURE 2. VM = 1.5V Input Pulse Requirements *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tw tr tf 3V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements 5 www.national.com AC Loading (Continued) DS100218-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100218-5 FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100218-7 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100218-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Ceramic Leadless Chip Carrier (L) Order Number 54ABT543E-QML NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package Order Number 54ABT543J-QML NS Package Number J24A 7 www.national.com 54ABT543 Octal Registered Transceiver with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak Package (F) Order Number 54ABT543W-QML NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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