SCHS310 – JANUARY 2001
Inputs Are TTL-Voltage Compatible
Speed of Bipolar FCT, AS, and S, With
CD54ACT04 . . . F PACKAGE
CD74ACT04 . . . E OR M PACKAGE
(TOP VIEW)
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
1A
1Y
2A
2Y
3A
3Y
GND
– Fanout to 15 FCT Devices
– Drives 50-Ω Transmission Lines
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
description
The ‘ACT04 devices contain six independent inverters. The devices perform the Boolean function Y = A.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
PDIP – E
–40°C
40 C to 85°C
85 C
SOIC – M
Tube
CD74ACT04E
Tube
CD74ACT04M
Tape and reel
CD74ACT04M96
TOP-SIDE
MARKING
CD74ACT04E
ACT04M
–55°C to 125°C
CDIP – F
Tube
CD54ACT04F3A
CD54ACT04F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic symbol‡
1A
2A
3A
4A
5A
6A
1
2
1
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
$'!(*&,$(' $+ -** ', + (! )-%$,$(' , *(-,+ ('!(*& ,( +) $!$,$('+ ) * ,# , *&+ (! /+ '+,*-& ',+
+,'* .**',0 *(-,$(' )*( ++$'" ( + '(, ' ++*$%0 $'%-
, +,$'" (! %% )*& , *+
' )*(-,+ (&)%$', ,( 11 %% )*& , *+ * , +, -'% ++ (,# *.$+ '(, ' %% (,# * )*(-,+ )*(-,$('
)*( ++$'" ( + '(, ' ++*$%0 $'%- , +,$'" (! %% )*& , *+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCHS310 – JANUARY 2001
logic diagram, each inverter (positive logic)
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN
MAX
VCC
VIH
Supply voltage
4.5
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
Low-level output current
High-level input voltage
5.5
2
CD54ACT04
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
0.8
High-level output current
VCC
VCC
0
0
10
VCC
VCC
0
0
–24
24
0
2
0.8
–24
Input transition rise or fall rate
CD74ACT04
MIN
24
0
10
0
UNIT
V
V
0.8
V
VCC
VCC
V
–24
mA
V
24
mA
10
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCHS310 – JANUARY 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VI = VIH or VIL
VOL
VI = VIH or VIL
II
ICC
VI = VCC or GND
VI = VCC or GND,
∆ICC
Ci
VI = VCC – 2.1 V
TA = 25°C
MIN
MAX
VCC
CD54ACT04
MIN
MAX
CD74ACT04
MIN
MAX
IOH = –50 µA
IOH = –24 mA
IOH = –50 mA†
4.5 V
4.4
4.4
4.4
4.5 V
3.94
3.7
3.8
IOH = –75 mA†
IOL = 50 µA
5.5 V
4.5 V
0.1
0.1
0.1
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
4.5 V
0.36
0.5
0.44
5.5 V
V
3.85
3.85
5.5 V
V
1.65
5.5 V
IO = 0
UNIT
1.65
5.5 V
±0.1
±1
±1
µA
5.5 V
4
80
40
µA
2.4
3
2.8
mA
10
10
10
4.5 V to 5.5 V
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD
A
0.18
Unit load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A
Y
CD54ACT04
CD74ACT04
MIN
MAX
MIN
MAX
2.3
9.3
2.4
8.5
2.3
9.3
2.4
8.5
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
UNIT
105
pF
3
SCHS310 – JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
S1
R1 = 500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 50 pF
(see Note A)
R2 = 500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
3V
1.5 V
Input
LOAD CIRCUIT
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
3V
Reference
Input
3V
1.5 V
1.5 V
0V
0V
trec
Data
Input
3V
1.5 V
CLK
th
tsu
1.5 V
10%
90%
90%
tr
0V
VOLTAGE WAVEFORMS
RECOVERY TIME
3V
1.5 V
10% 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3V
Input
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
50%
10%
90%
90%
tr
90%
1.5 V
1.5 V
0V
tPHL
tPHL
Out-of-Phase
Output
3V
Output
Control
VOH
50% VCC
10%
VOL
tf
tPLH
50% VCC
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
tPZL
20% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
≈VCC
20% VCC
VOL
80% VCC
VOH
80% VCC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
or services does not constitute TI’s approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated