DS25BR440
3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis
and Receive Equalization
General Description
Features
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR440 features two levels of transmit pre-emphasis (PE) and two levels of receive equalization (EQ). Both of
these features compensate for interconnect losses and ultimately maximize noise margin. A loss-of-signal (LOS) circuit
monitors each input channel and a unique LOS pin is asserted
when no signal is detected at that input
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device return losses,
reduce component count and further minimize board space.
■ DC - 3.125 Gbps low jitter, low skew, low power operation
■ Pin selectable transmit pre-emphasis and receive
equalization eliminate data dependant jitter
■ Wide input common mode voltage range allows DC-
coupled interface to LVDS, CML and LVPECL drivers
■ LOS circuitry detects open inputs fault
■ Integrated 100Ω input and output terminations
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 6 mm x 6 mm LLP-40 space saving package
Applications
■
■
■
■
Clock and data buffering and repeating
Copper cable driving and equalization
FR-4 equalization
OC-48 / STM-16
Typical Application
30007303
© 2008 National Semiconductor Corporation
300073
www.national.com
DS25BR440 3.125 Gbps Quad LVDS Buffer with Pre-Emphasis and Equalization
February 11, 2008
DS25BR440
Ordering Code
NSID
Function
DS25BR440TSQ
Quad Buffer / Repeater
Available Equalization
Levels
Available Pre-Emphasis
Levels
Off / On
Off / On
Block Diagram
30007301
Connection Diagram
30007302
DS25BR440 Pin Diagram
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2
DS25BR440
Pin Descriptions
Pin Name
Pin
Number
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EQ0, EQ1,
EQ2, EQ3
40, 39,
11, 12
I, LVCMOS
Receive equalization level select pins.
PE0, PE1,
PE2, PE3
31, 20,
19, 18
I, LVCMOS
Transmit pre-emphasis level select pins.
PWDN0,
PWDN1,
PWDN2,
PWDN3
35,
34,
33,
32
I, LVCMOS
Channel output power down pins. When the PWDNn is set to L,
the channel output OUTn is in the power down mode. The LOS
circuitry on the corresponding input remains enabled.
LOS0, LOS1,
LOS2, LOS3
14, 37,
36, 13
O, LVCMOS
Loss Of Signal output pins, LOSn report when an open input fault
condition is detected at the input, INn. These are open drain
outputs. External pull up resistors are required.
NC
17
NC
NO CONNECT pins. May be left floating.
PWDN
38
I, LVCMOS
Device power down pin. When the PWDN is set to L, the device
is in the power down mode. The LOS circuitry is disabled as well.
VDD
3, 8,
Power
15,25, 30
Power supply pins.
GND
16, DAP
Ground pin and a pad (DAP - die attach pad).
Power
3
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DS25BR440
Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
θJA
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+26.9°C/W
θJC
ESD Susceptibility
HBM (Note 1)
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Input Voltage
−0.3V to +4V
LVDS Differential Input Voltage
0.0V to +1V
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage
0.0V to +1V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
2.44W
Derate SQA Package
19.49 mW/°C above +25°C
+3.8°C/W
≥8 kV
≥250V
≥1250V
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Supply Voltage (VCC)
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
Min
3.0
0
Typ
3.3
Max
3.6
1
Units
V
V
−40
+25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
0
±10
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
0
±10
μA
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
VOL
Low Level Output Voltage
IOL= 4 mA
0.26
0.4
V
1
V
0
+100
mV
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = +3.6V or 0V
VCC = 3.6V or 0V
±1
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
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0
VCM = +0.05V or VCC-0.05V
−100
4
0
0.05
mV
VCC 0.05
V
±10
μA
Parameter
Conditions
Min
Typ
Max
Units
250
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
IOS
Output Short Circuit Current (Note 8)
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
RL = 100Ω
-35
1.05
1.2
-35
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC
Supply Current
PE = OFF, EQ = OFF
PWDN = H
162
190
mA
ICCZ
Power Down Supply Current
PWDN = L
55
63
mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
5
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DS25BR440
Symbol
DS25BR440
AC Electrical Characteristics
(Notes 9, 10)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
390
600
ps
400
600
ps
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
High (Note 11)
tPHLD
Differential Propagation Delay High to
Low (Note 11)
tSKD1
Pulse Skew |tPLHD − tPHLD|
(Notes 11, 12)
10
50
ps
tSKD2
Channel to Channel Skew
(Notes 11, 13)
18
65
ps
tSKD3
Part to Part Skew
(Notes 11, 14)
50
170
ps
tLHT
Rise Time (Note 11)
80
160
ps
tHLT
Fall Time (Note 11)
80
160
ps
tON
Any PWDN to Output Active Time
8
20
μs
tOFF
Any PWDN to Output Inactive Time
5
12
ns
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE WITH EQ = Off, PE = Off (Note 11) (Figure 5)
tRJ1
tRJ2
tDJ1
tDJ2
tTJ1
tTJ2
Random Jitter (RMS Value)
No Test Channels
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
No Test Channels
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
6
22
ps
3.125 Gbps
10
29
ps
Total Jitter (Peak to Peak)
No Test Channels
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.04
0.09
UIP-P
3.125 Gbps
0.06
0.14
UIP-P
JITTER PERFORMANCE WITH EQ = Off, PE = On (Note 11) (Figures 6, 9)
tRJ1B
tRJ2B
tDJ1B
tDJ2B
tTJ1B
tTJ2B
Random Jitter (RMS Value)
Test Channel B
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Test Channel B
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
7
15
ps
3.125 Gbps
4
23
ps
Total Jitter (Peak to Peak)
Test Channel B
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.05
0.10
UIP-P
3.125 Gbps
0.06
0.14
UIP-P
JITTER PERFORMANCE WITH EQ = On, PE = Off (Note 11) (Figures 7, 9)
tRJ1D
tRJ2D
tDJ1D
tDJ2D
tTJ1D
tTJ2D
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Random Jitter (RMS Value)
Test Channel D
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Test Channel D
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
14
30
ps
3.125 Gbps
15
30
ps
Total Jitter (Peak to Peak)
Test Channel D
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.15
UIP-P
3.125 Gbps
0.10
0.17
UIP-P
6
Parameter
Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH EQ = On, PE = On (Note 11) (Figures 8, 9)
tRJ1BD
tRJ2BD
tDJ1BD
tDJ2BD
tTJ1BD
tTJ2BD
Random Jitter (RMS Value)
Input Test Channel D
Output Test Channel B
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
11
23
ps
3.125 Gbps
5
24
ps
Total Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.14
UIP-P
3.125 Gbps
0.10
0.20
UIP-P
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
7
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DS25BR440
Symbol
DS25BR440
DC Test Circuits
30007320
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30007321
FIGURE 2. Differential Driver AC Test Circuit
30007322
FIGURE 3. Propagation Delay Timing Diagram
30007323
FIGURE 4. LVDS Output Transition Times
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8
DS25BR440
Pre-Emphasis and Equalization Test Circuits
30007329
FIGURE 5. Jitter Performance Test Circuit
30007327
FIGURE 6. Pre-emphasis Performance Test Circuit
30007326
FIGURE 7. Equalization Performance Test Circuit
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DS25BR440
30007330
FIGURE 8. Pre-emphasis and Equalization Performance Test Circuit
30007328
FIGURE 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7 and Loss Tangent of 0.02). The edge coupled
differential striplines have the following geometries: Trace
Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
500 MHz
750 MHz
1000 MHz
1250 MHz
1500 MHz
1560 MHz
A
10
-1.2
-1.7
-2.0
-2.4
-2.7
-2.8
B
20
-2.6
-3.5
-4.1
-4.8
-5.5
-5.6
C
30
-4.3
-5.7
-7.0
-8.2
-9.4
-9.7
D
15
-1.6
-2.2
-2.7
-3.2
-3.7
-3.8
E
30
-3.4
-4.5
-5.6
-6.6
-7.7
-7.9
F
60
-7.8
-10.3
-12.4
-14.5
-16.6
-17.0
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Insertion Loss (dB)
10
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy
FR-4 printed circuit board backplanes and balanced cables.
The DS25BR440 has a pre-emphasis control pin for each
output for switching the transmit pre-emphasis to ON and
OFF setting and an equalization control pin for each input for
switching the receive equalization to ON and OFF setting. The
following are the transmit pre-emphasis and receive equalization truth tables.
Transmit Pre-emphasis Truth Table
OUTPUT OUTn, n = {0, 1, 2, 3}
CONTROL Pin (PEn) State
Pre-emphasis Level
0
OFF
1
ON
Transmit Pre-emphasis Level Selection for an Output OUTn
Receive Equalization Truth Table
INPUT INn, n = {0, 1, 2, 3}
CONTROL Pin (EQn) State
Equalization Level
0
OFF
1
ON
Receive Equalization Level Selection for an Input INn
11
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DS25BR440
Functional Description
DS25BR440
drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS25BR440 inputs are internally
terminated with a 100Ω resistor.
Input Interfacing
The DS25BR440 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS25BR440 can be DC-coupled with all common differential
30007331
Typical LVDS Driver DC-Coupled Interface to an DS25BR440 Input
30007332
Typical CML Driver DC-Coupled Interface to an DS25BR440 Input
30007333
Typical LVPECL Driver DC-Coupled Interface to an DS25BR440 Input
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12
The DS25BR440 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DCcoupled interface to common differential receivers and
30007334
Typical DS25BR440 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
13
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DS25BR440
assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
Output Interfacing
DS25BR440
Typical Performance
30007350
30007355
Total Jitter as a Function of Data Rate
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and PE Level
30007351
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and EQ Level
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30007357
Supply Current as a Function of Data Rate and PE Level
14
DS25BR440
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25BR440TSQ
NS Package Number SQA40A
(See AN-1187 for PCB Design and Assembly Recommendations)
15
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DS25BR440 3.125 Gbps Quad LVDS Buffer with Pre-Emphasis and Equalization
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