® DEM-PCM1760 EVALUATION FIXTURE FPO FEATURES DESCRIPTION ● COMPLETE 20-BIT STEREO A/D CONVERSION SYSTEM ● 20-BIT A/D CONVERTER: PCM1760 The DEM-PCM1760 is an evaluation fixture for the PCM1760/DF1760 (20-bit stereo analog-to-digital conversion system) primarily intended for quick evaluation of the PCM1760/DF1760’s spectral purity and sound fidelity. ● HIGH PERFORMANCE DIGITAL FILTER: DF1760 ● SERIAL DIGITAL INTERFACE ● HIGH PERFORMANCE THD+N (F/S): 0.0015% Dynamic Range: 108dB (EIAJ) S/N Ratio: 108dB (EIAJ) ● ANALOG INPUT: ±2.5V ● POWER SUPPLY: ±5V, +5V ● DIRECT INTERFACE TO DEM-PCM1702 ● BOARD SIZE: 182mm x 128mm International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1994 Burr-Brown Corporation The PCM1760 is provided for evaluation with ±5V analog power supply and the DF1760 is provided for evaluation with +5V digital power supply. The input to the DEM-PCM1760 is ±2.5V full scale analog signal and output from the DEM-PCM1760 is a serial digital interface signal consisting of SYSCLK, SCLK, SDATA, and L/R. The output digital data format is selectable and the operation mode is also selectable by function switches on the board. • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 LI-428 Printed in U.S.A. July, 1994 BLOCK DIAGRAM 20-Bit ADC Digital Filter SYSCLK Analog In Lch SCLK PCM1760 DF1760 SDATA Digital I/O L/R Analog In Rch FSYNC System Clock (256Fs) VCC (+5V) VCC (–5V) VDD (+5V) AGND DGND COMPONENT LOCATION AND FUNCTION Power Supply For Analog: ±5V –VCC +VCC Power Supply For Digital: +5V AGND +VDD AGND System Clock Power Down Switch Calibration Selection Switch Pin Configuration of Connector 1 2 VDD (+5V) DGND SYSCLK Operation Mode Switch DF1760 SCLK 182mm SDATA L/R PCM1760 FSYNC AGND VCC (–5V) VCC (+5V) Analog In Rch Analog In Lch 19 20 Interface Connection (BNC) (BNC) 128mm ® DEM-PCM1760 2 C L K S E L S M NAME FUNCTION H L CLKSEL Master Clock Select 265fs 384fs S/M Slave/Master Select Slave Master M / M1, M2 M 1 Output Format Table of Below 1 L H H L L H (Standard Position) OUTPUT FORMAT M1 M2 MSB First, 16-Bit, Falling Edge H H MSB First, 20-Bit, Falling Edge L H MSB First, 20-Bit, Rising Edge H L MSB First, 20-Bit, Falling Edge L L NOTE: The detailed timing information of output format is referred to the data sheet of PCM1760/DF1760. FIGURE 1. Operation Mode Select Switch. COMBINATION WITH DEM-PCM1702 CALIBRATION SELECT SWITCH (CALD) L The DEM-PCM1760 can be directly combined with the DEM-PCM1702 (20-bit stereo D/A conversion system) through the interface connector on the board. In this case, the power supply should be connected to the DEM-PCM1702 and jumper line should be connected between the connector pin of the DEM-PCM1760 and the connector pin of the DEM-PCM1702. The power supply for the DEM-PCM1760 is supplied from the DEM-PCM1702 through the jumper line and the DEMPCM1760 outputs serial data for the DEM-PCM1702. H: Calibration off L: Calibration on H POWER DOWN SWITCH (PD) L H: Normal Mode L: Power Down Mode and Trigger of Calibration CALD = L, (Start at Rising Edge of PD) H Power Supply for Digital: +5V Power Supply for Analog: ±9V to ±12V Jumper Line JP DEM-PCM1760 DEM-PCM1702 JP CN1 CN1 CN2 CN2 Analog In Analog Out FIGURE 2. ® 3 DEM-PCM1760 (–5V) –VCC (+5V) +VCC (+5V) +VDD AGND DGND C • + • C30 • + C28 L K • C26 + S S MM E / L M 1 2 C27 C24 • C25 • • C26 System Clock L • H C23 • PD CALD • IC-2 DF1760 C21 OVR CAL C22 C18 + IC-1 C17 + PCM1760 R11 R12 R5 C18 C8 C6 R6 ® CN1 C11 C12 + R13 + + C15 R10 C6 C2 Analog IN Rch C8 R8 C13 + C14 R2 R4 C7 R7 C16 C21 OVL +VDD (+5V) DGND SYSCLK SCLK SDATA L/R FSYNC AGND –VCC (–5V) +VCC (+5V) + C3 R9 C1 R1 R3 Analog IN Lch DEM-PCM1760 FIGURE 3. DEM-PCM1760 Board Layout—Component Layout. ® DEM-PCM1760 4 LAYER 1 (TOP) LAYER 2 (BOTTOM) FIGURE 4. ® 5 DEM-PCM1760 ® DEM-PCM1760 6 2.2kΩ R1 R2 R3 R12 1.2kΩ C9 1800pF + C13 10µF + C14 10µF R6 1.3Ω –5VCC AGND +5VCC 1.2kΩ R11 1.3 kΩ C3 2200pF C7 1800pF C16 10µF + C11 0.1µF C12 0.1µF + C15 0.1µF R13 10kΩ C1 2200pF 560Ω R9 470Ω –VCC +VCC FIGURE 5. Circuit Diagram. Lch In Rch In C8 1800pF C2 C4 2200pF 2200pF R4 470Ω R10 560Ω C10 1800pF 14 13 12 11 9 8 7 6 5 4 3 2 1 C30 0.1µF –5VCC + C28 100µF to 470µF +5VCC 16 17 18 19 20 21 –VCC + C19 10µF C18 10µF +VCC + C21 3.3µF DGND +VDD +VDD C26 0.1µF CAL VSS1 D0 D1 D2 D3 OVL OVR C25 100µF to 470µF +VDD VDD2 VSS2 15 16 17 18 19 21 22 23 24 25 27 28 System Clock SYSCLK SCLK L/R SDATA FSYNC PD MODE 2 MODE 1 S/M CLKSEL DF1760 +VDD VDD1 10 STS 11 256FS 12 LRCK 13 CALD 14 CAL 9 C22 0.1µF C24 0.1µF CALD 6 23 + C27 100µF to 470µF BPO DCL L/R CK STS 256FS –VCC DGND 5 24 8 4 25 C17 10µF 3 22 2 26 1 27 C29 0.1µF OUT-2L IN-2L OUT1-L IN-1L DQ DO –VCC AGND D0 +VCC +VCC D1 D2 IN-1R SERVO DC D3 BPO DCR OUT-1R IN-2R OUT-2R PCM1760 OVR OVL C20 10µF + +VDD +VDD= +5V –VCC= –5V +VCC= +5V PD C23 0.1µF +VCC –VCC +5VDD +5VDD +VCC –VCC AGND FSYNC L/R SDATA SCLK SYSCLK DGND CN1