ETC FMS988AKAC140

www.fairchildsemi.com
FMS9884A
Graphics Digitizer
3x8-Bit, 108/140 Ms/s Triple Video A/D Converter with Clamps
Features
•
•
•
•
•
•
•
•
PLL. Output data is released through either one port at full
rate or both ports, each running at half-rate. Setup and control
is via registers, accessible through an SMBus/I2C compatible
serial port.
3-channels
100/140 Ms/s conversion rate
Programmable Clamps
500ps PLL clock jitter
Adjustable Gain and offset
Internal Reference Voltage
I2C/SMBus compatible Serial Port
Pin Compatible with AD9884A
Input amplitude range is 500–1000mV with either DC or AC
coupling. Lower reference of AC coupled inputs is established with input clamps that are either internally generated
or externally provided.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from a PLL or an external
source. Digital data levels are 2.5–3.3 volt CMOS compliant.
Applications
• Flat panel displays and projectors
• RGB Graphics Processing
Power can be derived from a single +3.3 Volt power supply.
Package is a 128-lead MQFP. Performance specifications are
guaranteed over 0°C to 70°C range.
Description
As a fully integrated analog interface, the FMS9884A can digitize RGB graphics with resolutions up to 1280 x 1024/75Hz
refresh or 1600 x 1200/85Hz using alternate pixel sampling.
ADC sampling clock can be derived from either an external
source or incoming horizontal sync signal using the internal
Product Number
Speed
FMS988AKAC100
108 Ms/s
FMS988AKAC140
140 Ms/s
Block Diagram
RIN
GIN
BIN
Clamp
Clamp
Clamp
Gain &
Offset
A/D
Converter
Gain &
Offset
A/D
Converter
Gain &
Offset
A/D
Converter
VREFIN
SCK
CLAMP
INVSCK
XCK
HS
HSIN
COAST
LPF
PLL
SDA
SCL
A0
A1
PWRDN
Control
Timing
Generator
PXCK
ACSIN
SYNC
STRIPPER
RPD7-0
DRA7-0
Switch
DRB7-0
GPD7-0
Switch
DGA7-0
DGB7-0
BPD7-0
Switch
DBA7-0
DBB7-0
Reference
VREFOUT
ICLAMP
DCK
DCK
HSOUT
DCSOUT
REV. 1.0.2 8/11/00
PRODUCT SPECIFICATION
FMS9884A
Architectural Overview
1.
Single 8-bit port at pixel rates up to 140Ms/s.
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
2.
Dual 8-bit ports, each running at half the conversion
rate. Maximum rate is 88Ms/s per port. Data streams
may be parallel or interleaved.
Conversion Channels
Typical RGB graphics signals, RIN, GIN, BIN are ground referenced with 700mV amplitude. If a sync signal is embedded
then the usual format is sync on green with the sync tip at
ground, the black level elevated to 300mV and peak green at
1000mV.
AC coupled video signals must be level shifted to establish
the lower level of the conversion range by clamping to the
black level of the back porch (see Figure 1). Clamp pulses
are derived from internal Timing and Control logic or from
the external CLAMP input.
RIN, GIN, BIN
ICLAMP
Figure 1. Clamping to the back-porch
Gain and Offset
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers GR,
GG and GB, which vary sensitivity (LSB/volt) over a 2:1
range. Incoming video signal amplitudes varying from 0.5 to
1.0 volt can be accommodated.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSR, OSG and OSB registers.
Range of adjustment is equivalent to –31 to +32 LSB.
A/D Converter
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 5–61/2 clock cycles, depending upon the
data out format.
VREFIN is the source of reference voltage for the three A/D
converters. VREFIN can be connected to either the internal
bandgap voltage, VREFOUT or an external voltage.
Timing and Control
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Bit XCKSEL selects
the Master Clock source. Two clocks are generated.
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK can be adjusted in 32 11.25 degree phase
increments using the 5-bit PHASE register.
DCK is the output data clock. DCK and DCK are supplied as
outputs for synchronizing data transfer from the digitizer
outputs.
Horizontal sync applied to the input, HSIN is propagated by
the Timing and Control to the HSOUT output with a delay
that aligns leading and trailing edges with the output data.
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock signal,
PXCK that is fed to the Timing and Control logic. Frequency
of PXCK is set by the register programmable PLL divide
ratio, PLLN.
COAST is an input that disables the PLL lock to the horizontal
sync input, HSIN. If HSIN is to be disregarded for a period
such as the vertical sync interval, COAST allows the VCO
frequency to be maintained. Omission of horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I2C/SMBus compatible
serial port. Four serial addresses are pin selectable.
Output Data Configuration
Output data number format for each channel is binary: 00 corresponds to the lowest input; FF corresponds to the highest
input. Data can be released in either of two timing formats:
2
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Pin Assignments (128-Lead MQFP (KA) Package)
65
102
103
64
128
39
1
38
No.
Name
No.
Name
No.
Name
No.
Name
1
NC
33
VDDP
65
DBA7
97
DRB5
2
NC
34
VDDP
66
DBA6
98
DRB4
3
NC
35
GND
67
DBA5
99
DRB3
4
VDDA
36
NC
68
DBA4
100
DRB2
5
GND
37
NC
69
DBA3
101
DRB1
6
GND
38
NC
70
DBA2
102
DRB0
7
RIN
39
GND
71
DBA1
103
GND
8
VDDA
40
HSIN
72
DBA0
104
VDDO
9
GND
41
COAST
73
GND
105
DRA7
10
VDDA
42
GND
74
VDDO
106
DRA6
11
VDDA
43
VDDP
75
DGB7
107
DRA5
12
GND
44
XCK
76
DGB6
108
DRA4
13
GND
45
LPF
77
DGB5
109
DRA3
14
ACSIN
46
NC
78
DGB4
110
DRA2
15
GIN
47
GND
79
DGB3
111
DRA1
16
VDDA
48
VDDP
80
DGB2
112
DRA0
17
GND
49
GND
81
DGB1
113
GND
18
VDDA
50
VDDP
82
DGB0
114
VDDO
19
VDDA
51
GND
83
GND
115
DCK
20
GND
52
GND
84
VDDO
116
DCK
21
GND
53
GND
85
DGA7
117
HSOUT
22
BIN
54
VDDO
86
DGA6
118
DCSOUT
23
VDDA
55
DBB7
87
DGA5
119
GND
24
GND
56
DBB6
88
DGA4
120
VDDO
25
VDDA
57
DBB5
89
DGA3
121
GND
26
GND
58
DBB4
90
DGA2
122
GND
27
INVSCK
59
DBB3
91
DGA1
123
GND
28
CLAMP
60
DBB2
92
DGA0
124
VDDA
29
SDA
61
DBB1
93
GND
125
PWRDN
30
SCL
62
DBB0
94
VDDO
126
VREFOUT
31
A0
63
GND
95
DRB7
127
VREFIN
32
A1
64
VDDO
96
DRB6
128
VDDA
REV. 1.0.2 8/11/00
3
PRODUCT SPECIFICATION
FMS9884A
Pin Descriptions
Pin Name
Pin No.
Type/Value
Pin Function Description
Converter Channels
RIN, GIN, BIN
7, 15, 22
Input
DRA7-0
105–112
Output
Red Channel Port A Data Output. Full rate/half rate, interleaved/
parallel data depending upon selected mode.
DRB7-0
95–102
Output
Red Channel Port B Data Output. Active for dual port mode only with
interleaved/parallel outputs. High impedance when inactive.
DGA7-0
85–92
Output
Green Channel Port A Data Output. See red channel port A.
DGB7-0
75–82
Output
Green Channel Port B Data Output. See red channel port B.
DBA7-0
65–72
Output
Blue Channel Port A Data Output. See red channel port A.
DBB7-0
55–62
Output
Blue Channel Port B Data Output. See red channel port B.
Analog Inputs.
Timing Generator
CLAMP
28
Input
External Clamp Input.
INVSCK
27
Input
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 350Ms/s.
XCK
44
Input
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10kΩ resistor.
DCK
115
Output
Output Data Clock. Clock for strobing output data to external logic.
DCK
116
Output
Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
HSOUT
117
Output
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9884A latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
40
Schmitt
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
COAST
41
Input
PLL Coast. Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
LPF
45
Passive
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Figure 19.)
Sync Stripper
ACSIN
14
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
DCSOUT
118
Digital Composite Sync Output. Output from sync stripper.
Control
4
SDA
29
Bi-directional Serial Port Data. Bi-directional data.
SCL
30
Input
Serial Port Clock. Clock input.
A0
31
Input
Address bit 0. Lower bit of serial port address.
A1
32
Input
Address bit 1. Upper bit of serial port address.
PWRDN
125
Input
Power Down/Output Control. Powers down the FMS9884A and
tri-states the outputs.
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Pin Descriptions (Continued)
Pin
Name
Pin No.
Pin Function Description
Power and Ground
VDDA
4, 8, 10, 11, 16, 18, 19, 23,
25, 124, 128
ADC Supply Voltages. Provide a quiet noise free voltage.
VDDP
33,34,43,48,50
VDDO
54, 64, 74, 84, 94, 104, 114,
120
Digital Output Supply Voltage. Decouple judiciously to avoid
propagation of switching noise.
GND
5, 6, 9,12, 13, 14, 17, 20, 21,
24, 26, 35, 39, 42, 47, 49, 51,
52, 53, 63, 73, 83, 93, 103,
113, 119, 121, 122, 123
Ground. Returns for all power supplies. Connect ground pins to a
solid ground plane.
VREFIN
127
Voltage Reference Input. Common reference input to RGB
converters. Connect to VREFOUT, if internal reference is used.
VREFOUT
126
Voltage Reference Output. Internal band-gap reference output. Tie
to ground through a 0.1µF capacitor.
PLL Supply Voltage. Most sensitive supply voltage. Provide a very
quiet noise free voltage.
Addressable Memory
Register Map
Name
Address
Function
Default (hex)
PLLN11-4
00
PLL divide ratio, MSBs. PLLN + 1 = total number of
pixels per horixontal line.
69 (1693)
PLLN3-0
01
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels
per horizontal line. PLLN3-0 stored in the four upper
register bits 7-4.
D0 (1693)
GR7-0
02
Gain, red channel. Adjustable from 70 to 140%.
80
GG7-0
03
Gain, green channel. Adjustable from 70 to 140%.
80
GB7-0
04
Gain, blue channel. Adjustable from 70 to 140%.
80
OSR5-0
05
Offset, red channel. OSR5-0 stored in the six upper
register bits 7-2.
20
OSG5-0
06
Offset, green channel. OSG5-0 stored in the six upper
register bits 7-2.
20
OSB5-0
07
Offset, blue channel. OSB5-0 stored in the six upper
register bits 7-2.
20
CD7-0
08
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
80
CW7-0
09
Clamp width. Width of clamp pulse in pixels.
80
CONFIG1
0A
Configuration Register No. 1
F4
PHASE7-0
0B
Sampling clock phase. PHASE4-0 stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments.
10
PLLCTRL
0C
PLL Control
24
CONFIG2
0D
Configuration
00
0E
Reserved
0X
0F
Reserved
00
REV. 1.0.2 8/11/00
5
PRODUCT SPECIFICATION
FMS9884A
Register Definitions
Configuration Register 1 (0A)
Bit no.
Name
Type
Description
1
XCKSEL
R/W
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
2
XCLAMPOL
R/W
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
3
XCLAMP
R/W
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
4
COASTPOL
R/W
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
5
HSPOL
R/W
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
6
PARALLEL
R/W
Output Data Format. Select format of data outputs.
0: Interleaved. DCK rising edge strobes port A data. DCK rising edge strobes
port B data.
1: Parallel. Rising edge of DCK strobes port A and port B data.
7
DEMUX
R/W
Output Data Porting. Data released at full rate through one port or through
two half-rate ports.
0: Single 8-bit port.
1: Dual 8-bit ports.
0
PLL Configuration Register (0C)
6
Bit no.
Name
Type
Description
1-0
—
4-2
IPUMP2-0
R/W
Charge Pump Current. Selects Charge Pump current (µA).
(see Table 5. Charge Pump Current Codes)
000: 50
001: 100
010: 150
011: 250
100: 350
101: 500
110: 750
111: 1500
6-5
FVCO1-0
R/W
VCO Frequency Range. Selects VCO frequency range (MHz).
(see Table 4. VCO Frequency Codes)
00: 20–60
01: 50–90
10: 80–120
11: 110–140
7
—
R/W
Reserved.
0: Run.
1: (reserved).
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FMS9884A
PRODUCT SPECIFICATION
Configuration Register 2 (0D)
Bit no.
Name
Type
Description
0
—
—
Reserved. Set to 0.
3-1
REV
R
Revision Number. Die revision number.
4
OUTPHASE
W
Output Data Phase. In the dual port mode, selects either odd (1, 3, 5, …) or
even (2, 4, 6 ….) samples following the HSYNC leading edge to be emitted
from Port 1.
0: Even samples to Port A, odd samples to Port B.
1: Odd samples to Port A, even samples to Port B.
7-5
-
R/W
Reserved. Set to 00.
Functional Description
Clamps
There are two major sections within the FMS9884A
Digitizer:
If the incoming signals are not ground referenced, a clamp
must be used to set the incoming video range relative to
ground. Prior to each A/D converter, each channel includes a
clamp that allows a capacitively coupled input to be referenced
to the A/D converter bottom reference voltage when the
clamp pulse is active. Source of the clamp signal is determined by the XCLAMP bit.
1.
Analog-to-digital Converter Channels, one for each
channel, RGB and the voltage reference.
2.
Timing and Control comprising the PLL, Timing
Generator, Sync Stripper and Serial Interface.
A/D Converter Channels
Each of the three RGB channels consists of:
1.
A clamp to set the lower reference level of an AC
coupled input.
2.
Gain and offset stages to tune the converter to input
signal levels.
Internal clamp timing is generated by the Timing and Control Block. Position and width of the internal clamp pulse,
ICLAMP are programmable through registers CD and CW.
External clamp input is selected by register bit XCLAMP
and the external clamp polarity selected through register bit
XCLAMPOL. To disable the clamp for DC coupled inputs,
set XCLAMP = 1 with either of these conditions:
1.
XCLAMPOL = 0 with input CLAMP = H.
XCLAMPOL = 1 with CLAMP = L.
3.
An Analog-to-Digital Converter to digitize the analog
input.
2.
4.
A commutating switch for dual port operation.
Best performance will be achieved with the clamp set active
for most of the black signal level interval between the trailing edge of horizontal sync and the start of active video.
Insufficient clamping can cause brightness changes at the top
of the image and slow recovery from large changes in Average Picture Level (APL). Recommended value of CD is
0x10 to 0x20 for most standard video sources.
Analog Inputs
Input signal range is 500 to 1000mV to support conversion of
single-ended signals with a typical amplitude of 700mV p-p.
With the clamp active, each input accommodates a negative
300mV excursion.
Inputs are optimized for a source resistance of 37.5 to 75Ω.
To reduce noise sensitivity, the ultra-wide 500MHz input
bandwidth may be reduced by adding a small series inductor
prior to the 75Ω terminating resistor. See Applications Section.
REV. 1.0.2 8/11/00
Analog-to-Digital Converter
Figure 2 is a block diagram of the ADC core with gain and
offset functions. G7-0, OS5-0, RGBIN and PD7-0 generically
refer to the gain and offset register values, analog input and
parallel data output of any RGB channel.
7
PRODUCT SPECIFICATION
FMS9884A
VREF
Gain
Register
G7-0
Offset
Register
OS5-0
D/A
Current
D/A
IBIAS + IOFFSET
A/D Core
RGBIN
+
Track &
Hold
-
PD7-0
A/D
RLEVEL
SCK
Figure 2. A/D Converter Architecture
Core of the ADC block is a high speed A/D encoder with differential inputs. Within the A/D converter core are the following elements:
The 6-bit Offset D/A converter injects a current into RLEVEL
with two components:
1.
IBIAS to establish the A/D common mode voltage.
1.
Differential track and hold.
2.
IOFFSET to set the offset from the common mode level.
2.
Differential analog-to-digital converter.
Setting the gain register value G7-0 (GR7-0, GG7-0, GB7-0),
establishes the gain D/A converter voltage which is the A/D
reference voltage. Increasing video gain reduces the contrast
of the picture since the number of output codes is reduced.
Conversion range is defined by the gain setting according to
Table 1.
Table 1. Gain Calibration
G7-0
Conversion Range (mV)
0
500
66h
700
FFh
1000
A/D Converter sensitivity is:
255
255
S = --------- • ----------------------------- LSB ⁄ mV
500 255 + G 7 – 0
Offset is set through the Single-Ended to Differential Amplifier
which translates the ground referenced input to a differential
voltage centered around A/D common mode bias voltage.
8
Offset from the common mode voltage is:
255 + G 7 – 0
AOS = ( OS 5 – 0 – 32 ) • ----------------------------- LSB
255
D/A converter gain tracks A/D gain with 1 LSB of offset corresponding to 1 LSB of gain. Increasing the offset of a video
signal increases brightness of the picture. Impact of the offset values OSR5-0, OSG5-0, and OSB5-0 is shown in Table 2.
Table 2. Offset Calibration
OS5-0
Equivalent Offset (bits)
0
-31d
1Fh
0
3Fh
32d
Sampling Clock PHASE Adjustment
Picture quality is strongly impacted by the PHASE4-0 value.
If PHASE is not set correctly, any section of an image consisting of vertical lines may exhibit tearing.
Figure 3 shows how an analog input, RINGINBIN is sampled
by the rising edge of SCK after a delay PHASE from the rising edge of either PXCK or XCK. SCK can be delayed up to
32 steps in 11.25° increments by adjusting the register value,
PHASE4-0.
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FMS9884A
PRODUCT SPECIFICATION
PHASE
PXCK/XCK
SCK
RINGINBIN
RGBn
DCK
D7-0
Figure 3. Internal Sampling Clock, SCK Timing
Output data, DCK and DCK are delayed in tandem with
SCK relative to PXCK or XCK. There is a 5-51/2 clock
latency between the data sample RGBn and the corresponding data out D7-0.
Ideally, incoming pixels would be trapezoidal with fast risetimes and the sampling edge of the A/D clock, SCK would
be positioned along the level section of the incoming pixel
waveform as shown in Figure 4. There is a narrow zone of
uncertainly where sampling during pixel rise time would
cause an error in the value of the A/D data output, D7-0,
which is shown as a value, 0-255.
Referring to Figure 6, when the sample clock, SCK has some
jitter, if the sampling edge occurs anywhere within the zone
of uncertainty where the pixel rise time is steep, there will be
amplitude modulation of the digitized data, D7-0, due to the
sampling clock jitter. To avoid corruption of the image, setting the value PHASE7-0 is critical. PHASE4-0 should be
trimmed to position the sampling edge of SCK within the
zone of serendipity.
Zones of Uncertainty
RIN, GIN, BIN
Zones of Uncertainty
SCK
RIN, GIN, BIN
D7-0
SCK
Figure 6. Improper Pixel Sampling
D7-0
Voltage References
Figure 4. Ideal Pixel Sampling
In practice, high-resolution pixels have long rise-times. As
shown in Figure 5, there are narrow zones of serendipity
when the pixel amplitude is level. Samples are valid in these
zones.
Zones of Serendipity
An on-chip voltage reference is generated from a bandgap
source. VREFOUT is the buffered output of this source that
can be connected to VREFIN to supply a voltage reference
that is common to the three converter channels.
VREFIN, with a nominal voltage of 1.25V, is the source of the
differential reference voltages for each A/D converter.
Reference voltages supplied to the differential inputs of the
comparators in the A/D converters are derived from VREFIN.
RIN, GIN, BIN
SCK
D7-0
Figure 5. Acceptable Pixel Sampling
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PRODUCT SPECIFICATION
FMS9884A
Digital Data Outputs
Input horizontal sync, HSIN and outgoing data, D[7..0] are
resynchronized to the delayed sample clock, SCK. Output
timing characteristics are defined in Figure 7. Latency of the
first pixel, N varies according to the mode:
1.
Single or dual output port.
2.
Interleaved or parallel output data.
3.
1-pixel or 2-pixel.
Levels are 3.3 volt CMOS with the output supply variable
between 2.5 and 3.3 V. PWRDN = L sets the outputs
high-impedance. PWRDN = H enables the outputs.
HSIN
PHASE
N
PXCK/XCK
SCK
RGBIN
S0
DCK
tDH
DCK
tDO
D[7..0]
D0
HSOUT
Figure 7. Output Timing
Figures 13 through 21 depict data output timing relative to
the sampling clock and inputs for all modes. Timing is referenced to the leading edge of HSIN when the first sample is
taken at the rising edge of SCK. Status of register bit OUTPHASE, determines if even samples are directed the A-port
and odd samples are directed to the B-port; or vice versa.
Note the timing of the HSOUT waveform:
HS is the internal sync pulse generated from HSYNC. SCK
is the internal A/D converter sampling clock.
Output data transitions are synchronized with the falling
edge of DCK. Output data should be strobed on the rising
edge of DCK. A 5 to 6.5 clock cycle delay must be flushed
before valid data is available.
Alternate Pixel Sampling Mode
A logic H on the CKINV pin inverts the sampling phase of
SCK. In the Alternate Pixel Sampling Mode:
1.
HSOUT is always active HIGH.
2.
Only the leading edge of HSOUT is active or selected by
the HSPOL register bit.
1.
PLL is run at half rate. SCK, DCK and DCK are half rate.
3.
HSOUT is aligned with DCK.
2.
CKINV is toggled between frames. (see Figure 18)
4.
Trailing edge is linked to HSIN.
5.
If HSIN does not terminate before mid-line, HSOUT is
forced low. A 50% duty cycle indicates that HSPOL is
incorrectly set.
10
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2
E
E
E
E
E
E
E
E
E
E
E
Figure 10. Even Pixels from Frame 2
Figure 8. Odd and Even Pixels in a Frame
On one frame, even pixels are sampled. On the other, odd
pixels are sampled.
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
Alternate Pixel Sampling is similar to interlacing used in
broadcast video, except that the columns of pixels are interlaced instead of lines.
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1
Figure 11. Combined Frames 1 and 2 Output.
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2
Figure 9. Odd Pixels from Frame 1
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
O3 E2
Figure 12. Subsequent Output Combining Frames 2 and 3
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSIN
PXCK
HS
5 PIPE DELAY
SCK
DATACK
DA7-0
D0
D1
D2
D3
D4
D5
D6
D7
HSOUT
Figure 13. Single Port Mode
REV. 1.0.2 8/11/00
11
PRODUCT SPECIFICATION
RGBIN
FMS9884A
P0 P1 P2 P3 P4 P5 P6 P7
HSIN
PXCK
HS
5 PIPE DELAY
SCK
DATACK
D0
DA7-0
D2
D4
D6
HSOUT
Figure 14. Single Port Mode, Alternate Pixel Sampling, (Even Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSIN
PXCK
HS
5.5 PIPE DELAY
SCK
DATACK
D1
DA7-0
D3
D5
D7
HSOUT
Figure 15. Single Port Mode, Alternate Pixel Sampling, (Odd Pixels)
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSIN
PXCK
HS
5 PIPE DELAY
SCK
DATACK
DA7-0
DB7-0
D2
D0
D1
D4
D3
D6
D5
D7
HSOUT
Figure 16. Dual Port Mode, Interleaved Outputs
12
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSIN
PXCK
HS
6 PIPE DELAY
SCK
DATACK
DA7-0
D0
D2
D4
D6
D1
D3
D5
D7
HSOUT
Figure 17. Dual Port Mode, Parallel Outputs
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5 PIPE DELAY
SCK
DATACK
D0
DA7-0
D4
D2
DB7-0
D6
HSOUT
Figure 18. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Even Pixels)
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5.5 PIPE DELAY
SCK
DATACK
DA7-0
D1
D5
D3
DB7-0
D7
HSOUT
Figure 19. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Odd Pixels)
REV. 1.0.2 8/11/00
13
PRODUCT SPECIFICATION
RGBIN
FMS9884A
P0 P1 P2 P3 P4 P5 P6 P7
HSIN
PXCK
HS
6 PIPE DELAY
SCK
DATACK
DA7-0
D0
D4
DB7-0
D2
D6
HSOUT
Figure 20. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Even Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSIN
PXCK
HS
6.5 PIPE DELAY
SCK
DATACK
DA7-0
D1
D5
DB7-0
D3
D7
HSOUT
Figure 21. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Odd Pixels)
Timing and Control
Timing and Control logic encompasses the PLL, Timing
Generator and Sync Stripper.
Phase Locked Loop
Two clock types originate in the PLL:
1.
Data clocks DCK and DCK.
2.
Internal sampling clock SCK.
DCK and DCK are used to strobe data from the FMS9884A
to following digital circuits. SCK is the ADC sample clock
which has adjustable phase controlled through the PHASE
register. DCK and DCK are phase aligned with SCK.
Reference for the PLL is the horizontal sync input, HSIN
with polarity selected by the HSPOL bit.
Frequency of the HSIN input is multiplied by the value PLLN
+ 1 derived from the PLLN11-4 and PLLN3-0 registers. PLLN
+ 1 should equal the number of pixels per horizontal line
including active and blanked sections. Typically blanking is
20–30% of active pixels. Divide ratios from 2–4095 are
supported. SCK, DCK and DCK run at a rate PLLN + 1
times the HSIN frequency.
14
The PLL consists of a phase comparator, charge pump VCO
and ÷N counter, with the charge pump connected through the
LPF pin to an external filter. These elements must be programmed to match the incoming video source to be captured.
Values of IPUMP and FVCO for Standard VESA timing
parameters are shown in Table 3. Timing of many computer
video outputs does not comply with VESA recommendations.
PLLN should be optimized to avoid vertical noise bars on the
displayed image.
Modes marked 2X are 2X-oversampled modes where the
number of samples per horizontal line is doubled. To select
this mode, the Phase-locked Loop Divide Ratio value must
changed from PLL1x to:
PLL 2x = 2 • ( PLL 1x + 1 ) – 1
Values of IPUMP and FVCO are set through the PLL
Configuration Register (0x0C). Recommended external filter
components are shown in Figure 22. RF Quality ±10%
ceramic capacitors with X7R dielectrc are recommended.
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Table 3. Recommended IPUMP and FVCO values for Standard Display Formats
Standard
Resolution
Refresh Rate
Horizontal
Frequency
Sample Rate
FVCO1-0
IPUMP2-0
VGA
640 X 480
60 Hz
72 Hz
75 Hz
85 Hz
31.5 kHz
37.7 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
31.500 MHz
36.000 MHz
01
01
01
100
100
100
2X
640 X 480
720 X 400
60 Hz
72 Hz
75 Hz
70 Hz
31.5 kHz
37.7 kHz
37.5 kHz
31.5 kHz
50 MHz
63 MHz
72 MHz
56.6MHz
01
01
01
01
111
111
111
111
Mac
640 X 480
67 Hz
35 kHz
31 MHz
10
100
SVGA
800 X 600
56 Hz
60 Hz
72 Hz
75 Hz
85 Hz
35.1 kHz
37.9 kHz
48.1 kHz
46.9 kHz
53.7 kHz
36.000 MHz
40.000 MHz
50.000 MHz
49.500 MHz
56.250 MHz
01
01
01
01
100
110
110
110
XGA
1024 X 768
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
01
01
10
111
111
111
Mac
1024 X 768
1152 X 870
60 Hz
75 Hz
75 Hz
48 kHz
60 kHz
69 kHz
64 MHz
80 MHz
100 MHz
01
10
10
111
111
111
Sun
1152 X 900
66 Hz
62 kHz
93 MHz
10
111
HP
1280 X 1024
60 Hz
63 kHz
108 MHz
10
111
SXGA
1280 X 1024
60 Hz
72 Hz
75 Hz
85 Hz
64.0 kHz
78.1 kHz
80.0 kHz
91.1 kHz
108.000 MHz
135.000 MHz
135.000 MHz
157.500 MHz
10
11
11
111
111
111
UXGA
1600 X 1200
60 Hz
65 Hz
70 Hz
75 Hz
85 Hz
75.0 kHz
81.3 kHz
87.5 kHz
93.8 kHz
106.3 kHz
162.000 MHz
175.500 MHz*
189.000 MHz*
202.500 MHz*
229.500 MHz*
VESA Monitor Timing Standards and Guidelines, September 17, 1998
* Graphics sampled at 1/2 incoming pixel rate using Alternate Pixel Sampling mode.
VDDP
C1
0.18µF
R1
1.5K
C2
0.018µF
Loop performance is established by setting:
1.
VCO frequency range through FVCO1-0. (see Table 4)
2.
Charge Pump Current through IPUMP2-0. (see Table 5)
3.
External loop filter component values.
LPF
Figure 22. Schematic, PLL Filter.
REV. 1.0.2 8/11/00
15
PRODUCT SPECIFICATION
FMS9884A
Table 4. VCO Frequency Bands
FVCO2-0 Frequency Range (MHz) KVCO (MHz/V)
00
20–75
60
10
75–108
90
11
108–140
100
01
Operation of COAST is depicted in Figure 23. HSOUT
polarity is always positive. When COAST = L, HSOUT
tracks HSIN (shown with postive polarity in Figure 23):
1.
HSOUT rising edge tracks HSIN delayed by a few pixels.
2.
HSOUT falling edge tracks the trailing edge of HSIN
with no delay.
When COAST = H, the PLL flywheels, disregarding the
incoming HSIN references, while the HSOUT waveform
depends upon the state of HSIN.
Table 5. Charge Pump Current Levels
IPUMP2-0
Current (µA)
000
50
001
100
a.) HSOUT rising edge remains locked to the PLL.
010
150
011
250
b.) HSOUT trailing edge falls after 50% of the HSOUT
period has expired.
100
350
101
500
a.) HSOUT rising edge remains locked to the PLL.
110
750
111
1500
b.) HSOUT falling edge is terminated by the trailing
edge of HSIN.
1.
2.
3.
Setting SPHASE4-0 selects the sampling phase of SCK relative to PXCK in 32 steps of 11.25°. Phase of the output data,
DCK and DCK is slaved to the SCK phase.
Clock jitter is less than 5% of pixel period in all operating
modes. At lower frequencies below 40MHz, the jitter rises
but can be reduced by over-sampling at a 2X clock rate. Data
should be read out of one port using the dual port mode. See
Performance section for jitter specifications and plots.
COAST
COAST = H disables PLL lock to HSIN, while the VCO
frequency is retained. VCO frequency remains stable over
several lines without updates from HSIN. COAST can be
connected directly to the vertical sync signal or supplied by
the graphics controller.
If HSIN = H:
HSIN transitions:
If HSIN = L, then HSOUT = L
Timing Generator
Timing and Control logic generates:
1.
Internal sampling clock, SCK.
2.
Output data clocks, DCK and DCK.
3.
Output horizontal sync, HSOUT.
4.
Internal clamp pulse, ICLAMP.
With HSPOL set correctly, ICLAMP delay follows the trailing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
HSIN
Trailing edge terminates HSOUT
COAST
HSOUT
50% Timeout
Figure 23.
16
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Sync Stripper
Some video signals include embedded composite sync rather
than separate horizontal and vertical sync signals, typically
sync on green. Composite sync is extracted from Composite
Video at the ACSIN pin.
Since the serial control port is design to interface with 3.3V
logic, the pins must be protected by series connected 150Ω
resistors if SDA and SCL signals originate from 5V logic.
(See Applications Section)
Table 6. Serial Interface Address Codes
When the ACSIN signal falls below a 150mV ground referenced threshold, sync is detected. Composite Sync Output,
DCSOUT reflects the ACSIN sync timing with non-inverted
CMOS digital levels.
Power Down
PWRDN = L minimizes FMS9884A power consumption.
Data outputs become high impedance. Clocks generation is
stopped. Register contents are maintained. Sync stripping
and the internal voltage reference function.
Serial Interface
Register access is via a 2-wire I2C/SMBus compatible interface. As a slave device, the 7-bit address is selected by the
A1-0 pins (see Table 6). Serial port pins SDA and SCL communicate with the host SMBus/I2C controller which act as a
master.
A1-0
7-bit Address
00
4C
01
4D
10
4E
11
4F
Two signals comprise the bus: clock (SCL) and bi-directional
data (SDA). When receiving and transmitting data through
the serial interface, the FMS9884A acts as a slave, responding
only to commands by the I2C/SMBus master.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
SDA
tBUFF
tDHO
tSTAH
tDSU
tSTASU
tSTOSU
tDAL
SCL
tDAH
Figure 24. Serial Bus: Read/Write Timing
SDA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACK
SCL
Figure 25. SerialBus: Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
A1
A0
R/W\
ACK
SCL
Figure 26. Serial Bus: Slave Address with Read/Write Bit
REV. 1.0.2 8/11/00
17
PRODUCT SPECIFICATION
There are five steps within an I2C/SMBus cycle:
1.
2.
3.
4.
5.
Start signal
Slave address byte
Pointer register address byte
Data byte to read or write
Stop signal
When the Serial Bus interface is inactive, SCL = H and SDA
= H. Communications are initiated by sending a start signal
(Figure 23, left waveform) that is a HIGH-to-LOW transition
on SDA while SCL is HIGH. A start signal alerts all slaved
devices that a data transfer sequence is imminent.
After a start signal, the first eight bits of data comprise a seven
bit slave address followed a single R/W bit (Read = H, Write
= L) to set the direction of data transfer: read from; or write
to the slave device. If the transmitted slave address matches
the address of the FMS9884A which set by the state of the
ADD pin, the FMS9884A acknowledges by pulling SDA
LOW on the 9th SCL pulse (see Figure 25). If the addresses
do not match, the FMS9884A does not acknowledge.
For each byte of data read or written, the MSB is the first bit
of the sequence.
Data Transfer via Serial Interface
If a slave device, such as the FMS9884A does not acknowledge the master device during a write sequence, SDA
remains HIGH so the master can generate a stop signal. During a read sequence, if the master device does not acknowledge by bringing SDA = L, the FMS9884A interprets SDA =
H as “end of data.” SDA remains HIGH so the master can
generate a stop signal.
To write data to a specific FMS9884A control register, three
bytes are sent:
1.
2.
3.
Write the slave address byte with bit R/W = L.
Write the pointer byte.
Write to the control register indexed by the pointer.
After each byte is written, the pointer auto-increments to
allow multiple data byte transfers within one write cycle.
Data is read from the control registers of the FMS9884A in a
similar manner, except that two data transfer operations are
required:
1.
2.
3.
4.
Write the slave address byte with bit R/W = L.
Write the pointer byte.
Write the slave address byte with bit R/W = H
Read the control register indexed by the pointer.
After each byte is read, the pointer auto-increments to allow
multiple data byte transfers within one read cycle.
Preceding each slave write, there must be a start cycle.
Following the pointer byte there should be a stop cycle.
After the last read, there must be a stop cycle comprising
18
FMS9884A
a LOW-to-HIGH transition of SDA while SCL is HIGH.
(see Figure 23, right waveform)
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generating a stop signal to terminate the current communication.
This is used to change the mode of communication (read,
write) between the slave and master without releasing the
serial interface lines.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake initiates further SCL clock cycles from the master to transfer
the next data byte.
Write to one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Stop signal
Write to four consecutive registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
7. Data byte to (base address + 3)
8. Stop signal
Read from one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Stop signal
Read from four registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Data byte from (base address + 1)
9. Data byte from (base address + 2)
10. Data byte from (base address + 3)
11. Stop signal
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
-0.5
4
V
-0.3
VDDA
V
-5.0
5.0
mA
-0.5
VDDA
V
-10.0
10.0
mA
Power Supply Voltages
VCC (Measured to GND)
Digital Inputs
Applied voltage (Measured to GND)2
Forced current
3, 4
Analog Inputs
Applied Voltage (Measured to GND)2
Forced current
3, 4
Digital Outputs
Applied voltage (Measured to GND)2
-0.5
Forced current 3, 4
-6.0
6.0
mA
Forced current 3, 4
-8.0
8.0
mA
1
second
Junction
150
°C
Lead Soldering (10 seconds)
300
°C
Vapor Phase Soldering (1 minute)
220
°C
150
°C
±150
V
V
Short circuit duration (single output in HIGH state to ground)
Temperature
Storage
Electrostatic
-65
Discharge5
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5. EIAJ test method.
Operating Conditions
Parameter
Min
Nom
Max
Units
VDDA
ADC Power Supply Voltage
3.0
3.3
3.6
V
VDDP
PLL Power Supply Voltage
3.0
3.3
3.6
V
VDDO
Output Power Supply Voltage
2.2
3.3
3.6
V
TA
Ambient Temperature, Still Air
0
70
°C
500
mV p-p
A/D analog input range, min.
A/D analog input range, max.
REV. 1.0.2 8/11/00
1000
mV p-p
19
PRODUCT SPECIFICATION
FMS9884A
Electrical Characteristics1
Parameter
Conditions
Min
Typ
Max
Unit
Power Supply Currents
IDDA
Supply current, ADC
2
Operating, 25°C
211
mA
IDDD
Supply current , Digital Output
Operating, 25°C
47
mA
IDDP
Supply current, PLL
Operating, 25°C
30
mA
PD
Power dissipation
0 to 70°C
950
mW
IPD
Power-down current
0 to 70°C
23
mA
PDD
Powered-down disspation
0 to 70°C
75
mW
3
pF
Digital Inputs/Outputs
CI
Input Capacitance
25°C
CO
Output Capacitance
25°C
pF
IIH
Input Current, HIGH
0 to 70°C
IIL
Input Current, LOW
0 to 70°C
-1
µA
VIH
Input Voltage, HIGH
0 to 70°C
VIL
Input Voltage, LOW
0 to 70°C
IOHD
Output Current, HIGH, data
0 to 70°C
IOHC
Output Current, HIGH, clock
0 to 70°C
8
mA
IOLD
Output Current, LOW, data
0 to 70°C
4
mA
IOLC
Output Current, LOW, clock
0 to 70°C
8
mA
VOH
Output Voltage, HIGH
IOH = max., 0 to 70°C
VOL
Output Voltage, LOW (VDD3)
IOL = max., 0 to 70°C
+1
2.5
µA
V
0.8
4
V
mA
VDDO–0.1
V
0.1
V
Serial Bus I/O
VSMIH
Input Voltage, HIGH
0 to 70°C
2.5
V
VSMIL
Input Voltage, LOW
0 to 70°C
0.8
V
VSMOL
Output Voltage, LOW
ISMOL = max.
0.1
V
ISMOH
Output Current, HIGH
0 to 70°C
µA
ISMOL
Output Current, HIGH
0 to 70°C
mA
Analog Inputs
IB
Input bias current
0 to 70°C
EOS
Input Offset Voltage
0 to 70°C
7
1
µA
50
mV
Reference Output
Output Voltage
0 to 70°C
Temperature Coefficient
0 to 70°C
1.20
1.25 1.30
±50
V
Ppm/°C
Notes:
1. Unless otherwise stated, 0 to 70°C
2. DEMUX = 1; DCK, DCK load = 15 pF; data load = 5 pF.
20
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions
Min.
Conversion rate
0 to 70°C
Data to clock skew
Typ.
Max.
Unit
10
140
Ms/s
0 to 70°C
-0.5
2.0
ns
0 to 70°C
15
110
kHz
0 to 70°C
108
Analog-to-Digital Converters
tSKEW
Timing Generator
HSIN input frequency
Maximum PLL clock rate
FMS9884AKAC100
FMS9884AKAC140
Minimum PLL clock rate
MHz
140
0 to 70°C
20
MHz
Serial Bus Interface
tDAL
SCL Pulse Width, LOW
0 to 70°C
4.7
µs
tDAH
SCL Pulse Width, HIGH
0 to 70°C
4.0
µs
tSTAH
SDA Start Hold Time
0 to 70°C
4.0
µs
tSTASU
SCL to SDA Setup Time (Stop)
0 to 70°C
4.7
µs
tSTOSU
SCL to SDA Setup Time (Start)
0 to 70°C
4.0
µs
tBUFF
SDA Stop Hold Time Setup
0 to 70°C
4.7
µs
tDSU
SDA to SCL Data Setup Time
0 to 70°C
250
ns
tDHO
SDA to SCL Data Hold Time
0 to 70°C
0
ns
System Performance Characteristics
Parameter
Conditions
Min
Typ1
Max
Unit
25°C
-1.4
±0.8
1.4
LSB
0 to 70°C
-2.5
2.5
LSB
25°C
-1.0
1.15
LSB
0 to 70°C
-1.0
1.25
LSB
Analog to Digital Converter
ELI
ELD
Integral Linearity Error
Differential Linearity Error
Missing Codes
0 to 70°C
Input full scale matching
0 to 70°C
Offset adjustment range
0 to 70°C
Gain tempco
BW
±0.5
0
%FS1
5
22
23.5
25
%FS1
25°C
280
ppm/°C
Analog bandwidth, full power
25°C
500
MHz
Transient response
25°C
2
ns
tOV
Over-voltage recovery time
25°C
1.5
ns
SNR
SNR without harmonics
45
dB
REV. 1.0.2 8/11/00
21
PRODUCT SPECIFICATION
FMS9884A
System Performance Characteristics (continued)
Parameter
Conditions
Min
Typ1
Max
Unit
Phase Locked Loop
tPP
tRMS
Peak-to-peak PLL Jitter @
MHz
25.175
RMS PLL Jitter @ MHz
25°C
7.9
31.5
5.5
36
4.5
49.5
3.1
78.75
2.1
108
1.8
135
1.1
25.175
25°C
ns
1000
31.5
700
36
600
49.5
420
78.75
270
108
250
135
150
ps
Thermal
θJC
Resistance, junction-to-case
8.4
°C/W
θJA
Resistance, junction-to-ambient
35
°C/W
Notes:
1. % FS is percentage of full scale.
9
8
7
6
Jitter (ns)
5
RMS
4
P-P
3
2
1
0
0
20
40
60
80
100
120
140
Pixel Clock (MHz)
Figure 27. Pixel Clock Jitter vs. Frequency
22
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Applications Information
AC Coupled Digitizer
Two applications circuits are reviewed:
1. AC coupled digitizer with clamp.
2. AC coupled digitizer with dual ported outputs and sync
stripping.
Shown in Figure 28 is an implementation of a video digitizer
with AC coupled RGB inputs. Horizontal sync input, HS is
passed through a voltage divider which attenuates the 5.0 V
logic HIGH excursion to the 3.3 V HIGH input level of the
FMS9884A. Vertical sync is also attenuated to make the
VSOUT level compatible with 3.3 V pixel processing following the FMS9884A.
To minimize component count, use of the following on-chip
circuits is recommended:
1. ADC sampling clock.
2. Clamp.
3. Voltage reference
4. Dual ported data outputs
Optimum PLL Configuration Register (address 0x0C) settings for typical graphics modes are listed in Table 3. Unless
otherwise indicated, all modes are compliant with VESA
specifications. For unlisted modes, values should be adjusted
to optimize performance.
Output data is three channel port A data only with a maximum rate of 140Ms/s 24-bit pixels. Data is clocked out on
the negative edge of DCK. HSOUT defines the active video
along a line, while incoming vertical sync, VSIN is propagated as VSOUT to the output data to synchronize handling
of digitized frames of output data.
Control is through the serial port with 150Ω resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
By adjusting the values in the gain (GR, GG, GB) and offset
(OSR, OSG, OSB) registers, the input conversion range can
be matched to the incoming analog signals.
REV. 1.0.2 8/11/00
23
PRODUCT SPECIFICATION
FMS9884A
C1
.047µF
C2
0.18µF
C6
0.018µF
R2
1.5K
R3
75
HSIN
VSIN
75
33
34
43
48
50
7
15
R4
SVGA
22
27
R5
1K
28
40
R6
1K
41
44
R7
1.8K
45
R10 150
29
SDA
30
SCL
31
R11 150
R8
1.8K
32
14
1
2
3
36
37
38
46
VDD
127
R9
10K
115
116
117
125
126
RIN
GIN
BIN
CLKINV
CLAMP
HSIN
COAST
CKEXT
FILT
SDA
SCL
A0
A1
ACSIN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
REFIN
DATACK
DATACK
HSOUT
PWRDN
REFOUT
DB _B7
DB _B6
DB _B5
DB _B4
DB _B3
DB _B2
D B_B1
DB _B0
DB _A7
DB _A6
DB _A5
DB _A4
DB _A3
DB _A2
DB _A1
DB _A0
DG_B7
DG_B6
DG_B5
DG_B4
DG_B3
DG_B2
DG_B1
DG_B0
DG_A7
DG_A6
DG_A5
DG_A4
DG_A3
DG_A2
DG_A1
DG_A0
DR_B7
DR_B6
DR_B5
DR_B4
DR_B3
DR_B2
DR_B1
DR_B0
DR_A7
DR_A6
DR_A5
DR_A4
DR_A3
DR_A2
DR_A1
DR_A0
DCSOUT
55
56
57
58
59
60
61
62
BA [ 7..0]
65
66
67
68
69
70
71
72
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
75
76
77
78
79
80
81
82
85
86
87
88
89
90
91
92
GA[7..0]
GA7
GA6
GA5
GA4
GA3
GA2
GA1
GA0
95
96
97
98
99
100
101
102
105
106
107
108
109
110
111
112
RA[7..0]
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
118
5
6
9
12
13
17
20
21
24
26
35
39
42
47
49
51
52
53
63
73
83
93
103
11 3
11 9
12 1
12 2
12 3
C19
0.1µF
PVD
PVD
PVD
PVD
PVD
54
VDD
VDD 64
74
VDD 84
VDD
VDD 94
104
VDD
VDD 114
VDD 120
AD9884
C7
.047µF
VDDO
U1
R1
75
4
8
10
11
16
18
19
23
25
124
128
C4
.047µF
VDDA
VDDP
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
RED
GREEN
BLUE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J1
DCK
HSOUT
VSOUT
Figure 28. Schematic, VGA Digitizer, Single-Port Outputs
VGA Source with Dual Ported Outputs
Shown in Figure 29 is a more complex implementation of a
video digitizer. Incoming RGB video has sync-on-green.
Output data is dual ported. COAST is shown to free wheel
the PLL when horizontal sync is inactive or 2H pulse are
present.
RGB inputs signals are AC coupled to the FMS9884A RGB
inputs with the green input connected to the Sync Separator
input, CVIN.
Output data is three channel dual port data with a maximum
rate of 70Ms/s per port. Port A data is synchronzed to the
negative edge of DCK. Port B data transitions on:
1.
Positive edge of DCK in the Parallel Data Out Mode.
2.
Negative edge of DCK in the Interleaved Data Out
Mode.
24
DCK and DCK clocks should be timed to strobe data that is
valid between transitions.
Composite Sync from the Sync Stripper output CSOUT is
supplied to the HSYNC input as a reference for the internal
PLL. CSSOUT contains horizontal and vertical sync signals
that can be extracted by subsequent Sync processing logic. If
the vertical sync pulse omits horizontal sync or if serrations
or equalizing pulses are present, then the sync processing
logic should emit a COAST signal to disengage the PLL
from the HSYNC input during the Vertical Sync interval.
Vertical and horizontal sync waveforms within CSSOUT
signal frame the active video area.
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
C1
.047µF
R4
75
C2
0.18µF
U1
AD9884
R2
1.5K
VDD
C4
0.018µF
33
34
43
48
50
R3
75
7
15
22
SVGA
27
28
40
41
COAST
44
45
PWRDN\
29
SDA
30
SCL
31
32
14
1
2
3
36
37
38
46
127
115
116
117
125
126
BB [ 7..0]
PVD
PVD
PVD
PVD
PVD
RIN
GIN
DB _B7
DB _B6
DB _B5
DB _B4
DB _B3
DB _B2
D B_B1
DB _B0
DB _A7
DB _A6
DB _A5
DB _A4
DB _A3
DB _A2
DB _A1
DB _A0
BIN
CLKINV
CLAMP
HSIN
DG_B7
DG_B6
DG_B5
DG_B4
DG_B3
DG_B2
DG_B1
DG_B0
COAST
CKEXT
FILT
SDA
SCL
DG_A7
DG_A6
DG_A5
DG_A4
DG_A3
DG_A2
DG_A1
DG_A0
A0
A1
ACSIN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
DR_B7
DR_B6
DR_B5
DR_B4
DR_B3
DR_B2
DR_B1
DR_B0
REFIN
DR_A7
DR_A6
DR_A5
DR_A4
DR_A3
DR_A2
DR_A1
DR_A0
DATACK
DATACK
HSOUT
PWRDN
REFOUT
DCSOUT
55
56
57
58
59
60
61
62
BB7
BB6
BB5
BB4
BB3
BB2
BB1
BB0
65
66
67
68
69
70
71
72
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
75
76
77
78
79
80
81
82
GB7
GB6
GB5
GB4
GB3
GB2
GB1
GB0
85
86
87
88
89
90
91
92
GA7
GA6
GA5
GA4
GA3
GA2
GA1
GA0
RB[7..0]
95
96
97
98
99
100
101
102
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA[7..0]
105
106
107
108
109
110
111
112
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
BA [7..0]
GB[7..0]
GA[7..0]
118
5
6
9
12
13
17
20
21
24
26
35
39
42
47
49
51
52
53
63
73
83
93
103
11 3
11 9
12 1
12 2
12 3
C17
0.1µF
54
64
74
84
94
104
114
120
R1
75
VADC
DDV
DDV
DDV
DDV
DDV
DDV
DDV
DDV
C3
.047µF
C5
.047µF
VPLL
4
8
10
11
16
18
19
23
25
124
128
RED
GREEN
BLUE
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J1
DCK
DCK \
HSOUT
Figure 29. Schematic, VGA Digitizer, Dual Port Outputs
Printed Wiring Board Design Guidelines
3.
Layout traces as 75Ω transmission lines.
Recommended strategy is to mount the FMS9884A over a
ground plane with carefully routed analog inputs and digital
outputs. All connections should be treated as transmission
lines to ensure that reflections due to mismatches are minimized and ground return currents do not interfere with critical
signals.
4.
Avoid running analog traces near digital traces. Due to
the wide input bandwidth (500MHz) digital noise can
easily leak into analog inputs.
5.
If necessary, limit bandwidth by adding a ferrite bead in
series with each RGB input as shown in Figure 30. A
Fair-Rite #2508051217Z0 is recommended. Mismatches,
reflections and noise may cause ringing or distortion of
the incoming video signals.
6.
Locate the PLL filter clear of other signals.
Analog Inputs
Recommendations:
1.
Keep analog trace lengths short to minimize crosstalk.
2.
Terminate analog inputs with 75Ω resistors, placed
close to the FMS9884A analog inputs, RIN, GIN and
BIN. By matching transmission line impedances,
reflections will be minimized.
REV. 1.0.2 8/11/00
25
PRODUCT SPECIFICATION
7.
FMS9884A
Bypass the reference with a 0.1µF capacitor to ground.
L1
BEAD
C1
47nF
RIN, GIN, BIN
R, G, B INPUT
5.
If necessary terminate the HSIN input with 330/220Ω.
6.
If necessary, to reduce reflections, EMI or spikes add a
50–200Ω resistor at each data output pin.
7.
To minimize noise within the FMS9884A, restrict the
capacitive load at the digital outputs to < 10pF.
R1
75
Power and Ground
A schematic of the recommended power distribution is
shown in Figure 31. Note that:
Figure 30. RGB Input Filter
Digital I/O
Recommendations:
1.
Analog and digital circuits are layed out over a common
solid ground plane.
2.
Each FMS9884A pin is decoupled with a 0.1µF capacitor.
1.
Route digital I/O signals clear of analog inputs.
2.
Terminate clock lines to reduce reflections. Treat clock
lines as transmission lines.
3.
A group of pins may be de-coupled through a common
capacitor if no pin is more than 5 mm from the capacitor.
3.
Scale the HSIN input to 3.3V, using a resistor network
or a series 1 kΩ resistor.
4.
A separate regulated supply is used for the phase-locked
loop power supply, VDDP.
4.
Limit Serial Port inputs SDA and SDL with 150Ω
resistors connected directly to the pins.
5.
Capacitors are attached to each PLL pin or pin-pair.
Pins 33, 34
C2
0.01µF
Pin 43
C4
0.1µF
Pin 48
C6
0.01µF
U1
RC1117-3.3
L1
VPLL BEAD
Pin 50
2 OUT
3
IN
4 OUT ADJ/GND
+ C7
10 µF
C8
0.1µF
1
Power Input
C17
0.1µF
+
C7
10µF
L2
BEAD
VADC Pins
C10
C11
C12
C13
C14
C15
C16
C17
+ C9
10µF
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
U2
RC1117-3.3
L3
BEAD
VDD Pins
C18
C19
C20
C21
C22
C23
2 OUT
3
ADJ/GND IN
4
OUT
C24
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
+
C25
10µF
1
C17
0.1µF
Figure 31. Recommended Power Distribution
26
REV. 1.0.2 8/11/00
FMS9884A
Physical placement of PLL power supply decoupling components is critical. Bearing in mind the following suggestions:
1.
All components should be placed in close proximity to
the FMS9884A pins.
2.
Routing through vias should be avoided, if possible.
REV. 1.0.2 8/11/00
PRODUCT SPECIFICATION
3.
Each VDDP/GND pin pair: 33&34/35, 43/42, 48/47, and
50/49 should be decoupled with a 100–1000p/10µF pair
of capacitors (see Figure 31). If board space is limited,
use as many capacitor pairs as possible.
4.
Use Fair-rite 274 301 9447 bead.
27
PRODUCT SPECIFICATION
FMS9884A
Mechanical Dimensions
128-Lead MQFP (KA) Package
Notes:
Millimeters
Symbol
A
A1
A2
D
D1
D2
E
Notes
Min.
Typ.
Max
—
0.25
2.57
3.04
0.33
3.40
—
2.87
3, 5
0.95
4
E1
E2
L
N
e
0.65
b
0.13
2.71
22.60 BSC
20.00 BSC
18.00 BSC
17.20 BSC
14.00 BSC
12.00 BSC
0.70
128
0.50 BSC
—
1. All dimensions and tolerances conform to ANSI Y14.5M-1994.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254mm per side.
3. "N" is the number of terminals.
4. Dimension "b" does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm in excess of the "b"
dimension at the maximum material condition.
0.28
E
E1
2
E2
.40 Min.
e
0° Min.
0.13 R Min.
Datum Plane
D2
.13/.30 R
D1/2
D
L
0–7°
1.60 Ref.
Lead Detail
A2
See Lead Detail
Base Plane
A
A1
28
B
Seating Plane
-CLEAD COPLANARITY
ccc C
REV. 1.0.2 8/11/00
PRODUCT SPECIFICATION
FMS9884A
Ordering Information
Product Number
Temperature Range
Screening
Package
FMS9884AKAC100
0°C to 70°C
Commercial
128 Lead MQFP
FMS9884AKAC140
Package Marking
9884AKAC100
9884AKAC140
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
8/11/00 0.0m 006
Stock#DS30009884
 2000 Fairchild Semiconductor Corporation