ETC MX88L284AEC

MX88L284AEC
Revision: 1.06A
Table of Contents
GENERAL DESCRIPTION ...................................................................................................................................4
APPLICATIONS .....................................................................................................................................................4
FEATURES .............................................................................................................................................................4
GENERAL FEATURES ...............................................................................................................................................4
INPUT.....................................................................................................................................................................5
OUTPUT .................................................................................................................................................................5
CPU INTERFACE .....................................................................................................................................................6
MEMORY INTERFACE ..............................................................................................................................................6
POWER ...................................................................................................................................................................6
OTHERS .................................................................................................................................................................6
CHIP BLOCK DIAGRAM .....................................................................................................................................7
SYSTEM BLOCK DIAGRAM FOR LCD MONITOR (TTL AND PANELLINK/LVDS INTERFACED)........7
SYSTEM DIAGRAM W/O FRAME BUFFER......................................................................................................8
SYSTEM DIAGRAM FOR DIGITAL INPUT INTERFACE ...............................................................................8
PIN CONFIGURATIONS.......................................................................................................................................9
GENERAL DESCRIPTION .................................................................................................................................10
VIP (VIDEO INPUT PROCESSOR) FUNCTION DESCRIPTION.......................................................................................10
MIU (MEMORY INTERFACE UNIT) FUNCTIONAL DESCRIPTION ...............................................................................10
MEMORY CONFIGURATION TABLE .........................................................................................................................11
VOP (VIDEO OUTPUT PROCESSOR) FUNCTION DESCRIPTION ..................................................................................11
BIU (BUS INTERFACE UNIT) FUNCTION DESCRIPTION ............................................................................................11
PIN DESCRIPTION..............................................................................................................................................12
CPU INTERFACE PINS: (15 PINS) ...........................................................................................................................12
DRAM INTERFACE PINS: (52 PINS) ** 3.3 VOLT INTERFACE *** ..........................................................................12
INPUT INTERFACE PINS: (30 PINS)..........................................................................................................................13
LCD INTERFACE PINS: (53 PINS)...........................................................................................................................13
OSD INTERFACE PINS: (6 PINS) .............................................................................................................................14
INTERNAL VCG INTERFACE PINS: (2 PINS) ............................................................................................................14
OTHER INTERFACE PINS: (9 PINS) ..........................................................................................................................14
EXTERNAL CLOCK INPUT INTERFACE PINS: (2) .....................................................................................................15
POWER PINS: ........................................................................................................................................................15
AC CHARACTERISTICS ....................................................................................................................................16
AC TIMINGS IF THE LOAD OF ALL OUTPUT PINS IS 5~20PF........................................................................................16
1.
INPUT SIGNAL ........................................................................................................................................16
2. OUTPUT SIGNAL ................................................................................................................................................19
EXTERNAL OSD SIGNAL .......................................................................................................................................20
3. DIRECT CPU INTERFACE...................................................................................................................................21
4. SERIAL BUS INTERFACE.....................................................................................................................................22
5. FRAME MEMORY (SDRAM/SGRAM) INTERFACE ..............................................................................................23
6. EXTERNAL CLOCK INPUT INTERFACE .................................................................................................................25
2
MX88L284AEC
Revision: 1.06A
DC CHARACTERISTICS ....................................................................................................................................26
1. ENVIRONMENTAL SPECIFICATION: .....................................................................................................................26
2. STANDARD DC SPECIFICATION FOR 3.3 VOLTS OPERATION:...............................................................................26
DIMENSIONS .......................................................................................................................................................27
3
MX88L284AEC
Revision: 1.06A
General Description
The MX88L284AEC is a highly integration chip for Flat Panel Display application. It’s fully
compatible with MX88L284. With Macronix’s SmartscalingTM -2 filter, it provides high quality
scaled video image and format conversion capability.
Applications
•
LCD monitor
•
LCD projector
•
Other Flat Panel Display Application (DMD, PDP, PALC …
)
Features
General Features
• Converts NTSC/PAL and PC video signal into flat panel display device timing and
resolution
•
Provide Full frame buffer, reduce frame buffer (w/ compression) and frame buffer less
optional architecture.
•
Built-in memory and output clock generator
•
Built-in OSD generator with 64 ROM font, and 64 programmable RAM fonts
•
Provide 90 degree rotation for internal OSD to support portrait direction display
•
Arbitrary scaling from 1/32 to 32 times with filters (SmartScalingTM – 2+ Technology)
•
Support Auto-tracking and Auto-position capabilities (SmartTrackingTM Technology)
•
Support Auto-gain capability for input image
•
Support Flip and Mirror capabilities
•
On-chip brightness and contrast adjustments
•
On-chip γ correction for panel compensation
•
Support dynamic dithering capability to make 18 bit video as good as 24 bit quality
•
Support H/V Sync. Polarity and pulse width information for mode detection
•
Support two types of CPU interface (direct and serial bus)
4
MX88L284AEC
Revision: 1.06A
•
Provide 1 pixel/clock and 2 pixel/clock output to connect TFT LCD panel directly
•
Built-in Color space converter for video decoder input
•
Support configurable SDRAM/SGRAM (x0 x1 and x2 ) for different resolution to
minimize the system cost
•
Support Composite Sync. input
•
Support DPMS and H/V sync. Interrupt
Input
• PC video up to 1024 x 768 @ 85Hz
•
Support YCrCb422, RGB888 mode (Interlaced and Non-interlaced)
•
Support Philips, Samsung, and Techwell NTSC/PAL video decoder in 16 bit interface
•
Support TTL clock input
•
Support input H/V sync. polarity and odd/even field detection
•
Support digital input capability
Output
• Support TFT LCD panel in following resolution and frequency
Resolution
Horizontal frequency (KHz)
Vertical frequency (Hz)
Dot clock (MHz)
800x600
20 ~ 55
50 ~ 75
32.5 ~ 60
1024x768
20 ~ 70
50 ~ 75
25 ~ 80
Remark:
The Max. output resolution and frequency is depend on memory bus bandwidth, input resolution/frequency and image
size.
•
Single (18/24) and Dual (36/48) bit RGB data output
•
Support Inverse, delay adjustment and frequency adjustment for LCD panel clock
(LCKA and LCKB)
•
Support programmable H/V sync. and LDTG timing for LCD panel
•
Support OSD MUX capability for On-Screen-Display chip input
•
Built-in OSD generator
•
Built-in YCrCb to RGB color space converter
•
Built-in programmable Brightness and Contrast control
5
MX88L284AEC
Revision: 1.06A
•
Built-in programmable gamma correction table
•
Support Horizontal and Vertical position adjustment
•
Support SmartScalingTM -2+ or double scan capability for Interlaced input
•
Support Edge Filter control
CPU Interface
• Support direct 8 bit uP interface and serial bus (high-speed) interface
•
Support CPU line write/read and flush screen capability
Memory Interface
• Optimized single buffer design
•
Support Memory clock fine-tune and frequency programmable capabilities
•
Support 32/16 bit bus width
•
Support SDRAM/SGRAM x0 x1 and x2 configuration
•
Support power down mode
•
Support DRAM self test
Power
• Power supplier: 3.3 volt power supplier
•
Power Consumption: less than 1.5W
Others
• Support power down mode
•
Power on strapped input for system configuration
•
Support GPIO pins to minimized the system cost.
6
MX88L284AEC
Revision: 1.06A
Chip Block Diagram
SDRAM/SGRAM
RGB24/YUV
PIXIN
(RGB or
YCrCb)
Scale Down
with
SmartScaling-2
Technology
MIU
Color
conversion
Scale up
with
SmartScaling-2
Technology
DRAM
controller
VOP
Autotracking
Autoposition
Autogain
Mode Detection
De-Interlaced
BIU
VCG x 2
CPU I/F
Brightness
Contrast
control
OSD
Generator
Gamma
Correction
Odd/Even
Mux
Dithering
OSD MUX
Blending
PIXOUT - A
(RGB)
PIXOUT - B
(RGB)
VIP
(RGB24)
External OSD
System Block Diagram for LCD monitor (TTL and PanelLink/LVDS Interfaced)
LVDS or
PanelLink
Transmitter
SDRAM or
SGRAM
Composite
S-Video
Video
Decoder
Video (YUV)
18/24 bit RGB
PC (RGB)
Pre-AMP
l
l
l
AD9884
TDA8752
SCL/Panstera
FPD MONITOR
CONTROLLER 18/24 bit RGB
ADC
H/V Sync,
CLK and DE
PLL 1
ROM
8/16 bit uP
7
OSD
GENERATOR
FPD
Panel
MX88L284AEC
Revision: 1.06A
System Diagram W/O Frame Buffer
PC (RGB)
Pre-AMP
18/24 bit RGB
ADC
FPD MONITOR
CONTROLLER 18/24 bit RGB
H/V Sync,
CLK and DE
PLL
ROM
FPD
Panel
8/16 bit uP
OSD
GENERATOR
System Diagram for Digital input Interface
24 bit RGB
PC (Digital
Signal)
Receiver
18/24 bit RGB
FPD MONITOR
CONTROLLER 18/24 bit RGB
H/V Sync,
CLK and DE
H/V Sync,
CLK and DE
8bit uP
8
FPD
Panel
MX88L284AEC
Revision: 1.06A
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DQM1
DQM0
VDDP
RAS#
CAS#
WE#
CKE
GNDP
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
VDDP
MA10
GND
MCLK
GNDP
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
VDDP
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
GNDP
DQM3
DQM2
VDD
OSDBLINK
OSDB
OSDG
OSDR
I2CDLK
I2CDATA
GOUT2
VDDP
Pin Configurations
GNDP
GND
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
VDDP
VDD
MD7
GNDP
MD6
MD5
MD4
MD3
MD2
MD1
MD0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GNDP
CPUA15/BCS#
VDDP
ALE
WR#
RD#
TMCLK
RST#
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
IRQ
SOGCS
TDCLK/CSYNC
HSYNC1
VSYNC1
GOUT3
GND
DCLKA
GNDP
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
MX88L284AEC
MX88L284
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GB4
GB5
GB6
GB7
VDDP
BB0
GNDP
BB1
BB2
BB3
BB4
BB5
BB6
BB7
VDDP
AVDD2
AVDD1
XO
XI
AGND1
AGND2
GNDP
GND
DDE
PIXINA16
PIXINA17
PIXINA18
PIXINA19
PIXINA20
PIXINA21
PIXINA22
PIXINA23
VDD
PIXINA8
PIXINA9
PIXINA10
PIXINA11
PIXINA12
PIXINA13
PIXINA14
PIXINA15
CLAMP
PIXINA0
PIXINA1
PIXINA2
PIXINA3
PIXINA4
PIXINA5
PIXINA6
PIXINA7
VDDP
BUSTYPE
9
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
73
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
GOUT1
GNDP
GOUT0
LDTG
LVSYNC
LHSYNC
RA0
RA1
RA2
RA3
RA4
RA5
RA6
GNDP
RA7
VDDP
VDD
GA0
GA1
GA2
GA3
GA4
GA5
GA6
GA7
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
GNDP
LCKA
GND
LCKB
GNDP
RB0
VDDP
RB1
RB2
RB3
RB4
RB5
RB6
RB7
GNDP
GB0
GB1
GB2
GB3
MX88L284AEC
Revision: 1.06A
General Description
There are four major parts in this chip which include VIP (Video Input Processor), MIU (Memory
Interface Unit), VOP (Video Output Processor) and BIU (CPU Bus Interface Unit). Following is the block
and description of these parts.
SDRAM or
SGRAM
PC (RGB)/
Video (YUV)
VIP
VIP LB
MIU
VOP LB
VOP
FPD
Panel
BIU
OSD
8/16 bit uP
GENERATOR
Fig. 1 Chip Level Block Diagram
VIP (Video Input Processor) Function Description
VIP is a Video Input Process unit which processes incoming data either from Graphic card or Video
Decoder.
With Line Buffers and Decimation logic based on proprietary SmartscalingTM –2 algorithm , it can process
input data and then write to frame buffer . Furthermore, it can detect the polarity of input H/V SYNC and
then do the normalization of them and also detect the ODD/EVEN field of the input interlaced data. It can
also measure the pulse width and period of input H/V SYNC for system application purposes.
Video encoder interface is supported for video image input.
MIU (Memory Interface Unit) Functional Description
MIU is a interface unit between external DRAM and this chip. We support 6 kinds of configurations for
SDRAM and SGRAM through POWER_ON Strapped_Input or register defined value.
DRAM Configuration (Support 8M SGRAM and 16M SDRAM)
DRAM Type
DRAM Number
Bus Width
SGRAM
1
32 bits
SGRAM
2
32 bits
SDRAM
1
16 bits
SDRAM
2
32 bits
10
MX88L284AEC
Revision: 1.06A
Memory Configuration Table
Input Resolution
NO. of SGRAM
NO. of SDRAM
YCrCb
1
1
640X480
1/2
1
800X600
1
2
1024X768
1 or 2
2
1280X1024
2
2
VOP (Video Output Processor) Function Description
VOP is a Video Output Process unit which reads data from Frame buffer and then process it to display Flat
panel Display.
With Line Buffers and Scale- up logic based on proprietary SmartscalingTM –2 algorithm, it can enlarge
image smoothly. Furthermore, it provides many adjusting functions like programmable Brightness and
Contrast control, programmable GAMMA table, programmable Dithering control, and OSD MUX to
adjust the output quality. It also provides Single/Dual output to cope with different flat panels display
device.
BIU (Bus Interface Unit) Function Description
BIU is a bus interface unit between the host CPU and MX88281/MX88282, which supports two bus
types : direct and Serial Bus through POWER_ON Strapped_Input value.
It also supports 3 functions to access frame buffer:
1.
Line Write Allow WRITE data from CPU to frame buffer line by line.
2.
Flush Write Allow WRITE assigned color data defined in the register to frame buffer to clean screen.
3.
Line Read Allow READ data from frame buffer to CPU line by line.
11
MX88L284AEC
Revision: 1.06A
Pin Description
CPU Interface Pins: (15 pins)
Pin Name
Drive
I/O
No.
I
193
System reset.
IO
185-178
Multiplexed low_order address and data bus.
AD7/SBCLK
185
Serial Bus Clock
AD6/SBDATA
184
Serial Bus Data
AD5/SBCS#
183
Serial Bus CS# Low Active
RSTZ#
AD[7:0]
4 mA
DESCRIPTION
CPUA15/BCS
I
187
high_order a15 address input, or BIU Valid
cycle.(for ISA bus debug)
ALE
I
189
Address Latch Enable for 8051 Bus.
WR#
I
190
Memory Write Strobe.
RD#
I
191
Memory Read Strobe
BUSTYPE
I
1
Bus type select
IRQ
O
200
Interrupt request
DRAM Interface Pins: (52 pins) ** 3.3 Volt Interface ***
Pin Name
Drive
I/O
No.
DESCRIPTION
MCLK
20 mA
O
135
Memory clock
CKE
4 mA
O
150
Memory clock enable
RAS#
8 mA
O
153
Row address strobe
CAS#
8 mA
O
152
Column address strobe
WE#
8 mA
O
151
Write Enable
DQM[3:0]
8 mA
O
115,114,
data mask byte enable (For SGRAM)
156,155
MA[10:0]
8 mA
O
137,139148
Memory address
MD[31:0]
4 mA
IO
117-124,
Memory data input/output
126-133,
159-166,
169,
171-177,
12
MX88L284AEC
Revision: 1.06A
Input Interface Pins: (30 pins)
I/O
No.
DESCRIPTION
DCLKA
I
207
Input dot clock
VSYNC1
I
204
Input VSYNC
HSYNC1
I
203
Input HSYNC
SOGCS
I
201
Input Sync on Green composite Sync
PIXINA[7:0]
I
3-10
Pixel input A RED[7:0] from ADC.
Pin Name
Drive
Y[7:0]: Luminance data from Video Decoder.
PIXINA[15:8]
I
12-19
Pixel input A GREEN[7:0] from ADC.
CbCr[7:0]: Color data from Video Decoder.
PIXINA[23:16]
I
21-28
Pixel Input A BLUE[7:0] from ADC.
D23: MPLLC2, (Video input clk signal)/2.
D22: MPHS, Video input Hsync signal.
D21: MPVS, Video input Vsync signal.
D20: MPODD, Video input Odd/Even field signal.
D19: MPHREF, Video input horizontal reference
signal.
D18: MPLLC, Video input clk signal.
D17: MPCREF, Video input clk reference ignal
D16: MPVREF, Video input vertical reference
signal.
DDE
16 mA
I
29
Digital display enable input pin
CLAMP
2 mA
O
11
Clamp signal
LCD Interface Pins: (53 pins)
Pin Name
Drive
I/O
No.
DESCRIPTION
RA[7:0]
4 mA
O
90, 9298
RED DATA (Odd),
GA[7:0]
4 mA
O
80-87
GREEN DATA (Odd),
BA[7:0]
4 mA
O
72-79
BLUE DATA (Odd),
RB[7:0]
4 mA
O
58-64,
66
RED DATA (Even).
GB[7:0]
4 mA
O
49-56
GREEN DATA (Even).
BB[7:0]
4 mA
O
39-45,
47
BLUE DATA (Even),
LVSYNC
8 mA
O
100
VSYNC output for LCD display.
13
MX88L284AEC
Revision: 1.06A
Pin Name
Drive
I/O
No.
DESCRIPTION
LHSYNC
8 mA
O
99
HSYNC output for LCD display.
LDTG
8 mA
O
101
Data Enable output for LCD display.
LCKA
16 mA
O
70
Odd data clock output for LCD display.
LCKB
16 mA
O
68
Even data clock output for LCD display.
I/O
No.
DESCRIPTION
OSDR
I
109
OSD RED input
OSDG
I
110
OSD GREEN input
OSDB
I
111
OSD BLUE input
OSDBLNK
I
112
OSD select.
OSD interface Pins: (6 pins)
Pin Name
Drive
OSDR0
/OSDINT/GOUT2
4mA
I/O
106
Extended OSD RED input or use as Motorola
OSD intensity input ( Output Share With GOUT4)
OSDG0/GOUT1
2mA
I/O
104
Extended OSD GREEN input (Support in 6-bit
format)
Output Share with GOUT1
OSDB0/GOUT0
2mA
I/O
102
Extended OSD BLUE input (Support in 6 -bit
format)
Output Share with GOUT0
I2CCLK
4 mA
IO
108
I2C CLK.
Pull up by internal 20K Ohm resistor
I2CDATA
4 mA
IO
107
I2C DATA.
Pull up by internal 20K Ohm resistor
Internal VCG Interface Pins: (2 pins)
Pin Name
I/O
No.
DESCRIPTION
XI
I
34
Analog pad for Reference Frequency Input for internal
oscillator.
XO
O
35
Analog pad for Reference Frequency Output for internal
oscillator.
Other Interface Pins: (9 pins)
Pin Name
Drive
I/O
No.
DESCRIPTION
GOUT3
4 mA
O
205
General Output 3
GOUT2
4 mA
O
106
General Output 2
14
MX88L284AEC
Revision: 1.06A
Pin Name
Drive
I/O
No.
DESCRIPTION
GOUT1
2 mA
O
104
General Output1
GOUT0
2 mA
O
102
General Output0
GPIOA[5:0]
2 mA
IO
199-194 General I/O
GPIOA[5] : Input select
GPIOA[4] : PDEN for External PLL
GPIOA[3] : DS for External ADC
GPIOA[1] : ADC-Coast source select
GPIOA[0] : Hsync source select
Pull down by internal 20Kohm resistors
External Clock Input Interface Pins: (2)
Pin Name
I/O
No.
DESCRIPTION
TMCLK
I
192
External MCLK input
TDCLK/CSYNC
I
202
External DCLK input/Composite Sync input
Power Pins:
All Power 3.3 Volt
Pin Name
No.
DESCRIPTION
VDD
20,88,113,168
Core Power
GND
30,69,136,158, 206
Core GND
VDDP
2,38,48,65,89,105,125,138,154,167,1
88
PAD Power
GNDP
31,46,57,67,71,91,103,116,
134,149,157,170,186,208
PAD GND
AVDD
36 ,37
Analog Power
32,33
Analog GND
AGND
Remark:
1. All the input loading is 5pf
2. Driving capability is measured under 30pf loading
3. MCLK, LCKA driving capability is measured under 50pf loading
15
MX88L284AEC
Revision: 1.06A
AC Characteristics
AC timings if the load of all output pins is 5~20pF
1. Input signal
AC timing of input horizontal sync
Dead window
Note : in the following case, it assumes that registerE4.bit6 is 0, and registerF1 and F2 are 0x00
Case
Register10, bit 5
RegisterE8, bit 5:4
remark
0
00,10 or 11
Low power disabled, HSYNC1 strobed
Note : it assumes the DCLKA rising edge is at 0 ns
Case
Dead window for HSYNC1
1~6ns
16
MX88L284AEC
Revision: 1.06A
DCLKA
HSYNC1
PIXINA
2.0V
2.0V
0.8V
tIS0S
tIS1S
tIS0H
tIS1H
Symbol
Parameter
Min.
tIS1S
Input image PIXINA setup time for DCLKA
-1
ns
tIS0S
Input image HSYNC1 setup time for DCLKA
tIS1H
Input image PIXINA hold time for DCLKA
7
ns
tIS0H
Input image HSYNC1 hold time for DCLKA
6
ns
17
Max.
Unit
MX88L284AEC
Revision: 1.06A
(note2 : MX88L284 does not need tIS0S/tIS0H for VSYNC1 to properly operate if regE8[6:4]=111)
(note3 : -1ns means that PIXINA and HSYNC1 can be earlier than, or late than DCLKA by less than 1ns,
without sampling problem. These -1ns and 7/6ns might look non-straightforward, it’s because there is added
internal delay for DCLKA to gain more safety margin and prevent any sampling problem caused by skew
between PIXINA/HSYNC1 and DCLKA on the PCB board)
DCLKA
2.0V
-1ns
HSYNC1
PIXINA
tDLY1
2.0V
Internal DCLKA
tDLY2, tDLY3
Internal HSYNC1
Internal PIXINA
18
MX88L284AEC
Revision: 1.06A
2. Output signal
1. the setup/hold time of pixel data, LHSYNC and LDTG with respect to LCKA
(5pF <= load of signal data <= load of LCKA <= 15pF)
Tjitter=0.12ns
The worst case of
Ts happens if load
of LCKA and
Signals are 15pF
2.4V
LCKA
7.65ns
+3.5ns
LHSYNC
LDTG
PIXOUT [N]
Th
Ts=4.09ns
Tjitter=0.12ns
The worst case of
Ts happens if load
of LCKA is 15pF,
and load of Signals
are 5pF
LCKA
7.65ns
-2.4ns
LHSYNC
LDTG
PIXOUT [N]
Ts
19
Th=4.84ns
0.35ns
MX88L284AEC
Revision: 1.06A
Symbol
Parameter
Min.
Max.
Unit
TOS1DL
Output LHSYNC, LDTG, Pixel Signal output delay
-2.4
3.5
ns
External OSD signal
OSDCLK
(GOUT1)
2.4V
OSDBLINK
OSDR
OSDG
OSDB
TOSDS
TOSDH
Symbol
Parameter
Min.
Max.
Unit
tOSDS
OSD input setup time
3
ns
tOSDH
OSD input hold time
2
ns
(note : this data value is measured at the condition of regA5[7:0]=0000_0000, regA6[7:0]=0000_0100)
20
MX88L284AEC
Revision: 1.06A
3. Direct CPU Interface
TWHLH
ALE
TLLWL
TWLWH
WR/RD
TWHQX
TAVLL
TLLAX
TWSQX
A0-A7
AD(7:0)/WR
DATA OUT
A0-A7
TAVWL
A0-A7
AD(7:0)/RD
DATA OUT
TRRS
TRDLY
TRDOFFF
Symbol
Parameter
Min.
Max.
Unit
TAVLL
Address Valid to ALE Low
6
ns
TLLAX
Address Hold After ALE Low
6
ns
TWLWH
WR Pulse Width
40
ns
TWSQX
Data Setup Before WR
6
ns
TWHQX
Data Hold After WR
6
ns
TWHLH
---
*
TRDLY
*
*
Data delay after RD Low
35
ns
TRDOFF
Data off delay after RD High
15
ns
TALLWL
ALE falling edge to Write active Low
15
TAVWL
Address Valid to Write Active Low
21
TRRS
Minimum Address Release time from Address
0
to invalid RD active Low
(note : there is no need of tWHLH for MX88L284AEC to operate properly)
21
MX88L284AEC
Revision: 1.06A
4. Serial Bus Interface
Tcsck
SBCSZ
Tcp
Tckcs
Tc1
SBCLK
Tch
SBDATA
(WRITE)
Tds
Tdh
Tdd
SBDATA
(READ)
Tdd
Symbol
Parameter
Min.
Tcsck
CS to CLK Start
15
ns
Tckcs
CLK to CS high
15
ns
Tds
Data setup time versus CLK
3
ns
Tdh
Data hold time versus CLK
4
ns
Tdd
Data delay time
5
22
Max.
16
Unit
ns
MX88L284AEC
Revision: 1.06A
5. Frame memory (SDRAM/SGRAM) Interface
0.4v
MCLK
2.4v
RAS,CAS,MA,MD,
WE,DQM,CKE
0.4v
WE=0
(Write)
Tfmdl (MCLK falling edge to output signals)
Load of
MCLK(pF)
Load of signals(pF)
Min(ns)
Max(ns)
5~20
5~20
-1.5*
2.5
5
5
0
2
20
20
-1.5
2.3
(note1 : this data value is measured at the condition of reg91[3:0]=1000. Reg91[3:0] is used to choose
MCLK inversion and internal delay time
note2 : -1.5ns means that memory data and control signals may appear earlier than MCLK)
23
MX88L284AEC
Revision: 1.06A
2.4v
MCLK
2.4v
MD
WE=1
(Read)
0.4v
tFMDS
tFMDH
Min(ns)
tFMDS
1
tFMDH
1.5
Max(ns)
(note : this data value is measured at the condition of reg92[7]=1. Reg92[7] is used to choose
either internal memory clock or pad feedback MCLK as MD’s sampling clock)
24
MX88L284AEC
Revision: 1.06A
6. External Clock Input Interface
Symbol
Parameter
Min.
Fclk
Maximum TMCLK/TDCLK input frequency
Fpw
Minimum pulse width
3
25
Max.
Unit
80
MHz
ns
MX88L284AEC
Revision: 1.06A
DC characteristics
1. Environmental specification:
Rating
Value
Unit
Ambient Operating Temperature
0 to 70
°C
Storage Temperature
-55 to 125
°C
Maximum Junction Temperature
125
°C
Maximum Case Temperature
100
°C
2. Standard DC Specification for 3.3 Volts Operation:
(Ta=0°C to 70°C, VCC=3V to 3.6V)
Symbol
Parameter
Min
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
RPU
I/O Pull-up Resistance
RPD
Max
Unit
V
0.5
0.7VCC
V
V
0.8
V
15
100
KOhm
I/O Pull-down Resistance
15
100
KOhm
ILI
Input Leakage Current
-10
+10
uA
ILO
Output Leakage Current
-20
+20
uA
26
Conditions
MX88L284AEC
Revision: 1.06A
Dimensions
D
28.00 ±0.05
ZD
D3
DETAIL "A" 144F2828-A160F2828-A208F2828-A 256F2828-A
15
DETAIL "A"
R 0.15
E
E3
28.00±0.05
3-
10°
R 0.20
5
N
L
2.54
0.22
0.18
0.10
0.10
b1
0.30
0.30
0.20
0.10
0.16
e
0.65
L1
1.60
0.65
1.60
1.30
L
ZE (REF.)
0.80
1.33
0.80
1.33
E3 (REF.)
25.35
25.35
31.2
2.63
25.35
31.2
1.33
1.25
30.6
1.40
25.35
25.50
25.20
31.2
0.35
31.2
30.6
30.6
0.35
0.35
N
3.80
144L
3.80
160L
0.35
3.80
208L
3.80
256L
JEDEC
MO-108
DC-1
MO-108
DD-1
MO-143
FA-1
MO-143
FB1
D3 (REF.)
D
A1
A (MAX.)
A
DATUM PLANE
0.32
0.10
ZD (REF.)
1.60
12
L1
0.32
C
E
TERMINAL
DETAILS
ZE
2.54
DETAIL "B"
b
0.50
0.50
1.25
25.50
30.6
0.40
1.30
0.50
1.25
25.50
BASE PLANE
0.15 TYP.
e
e/2
b
A1
0.10MM
SEATING PLANE
WITH PLATING
b
C
BASE METAL
b1
DETAIL "B"
DETAIL "A"
DWG. NO.
6110-0212
TOLERANCE
Macronix International Co., Ltd.
TITLE
OUTLINE DIMENSIONS FOR
QFP2828 MM PACKAGE
DRAWN
CH Lin
27
APPROVED
JW Lin
ANGLE
SCALE UNIT
mm
REVISION
2