HT24LC04 4K 2-Wire CMOS Serial EEPROM Features · · · · · · Operating voltage: 2.4V~5.5V Low power consumption - Operation: 5mA max. - Standby: 5mA max. Internal organization - 4K (HT24LC04): 512´8 2-wire serial interface Write cycle time: 5ms max. Automatic erase-before-write operation · · · · · · · · Partial page write allowed 8-byte page write modes Write operation with built-in timer Hardware controlled write protection 40-year data retention 106 erase/write cycles per word 8-pin DIP/SOP/TSSOP package Commerical temperature range (0°C to +70°C) General Description The HT24LC04 is a 4K-bit serial read/write non-volatile memory device using the CMOS floating gate process. Its 4096 bits of memory are organized into 512 words and each word is 8 bits. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. Up to four HT24LC04 devices may be connected to the same two-wire bus. The HT24LC04 is guaranteed for 1M erase/write cycles and 40-year data retention. Block Diagram Pin Assignment S C L S D A I/O C o n tro l L o g ic H V P u m p X W P M e m o ry C o n tro l L o g ic E E P R O M A rra y D E A 0 1 8 V C C A 1 2 7 W P A 2 3 6 S C L V S S 4 5 S D A H T 2 4 L C 0 4 8 D IP /S O P /T S S O P C P a g e B u f Y D E C A 0 ~ A 2 A d d re s s C o u n te r S e n s e A M P R /W C o n tro l V C C V S S 1 6th May ¢99 HT24LC04 Pin Description Pin No. Pin Name I/O Description 1~3 A0~A2 I Address inputs 4 VSS — Negative power supply 5 SDA I/O Serial data inputs/output 6 SCL I Serial clock data input 7 WP I Write protect 8 VCC I Positive power supply Absolute Maximum Ratings Operating Temperature (Commercial) ................................................................................. 0°C to 70°C Storage Temperature ....................................................................................................... –50°C to 125°C Applied VCC Voltage with Respect to VSS ........................................................................ –0.3V to 6.0V Applied Voltage on any Pin with Respect to VSS .................................................................. –0.3V to VCC+0.3V Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Ta=0°C to 70°C D.C. Characteristics Symbol Parameter Test Conditions VCC Conditions Min. Typ. Max. Unit VCC Operating Voltage — — 2.4 — 5.5 V ICC1 Operating Current 5V Read at 100kHz — — 2 mA ICC2 Operating Current 5V Write at 100kHz — — 5 mA VIL Input Low Voltage — — –1 — 0.3VCC V VIH Input High Voltage — — 0.7VCC — VCC+0.5 V VOL Output Low Voltage — — 0.4 V ILI Input Leakage Current 5V VIN=0 or VCC — — 1 µA ILO Output Leakage Current 5V VOUT=0 or VCC — — 1 µA ISTB1 Standby Current 5V VIN=0 or VCC — — 5 µA ISTB2 Standby Current 2.4V VIN=0 or VCC — — 4 µA CIN Input Capacitance (See Note) — f=1MHz 25°C — — 6 pF COUT Output Capacitance (See Note) — f=1MHz 25°C — — 8 pF 2.4V IOL=2.1mA Note: These parameters are periodically sampled but not 100% tested 2 6th May ’99 HT24LC04 Ta=0°C to 70°C A.C. Characteristics Symbol Parameter Remark Standard Mode* VCC=5V±10% Min. Max. Min. Max. — 100 — 400 Unit fSK Clock Frequency tHIGH Clock High Time 4000 — 600 — ns tLOW Clock Low Time 4700 — 1200 — ns tR SDA and SCL Rise Time Note — 1000 — 300 ns tF SDA and SCL Fall Time Note — 300 — 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 4000 — 600 — ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 4000 — 600 — ns tHD:DAT Data Input Hold Time 0 — 0 — ns tSU:DAT Data Input Setup Time 200 — 100 — ns tSU:STO STOP Condition Setup Time 4000 — 600 — ns tAA Output Valid from Clock — 3500 — 900 ns 4700 — 1200 — ns — 100 — 50 ns — 5 — 5 ms tBUF Bus Free Time Time in which the bus must be free before a new transmission can start tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time tWR Write Cycle Time kHz Notes: These parameters are periodically sampled but not 100% tested * The standard mode means V CC=2.4V to 5.5V For relative timing, refer to timing diagrams 3 6th May ’99 HT24LC04 Functional Description • Serial clock (SCL) line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition. The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. • Start condition • Serial data (SDA) A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram). The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. • Stop condition • A0, A1, A2 A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). The HT24LC04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is not connected. (The device addressing is discussed in detail under the Device Addressing section). • Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. • Write protect (WP) The HT24LC04 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to the VSS. When the write protect pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following table. Protect Array WP Pin Status HT24LC04 At VCC At VSS Full Array (4K) Normal Read/Write Operations Device addressing Memory organization The 4K EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to diagram showing the Device Address). This is common to all the EEPROM device. • HT24LC04, 4K Serial EEPROM Internally organized with 512 8-bit words, random word addressing requires a 9-bit data word address. Device operations • Clock and data transition The next three bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These three bits must compare to their corresponding hard-wired input pins. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock 4 6th May ’99 HT24LC04 • Page write The 4K EEPROM only use the A2 and A1 device address bits with the third bit as a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is not connected. The 4K device is capable of 16-byte page writes. A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition. The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state. The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location (refer to Page write timing). Write operations • Byte write • Acknowledge polling A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write is completed (refer to Byte write timing). Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W=0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is completed, then the device will return the ACK and the master can then proceed with the next read or write command. 5 6th May ’99 HT24LC04 • Write protect The HT24LC04 can be used as a serial ROM when the WP pin is connected to VCC. Programming will be inhibited and the entire memory will be write-protected. • Read operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. • Current address read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but generates a following stop condition (refer to Current read timing). Acknowledge polling flow • Random read A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generates a following stop condition (refer to Random read timing). 6 6th May ’99 HT24LC04 • Sequential read words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition (refer to Sequential read timing). Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data Timing Diagrams Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. 7 6th May ’99 HT24LC04 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holtek Semiconductor (Shanghai) Ltd. 7th Floor, Building 2, No.889, Yi Shan Road, Shanghai, China Tel:021-6485-5560 Fax:021-6485-0313 Holmate Technology Corp. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 8 May 6, 1999