AD ADSP-2171KST-104

a
DSP Microcomputer
ADSP-2171/ADSP-2172/ADSP-2173
FEATURES
30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V
ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipulation Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
2K Words of On-Chip Program Memory RAM
2K Words of On-Chip Data Memory RAM
8K Words of On-Chip Program Memory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 mW Typical Power Dissipation at 5.0 V at 30 ns
70 mW Typical Power Dissipation at 3.3 V at 50 ns
Powerdown Mode Featuring Less than 0.55 mW (ADSP2171/ADSP-2172) or 0.36 mW (ADSP-2173) CMOS
Standby Power Dissipation with 100 Cycle Recovery
from Powerdown
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
GENERAL DESCRIPTION
The ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. The
ADSP-2171 and ADSP-2172 are designed for 5.0 V applications. The ADSP-2173 is designed for 3.3 V applications. The
ADSP-2172 also has 8K words (24-bit) of program ROM.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1
PROGRAM
ROM
8K x 24
PROGRAM
SEQUENCER
PROGRAM
RAM
2K x 24
DAG 2
MEMORY
DATA
MEMORY
2K x 16
POWERDOWN
CONTROL
LOGIC
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
EXTERNAL
DATA
BUS
TIMER
SERIAL PORTS
SPORT 0
SPORT 1
HOST
INTERFACE
PORT
ADSP-2100 BASE
ARCHITECTURE
The ADSP-217x combines the ADSP-2100 base architecture
(three computational units, data address generators, and a program sequencer) with two serial ports, a host interface port, a
programmable timer, extensive interrupt capabilities, and onchip program and data memory.
In addition, the ADSP-217x supports new instructions, which
include bit manipulations–bit set, bit clear, bit toggle, bit test–
new ALU constants, new multiplication instruction (x squared),
biased rounding, and global interrupt masking, for increased
flexibility. The ADSP-217x also has a Bus Grant Hang Logic
(BGH) feature.
The ADSP-217x provides 2K words (24-bit) of program RAM
and 2K words (16-bit) of data memory. The ADSP-2172 provides an additional 8K words (24-bit) of program ROM. Powerdown circuitry is also provided to meet the low power needs of
battery operated portable equipment. The ADSP-217x is available in 128-pin TQFP and 128-pin PQFP packages.
Fabricated in a high-speed, double metal, low power, CMOS
process, the ADSP-217X operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-217x’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-217x can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
This takes place while the processor continues to:
• receive and transmit data through the two serial ports
• receive and/or transmit data through the host interface port
• decrement timer
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADSP-2171/ADSP-2172/ADSP-2173
Development System
Additional Information
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-217x. The System Builder provides a high-level
method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into
an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-217x assembly source
code. The Runtime Library includes over 100 ANSI-standard
mathematical and DSP-specific functions.
This data sheet provides a general overview of ADSP-217x
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the Development
System and ADSP-217x programmer’s reference information,
refer to the ADSP-2100 Family Assembler Tools & Simulator
Manual.
ARCHITECTURE OVERVIEW
Figure 1 is an overall block diagram of the ADSP-217x. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
EZ-Tools, low cost, easy-to-use hardware tools, also support the
ADSP-217x.
The ADSP-217x EZ-ICE® Emulator aids in the hardware debugging of ADSP-217x systems. The emulator consists of hardware, host computer resident software, the emulator probe, and
the pin adaptor. The emulator performs a full range of emulation functions including stand-alone operation or operation in
the target, setting up to 20 breakpoints, single-step or full-speed
operation in the target, examining and altering registers and
memory values, and PC upload/download functions. If you plan
to use the emulator, you should consider the emulator’s restrictions (differences between emulator and processor operation).
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-217x executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
The EZ-LAB® Evaluation Board is a PC plug-in card, but it can
operate in stand-alone mode. The evaluation board/system development board executes EPROM-based or downloaded programs. Modular Analog Front End daughter cards with different
codecs will be made available.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PROGRAM ROM
8K X 24
PROGRAM SRAM
2K X 24
PROGRAM
SEQUENCER
14
BOOT
ADDRESS
GENERATOR
DATA
SRAM
2K X 16
2
POWER DOWN
CONTROL
LOGIC
3
FLAGS
EXTERNAL
ADDRESS
BUS
PMA BUS
14
14
DMA BUS
24
PMD BUS
MUX
EXTERNAL
DATA
BUS
24
BUS
EXCHANGE
16
INPUT REGS
INPUT REGS
INPUT REGS
ALU
MAC
SHIFTER
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
MUX
DMD BUS
COMPANDING
CIRCUITRY
CONTROL
LOGIC
TIMER
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
RECEIVE REG
SERIAL
PORT 0
SERIAL
PORT 1
16
R BUS
5
HIP
CONTROL
11
HIP
DATA
BUS
HIP
REGISTERS
16
5
Figure 1. ADSP-217x Block Diagram
–2–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
and loaded from the EPROM with no additional hardware. The
on-chip program memory can also be initialized through the
HIP.
The ADSP-217x features three general-purpose flag outputs
whose states can be simultaneously changed through software.
You can use these outputs to signal an event to an external
device. In addition, the data input and output pins on SPORT1
can be alternatively configured as an input flag and an output
flag.
Efficient data transfer is achieved with the use of five internal
buses.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycles, where n-l is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
The ADSP-217x instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The ADSP-217x assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus.
Program memory can store both instructions and data, permitting the ADSP-217x to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP217x can fetch an operand from on-chip program memory and
the next instruction in the same cycle.
Serial Ports
The ADSP-217x incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of external buses with bus
request/grant signals (BR and BG). One execution mode (Go
Mode) allows the ADSP-217x to continue running from internal memory. Normal execution mode requires the processor to
halt while buses are granted.
Here is a brief list of the capabilities of the ADSP-217x
SPORTs. Refer to the ADSP-2100 Family User’s Manual for
further details.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their own
serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
In addition to the address and data bus for external memory
connection, the ADSP-217x has a configurable 8- or 16-bit
Host Interface Port (HIP) for easy connection to a host processor. The HIP is made up of 16 data/address pins and 11 control
pins. The HIP is extremely flexible and provides a simple interface to a variety of host processors. For example, the Motorola
68000 series, the Intel 80C51 series and the Analog Devices’
ADSP-2101 can be easily connected to the HIP. The host processor can initialize the ASDP-217x’s on-chip memory through
the HIP.
The ADSP-217x can respond to eleven interrupts. There can be
up to three external interrupts, configured as edge or level sensitive, and eight internal interrupts generated by the Timer, the
Serial Ports (“SPORTs”), the HIP, the powerdown circuitry,
and software. There is also a master RESET signal.
The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable
serial clock or accept an external serial clock.
Boot circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
seven wait states are automatically generated. This allows, for
example, a 30 ns ADSP-217x to use an external 200 ns
EPROM as boot memory. Multiple programs can be selected
REV. A
–3–
ADSP-2171/ADSP-2172/ADSP-2173
Pin Description
The ADSP-217x is available in 128-lead TQFP and 128-lead
PQFP packages. Table I contains the pin descriptions.
Table I. ADSP-217x Pin List
Pin
Group
Name
#
of
Input/
Pins Output Function
Address
14
O
Data
24
I/O
Address output for program,
data and boot memory spaces
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2
External bus request input
External bus grant output
External bus grant hang output
External program memory select
External data memory select
Boot memory select
External memory read enable
External memory write enable
Memory map select
RESET
IRQ2
BR
BG
BGH
PMS
DMS
BMS
RD
WR
MMAP
CLKIN,
XTAL
1
1
1
1
1
1
1
1
1
1
1
I
I
I
O
O
O
O
O
O
O
I
2
I
CLKOUT
HSEL
HACK
HSIZE
1
1
1
1
O
I
O
BMODE
1
I
HMD0
1
I
HMD1
1
I
HRD/HRW
1
I
HWR/HDS
1
I
HD15–0/
HAD15-0
HA2/ALE
16
1
I/O
I
HIP data/data and address
Host address 2/Address latch
enable input
HA1–0/
Unused
SPORT0
2
5
I
I/O
Host addresses 1 and 0 inputs
Serial port 0 I/O pins (TFS0,
RFS0, DT0, DR0, SCLK0)
SPORT1
or
IRQ1 (TFS1)
IRQ0 (RFS1)
SCLK1
FO (DT1)
FI (DR1)
FL2–0
5
I/O
Serial port 1 I/O pins
1
1
1
1
1
3
I
I
O
O
I
O
VDD
GND
PWD
PWDACK
6
11
1
1
I
O
External interrupt request #1
External interrupt request #0
Programmable clock output
Flag Output pin
Flag Input pin
General purpose flag output
pins
Power supply pins
Ground pins
Powerdown pin
Powerdown acknowledge pin
Host Interface Port
The ADSP-217x host interface port is a parallel I/O port that allows for an easy connection to a host processor. Through the
HIP, the ADSP-217x can be used as a memory-mapped peripheral to a host computer. The HIP can be thought of as an area
of dual-ported memory, or mailbox registers, that allow communication between the computational core of the ADSP-217x and
the host computer.
The HIP is completely asynchronous. The host processor can
write data into the HIP while the ADSP-217x is operating at full
speed.
The HIP can be configured with the following pins:
• HSIZE configures HIP for 8-bit or 16-bit communication with
the host processor.
• BMODE (when MMAP = 0) determines whether the ADSP217x boots from the host processor (through the HIP) or external EPROM (through the data bus).
• HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
• HMD1 selects separate address (3-bit) and data (16-bit)
buses, or a multiplexed, 16-bit address/data bus with address
latch enable.
External clock or quartz crystal
input
Processor clock output
HIP select input
HIP acknowledge output
8/16 bit host select input
0 = 16-bit; 1 = 8-bit
Boot mode select input
0 = EPROM/data bus; 1 = HIP
Bus strobe select input
0 = RD, WR; 1 = RW, DS
HIP address/data mode select
input 0 = separate; 1 =
multiplexed
HIP read strobe/read/write
select input
HIP write strobe/host data
strobe select input
Tying these pins to appropriate values configures the ADSP217x for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
In 8-bit reads, the ADSP-217x three-states the upper eight bits
of the bus. When the host processor writes an 8-bit value to the
HIP, the upper eight bits are all zeros. For additional information refer to the ADSP-2100 Family User’s Manual.
HIP Operation
The HIP contains six data registers (HDR5–0) and two status
registers (HSR7–6) with an associated HMASK register for
masking interrupts from individual HIP data registers. All HIP
data registers are memory-mapped into the internal data
memory of the ADSP-217x. HIP transfers can be managed using either interrupts or a polling scheme. These registers are
shown in the section “ADSP-217x Registers.”
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-217x processor cycles.
–4–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Interrupts
Table II. Interrupt Priority & Interrupt Vector Addresses
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedicated pin; SPORT1 may be reconfigured for IRQ0, IRQ1, and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are internally prioritized and individually maskable (except powerdown and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
Source of Interrupt
Interrupt Vector
Address (Hex)
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
On-chip stacks preserve the processor status and are automatically maintained during interrupt handling.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servicing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
The interrupt control register, ICNTL, allows the external interrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking precedence or processed sequentially.
ENA INTS;
DIS INTS;
The IFC register is a write-only register used to force and clear
interrupts generated from software.
When you reset the processor, the interrupt servicing is enabled.
IMASK
ICNTL
4
3
2
1
0
0
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
1 = edge
0 = level
Interrupt Nesting
1 = enable, 0 = disable
1 = enable, 0 = disable
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
IFC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTERRUPT FORCE
INTERRUPT CLEAR
IRQ2
SPORT0 Transmit
SPORT0 Receive
Software 1
Software 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
Figure 2. Interrupt Registers
REV. A
–5–
ADSP-2171/ADSP-2172/ADSP-2173
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
LOW POWER OPERATION
The ADSP-217x has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Powerdown
• Idle
• Slow Idle
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
The CLKOUT pin may also be disabled to reduce external
power dissipation. The CLKOUT pin is controlled by Bit 14 of
SPORT0 Autobuffer Control Register, DM[0x3FF3].
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-217x will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
Powerdown
The ADSP-217x processor has a low power feature that lets the
processor enter a very low power dormant state through hardware or software control. Here is a brief list of powerdown features. Refer to the ADSP-2100 Family User’s Manual, Chapter 9
“System Interface” for detailed information about the
powerdown feature.
• Powerdown mode holds the processor in CMOS standby with
a maximum current of less than 100 µA in some modes.
• Quick recovery from powerdown. The processor begins executing instructions in as few as 100 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 100 CLKIN cycle startup.
• Powerdown is initiated by either the powerdown pin (PWD)
or the software powerdown force bit.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The
powerdown interrupt also can be used as a non-maskable,
edge sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
powerdown state.
• The RESET pin also can be used to terminate powerdown,
and the host software reset feature can be used to terminate
powerdown under certain conditions.
• Powerdown acknowledge pin indicates when the processor has
entered powerdown.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 3 shows a basic system configuration with the ADSP217x, two serial devices, a host processor, a boot EPROM, and
optional external program and data memories. Up to 14K words
of data memory and 16K words of program memory can be supported. Programmable wait state generation allows the processor
to interface easily to slow memories. The ADSP-217x also provides one external interrupt and two serial ports or three external interrupts and one serial port.
Clock Signals
The ADSP-217x can be clocked by either a crystal or by a TTLcompatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation. The only exception is while the processor is in the Powerdown State. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual for detailed information on
this powerdown feature.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
Idle
When the ADSP-217x is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
The ADSP-217x uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally, instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Slow Idle
The IDLE instruction is enhanced on the ADSP-217x to let the
processor’s internal clock signal be slowed during IDLE, further
reducing power consumption. The reduced clock frequency, a
–6–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
HIP CONTROL
CLOCK OR
CRYSTAL
6
CLKIN
HOST
PROCESSOR
(OPTIONAL)
HIP DATA/ADDR
XTAL
PWDACK
PWD
VDD
9
4
GND
HOST
MODE
7
16
SCLK
HIP
RFS
CLKOUT
RESET
SERIAL DEVICE
TFS
SERIAL
PORT 0
(OPTIONAL)
DT
DR
IRQ2
ADSP-217x
BR
SCLK
BG
RFS or IRQ0
SERIAL DEVICE
TFS or IRQ1
SERIAL
PORT 1
MMAP
3
(OPTIONAL)
DT or FO
FL2-0
PMS
RD
WR
ADDRESS
14
DATA
DMS
DR or FI
BMS
24
D23-22
D23-8
24
14
2
8
16
A
D
PROGRAM
MEMORY
(OPTIONAL)
A
CS
OE
OE
WE
WE
D15-8
CS
D
DATA MEMORY
&
PERIPHERALS
A
D
CS
BOOT MEMORY
OE
(OPTIONAL)
e.g., EPROM
27C64
27C128
27C256
27C512
NOTE:
THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF THE BOOT EPROM ADDRESS.
THIS IS ONLY REQUIRED FOR THE 27C256 AND 27C512.
Figure 3. ADSP-217x Basic System Configuration
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
Because the ADSP-217x includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
CLKIN
XTAL
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulse width specification, tRSP.
CLKOUT
ADSP-217x
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended.
Figure 4. External Crystal Connections
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control Register, DM[0x3FF3].
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000.
Reset
The RESET signal initiates a master reset of the ADSP-217x.
The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
REV. A
–7–
ADSP-2171/ADSP-2172/ADSP-2173
The optional ROM always resides at locations PM[0x0800]
through PM[0x27FF] regardless of the state of the MMAP pin.
The ROM is enabled by setting the ROMENABLE bit in the
Data Memory Wait State control register, DM[0x3FFE]. When
the ROMENABLE bit is set to 1, addressing program memory
in this range will access the on-chip ROM. When set to zero,
addressing program memory in this range will access external
program memory. The ROMENABLE bit is set to 0 on chip reset unless MMAP and BMODE = 1.
Program Memory Interface
The on-chip program memory address bus (PMA) and the onchip program memory data bus (PMD) are multiplexed with
on-chip DMA and DMD buses, creating a single external data
bus and a single external address bus. The 14-bit address bus
directly addresses up to 16K words. 10K words of memory for
ADSP-217x with optional 8K ROM and 2K words of memory
for the non-ROM version are on-chip. The data bus is bidirectional and 24 bits wide to external program memory. Program
memory may contain code and data.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to the program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and is used as a write strobe.
Boot Memory Interface
The ADSP-217x can load on-chip memory from external boot
memory space. The boot memory space consists of 64K by 8-bit
space, divided into eight separate 8K by 8-bit pages. Three bits
in the system control register select which page is loaded by the
boot memory interface. Another bit in the system control register allows the user to force a boot loading sequence under software control. Boot loading from page 0 after RESET is initiated
automatically if MMAP = 0.
The read (RD) signal indicates a read operation and is used as a
read strobe or output enable signal.
The ADSP-217x writes data from its 16-bit registers to the 24bit program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are
placed in the PX register.
The boot memory interface can generate 0 to 7 wait states; it
defaults to 7 wait states after RESET. This allows the ADSP217x to boot from a single low cost EPROM such as a 27C256.
Program memory is booted one byte at a time and converted to
24-bit program memory words.
Program Memory Maps
ADSP-217x
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 5 shows the different configurations. When MMAP = 0, internal RAM occupies 2K words beginning at address 0x0000. In this configuration, the boot
loading sequence (described in “Boot Memory Interface”) is automatically initiated when RESET is released.
2K
INTERNAL RAM
BOOTED
0000
07FF
0800
0000
2K
EXTERNAL
07FF
0800
8K
INTERNAL ROM
8K
INTERNAL ROM
(ROMENABLE = 1)
(ROMENABLE = 1)
2K
INTERNAL RAM
NOT BOOTED
The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8–D15. To accommodate addressing up to eight
pages of boot memory, the two MSBs of the data bus are used
in the boot memory interface as the two MSBs of the boot space
address.
0000
07FF
0800
The ADSP-2100 Family Assembler and Linker support the creation of programs and data structures requiring multiple boot
pages during execution.
RD and WR must always be qualified by PMS, DMS, or BMS
to ensure the correct program, data, or boot memory accessing.
8K
INTERNAL ROM
OR
OR
8K
EXTERNAL
8K
EXTERNAL
(ROMENABLE = 0)
(ROMENABLE = 0)
27FF
2800
4K
EXTERNAL
6K
EXTERNAL
2K
INTERNAL RAM
3FFF
MMAP = 0
BMODE = 0 or 1
(ROMENABLE
DEFAULTS
TO 1
DURING RESET)
27FF
2800
37FF
3800
The ADSP-217x can also boot programs through its Host Interface Port. If BMODE = 1 and MMAP = 0, the ADSP-217x
boots from the HIP. If BMODE = 0, the ADSP-217x boots
through the data bus (in the same way as the ADSP-2101), as
described above in “Boot Memory Interface.” For additional information about HIP booting, refer to the ADSP-2100 Family
User’s Manual, Chapter 7, “Host Interface Port.”
27FF
2800
6K
EXTERNAL
3FFF
MMAP = 1
BMODE = 0
HIP Booting
3FFF
The ADSP-2100 Family Development Software includes a utility program called the HIP Splitter. This utility allows the creation of programs that can be booted via the ADSP-217x’s HIP,
in a similar fashion as EPROM-bootable programs generated by
the PROM Splitter utility.
MMAP = 1
BMODE = 1
Figure 5. ADSP-217x Memory Maps
When MMAP = 1, words of external program memory begin at
address 0x0000 and internal RAM is located in the upper 2K
words, beginning at address 0x3800. In this configuration, program memory is not loaded although it can be written to and
read from under program control.
–8–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Upon completion of the prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for production units. An invoice against your purchase order for the
NRE charges is issued at this time.
Stand-Alone ROM Execution
When the MMAP and BMODE pins both are set to 1, the
ROM is automatically enabled and execution commences from
program memory location 0x0800 at the start of ROM. This
feature lets an embedded design operate without external
memory components. To operate in this mode, the ROM coded
program must copy an interrupt vector table to the appropriate
locations in program memory RAM. In this mode, the ROM
enable bit defaults to 1 during reset.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
Data Memory Interface
The data memory address (DMA) bus is 14 bits wide. The bidirectional external data bus is 24 bits wide, with the upper 16
bits (D8–D23) used for data memory data (DMD) transfers.
Table III. Boot Summary Table
BMODE = 0
MMAP = 0 Boot from EPROM,
then execution starts
at internal RAM
location 0x0000
BMODE = 1
The data memory select (DMS) signal indicates access to the
data memory and can be used as a chip select signal. The write
(WR) signal indicates a write operation and can be used as a
write strobe. The read (RD) signal indicates a read operation
and can be used as a read strobe or output enable signal.
Boot from HIP, then
execution starts at
internal RAM location
0x0000
MMAP = 1 No booting, execution
Stand-Alone Mode,
starts at external memory execution starts at
location 0x0000
internal ROM location
0x0800
The ADSP-217x supports memory-mapped I/O, with the peripherals memory mapped into the data or program memory address spaces and accessed by the processor in the same manner.
Data Memory Map
The on-chip data memory RAM resides in the 2K words of data
memory beginning at address 0x3000, as shown in Figure 6. In
addition, data memory locations from 0x3800 to the end of data
memory at 0x3FFF are reserved. Control registers for the system, timer, wait state configuration, host interface port, and serial port operations are located in this region of memory.
Ordering Procedure for ADSP-2172 Processors
To place an order for a custom ROM-coded ADSP-2172 processor, you must:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-2172 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-production ROM Products.
0000
DWAIT 1
(1K EXTERNAL)
12K
EXTERNAL
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
IBM PC (DOS 2.01 or higher).
03FF
0400
07FF
0800
DWAIT 2
(10K EXTERNAL)
2FFF
3000
2FFF
3000
3. Place a purchase order with Analog Devices for nonrecurring
engineering charges (NRE) associated with ROM product
development.
2K
INTERNAL
DATA RAM
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
1K
RESERVED
37FF
3800
NO WAIT
STATES
3BFF
3C00
MEMORY MAPPED
REGISTERS/
RESERVED
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks are
identical, and recalculates the checksums for the .EXE file entered into the ROM Manager System. The checksum data, in the
form of a ROM memory map, a hard copy of the .EXE file, and a
ROM Data Verification Form are returned to you for inspection.
3FFF
3FFF
DATA MEMORY
WAIT STATES
Figure 6. ADSP-217x Data Memory Map
The remaining 12K of data memory is external. External data
memory is divided into three zones, each associated with its own
wait state generator. By mapping peripherals into different
zones, you can accommodate peripherals with different wait
state requirements. All zones default to 7 wait states after
RESET. For compatibility with other ADSP-2100 Family processors, bit definitions for DWAIT 3 and DWAIT4 are shown
in the Data Memory Wait State Control Register, but they are
not used by the ADSP-217x.
A signed ROM Verification Form and a purchase order for production units are required prior to any product being manufactured. Prototype units may be applied toward the minimum
order quantity.
REV. A
0000
DWAIT 0
(1K EXTERNAL)
–9–
ADSP-2171/ADSP-2172/ADSP-2173
but cannot execute it because the bus is granted to some other
processor. With the BGH signal, the other processor(s) in the
system can be alerted that the ADSP-217x is hung and release
the bus by deasserting bus request. Once the bus is released the
ADSP-217x executes the external access and deasserts BGH.
This is a signal to the other processors that external memory is
now available.
Bus Request & Bus Grant
The ADSP-217x can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-217x is not performing an external memory access, then
it responds to the active BR input in the following processor
cycle by:
• three-stating the data and address buses and the PMS, DMS,
BMS, RD, WR output drivers,
• asserting the bus grant (BG) signal, and
• halting program execution.
ADSP-217X REGISTERS
Figure 7 summarizes all the registers in the ADSP-217x. Some
registers store values. For example, AX0 stores an ALU operand; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example, ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the numbers of wait states for different zones of data
memory.
If the Go Mode is enabled, the ADSP-217x will not halt program execution until it encounters an instruction that requires
an external memory access.
If the ADSP-217x is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes, which can be up
to eight cycles later depending on the number of wait states.
The instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except for IMASK, ICNTL and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory; that is, registers are accessed by
reading and writing data memory locations rather than register
names. The particular data memory address is shown with each
memory-mapped register.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeterminate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
The new Bus Grant Hang logic and associated BGH pin allow
the ADSP-217x to operate in a multiprocessor environment
with a minimal number of “wasted” processor cycles. The bus
grant hang pin is asserted when the ADSP-217x desires a cycle,
PROGRAM SEQUENCER
ICNTL
IFC
SSTAT
DAG 1
I0
I1
I2
I3
M0
M1
M2
M3
DAG 2
L0
L1
L2
L3
I4
I5
I6
I7
M4
M5
M6
M7
L4
L5
L6
L7
CNTR
OWRCNTR
COUNT
STACK
4 X 14
PROGRAM
ROM
8K X 24
LOOP
STACK
4 X 18
IMASK
MSTAT
ASTAT
PC
STACK
16 X 14
STATUS
STACK
12 X 25
0x3FFF
0x3FFE
14
PMA BUS
14
DMA BUS
24
PMD BUS
16
DMD BUS
SYSTEM CONTROL
DM WAIT CONTROL
PROGRAM
SRAM
2K X 24
HOST
INTERFACE
PORT
DATA
SRAM
2K X 16
0x3FE0-0x3FE5
0x3FE6-0x3FE7
0x3FE8
DATA
STATUS
HMASK
PX
FLAGS
AX0 AX1 AY0 AY1
ALU
AR
AF
MX0 MX1 MY0 MY1
MAC
MR0 MR1 MR2 MF
SI
SE
SB
SHIFTER
SR0 SR1
RX0 TX0
RX1 TX1
0x3FFA-0x3FF3
0x3FF2-0x3FEF
CONTROL REGISTERS
CONTROL REGISTERS
SPORT 0
SPORT 1
TIMER
0x3FFD
0x3FFC
0x3FFB
TPERIOD
TCOUNT
TSCALE
POWERDOWN
CONTROL
LOGIC
Figure 7. ADSP-217x Registers Control Register
–10–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
SSTAT (Read-Only)
ASTAT
7 6 5
0 0
4 3 2 1
0 0 0
0 0
0
7
6 5
4 3 2
0
0
1 0
1 0
1 0
1 0
1
AZ ALU Result Zero
PC Stack Empty
AN ALU Result Negative
PC Stack Overflow
AV ALU Overflow
Count Stack Empty
AC ALU Carry
Count Stack Overflow
AS ALU X Input Sign
Status Stack Empty
AQ ALU Quotient
Status Stack Overflow
MV MAC Overflow
Loop Stack Empty
SS Shifter Input Sign
Loop Stack Overflow
MSTAT
6 5 4 3 2 1 0
0
0 0 0
0 0 0
Data Register Bank Select
0 = primary, 1 = secondary
Bit Reverse Mode Enable (DAG1)
ALU Overflow Latch Mode Enable
AR Saturation Mode Enable
MAC Result Placement
0 = fractional, 1 = integer
Timer Enable
Go Mode Enable
System Control Register
0x3FFF
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
SPORT0 Enable
1 = enabled, 0 = disabled
PWAIT
Program Memory
Wait States
SPORT1 Enable
1 = enabled, 0 = disabled
BWAIT
Boot Wait States
BPAGE
Boot Page Select
SPORT1 Configure
1 = serial port
0 = FI, FO, IRQ0, IRQ1, SCLK
BFORCE
Boot Force Bit
Timer Registers
15
0
14
0
13 12
0
0
11
0
10
9
8
7
6
5
4
2
1
0
TPERIOD Period Register
0x3FFD
TCOUNT Counter Register
0x3FFC
0
0
0
TSCALE Scaling Register
Control Registers
REV. A
3
–11–
0x3FFB
ADSP-2171/ADSP-2172/ADSP-2173
ROM Enable/Data Memory Wait State
Control Register
0x3FFE
15
14 13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DWAIT4
DWAIT3
DWAIT2
DWAIT1
DWAIT0
ROM enable
1 = enable
0 = disable
SPORT0 Multichannel Receive Word Enable Registers
SPORT0 Multichannel Transmit Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
1 = Channel Enabled
0 = Channel Ignored
0x3FFA
0x3FF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x3FF7
0x3FF9
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SPORT0 Control Register
0x3FF6
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Multichannel Enable MCE
SLEN Serial Word Length
Internal Serial Clock Generation ISCLK
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
Multichannel Frame Delay MFD
Only If Multichannel Mode Enabled
INVRFS Invert Receive Frame Sync
INVTFS Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid
Only If Multichannel Mode Enabled)
Transmit Frame Sync Required TFSR
Transmit Frame Sync Width TFSW
IRFS Internal Receive Frame Sync Enable
ITFS Internal Transmit Frame Sync Enable
(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words
Only If Multichannel Mode Enabled)
Control Registers
–12–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
SPORT0 SCLKDIV
Serial Clock Divide Modulus
0x3FF5
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
2
1
0
0
0
SPORT0 RFSDIV
Receive Frame Sync Divide Modulus
0x3FF4
15
14
13 12
11
10
9
8
7
6
5
4
3
SPORT0 Autobuffer Control Register
0x3FF3
15
14
13 12
0
0
0
11
10
9
8
7
6
5
4
3
0
RBUF
Receive Autobuffering Enable
CLKODIS
CLKOUT Disable Control Bit
BIASRND
MAC Biased Rounding Control Bit
TBUF
Transmit Autobuffering Enable
TIREG
Transmit Autobuffer I Register
RMREG
Receive Autobuffer M Register
TMREG
Transmit Autobuffer M Register
RIREG
Receive Autobuffer I Register
SPORT1 Control Register
0x3FF2
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flag Out (Read Only)
SLEN Serial Word Length
Internal Serial Clock Generation ISCLK
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
Transmit Frame Sync Required TFSR
INVRFS Invert Receive Frame Sync
Transmit Frame Sync Width TFSW
INVTFS Invert Transmit Frame Sync
ITFS Internal Transmit Frame Sync Enable
IRFS Internal Receive Frame Sync Enable
Control Registers
REV. A
–13–
ADSP-2171/ADSP-2172/ADSP-2173
SPORT1 SCLKDIV
Serial Clock Divide Modulus
0x3FF1
15 14 13 12 11 10
9
8
7
6
5
SPORT1 RFSDIV
Receive Frame Sync Divide Modulus
0x3FF0
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SPORT1 Autobuffer Control Register
0x3FEF
15
14
13
12 11
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
0
0
RBUF
Receive Autobuffer Enable
XTALDIS
XTAL Pin Drive Disable
during Powerdown
1 = disabled, 0 = enabled
(disable XTAL pin when no external
crystal connected)
TBUF
Transmit Autobuffer Enable
RMREG
Receive M Register
XTALDELAY
4096 Cycle Delay Enable
1 = delay, 0 = no delay
RIREG
Receive I Register
PDFORCE
Powerdown Force
TMREG
Transmit M Register
PUCR
Powerup Context Reset Enable
1 = soft reset (context clear),
0 = resume execution
HIP Data Registers
HDR5
TIREG
Transmit I Register
HMASK Register
0x3FE8
0x3FE5
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
0
HDR4
0x3FE4
HDR3
0x3FE3
HDR2
0x3FE2
HDR1
0x3FE1
HDR0
0x3FE0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Host HDR5
Read
Host HDR0
Write
Host HDR4
Read
Host HDR1
Write
Host HDR3
Read
Host HDR2
Write
Host HDR2
Read
Host HDR3
Write
Host HDR1
Read
Host HDR4
Write
Host HDR0
Read
Host HDR5
Write
Interrupt Enables
1 = Enable
0 = Disable
Control Registers
–14–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
HSR6
0x3FE6
15
14 13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2171 HDR5 Write
Host HDR0 Write
2171 HDR4 Write
Host HDR1 Write
2171 HDR3 Write
Host HDR2 Write
2171 HDR2 Write
Host HDR3 Write
2171 HDR1 Write
Host HDR4 Write
2171 HDR0 Write
Host HDR5 Write
HSR7
0x3FE7
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
2171 HDR0 Write
2171 HDR1 Write
2171 HDR2 Write
2171 HDR3 Write
Overwrite Mode
2171 HDR4 Write
Software Reset
2171 HDR5 Write
Control Registers
Biased Rounding
INSTRUCTION SET DESCRIPTION
A new mode allows biased rounding in addition to the normal
unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased rounding operations occur. When the BIASRND
bit is set to 1, biased rounding occurs instead of the normal unbiased rounding. When operating in biased rounding mode all
rounding operations with MR0 set to 0x8000 will round up,
rather than only rounding odd MR1 values up. For example:
MR value before RND
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
biased RND result
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
unbiased RND result
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit specified algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.
The ADSP-217x assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be relocated to utilize internal memory and conform to the ADSP217x’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle.
Consult the ADSP-2100 Family User’s Manual for a complete
description of the syntax and an instruction set reference.
REV. A
–15–
ADSP-2171/ADSP-2172/ADSP-2173
Example Code
The following example is a code fragment that performs the
filter tap update for an adaptive (least-mean-squared algorithm)
filter. Notice that the computations in the instructions are
written like algebraic equations.
MF=MX0*MY1 (RND), MX0=DM (I2,M1); /* MF=error*beta */
MR=MX0*MF (RND), AY0=PM (I6,MS);
DO adapt UNTIL CE;
AR=MR1 + AY0, MX0=DM (I2,M1), AY0=PM (I6,M7);
adapt: PM(I6,M6) =AR, MR=MX0*MF (RND);
MODIFY (I2, M3);
MODIFY (I6, M7);
/* Point to oldest data */
/* Point to start of data */
Interrupt Enable
The ADSP-217x supports an interrupt enable instruction. Interrupts are enabled by default at reset. The instruction source
code is specified as follows:
Syntax:
ENA INTS;
Description: Executing the ENA INTS instruction allows all
unmasked interrupts to be serviced again.
Interrupt Disable
The ADSP-217x supports an interrupt disable instruction. The
instruction source code is specified as follows:
Syntax:
DIS INTS;
Description: Reset enables interrupt servicing. Executing the
DIS INTS instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
–16–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
B Grade
Min
Max
Min
Max
Unit
4.5
0
5.5
+70
4.5
–40
5.5
+85
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIH
VIL
VOH
Test Conditions
Hi-Level Input Voltage1, 2
Hi-Level CLKIN Voltage
Hi-Level RESET Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Tristate Leakage Current7
IOZL
Tristate Leakage Current7
IDD
IDD
Supply Current (Idle)9, 10
Supply Current (Dynamic)10
IDD
CI
Supply Current (Powerdown)10
Input Pin Capacitance3, 6, 13
CO
Output Pin Capacitance6, 7, 13, 14
@ VDD = max
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max,
VIN = VDD max8
@ VDD = max,
VIN = 0 V8
@ VDD = max
@ VDD = max
tCK = 30 ns11
Lowest Power Mode12
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
K/B Grades
Min
Max
2.0
2.2
2.2
0.8
Unit
V
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
18
µA
mA
75
100
mA
µA
8
pF
8
pF
NOTES
1
Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, HD0-HD15/HAD0-HAD15.
2
Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
3
Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
4
Output pins: BG, PMS, DMS, BMS, RD, WR, PWDACK, A0-A13, DT0, DT1, CLKOUT, HACK, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSP-2171/ADSP-2172 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15.
8
0 V on BR, CLKIN Active (to force three-state condition).
9
Idle refers to ADSP-2171/ADSP-2172 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. Current reflects
device operation with CLKOUT disabled.
10
Current reflects device operating with no output loads.
11
VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.
12
See Chapter 9, of the ADSP-2100 Family User’s Manual for details.
13
Applies to TQFP and PQFP package types.
14
Output pin capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
REV. A
–17–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C
Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280°C
*
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The ADSP-217x is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-217x features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-217x has been classified as
a Class 1 device.
WARNING!
Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.
ESD SENSITIVE DEVICE
ADSP-2171/ADSP-2172 TIMING PARAMETERS
ADSP-2171/ADSP-2172
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing; it is dependent on
the internal design. Timing requirements apply to signals that
are controlled outside the processor, such as the data input for a
read operation.
Timing requirements guarantee that the processor operates correctly with another device. Switching characteristics tell you
what the device will do under a given circumstance. Also, use
the switching characteristics to ensure any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
MEMORY REQUIREMENTS
This chart links common memory device specification names
and ADSP-2171/ADSP-2172 timing parameters for your
convenience.
Parameter
Name
Function
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
–18–
A0-A13, DMS, PMS
Setup before WR Low
A0-A13, DMS, PMS
before WR Deasserted
A0-A13, DMS, PMS
Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0-A13, DMS, PMS,
BMS to Data Valid
Common
Memory Device
Specification Name
Address Setup to
Write Start
Setup Address Setup
to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
60
20
20
150
Unit
Clock Signals
tCK is defined as 0.5 tCKI. The ADSP-2171/ADSP-2172 uses an
input clock with a frequency equal to half the instruction rate; a
clock (which is equivalent to 60 ns) yields a 30 ns processor cycle
16.67 MHz input (equivalent to 33 MHz). tCK values within the
range of 0.5 tCKI period should be substituted for all relevant
timing parameters to obtain specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (30 ns) – 7 ns = 8 ns.
Timing Requirement:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
ns
ns
ns
Switching Characteristic:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 7
0.5tCK – 7
0
20
ns
ns
ns
Control Signals
Timing Requirement:
tRSP
RESET Width Low
5tCK1
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 8. Clock Signals
REV. A
–19–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirement:
tIFS
tIFH
IRQx or FI Setup before CLKOUT Low1, 2, 3
IRQx or FI Hold after CLKOUT High1, 2, 3
0.25tCK + 15
0.25tCK
ns
ns
Switching Characteristic:
tFOH
tFOD
Flag Output Hold after CLKOUT Low4
Flag Output Delay from CLKOUT Low4
0.5tCK – 7
0.5tCK + 5
ns
ns
NOTES
1
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, and IRQ2.
4
Flag Output = FL0, FL1, FL2, and FO.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
tIFS
Figure 9. Interrupts and Flags
–20–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirement:
tBH
tBS
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
0.25tCK + 2
0.25tCK + 17
ns
ns
Switching Characteristic:
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
CLKOUT High to DMS, PMS, BMS,
RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS, BMS,
RD, WR Enable
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
DMS, PMS, BMS, RD, WR
Disable to BGH Low2
BGH High to DMS, PMS, BMS,
RD, WR Enable2
0.25tCK + 16
ns
0
ns
0
ns
0.25tCK – 7
ns
0
ns
0
ns
NOTES
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
t SDBH
tSEH
Figure 10. Bus Request–Bus Grant
REV. A
–21–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
0.5tCK – 9 + w
0.75tCK – 10.5 + w
ns
ns
ns
Memory Read
Timing Requirement:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High
0
Switching Characteristic:
tRP
tCRD
tASR
tRDA
tRWR
RD Pulse Width
CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS Setup before RD Low
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
RD High to RD or WR Low
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 6
0.25tCK – 3
0.5tCK – 5
0.25tCK + 7
ns
ns
ns
ns
ns
w = wait states x tCK.
CLKOUT
A0–A13
DMS, PMS
BMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tRDD
tRDH
tAA
WR
Figure 11. Memory Read
–22–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Memory Write
Switching Characteristic:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
tWRA
tWWR
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
A0–A13, DMS, PMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
WR High to RD or WR Low
0.5 tCK – 7 + w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 6
0.25tCK – 7
0.25tCK – 5
0.75tCK – 9 + w
0.25tCK – 3
0.5tCK – 5
0.25 tCK + 7
w = wait states x t CK.
CLKOUT
A0–A13
DMS, PMS
tWRA
WR
tAS W
tWP
tWWR
tAW
tDH
tCWR
D
tDW
tWDE
RD
Figure 12. Memory Write
REV. A
–23–
tDDR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Serial Ports
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
50
4
7
20
ns
ns
ns
ns
Switching Characteristic:
tCC
tSCDE
tSCDV
tRH
tRD
tSCDH
tTDE
tTDV
tSCDD
tRDV
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
TFS(Alt) to DT Enable
TFS(Alt) to DT Valid
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
0.25tCK
0
0.25tCK + 10
15
0
15
0
0
15
15
15
tCC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
SCLK
tSCP
tSCS
tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFS OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
ALTERNATE
FRAME MODE
tRDV
RFS
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 13. Serial Ports
–24–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 0)
Timing Requirement:
tHSU
tHDSU
tHWDH
tHH
tHRWP
HA2–0 Setup before Start of Write or Read1, 2
Data Setup before End of Write3
Data Hold after End of Write3
HA2–0 Hold after End of Write or Read3, 4
Read or Write Pulse Width5
5
5
3
3
20
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1, 2
HACK Hold after End of Write or Read3, 4
Data Enabled after Start of Read2
Data Valid after Start of Read2
Data Hold after End of Read4
Data Disabled after End of Read4
0
0
0
15
15
18
0
7
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
HA2–0
ADDRESS
tHRWP
HSEL
tHSU
Host Write Cycle
tHH
HWR
HACK
tHKH
tHSHK
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
Host Read Cycle
tHH
HRD
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHRDH
tHDD
tHRDD
Figure 14. Host Interface Port (HMD1 = 0, HMD0 = 0)
REV. A
–25–
ns
ns
ns
ns
ns
ns
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHSU
tHDSU
tHWDH
tHH
tHRWP
HA2–0, HRW Setup before Start of Write or Read1
Data Setup before End of Write2
Data Hold after End of Write2
HA2–0, HRW Hold after End of Write or Read2
Read or Write Pulse Width3
5
5
3
3
20
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1
HACK Hold after End of Write or Read2
Data Enabled after Start of Read1
Data Valid after Start of Read1
Data Hold after End of Read2
Data Disabled after End of Read2
0
0
0
15
15
18
0
7
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High and HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
Host Write Cycle
HRW
tHH
HDS
HACK
tHSHK
tHKH
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
Host Read Cycle
HRW
tHH
HDS
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHRDH
tHDD
tHRDD
Figure 15. Host Interface Port (HMD1 = 0, HMD0 = 1)
–26–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 0)
Timing Requirement:
tHALP
tHASU
tHAH
tHALS
tHDSU
tHWDH
tHRWP
ALE Pulse Width
HAD15–0 Address Setup, before ALE Low
HAD15–0 Address Hold after ALE Low
Start of Write or Read after ALE Low1, 2
HAD15–0 Data Setup before End of Write3
HAD15–0 Data Hold after End of Write3
Read or Write Pulse Width4
10
5
2
10
5
3
20
ns
ns
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1, 2
HACK Hold after End of Write or Read3, 5
HAD15–0 Data Enabled after Start of Read2
HAD15–0 Data Valid after Start of Read2
HAD15–0 Data Hold after End of Read
HAD15–0 Data Disabled after End of Read5
0
0
0
15
15
18
0
7
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
5
End of Read = HRD High or HSEL High.
ALE
tHALP
tHRWP
HSEL
tHALS
Host Write Cycle
HWR
tHSHK
HACK
HD15–0
tHASU
tHKH
tHAH
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
Host Read Cycle
tHRWP
HSEL
tHALS
HRD
tHKH
tHSHK
HACK
HAD15–0
tHASU
tHAH
tHDE
ADDRESS
DATA
tHDD
tHRDH
tHRDD
Figure 16. Host Interface Port (HMD1 = 1, HMD0 = 0)
REV. A
–27–
ns
ns
ns
ns
ns
ns
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHALP
tHASU
tHAH
tHALS
tHSU
tHDSU
tHWDH
tHH
tHRWP
ALE Pulse Width
HAD15–0 Address Setup before ALE Low
HAD15–0 Address Hold after ALE Low
Start of Write or Read after ALE Low1
HRW Setup before Start of Write or Read1
HAD15–0 Data Setup before End of Write2
HAD15–0 Data Hold after End of Write2
HRW Hold after End of Write or Read2
Read or Write Pulse Width3
10
5
2
10
5
5
3
3
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1
HACK Hold after End of Write or Read2
HAD15–0 Data Enabled after Start of Read1
HAD15–0 Data Valid after Start of Read1
HAD15–0 Data Hold after End of Read2
HAD15–0 Data Disabled after End of Read2
0
0
0
15
15
18
0
7
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High and HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
ALE
tHALP
tHRWP
HSEL
tHH
tHALS
Host Write Cycle
HRW
tHSU
HDS
tHSHK
HACK
HD15–0
tHASU
tHKH
tHAH
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
tHALS
tHRWP
HSEL
tHH
HRW
tHSU
Host Read Cycle
HDS
tHKH
tHSHK
HACK
tHASU
tHAH
tHDE
HD15–0
ADDRESS
DATA
tHDD
tHRDH
tHRDD
Figure 17. Host Interface Port (HMD1 = 1, HMD0 = 1)
–28–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
POWER, INTERNAL 1
ADSP-2171/ADSP-2172
400
382mW
375
ENVIRONMENTAL CONDITIONS
350
Ambient Temperature Rating:
325
POWER (P INT ) – mW
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
301mW
300
VDD = 5.5V
275
250
225
VDD = 5.0V
200
175
229mW
186mW
VDD = 4.5V
148mW
150
Package
θJA
θJC
θCA
TQFP
PQFP
50°C/W
41°C/W
2°C/W
10°C/W
48°C/W
31°C/W
125 110mW
13 15 17 19 21 23 25 27 29 31 33
1/ tCK – MHz
POWER, IDLE 1, 2
POWER DISSIPATION
85
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
80
75
POWER (PIDLE ) – mW
70
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
55
40
Each address and data pin has a 10 pF total load at the pin.
72
The application operates at VDD = 5.0 V and tCK = 30 ns.
68
30
26mW
13 15 17 19 21 23 25 27 29 31 33
1/ tCK – MHz
POWER, IDLE n MODES 3
82mW
64mW
IDLE;
64
POWER (PIDLE n ) – mW
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 18).
(C × VDD2 × f ) is calculated for each output:
× VDD2 × f
× 33.3 MHz
× 16.67 MHz
× 16.67 MHz
× 33.3 MHz
VDD = 4.5V
37mW
35
•
•
× 52 V
× 52 V
× 52 V
× 52 V
VDD = 5.0V
48mW
45
External data memory writes occur every other cycle with
50% of the data pins switching.
× 10 pF
× 10 pF
× 10 pF
× 10 pF
48mW
50
•
8
9
1
1
64mW
60
External data memory is accessed every cycle with 50% of the
address pins switching.
Address, DMS
Data Output, WR
RD
CLKOUT
VDD = 5.5V
65
•
# of
Pins × C
82mW
60
56
52
48
44
40
37mW
36
= 66.6 mW
= 37.5 mW
= 4.2 mW
= 8.3 mW
116.6 mW
31mW
32
IDLE (16)
28
24
IDLE (128)
23mW
28mW
20
16
Total power dissipation for this example is PINT + 116.6 mW.
20mW
13 15 17 19 21 23 25 27 29 31 33
1/ tCK – MHz
VALID FOR ALL TEMPERATURE GRADES.
1 POWER
REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
REFERS TO ADSP-2171 STATE OF OPERATION DURING
EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE
DRIVEN TO EITHER VDD OR GND. POWER REFLECTS DEVICE
OPERATING WITH CLKOUT DISABLED.
3 TYPICAL POWER DISSIPATION AT 5.0V V
DD DURING EXECUTION
OF IDLE N INSTRUCTION (CLOCK FREQUENCY REDUCTION).
POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.
2 IDLE
Figure 18. Power vs. Frequency
REV. A
–29–
ADSP-2171/ADSP-2172/ADSP-2173
tDECAY, is dependent on the capacitative load, CL, and the current load, iL, on the output pin. It can be approximated by the
following equation:
ADSP-2171/ADSP-2172
CAPACITIVE LOADING
Figures 19 and 20 show the capacitive loading characteristics of
the ADSP-2171/ADSP-2172.
t DECAY =
from which
28
t DIS = t MEASURED – t DECAY
24
RISE TIME (0.4V - 2.4V) – ns
CL • 0.5V
iL
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
20
VDD = 4.5V
16
3.0V
1.5V
0.0V
INPUT
12
2.0V
1.5V
0.3V
8
OUTPUT
4
25
50
75
100
CL – pF
125
Figure 21. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
150
Output Enable Time
Figure 19. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
VALID OUTPUT DELAY OR HOLD – ns
+14
+12
+10
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
+8
REFERENCE
SIGNAL
+4
tMEASURED
tENA
+2
VOH
NOMINAL
tDIS
VOH
(MEASURED)
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
OUTPUT
–2
VOL
25
50
75
100
CL – pF
125
VOL
tDECAY
(MEASURED)
150
(MEASURED)
OUTPUT STOPS
DRIVING
Figure 20. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 22. Output Enable/Disable
TEST CONDITIONS
Output Disable Time
IOL
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 23. Equivalent Device Loading for AC Measurements (Including All Fixtures)
–30–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
B Grade
Min
Max
Min
Max
Unit
3.0
0
3.6
+70
3.0
–40
3.6
+85
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIH
VIL
VOH
Test Conditions
1, 2
Hi-Level Input Voltage
Hi-Level CLKIN Voltage
Hi-Level RESET Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Tristate Leakage Current7
IOZL
Tristate Leakage Current7
IDD
IDD
Supply Current (Idle)9, 10
Supply Current (Dynamic)10
IDD
CI
Supply Current (Powerdown)10
Input Pin Capacitance3, 6, 13
CO
Output Pin Capacitance6, 7, 13, 14
@ VDD = max
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 mA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max,
VIN = VDD max8
@ VDD = max,
VIN = 0 V8
@ VDD = max
@ VDD = max
tCK = 50 ns11
Lowest Power Mode12
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
K/B Grades
Min
Max
2.0
2.0
2.2
0.4
Unit
V
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
7
µA
mA
27
100
mA
µA
8
pF
8
pF
NOTES
1
Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, HD0-HD15/HAD0-HAD15.
2
Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
3
Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
4
Output pins: BG, PMS, DMS, BMS, RD, WR, PWDACK, A0-A13, DT0, DT1, CLKOUT, HACK, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSP-2173 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15.
8
0 V on BR, CLKIN Active (to force three-state condition).
9
Idle refers to ADSP-2173 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. Current reflects
device operation with CLKOUT disabled.
10
Current reflects device operating with no output loads.
11
VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.
12
See Chapter 9, of the ADSP-2100 Family User’s Manual for details.
13
Applies to TQFP and PQFP package types.
14
Output pin capacitance is the capacitve load for any three-state output pin.
Specifications subject to change without notice.
REV. A
–31–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173 TIMING PARAMETERS
GENERAL NOTES
MEMORY REQUIREMENTS
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
This chart links common memory device specification names
and ADSP-2173 timing parameters for your convenience.
tASW
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing; it is dependent on
the internal design. Timing requirements apply to signals that
are controlled outside the processor, such as the data input for a
read operation.
Timing requirements guarantee that the processor operates correctly with another device. Switching characteristics tell you
what the device will do under a given circumstance. Also, use
the switching characteristics to ensure any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Parameter
Name
Function
tAW
tWRA
tDW
tDH
tRDD
tAA
–32–
A0-A13, DMS, PMS
Setup before WR Low
A0-A13, DMS, PMS
before WR Deasserted
A0-A13, DMS, PMS
Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0-A13, DMS, PMS,
BMS to Data Valid
Common
Memory Device
Specification Name
Address Setup to
Write Start
Setup Address Setup
to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
100
20
20
160
Unit
Clock Signals
tCK is defined as 0.5 tCKI. The ADSP-2173 uses an input clock with
a frequency equal to half the instruction rate; a 10.0 MHz input
clock (which is equivalent to 100 ns) yields a 50 ns processor cycle
(equivalent to 20 MHz). tCK values within the range of 0.5 tCKI
period should be substituted for all relevant timing parameters
to obtain specification value.
Example: tCKH = 0.5tCK – 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
Timing Requirement:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
ns
ns
ns
Switching Characteristic:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 10
0.5tCK – 10
0
25
ns
ns
ns
Control Signals
Timing Requirement:
tRSP
RESET Width Low
5tCK1
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 24. Clock Signals
REV. A
–33–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirement:
tIFS
tIFH
IRQx or FI Setup before CLKOUT Low1, 2, 3
IRQx or FI Hold after CLKOUT High1, 2, 3
0.25tCK + 23
0.25tCK
ns
ns
Switching Characteristic:
tFOH
tFOD
Flag Output Hold after CLKOUT Low4
Flag Output Delay from CLKOUT Low4
0.5tCK – 10
0.5tCK + 5
ns
ns
NOTES
1
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, and IRQ2.
4
Flag Output = FL0, FL1, FL2, and FO.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
tIFS
Figure 25. Interrupts and Flags
–34–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirement:
tBH
tBS
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
0.25tCK + 2
0.25tCK + 22
ns
ns
Switching Characteristic:
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
CLKOUT High to DMS, PMS, BMS,
RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS, BMS,
RD, WR Enable
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
DMS, PMS, BMS, RD, WR
Disable to BGH Low2
BGH High to DMS, PMS, BMS,
RD, WR Enable2
0.25tCK + 16
ns
0
ns
0
ns
0.25tCK – 10
ns
0
ns
0
ns
NOTES
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
t SDBH
tSEH
Figure 26. Bus Request–Bus Grant
REV. A
–35–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
0.5tCK – 15 + w
0.75tCK – 20.5 + w
ns
ns
ns
Memory Read
Timing Requirement:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High
0
Switching Characteristic:
tRP
tCRD
tASR
tRDA
tRWR
RD Pulse Width
CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS Setup before RD Low
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
RD High to RD or WR Low
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 7
0.25tCK – 3
0.5tCK – 5
0.25tCK + 10
ns
ns
ns
ns
ns
w = wait states x tCK.
CLKOUT
A0–A13
DMS, PMS
BMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tRDD
tRDH
tAA
WR
Figure 27. Memory Read
–36–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Memory Write
Switching Characteristic:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
tWRA
tWWR
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
A0–A13, DMS, PMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
WR High to RD or WR Low
0.5 tCK – 7 + w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 7
0.25tCK – 7
0.25tCK – 5
0.75tCK – 11.5 + w
0.25tCK – 3
0.5tCK – 5
0.25 tCK + 10
w = wait states x t CK.
CLKOUT
A0–A13
DMS, PMS
tWRA
WR
tAS W
tWP
tWWR
tAW
tDH
tCWR
D
tDW
tWDE
RD
Figure 28. Memory Write
REV. A
–37–
tDDR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Serial Ports
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
76.9
8
10
28
ns
ns
ns
ns
Switching Characteristic:
tCC
tSCDE
tSCDV
tRH
tRD
tSCDH
tTDE
tTDV
tSCDD
tRDV
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
TFS(Alt) to DT Enable
TFS(Alt) to DT Valid
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
0.25tCK
0
0.25tCK + 15
20
0
20
0
0
19
25
20
tCC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
SCLK
tSCP
tSCS
tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFS OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
ALTERNATE
FRAME MODE
tRDV
RFS
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 29. Serial Ports
–38–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 0)
Timing Requirement:
tHSU
tHDSU
tHWDH
tHH
tHRWP
HA2–0 Setup before Start of Write or Read1, 2
Data Setup before End of Write3
Data Hold after End of Write3
HA2–0 Hold after End of Write or Read3, 4
Read or Write Pulse Width5
8
8
3
3
30
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1, 2
HACK Hold after End of Write or Read3, 4
Data Enabled after Start of Read2
Data Valid after Start of Read2
Data Hold after End of Read4
Data Disabled after End of Read4
0
0
0
20
20
23
0
15
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
HA2–0
ADDRESS
tHRWP
HSEL
tHSU
Host Write Cycle
tHH
HWR
HACK
tHKH
tHSHK
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
Host Read Cycle
tHH
HRD
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHRDH
tHDD
tHRDD
Figure 30. Host Interface Port (HMD1 = 0, HMD0 = 0)
REV. A
–39–
ns
ns
ns
ns
ns
ns
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHSU
tHDSU
tHWDH
tHH
tHRWP
HA2–0, HRW Setup before Start of Write or Read1
Data Setup before End of Write2
Data Hold after End of Write2
HA2–0, HRW Hold after End of Write or Read2
Read or Write Pulse Width3
8
8
3
3
30
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1
HACK Hold after End of Write or Read2
Data Enabled after Start of Read1
Data Valid after Start of Read1
Data Hold after End of Read2
Data Disabled after End of Read2
0
0
0
20
20
23
0
15
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High and HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
Host Write Cycle
HRW
tHH
HDS
HACK
tHSHK
tHKH
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
Host Read Cycle
HRW
tHH
HDS
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHRDH
tHDD
tHRDD
Figure 31. Host Interface Port (HMD1 = 0, HMD0 = 1)
–40–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 0)
Timing Requirement:
tHALP
tHASU
tHAH
tHALS
tHDSU
tHWDH
tHRWP
ALE Pulse Width
HAD15–0 Address Setup, before ALE Low
HAD15–0 Address Hold after ALE Low
Start of Write or Read after ALE Low1, 2
HAD15–0 Data Setup before End of Write3
HAD15–0 Data Hold after End of Write3
Read or Write Pulse Width5
15
5
2
15
8
3
30
ns
ns
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1, 2
HACK Hold after End of Write or Read3, 4
HAD15–0 Data Enabled after Start of Read2
HAD15–0 Data Valid after Start of Read2
HAD15–0 Data Hold after End of Read
HAD15–0 Data Disabled after End of Read4
0
0
0
20
20
23
0
15
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
ALE
tHALP
tHRWP
HSEL
Host Write Cycle
tHALS
HWR
tHSHK
HACK
HD15–0
tHASU
tHKH
tHAH
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
Host Read Cycle
tHRWP
HSEL
tHALS
HRD
tHKH
tHSHK
HACK
HAD15–0
tHASU
tHAH
tHDE
ADDRESS
DATA
tHDD
tHRDH
tHRDD
Figure 32. Host Interface Port (HMD1 = 1, HMD0 = 0)
REV. A
–41–
ns
ns
ns
ns
ns
ns
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHALP
tHASU
tHAH
tHALS
tHSU
tHDSU
tHWDH
tHH
tHRWP
ALE Pulse Width
HAD15–0 Address Setup before ALE Low
HAD15–0 Address Hold after ALE Low
Start of Write or Read after ALE Low1
HRW Setup before Start of Write or Read1
HAD15–0 Data Setup before End of Write2
HAD15–0 Data Hold after End of Write2
HRW Hold after End of Write or Read2
Read or Write Pulse Width3
15
5
2
15
8
8
3
3
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristic:
tHSHK
tHKH
tHDE
tHDD
tHRDH
tHRDD
HACK Low after Start of Write or Read1
HACK Hold after End of Write or Read2
HAD15–0 Data Enabled after Start of Read1
HAD15–0 Data Valid after Start of Read1
HAD15–0 Data Hold after End of Read2
HAD15–0 Data Disabled after End of Read2
0
0
0
20
20
23
0
15
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High and HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
ALE
tHALP
tHRWP
HSEL
tHH
tHALS
Host Write Cycle
HRW
tHSU
HDS
tHSHK
HACK
HD15–0
tHASU
tHKH
tHAH
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
tHALS
tHRWP
HSEL
tHH
HRW
tHSU
Host Read Cycle
HDS
tHKH
tHSHK
HACK
tHASU
tHAH
tHDE
HD15–0
ADDRESS
DATA
tHDD
tHRDH
tHRDD
Figure 33. Host Interface Port (HMD1 = 1, HMD0 = 1)
–42–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
POWER, INTERNAL 1
ADSP-2173
89 mW
90
ENVIRONMENTAL CONDITIONS
85
Ambient Temperature Rating:
80
POWER (P INT ) – mW
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
75
71 mW
70
65
60
55 mW
57 mW
55
50
44 mW
45
Package
θJA
θJC
θCA
TQFP
PQFP
50°C/W
41°C/W
2°C/W
10°C/W
48°C/W
31°C/W
40
35
32 mW
12
13
14
15
16
17
18
19
20
1/ tCK – MHz
POWER, IDLE 1, 2
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
20
20.5 mW
19
POWER (PIDLE ) – mW
18
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
17
16.2 mW
16
15
15.5 mW
14
13
12.7 mW
11.8 mW
12
11
10
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
9
12
Address, DMS
Data Output, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
× 20 MHz
× 10 MHz
× 10 MHz
× 20 MHz
16
17
18
19
20
16.2 mW
15
IDLE;
14
POWER (PIDLE n ) – mW
× 3.32 V
× 3.32 V
× 3.32 V
× 3.32 V
15
16
(C × VDD2 × f ) is calculated for each output:
×f
14
POWER, IDLE n MODES 3
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 18).
× VDD2
13
1/ tCK – MHz
The application operates at VDD = 3.3 V and tCK = 50 ns.
# of
Pins × C
8.5 mW
13
12
11 11.8 mW
10
9
8
7
= 17.4 mW
= 9.8 mW
= 1.1 mW
= 2.2 mW
30.5 mW
7.8 mW
IDLE (16)
7.2 mW
IDLE (128)
6.8 mW
6
6.2 mW
5
12
13
14
15
16
17
18
19
20
1/ tCK – MHz
Total power dissipation for this example is PINT + 30.5 mW.
VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-2173 STATE OF OPERATION DURING
EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE
DRIVEN TO EITHER VDD OR GND. POWER REFLECTS DEVICE
OPERATING WITH CLKOUT DISABLED.
3 TYPICAL POWER DISSIPATION AT 3.3V V
DD DURING EXECUTION
OF IDLE n INSTRUCTION (CLOCK FREQUENCY REDUCTION).
POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.
2
Figure 34. Power vs. Frequency
REV. A
–43–
ADSP-2171/ADSP-2172/ADSP-2173
tDECAY, is dependent on the capacitative load, CL, and the current load, iL, on the output pin. It can be approximated by the
following equation:
ADSP-2173
CAPACITIVE LOADING
Figures 35 and 36 show the capacitive loading characteristics of
the ADSP-2173.
t DECAY =
CL • 0.5V
iL
from which
t DIS = t MEASURED – t DECAY
RISE TIME (0.4 V – 2.4 V) – ns
28
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
24
VDD = 3.3 V
20
INPUT
VDD
2
OUTPUT
VDD
2
16
12
8
25
50
75
100
125
Figure 37. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
150
CL – pF
Output Enable Time
Figure 35. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
VALID OUTPUT DELAY OR HOLD – ns
+14
+12
+10
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
+8
REFERENCE
SIGNAL
+4
tMEASURED
tENA
+2
VOH
NOMINAL
tDIS
VOH
(MEASURED)
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
OUTPUT
-2
VOL
25
50
75
100
125
CL – pF
VOL
tDECAY
(MEASURED)
150
(MEASURED)
OUTPUT STOPS
DRIVING
Figure 36. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 38. Output Enable/Disable
TEST CONDITIONS
Output Disable Time
IOL
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
TO
OUTPUT
PIN
VDD
2
50pF
IOH
Figure 39. Equivalent Device Loading for AC Measurements (Including All Fixtures)
–44–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
HWR/HDS
HRD/HRW
HSIZE
HD6
HD7
HD8
HD9
HD10
VDD
HD11
HD12
HD13
HD14
HD15
PWDACK
BMS
DMS
PMS
VDD
GND
GND
WR
RD
NC
NC
NC
128-Lead TQFP Package Pinout
128
103
102
1
GND
GND
HA2/ALE
HA1
HA0
HSEL
HD5
HD4
HD3
HD2
HD1
HD0
V DD
GND
V DD
A0
A1
A3
A2
A4
A5
A6
A7
XTAL
CLKIN
CLKOUT
GND
A8
A9
A10
A11
A12
A13
NC
MMAP
NC
NC
PWD
NC
NC
D23
D22
D21
D20
D19
GND
D18
D17
D16
D15
D14
D13
D12
D11
VDD
GND
D10
D9
D8
D7
D6
D5
D4
D3
GND
D2
D1
D0
BG
NC
BR
NC
NC
NC
BGH
NC
TOP VIEW
(PINS DOWN)
38
65
39
IRQ2
NC
BMODE
NC
NC
VDD
GND
RESET
NC
HACK
HMD0
HMD1
DT0
TFS0
RFS0
DR0
SCLK0
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
FL0
FL1
FL2
64
NC = NO CONNECT
REV. A
–45–
ADSP-2171/ADSP-2172/ADSP-2173
TQFP Pin Configurations
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
HA2/ALE
HA1
HA0
HSEL
HD5
HD4
HD3
HD2
HD1
HD0
VDD
GND
VDD
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
CLKOUT
GND
A8
A9
A10
A11
A12
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A13
NC
MMAP
NC
NC
PWD
IRQ2
NC
BMODE
NC
NC
VDD
GND
RESET
NC
HACK
HMD0
HMD1
DT0
TFS0
RFS0
DR0
SCLK0
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/F1
SCLK1
FL0
FL1
FL2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
BGH
NC
NC
NC
BR
NC
BG
D0
D1
D2
GND
D3
D4
D5
D6
D7
D8
D9
D10
GND
VDD
D11
D12
D13
D14
D15
D16
D17
D18
GND
D19
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
D20
D21
D22
D23
NC
NC
NC
NC
NC
RD
WR
GND
GND
VDD
PMS
DMS
BMS
PWDACK
HD15
HD14
HD13
HD12
HD11
VDD
HD10
HD9
HD8
HD7
HD6
HSIZE
HRD/HRW
HWR/HDS
NC = These pins MUST remain unconnected.
–46–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
OUTLINE DIMENSIONS
128-Lead Metric Thin Plastic Quad Flatpack (TQFP)
D
SEATING
PLANE
D1
D3
A
L
103
128
102
1
TOP VIEW
(PINS DOWN)
E3 E1 E
D
38
65
64
39
A1
A2
SYMBOL
e
MILLIMETERS
MIN
TYP
MAX
A
MIN
1.60
A1
0.05
A2
1.30
D
D1
INCHES
TYP
MAX
0.063
0.15
0.002
1.40
1.50
0.051
0.055
0.059
15.75
16.00
16.25
0.620
0.630
0.640
13.90
14.00
14.10
0.547
0.551
0.555
12.50
12.58
0.492
0.495
D3
0.006
E
21.75
22.00
22.25
0.856
0.866
0.876
E1
19.90
20.00
20.10
0.783
0.787
0.792
18.50
18.58
0.728
0.731
E3
L
0.45
0.60
0.75
0.018
0.024
0.030
e
0.42
0.50
0.58
0.017
0.019
0.023
B
0.17
0.22
0.27
0.007
0.009
0.011
D
REV. A
B
0.10
–47–
0.004
ADSP-2171/ADSP-2172/ADSP-2173
NC
GND
GND
HWR/HDS
HRD/HRW
HSIZE
HD6
HD7
HD8
HD9
HD10
V DD
HD11
HD12
HD13
HD14
HD15
PWDACK
BMS
DMS
PMS
VDD
GND
GND
WR
RD
NC
NC
NC
NC
NC
NC
128-Lead PQFP Package Pinout
97
128
96
1
HA2/ALE
HA1
HA0
HSEL
HD5
HD4
HD3
HD2
HD1
HD0
V DD
GND
VDD
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
CLKOUT
GND
A8
A9
A10
A11
A12
A13
NC
D23
D22
D21
D20
D19
GND
D18
D17
D16
D15
D14
D13
D12
D11
V DD
GND
D10
D9
D8
D7
D6
D5
D4
D3
GND
D2
D1
D0
BG
NC
BR
NC
128L PQFP
(28MM x 28MM)
TOP VIEW
(PINS DOWN)
32
65
64
MMAP
NC
PWD
IRQ2
NC
BMODE
NC
NC
V DD
GND
RESET
NC
HACK
HMD0
HMD1
DT0
TFS0
RFS0
DR0
SCLK0
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
FL0
FL1
FL2
NC
BGH
NC
33
NC = NO CONNECT
–48–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
PQFP Pin Configurations
PQFP
Number
Pin
Name
PQFP
Number
Pin
Name
PQFP
Number
Pin
Name
PQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HA2/ALE
HA1
HA0
HSEL
HD5
HD4
HD3
HD2
HD1
HD0
VDD
GND
VDD
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
CLKOUT
GND
A8
A9
A10
A11
A12
A13
NC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MMAP
NC
PWD
IRQ2
NC
BMODE
NC
NC
VDD
GND
RESET
NC
HACK
HMD0
HMD1
DT0
TFS0
RFS0
DR0
SCLK0
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/F1
SCLK1
FL0
FL1
FL2
NC
BGH
NC
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
BR
NC
BG
D0
D1
D2
GND
D3
D4
D5
D6
D7
D8
D9
D10
GND
VDD
D11
D12
D13
D14
D15
D16
D17
D18
GND
D19
D20
D21
D22
D23
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
NC
NC
NC
NC
NC
RD
WR
GND
GND
VDD
PMS
DMS
BMS
PWDACK
HD15
HD14
HD13
HD12
HD11
VDD
HD10
HD9
HD8
HD7
HD6
HSIZE
HRD/HRW
HWR/HDS
GND
GND
NC
NC = These pins MUST remain unconnected.
REV. A
–49–
ADSP-2171/ADSP-2172/ADSP-2173
OUTLINE DIMENSIONS
128-Lead Metric Thin Plastic Quad Flatpack (PQFP)
D
SEATING
PLANE
D1
D3
A
L
97
128
96
1
TOP VIEW
(PINS DOWN)
E3 E1 E
D
32
65
33
64
A1
A2
SYMBOL
e
MILLIMETERS
MIN
TYP
MAX
A
B
MIN
INCHES
TYP
MAX
4.07
0.160
0.25
A2
3.17
3.49
3.67
0.125
0.137
0.144
D, E
30.95
31.20
31.45
1.219
1.228
1.238
D 1, E1
27.90
28.00
28.10
1.098
1.102
1.106
D 3, E3
24.73
24.80
24.87
0.974
0.976
0.979
L
0.65
0.88
1.03
0.031
0.035
0.041
e
0.73
0.80
0.87
0.029
0.031
0.034
B
0.30
0.35
0.45
0.012
0.014
0.018
D
A1
0.010
0.10
–50–
0.004
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ORDERING GUIDE*
Part Number**
Ambient
Temperature
Range
Instruction
Rate
(MHz)
Package
Description
ADSP-2171KST-133
ADSP-2171BST-133
ADSP-2171KS-133
ADSP-2171BS-133
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
33.33
33.33
33.33
33.33
128-Lead TQFP
128-Lead TQFP
128-Lead PQFP
128-Lead PQFP
ADSP-2171KST-104
ADSP-2171BST-104
ADSP-2171KS-104
ADSP-2171BS-104
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
26
26
26
26
128-Lead TQFP
128-Lead TQFP
128-Lead PQFP
128-Lead PQFP
ADSP-2173BST-80
ADSP-2173BS-80
–40°C to +85°C
–40°C to +85°C
20
20
128-Lead TQFP
128 Lead PQFP
*Refer to section titled “Ordering Procedure for ADSP-2172 ROM Processors” for information about ordering ROM-coded parts.
**S = Plastic Quad Flatpack, ST = Plastic Thin Quad Flatpack.
REV. A
–51–
–52–
PRINTED IN U.S.A.
C1984a–6–11/95