ETC ADSP-21MOD970

a
Multiport Internet
Gateway Processor
ADSP-21mod970
FEATURES
PERFORMANCE
Complete Single-Chip Multiport Internet Gateway
Processor (No External Memory Required)
Implements Six Modem Channels in One Package
Each Processor Can Implement V.34/V.90 Data/Fax
Modem (Includes Datapump and Controller)
312 MIPS Sustained Performance, 19 ns Instruction Time
@ 3.3 V
Open Architecture Extensible to Voice Over IP and Other
Applications
Low Power Dissipation, 100 mW (Typical) per Digital
Modem Processor
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
960K Bytes of On-Chip RAM, Configured as 576K Bytes
of Program Memory and 384K Bytes of Data Memory
Dual Purpose Program Memory for Both Instruction
and Data Storage
304-Ball PBGA with a 1.45 Square Inch (961 sq. mm)
Footprint
SYSTEM CONFIGURATION
16-Bit Internal DMA Port for High Speed Access to OnChip Memory (Mode Selectable)
Programmable Multichannel Serial Port Supports
24 Channels/32 Channels
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate RESET Pins for Each Internal Processor
GENERAL DESCRIPTION
The ADSP-21mod970 is a Multiport Internet Gateway Processor optimized for implementation of a complete V.34/56K
modem. All data pump and controller functions can be implemented on a single device, offering the lowest power consumption and highest possible modem port density.
The ADSP-21mod970 combines the ADSP-2100 family base
architecture (three computational units, data address generators
and a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-21mod970 integrates 960 bytes of on-chip memory,
configured as 192K words (24-bit) of program RAM, and 192K
words (16-bit) of data RAM. Power-down circuitry is also
provided to meet the low power needs of battery operated portable equipment. The ADSP-21mod970 is available in a
31 sq-mm., 304-lead PBGA package.
FUNCTIONAL BLOCK DIAGRAM
16
55
27
DATA<23:8>
CLKIN
IAD<15:0>
IDMA CNTL
16
4
MODEM
CHANNEL
2
SPORT0A
SPORT1
EMULATOR
MODEM
CHANNEL
5
MODEM
CHANNEL
6
4
SPORT0B
8
16
16
IDMA CNTL_1
MODEM
CHANNEL
4
4
IAD<15:0>_1
CLKIN_1,
BUS CNTL_1
MODEM
CHANNEL
3
4
MODEM
CHANNEL
1
DATA<23:8>_1
GROUND
VDD
9
4
ADSP-21mod970
IDMA CNTL = IAL, IRD, IWR, IACK
FLAGS = FL<0:2>, PF<0:7>
BUS CNTL = A0, BMS, PMS, DMS, CMS, IOMS, RD, WR
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK,
ELOUT, ERESET
SPORT0A, SPORT0B = RFS0, DR0, DT0, SCLK0
SPORT1 = RFS1, DR1, SCLK1, TFS1
6
6
6
66
6
6
6
6
6
6
BR<5:0>
BG<5:0>
BGH<5:0>
FLAGS
RESET<5:0>
CLKOUT<5:0>
EE<5:0>
IS<5:0>
TFS0<5:0>
DT1<5:0>
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADSP-21mod970
Fabricated in a high speed, low power, CMOS process, the
ADSP-21mod970 operates with a 19 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-21mod970 assembly source
code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes
over 100 ANSI-standard mathematical and DSP-specific
functions.
The ADSP-21mod970’s flexible architecture and comprehensive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle, the ADSP21mod970 can:
•
•
•
•
•
The ADSP-218x EZ-ICE® Emulator aids in the hardware debugging of an ADSP-21mod970 system. The EZ-ICE, in conjunction with the required processor selection hardware, lets you
independently debug code on individual modem processors.
The emulator consists of hardware, host computer resident
software, and the target board connector. The ADSP-21mod970
integrates on-chip emulation support with a 14-pin ICE-Port™
interface. The ADSP-21mod970 device need not be removed
from the target system when using the EZ-ICE, nor are any
adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
This takes place while the processor continues to:
•
•
•
•
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
Modem Software
The EZ-ICE performs a full range of functions, including:
The modem software executes general modem control, command sets, error correction and data compression, data
modulations (for example, V.90 and V.34), and host interface
functions. The host interface allows system access to modem
statistics such as call progress, connect speed, retrain count,
symbol rate and other modulation parameters.
•
•
•
•
•
•
•
•
The modem data pump and controller software reside in onchip SRAM and do not require additional memory. The user
can configure the ADSP-21mod970 dynamically by downloading software from the host through the 16-bit DMA interface.
This SRAM-based architecture provides a software upgrade
path to future standards and applications, such as voice over IP.
In-target operation
Up to 20 breakpoints
Single-step or full-speed operation
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
The modem software is available as object code.
Additional Information
DEVELOPMENT SYSTEM
This data sheet provides a general overview of ADSP-21mod970
functionality. For specific information about the modem processors, refer to the ADSP-21mod870 data sheet. For additional
information on the architecture and instruction set of the modem processors, refer to the ADSP-2100 Family User’s Manual,
Third Edition. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools Data
Sheet.
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-21mod970. The System Builder provides a high level
method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display
different portions of the hardware environment.
EZ-ICE is a registered trademark of Analog Devices, Inc.
ICE-Port is a trademark of Analog Devices, Inc.
–2–
REV. 0
ADSP-21mod970
ARCHITECTURE OVERVIEW
MODEM PROCESSOR
INDIVDUAL
SIGNALS
Figure 1 is an overall block diagram of the ADSP-21mod970
modem pool. The modem pool contains six independent digital
modem processors.
BUSED
SIGNALS
PF7/IRQ2
DATA 23:8
PF6/IRQ1
IAD 15:0
IAL
PF5/IRQ0
IRD
PF4/IRQE
IRW
PF3/MODE D
IACK
PF2/MODE C
PF1/MODE B
DATA 23:8
PF0/MODE A
IAD 15:0
FL2
IAL
MODEM
FL1
IRD
PROCESSOR 1
FL0
IRW
EE
IACK
IS
EMS
TFS0
EINT
DT1
ELIN
BGH
EBR
BG
EBG
BR
ECLK
ELOUT
CLKOUT
ERESET
RESET
RFS0
A0
DR0
BMS
DT0
PMS
SCLK0
MODEM
DMS
PROCESSOR 1
RFS1
CMS
(ONLY)
DR1
IOMS
TFS1
RD
SCLK1
WR
CLKIN
Each individual modem processor has a DSP core, 160K bytes
of RAM, two serial ports, and a DMA port. The signals for a
single processor are shown in Figure 2. The signals of each
modem processor are accessed through the external pins of the
ADSP-21mod970. Some signals are bused with the signals of
the other processors and are accessed through a single external
pin. Other signals remain separate and they are accessed through
separate external pins for each processor.
The arrangement of the six modem processors in the ADSP21mod970 makes two basic configurations possible: a master
configuration and a slave configuration. In both configurations,
the control and data pins of five of the six processors connect to
a single bus structure. The control and data pins of the one
modem processor (Modem Processor 1) are separate from the
other modem processors and accessed through external pins.
In Slave Mode, all six modem processors have identical functions and have equal status. Each modem processor is connected to a common DMA bus and each modem processor is
configured to operate in the same mode (see the Slave Mode
and the Memory Mode descriptions in the Memory Architecture
Figure 2. Modem Processor Signals
ADSP-21mod970
16
DATA<23:8>
CLKIN
IAD<15:0>
IDMA CNTL
16
4
MODEM
CHANNEL
2
SPORT0A
SPORT1
EMULATOR
IAD<15:0>
CLKIN_1,
BUS CNTL
IDMA CNTL
MODEM
CHANNEL
4
MODEM
CHANNEL
5
4
SPORT0B
4
8
16
16
IDMA CNTL = IAL, IRD, IWR, IACK
FLAGS = FL<0:2>, PF<0:7>
BUS CNTL = A0, BMS, PMS, DMS, CMS, IOMS, RD, WR
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET
SPORT0A, SPORT0B = RFS0, DR0, DT0, SCLK0
SPORT1 = RFS1, DR1, SCLK1, TFS1
THE FOLLOWING SIGNALS ARE ROUTED TO EACH ADSP-21mod970:
9
4
6
6
6
66
BR<5:0>
BG<5:0>
BGH<5:0>
FLAGS
6
6
RESET<5:0>
CLKOUT<5:0>
EE<5:0>
NOTES:
IRQ FUNCTIONS ARE MULTIPLEXED
WITH PROGRAMMABLE FLAGS
(SEE ADSP-21mod870 DATA SHEET)
6
6
6
IS<5:0>
TFS0<5:0>
DT1<5:0>
6
Figure 1. Modem Pool
REV. 0
MODEM
CHANNEL
6
4
MODEM
CHANNEL
1
DATA<23:8>
MODEM
CHANNEL
3
–3–
GND
VDD
55
27
ADSP-21mod970
section). The Slave Mode is considered to be the normal mode
of operation in a modem pool application. Figure 3 shows the
modem pool configured for slave mode operation.
The master mode of the ADSP-21mod970 configures five of the
modem processors with identical functions and isolates one of
the modem processors, Processor 1. In the Master Mode, Processor 1 is not connected to the DMA bus as are the other five
modem processors. Processor 1 operates in a different mode
where external pins can be used for access to a 16-bit data bus,
a 14-bit address bus with associated bus control pins. In master
CLKOUT
RESET
BR
BG
BGH
FLAGS
HIGH/1
LOW/0
HIGH/1
HIGH/1
Since the memory bus of Processor 1 is accessible via external
pins in master mode, Processor 1 can be configured for one of
the several memory modes available on the ADSP-21xx family.
(See Full Memory, Host Mode Descriptions.)
6
ADSP-21mod970
6
6
SPORT0A BUS
4
6
SPORT0B BUS
6
42
ICE
MODE A
SPORT0
MODE B
MODEM
PROCESSOR
1
(MASTER)
MODE C
MODE D
4
ICE BUS
SPORT0
ICE
MODEM
PROCESSOR
2
(SLAVE)
CNTL ADDR
IDMA
DATA &
CONTROL BUS
mode, Processor 1 is treated as a master of the modem pool and
communicates with an external device such as a RAM, ROM or
a memory shared with a host processor. In this configuration,
the master processor performs some controlling function of the
remaining five modem processors. Figure 4 shows the modem
pool configured for Slave Mode operation.
D&CB IDMA
SPORT0
ICE
MODEM
PROCESSOR
3
(SLAVE)
14
SPORT0
ICE
MODEM
PROCESSOR
4
(SLAVE)
D&CB IDMA
D&CB IDMA
SPORT0
ICE
ICE
MODE A
MODEM
PROCESSOR
6
(SLAVE)
MODE B
SPORT0
MODEM
PROCESSOR
5
(SLAVE)
D&CB IDMA
SPORT0A
SPORT0B
ICE
HIGH/1
LOW/0
MODE C
35
HIGH/1
MODE D
HIGH/1
D&CB IDMA
21
25
24
16
IDMA
DATA BUS
CLKIN
CLKIN
Figure 3. Configured for Slave Mode
CLKOUT
RESET
BR
BG
BGH
FLAGS
HIGH/1
LOW/0
HIGH/1
HIGH/1
6
ADSP-21mod970
6
6
SPORT0A BUS
SPORT0B BUS
ADDRESS
MASTER
DATA
4
6
MODE A
SPORT0
MODE B
MODEM
PROCESSOR
1
(MASTER)
MODE C
MODE D
14
ICE BUS
42
ICE
CNTL ADDR
CONTROL
4
6
SPORT0
ICE
MODEM
PROCESSOR
2
(SLAVE)
D&CB IDMA
SPORT0
ICE
MODEM
PROCESSOR
3
(SLAVE)
SPORT0
ICE
MODEM
PROCESSOR
4
(SLAVE)
D&CB IDMA
D&CB IDMA
SPORT0
ICE
MODEM
PROCESSOR
5
(SLAVE)
D&CB IDMA
SPORT0
ICE
MODE A
MODEM
PROCESSOR
6
(SLAVE)
MODE B
MODE C
MODE D
SPORT0B
ICE
HIGH/1
LOW/0
35
HIGH/1
HIGH/1
D&CB IDMA
7
25
14
16
24
SPORT0A
IDMA
DATA BUS
CLKIN
CLKIN
Figure 4. Configured for Master Mode
–4–
REV. 0
ADSP-21mod970
Serial Ports
Common-Mode Pins
The ADSP-21mod970 has a multichannel serial port (SPORT)
connected to each internal digital modem processor for serial
communications.
Pin
Name(s)
#
Input/
of
OutPins put
Function
RESET
BR
BG
BGH
DMS
PMS
BMS
IOMS
CMS
RD
WR
IRQ2/
6
6
6
6
1
1
1
I
1
1
1
6
Following is a brief list of the capabilities of the ADSP-21mod970
SPORT. For additional information on the internal Serial Ports,
refer to the ADSP-2100 Family User’s Manual, Third Edition.
•
•
•
•
•
•
•
SPORT is bidirectional and has a separate, double-buffered
transmit and receive section.
SPORT can use an external serial clock or generate its own
serial clock internally.
SPORT has independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
SPORT supports serial data word lengths from 3 to 16 bits
and provides optional A-law and µ-law companding according to CCITT recommendation G.711.
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
SPORT can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An interrupt is
generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24- or 32-word, time-division multiplexed, serial bitstream.
CLKIN
CLKOUT
SPORT
FL0, FL1, FL2
VDD and GND
2
6
24
18
82
I
O
I/O
O
I
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hang Output
Data Memory Select Output
Program Memory Select Output
Byte Memory Select Output
I/O Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Request1
Programmable I/O Pin
Level-Sensitive Interrupt Requests 1
Programmable I/O Pin
Level-Sensitive Interrupt Requests 1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests 1
Programmable I/O Pin
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Clock Input
Processor Clock Output
Serial Port I/O Pins2
Output Flags
Power and Ground
EZ-Port
14
I/O
For Emulation Use
PF7
IRQL1/
PF6
IRQL0/
PF5
IRQE/
PF4
Mode D/
PIN DESCRIPTIONS
6
6
6
6
Mode C/
6
6
I
I/O
PF1
Mode A/
I
I/O
PF2
Mode B/
I/O
I
I/O
I
I/O
I
I/O
I
I/O
PF3
The ADSP-21mod970 is available in a 304-lead PBGA package.
In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag,
interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics.
I
I
O
O
O
O
O
O
O
O
O
I
6
I
I/O
PF0
NOTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the modem pool will vector to the appropriate interrupt vector address when the pin is asserted, either by external
devices, or set as a programmable flag.
2
SPORT configuration determined by the modem pool’s System Control Register. Software configurable.
REV. 0
–5–
ADSP-21mod970
Memory Interface Pins
Table I. Interrupt Priority and Interrupt Vector Addresses
The ADSP-21mod970 modem pool can be used in one of two
modes, master mode or slave mode. In master mode, Modem
Processor 1 operates with full memory (BDMA operation with
full external overlay memory and I/O capability). In Slave Mode,
Modem Processor 1 operates in host configuration (IDMA
operation with limited external addressing capabilities). The
operating mode is determined by the state of the Mode C pin
during RESET and cannot be changed while the modem pool
is running. See the Memory Architecture section for more
information.
Full Memory Pins (Mode C = 0) Modem Processor 1 Only
Pin
Name
#
of
Input/
Pins Output Function
A13:0
14
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
D23:0
24
I/O
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs Are
Also Used as Byte Memory Addresses)
I/O
O
D23:8
32
I/O
IWR
IRD
IAL
IS
IACK
2
2
2
6
2
I
I
I
I
O
RESET (or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
LOW POWER OPERATION
The ADSP-21mod970 has three low power modes that significantly reduce the power dissipation when the device operates
under standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
#
of
Input/
Pins Output Function
IAD15:0 32
A0
1
Interrupt Vector
Address (Hex)
When the modem pool is reset, interrupt servicing is disabled.
Host Pins (Mode C = 1)*
Modem Processor 1 and Modem Processors 2–6
Pin
Name
Source Of Interrupt
The CLKOUT pin may also be disabled to reduce external
power dissipation.
IDMA Port Address/Data Bus
Address Pin for External I/O, Program, Data, or Byte Access (Modem
Processor 1 Only)
Data I/O Pins for Program, Data
Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Drain
Power-Down
The ADSP-21mod970 modem pool has a low power feature
that lets the modem pool enter a very low power dormant state
through software control. Following is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
*In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, BMS and IOMS signals of Modem Processor 1.
•
Quick recovery from power-down. The modem pool begins
executing instructions in as few as 400 CLKIN cycles.
•
Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating and 400
CLKIN cycle recovery.
•
Power-down is initiated by the software power-down force
bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The
power-down interrupt also can be used as a nonmaskable,
edge-sensitive interrupt.
•
Context clear/save control allows the modem pool to continue where it left off or start with a clean context when leaving the power-down state.
•
The RESET pin also can be used to terminate power-down.
Interrupts
The interrupt controller allows each modem processor in the
modem pool to respond individually to eleven possible interrupts and reset with minimum overhead. The ADSP-21mod970
provides four dedicated external interrupt input pins, IRQ2,
IRQL1, IRQL0, and IRQE (shared with the PF7:4 pins) for
each modem processor. The ADSP-21mod970 also supports
internal interrupts from the timer, the byte DMA port, the serial
port, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable
(except power-down and reset). The IRQ2, IRQL1, and IRQL0
input pins can be programmed to be either level- or edge-sensitive.
IRQL0 and IRQL1 are level-sensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are
shown in Table I.
Idle
When the ADSP-21mod970 is in the idle mode, the modem
pool waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction. In idle mode IDMA, BDMA and autobuffer
cycle steals still occur.
–6–
REV. 0
ADSP-21mod970
Slow Idle
the host access server data directly from the ADSP-21mod970’s
internal memory. In this configuration, the Modem Processor 1
should be put into host memory mode where Mode D = 1,
Mode C = 1, Mode B = 0, and Mode A = 1 (see Table II).
The IDLE instruction is enhanced on the ADSP-21mod970 to
let the modem pool’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
CLOCK SIGNALS
The ADSP-21mod970 is clocked by a TTL-compatible clock
signal that runs at half the instruction rate; a 26 MHz input clock
yields a 19 ns processor cycle (which is equivalent to 52 MHz).
Normally, instructions are executed in a single processor cycle.
All device timing is relative to the internal instruction clock
rate, which is indicated by the CLKOUT signal when enabled.
The clock input signal is connected to the processor’s CLKIN
input.
The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the modem
pool fully functional, but operating at the slower clock rate.
While it is in this state, the modem pool’s other internal clock
signals, such as SCLK, CLKOUT and timer clock, are reduced
by the same ratio. The default form of the instruction, when no
clock divisor is given, is the standard IDLE instruction.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for a detailed
explanation of this power-down feature.
When the IDLE (n) instruction is used, it effectively slows down
the modem pool’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-21mod970 will remain
in the idle state for up to a maximum of n modem pool cycles
(n = 16, 32, 64 or 128) before resuming normal operation.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the modem pool’s reduced internal clock
rate. Under these conditions, interrupts must not be generated
at a faster rate than can be serviced, due to the additional time
the modem pool takes to come out of the idle state (a maximum
of n cycles).
Reset
The RESET signals initiate a reset of each modem processor in
the ADSP-21mod970. The RESET signals must be asserted
during the power-up sequence to assure proper initialization.
RESET during initial power-up must be held long enough to
let the internal clocks stabilize. If RESETs are activated any
time after power-up, the clocks continue to run and do not
require stabilization time.
SYSTEM CONFIGURATION
The power-up sequence is defined as the total time required for
the oscillator circuits to stabilize after a valid VDD is applied to
the processors, and for the internal phase-locked loops (PLL)
to lock onto the specific frequency. A minimum of 2000 CLKIN
cycles ensures that the PLLs have locked, but this does not
include the oscillators start-up time. During this power-up
sequence, the RESET signals should be held low. On any subsequent resets, the RESET signals must meet the minimum
pulsewidth specification, tRSP.
Figure 5 shows a typical multichannel modem configuration
with the ADSP-21mod970. A line interface can be used to
connect the multichannel subscriber or client data stream to the
multichannel serial port of the ADSP-21mod970. The ADSP21mod970 can support up to 64 channels. The IDMA port of
the ADSP-21mod970 is used to give a host processor full access
to the internal memory of the ADSP-21mod970. This lets the
host dynamically configure the ADSP-21mod970 by loading code
and data into its internal memory. This configuration also lets
T1/E1
LINE
INTERFACE
SPORT
SPORT
SPORT
SPORT
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
(SLAVE MODE)
(SLAVE MODE)
(SLAVE MODE)
(SLAVE MODE)
ST/CNTL
IDMA
ST/CNTL
IDMA
STATUS
& CONTROL
HOST CONTROL
HOST
MICRO
HOST ADDRESS
HOST DATA
STATUS
&
CONTROL
PAL
IDMA CONTROL
IDMA
PAL
IDMA ADDRESS
Figure 5. Multichannel Modem Configuration
REV. 0
–7–
ST/CNTL
IDMA
ST/CNTL
IDMA
ADSP-21mod970
The RESET inputs contain some hysteresis; however, if an RC
circuit is used to generate the RESET signals, the use of external
Schmidt triggers are recommended.
Memory and I/O. Refer to the figures and tables below for PM
and DM memory allocations in the ADSP-21mod970.
The ADSP-21mod970 modem pool operates in one of two
memory modes: Slave Mode or Master Mode. The memory
modes determine the memory access to Modem Processor 1. In
Slave Mode, the memory of Modem Processor 1 is configured
for Host Mode; in Master Mode, the memory of Modem Processor 1 is configured for Full-Memory Mode. Memories for
Modem Processors 2–6 are configured only for Host Mode.
The differences between these memory modes are explained in
the following sections. Figure 6 shows Program Memory, while
Figure 7 shows Data Memory. Table II summarizes ADSP21mod970 operating modes. Table III explains the mode bits
and memory booting.
The reset for each individual modem processor sets the internal
stack pointers to the empty stack condition, masks all interrupts
and clears the MSTAT register. When a RESET is released, if
there is no pending bus request and the modem processor is
configured for booting, the boot-loading sequence is performed.
The first instruction is fetched from on-chip program memory
location 0x0000 once boot loading completes.
MEMORY ARCHITECTURE
The ADSP-21mod970 provides a variety of memory and peripheral interface options for Modem Processor 1. The key
functional groups are Program Memory, Data Memory, Byte
MODE B = 0
PROGRAM MEMORY
ADDRESS
MODE B = 0
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
8K INTERNAL
PMOVLAY = 0, 4, 5
OR
8K EXTERNAL
PMOVLAY = 1, 2
0x2000–
ACCESSIBLE WHEN 0x3FFF
PMOVLAY = 0
0x2000–
0x3FFF
0x2000–
ACCESSIBLE WHEN
0x3FFF
INTERNAL PMOVLAY = 4
0x2000–
MEMORY
ACCESSIBLE WHEN
0x3FFF
PMOVLAY = 5
0x3FFF
DATA MEMORY
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
32 MEMORY
MAPPED
REGISTERS
0x3FFF
0x3FE0
0x3FDF
0x0000–
ACCESSIBLE WHEN 0x1FFF
DMOVLAY = 0
0x0000–
0x1FFF
0x0000–
ACCESSIBLE WHEN
0x1FFF
INTERNAL DMOVLAY = 4
0x0000–
MEMORY
ACCESSIBLE WHEN
0x1FFF
DMOVLAY = 5
0x2000
0x1FFF
8K INTERNAL
0x0000
0x2000–
ACCESSIBLE WHEN
0x3FFF
EXTERNAL PMOVLAY = 1
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 2
ADDRESS
INTERNAL
8160 WORDS
0x0000–
ACCESSIBLE WHEN
0x1FFF
EXTERNAL DMOVLAY = 1
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 2
8K INTERNAL
DMOVLAY = 0, 4, 5
OR
8K EXTERNAL
DMOVLAY = 1, 2
0x2000
0x1FFF
0x0000
PMOVLAY
MEMORY
A13*
A12:0*
PMOVLAY
MEMORY
A13*
0, 4, 5
INTERNAL
NOT APPLICABLE
NOT APPLICABLE
0, 4, 5
INTERNAL
NOT APPLICABLE
NOT APPLICABLE
1
EXTERNAL
OVERLAY1
0
13 LSBs OF ADDRESS BETWEEN
0x2000 AND 0x3FFF
1
EXTERNAL
OVERLAY1
0
13 LSBs OF ADDRESS BETWEEN
0x2000 AND 0x3FFF
2
EXTERNAL
OVERLAY2
1
13 LSBs OF ADDRESS BETWEEN
0x2000 AND 0x3FFF
2
EXTERNAL
OVERLAY2
1
13 LSBs OF ADDRESS BETWEEN
0x2000 AND 0x3FFF
*FULL-MEMORY MODE ONLY
A12:0*
*FULL-MEMORY MODE ONLY
Figure 6. Program Memory (Memory Shown in Grey Is
Accessible Only in Full-Memory Mode)
Figure 7. Data Memory
Table II. Processor and Memory Mode
Memory Modes
for
Modem Processor 1
ADSP-21mod970 Modes
Master
Slave
Host
• All Internal Program Memory Available
• All Internal Data Memory Available
• IDMA Port Enabled
• All Internal Program Memory Available
• All Internal Data Memory Available
• IDMA Port Enabled
Full-Memory
• All Internal and External Program Memory Available
• All Internal and External Data Memory Available
• I/O Space Available
• Byte Memory DMA (BDMA) Enabled
Not Applicable
–8–
REV. 0
ADSP-21mod970
Table III. Modes of Operation
MODE D
MODE C
MODE B
MODE A
Booting Method
X
0
0
0
BDMA feature is used to load the first 32 program memory words from
byte memory space. Program execution is held off until all 32 words are
loaded. Chip is configured in Full-Memory Mode1
0
1
0
0
BDMA feature is used to load the first 32 program memory words from
byte memory space. Program execution is held off until all 32 words are
loaded. Chip is configured in Host Mode. IACK requires pull-down.
(REQUIRES ADDITIONAL HARDWARE.)
0
1
0
1
IDMA feature is used to load internal memory as desired. Program execution is held off until internal program memory location 0x0000 is written
to. Chip is configured in Host Mode.1 IACK requires pull-down.
1
1
0
0
BDMA feature is used to load the first 32 program memory words from
byte memory space. Program execution is held off until all 32 words are
loaded. Chip is configured in Host Mode. IACK requires external pulldown. (REQUIRES ADDITIONAL HARDWARE.)
1
1
0
1
IDMA feature is used to load internal memory as desired. Program execution is held off until internal program memory location 0x0000 is written
to. Chip is configured in Host Mode.1 IACK requires external pull-down.1
NOTE
1
Considered standard operating settings. These configurations simplify your design and improve memory management.
5. Host checks IACK line to see if the processor has completed
the previous IDMA operation.
Slave Mode
This section describes the Slave Mode memory configuration of
Modem Processor 1. Modem Processors 2–6 are always configured for Slave Mode.
6. Host ends IDMA transfer.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.
Data Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient way for a host system and
the ADSP-21mod970 to communicate. The port is used to
access the on-chip program memory and data memory of each
modem processor with only one processor cycle per word overhead. The IDMA port cannot be used, however, to write to the
processor’s memory-mapped control registers. A typical IDMA
transfer process is described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the processor is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the processor’s IDMA control registers.
If IAD [15] = 1, the value of IAD [7:0] represent the IDMA
overlay: IAD [14:8] must be set to 0.
If IAD [15] = 0, the value of IAD [13:0] represent the starting address of internal memory to be accessed and IAD [14]
reflects PM or DM for access.
4. Host uses IS and IRD (or IWR) to read (or write) processor
internal memory (PM or DM).
REV. 0
–9–
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP21mod970 is operating at full speed.
The processor memory address is latched and then automatically incremented after each IDMA transaction. An external
device can therefore access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to be
sent for each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Once the address is stored, data can then either be read from or
written to, the ADSP-21mod970’s on-chip memory. Asserting
the select line (IS) and the appropriate read or write line (IRD
and IWR respectively) signals the ADSP-21mod970 that a particular transaction is required. In either case, there is a oneprocessor-cycle delay for synchronization. The memory access
consumes one additional processor cycle.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
Through the IDMAA register, the processor can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL)
directs the ADSP-21mod970 to write the address onto the
ADSP-21mod970
IAD0[14.0] bus into the IDMA Control Register. If IAD[15]
is set to 0, IDMA latches the address. If IAD[15] is set to 1,
IDMA latches OVLAY memory. The IDMAA register is memory
mapped at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host. The IDMA Overlay
Register is memory mapped at address DM (0x3FE7). See Figure 8 for more information on IDMA memory maps.
DMA
PROGRAM MEMORY
OVLAY
DMA
DATA MEMORY
OVLAY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x2000–
ACCESSIBLE WHEN 0x3FFF
PMOVLAY = 0
0x2000–
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 4
0x0000–
ACCESSIBLE WHEN 0x1FFF
DMOVLAY = 0
0x0000–
0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 4
0x2000–
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 5
I/O Space (Full Memory Mode)
The ADSP-21mod970 supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0-3, which specify up to seven wait states to
be automatically generated for each of four regions. The wait
states act on address ranges as shown in Table IV.
Table IV. Wait States
0x0000–
0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 5
NOTE:
IDMA AND BDMA HAVE SEPERATE DMA CONTROL REGISTERS
15
14
13
12
11
10
0
0
0
0
0
IDMA OVERLAY
9
8
7
6
0
0
RESERVED
SET TO 0
15
14
U
13
U
0
0
5
4
3
2
1
0
0
0
0
0
0
0
ID DMOVLAY
U
U
IDMAD
DESTINATION MEMORY
TYPE:
0 = PM
1 = DM
U
U
U
U
U
U
U
2
1
0
U
U
U
Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.
ID PMOVLAY
IDMA CONTROL (U = UNDEFINED AT RESET)
12 11 10 9
8
7
6
5
4
3
U
DM
(0x3FE7)
Address Range
DM
(0x3FE0)
The byte memory space on the ADSP-21mod970 supports read
and write operations as well as four different data formats. The
byte memory uses data bits 15:8 for data. The byte memory uses
Data Bits 23:16 and Address Bits 13:0 to create a 22-bit address. This allows up to a 4 meg × 8 (32 megabit) ROM or
RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register.
IDMAA ADDRESS
Figure 8. IDMA Control/OVLAY Registers
IDMA Port Booting
The ADSP-21mod970 can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1,
the ADSP-21mod970 boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program
execution is held off until on-chip program memory location 0 is
written to.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit can access the byte memory space while the
processor is operating normally and steals only one processor
cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table V shows the data formats supported by the BDMA circuit.
Master Mode
This section describes the Master Mode memory configuration
of Modem Processor 1. Master Mode is not available for
Modem Processors 2–6.
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction op codes and data. The
ADSP-21mod970 has 32K words of Program Memory RAM on
chip, and it can access up to two 8K external memory overlay
spaces using the external data bus.
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-21mod970 has 32K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible
locations and 32 memory-mapped registers. The ADSP-21mod970
also supports up to two 8K external memory overlay spaces
through the external data bus. All internal accesses complete
in one cycle. Accesses to external memory are timed using the
wait states specified by the DWAIT register.
Table V. Data Formats
BTYPE
Internal
Memory Space
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
–10–
REV. 0
ADSP-21mod970
memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses
to boot memory must be constructed externally to the ADSP21mod970. The only memory address bit provided by the processor is A0.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the processor during BDMA operations.
Composite Memory Select (CMS)
The ADSP-21mod970 has a programmable memory select
signal that is useful for generating memory select signals for
memories mapped to more than one space. The CMS signal is
generated to have the same timing as each of the individual
memory select signals (PMS, DMS, BMS, IOMS) but can
combine their functionality.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one processor cycle. Processor
accesses to external memory have priority over BDMA byte
memory accesses.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory, and use either DMS or PMS as the additional
address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at Address 0 when
the BDMA accesses have completed. The BDMA overlay bits
specify the OVLAY memory blocks to be accessed for internal
memory.
Boot Memory Select (BMS) Disable
The ADSP-21mod970 also lets you boot the processor from one
external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for BDMA
transfers and BMS to select the second external memory space
for booting. The BMS signal can be disabled by setting Bit 3 of
the System Control Register to 1. The System Control Register
is illustrated in Figure 9.
Bootstrap Loading (Booting)
The ADSP-21mod970 has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits. When the MODE pins specify BDMA booting, the ADSP21mod970 initiates a BDMA boot sequence when reset is released.
Bus Request and Bus Grant
Each modem processor in the ADSP-21mod970 can relinquish
control of the data and address buses to an external device.
When the external device requires access to memory, it asserts
the bus request (BR) signal. If the modem processor is not performing an external memory access, then it responds to the
active BR input in the following processor cycle by:
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at Address 0.
Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
Asserting the bus grant (BG) signal, and
Halting program execution.
•
•
•
SYSTEM CONTROL REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
SPORT0A/SPORT0B ENABLED
1 = ENABLED, 0 = DISABLED
SPORT1 ENABLED
1 = ENABLED, 0 = DISABLED
1 = SERIAL PORT
0 = FI, FO, IRQ0, IRQ1, SCLK
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0 = ENABLED, 1 = DISABLED
Figure 9. System Control Register
REV. 0
DM (0x3FFF)
–11–
ADSP-21mod970
of its memory mode. Therefore, it is vital that the mode pins are
set correctly PRIOR to issuing a chip reset command from the
emulator user interface. As the mode pins share functionality
with PF0:3 on the ADSP-21mod970, it may be necessary to
reset the target hardware separately to insure the proper mode
selection state on emulator chip reset. See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products.
If Go Mode is enabled, the modem processor will not halt program execution until it encounters an instruction that requires
an external memory access.
If a modem processor is performing an external memory access
when an external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
The ICE-Port interface consists of the following ADSP-21mod970
pins:
EBR
EBG
ERESET
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when a modem processor is ready to
execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
modem processor deasserts BG and BGH and executes the
external memory access.
EMS
EINT
ECLK
ELIN
ELOUT
EE
These ADSP-21mod970 pins must be connected only to the
EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pull-up or
pull-down resistors. The traces for these signals between the
ADSP-21mod970 and the connector must be kept as short as
possible, no longer that 3 inches.
ADSP-21
mod970
ELOUT
EBR
EBG
EINT
ELIN
ECLK
EMS
ERESET
When the ADSP-21mod970 is powered up, all the modem
processors must relinquish bus control, and only one processor
at a time may control the bus.
ICE-PORT
CONNECTOR
Flag I/O Pins
Each modem processor has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP21mod970’s clock. Bits that are programmed as outputs will
read the value being output. The PF pins default to input during reset.
BG
GND
1
2
3
4
5
6
7
8
BR
EBG
ELIN
KEY
BG2
BR2
RESET2
EE2
ECLK
ELOUT
9
10
11
12
13
14
EMS
EE
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
BG1
BR1
RESET1
EE1
EINT
EBR
In addition to the programmable flags, each modem processor
has three fixed-mode output flags, FL0, FL1, and FL2.
BG0
BR0
RESET0
EE0
RESET
BG3
BR3
RESET3
EE3
ERESET
BG4
BR4
RESET4
EE4
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21mod970 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a
14-pin plug.
The EZ-ICE can emulate only one modem processor at a time.
You must include hardware to select which processor in the
ADSP-21mod970 you want to emulate. Figure 10 is a functional
representation of the modem processor selection hardware. You
can use one ICE-Port connector with two ADSP-21mod970
processors without using additional buffers.
Issuing the “chip reset” command during emulation causes the
modem processor to perform a full chip reset, including a reset
BG5
BR5
RESET5
EE5
Figure 10. Selecting a Modem Processor in the
ADSP-21mod970
The following pins are also used by the EZ-ICE:
BR
BG
RESET
GND
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-21mod970 in the target system. This causes
the processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in a system.
–12–
REV. 0
ADSP-21mod970
The EZ-ICE connects to target system via a ribbon cable and a
14-pin female plug. The female plug is plugged onto the 14-pin
connector (a pin strip header) on the target board.
this data sheet. The performance of the EZ-ICE may approach
published worst case specification for some memory access
timing requirements and switching characteristics.
Target Board Connector for EZ-ICE Probe
Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may
have trouble manufacturing your system as processor components statistically vary in switching characteristic and timing
requirements within published limits.
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 11. This connector must be added to the target board
design if the EZ-ICE is to be used. Be sure to allow enough
room in the system to fit the EZ-ICE probe onto the 14-pin
connector.
GND
BG
EBG
BR
EBR
EINT
KEY (NO PIN)
ELIN
ELOUT
EE
RESET
Restriction: All memory strobe signals on the ADSP-21mod970
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
ECLK
EMS
ERESET
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
Figure 11. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed
below.
•
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the processor on the
RESET signal.
•
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the processor on the BR
signal.
•
EZ-ICE emulation ignores RESET and BR when singlestepping.
•
EZ-ICE emulation ignores RESET and BR when in Emulator Space (processor halted).
•
EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
processor’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s processor.
PM, DM, BM, IOM, and CM
Design the Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in
REV. 0
–13–
ADSP-21mod970–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
Min
Max
Unit
VDD
TAMB
3.15
0
3.45
+70
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
1, 2
Hi-Level Input Voltage
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
Supply Current (Idle)9
IDD
Supply Current (Dynamic)11
CI
Input Pin Capacitance6
CO
Output Pin Capacitance6, 7, 12
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max
VIN = VDD max8
@ VDD = max
VIN = 0 V8
@ VDD = 3.3
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VDD = 3.3
TAMB = +25°C
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
2.0
2.2
K/B Grades
Typ
Max
0.8
Unit
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
62
53
47
µA
µA
mA
mA
mA
387
299
253
mA
mA
mA
40
pF
40
pF
NOTES
1
Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5
Although specified for TTL outputs, all ADSP-21mod970 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1.
8
0 V on BR.
9
Idle refers to ADSP-21mod970 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
12
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–14–
REV. 0
ADSP-21mod970
ABSOLUTE MAXIMUM RATINGS*
MEMORY TIMING SPECIFICATIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Table VI shows common memory device specifications and the
corresponding ADSP-21mod970 timing parameter.
Table VI. Memory Devices and Timing Parameters
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the processor operates correctly with other devices.
ADSP21mod970
Timing
Parameter
Memory
Device
Specification
Address Setup to
Write Start
Address Setup to
Write End
Address Hold Time
tAW
Data Setup Time
tDW
Data Hold Time
OE to Data Valid
Address Access Time
tDH
tRDD
tAA
Timing
Parameter
Definition
A0–A13, xMS Setup
before WR Low
A0–A13, xMS Setup
before WR Deasserted
A0–A13, xMS Hold
before WR Low
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data
Valid
tASW
tWRA
Note: xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5 tCKI. The ADSP-21mod970 uses an input
clock with a frequency equal to half the instruction rate: a
26.32 MHz input clock (which is equivalent to 38.0 ns) yields a
19 ns processor cycle (equivalent to 52 MHz). tCK values within
the range of 0.5 tCKI period should be substituted for all relevant
timing parameters to obtain the specification value.
Example: tCKH = 0.5 tCK – 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB
TJ
PD
θJA
=
=
=
=
TJ – (PD × θJA)
Junction Temperature in °C
Power Dissipation in W
Thermal Resistance (Junction-to-Ambient)
Package
␪JA
PBGA
26.9°C/W
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21mod970 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–15–
WARNING!
ESD SENSITIVE DEVICE
ADSP-21mod970
POWER DISSIPATION
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 13 and 14 show the capacitive loading characteristics of
the ADSP-21mod970.
C × VDD2 × f
20
C = load capacitance, f = output switching frequency.
T = +858C
VDD = +3.0V
RISE TIME (0.4V – 2.4V) – ns
18
POWER, INTERNAL
1600
1537.2
1400
POWER – mW
3.6V
1277.1
1200
3.3V
1029
1008
1000
16
14
12
10
8
6
3.0V
800
834.9
4
50
0
100
678
600
52
33.3
FREQUENCY – MHz
250
Figure 13. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)
10
VDD = 3.3V
200
VALID OUTPUT DELAY
OR HOLD – ns
223.2
VDD = 3.6V
POWER – mW
200
POWER, IDLE
250
204.6
186
169.2
150
150
CL – pF
155.1
VDD = 3.0V
141
8
6
4
2
NOMINAL
100
33.33
52
FREQUENCY – MHz
–2
POWER, IDLE n MODES
210
204.6
–4
0
IDLE
POWER – mW
170
40
80
120
160
200
CL – pF
190
Figure 14. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
155.1
150
130
110
90 82.4076
86.3709
70 79.2
33.33
83.0709
IDLE (16)
IDLE (128)
52
FREQUENCY – MHz
Figure 12. Power vs. Frequency
–16–
REV. 0
ADSP-21mod970
TEST CONDITIONS
Output Disable Time
output has reached a specified high or low trip point, as shown
in Figure 16. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference between tMEASURED and
tDECAY, as shown in Figure 15. The time is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
VOH
(MEASURED)
OUTPUT
The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be approximated by the following equation:
t DECAY
tENA
tDIS
VOH
(MEASURED)
VOH (MEASURED) –0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOL
(MEASURED)
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 16. Output Enable/Disable
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
1.5V
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
CL × 0.5 V
=
iL
from which
INPUT
OR
OUTPUT
VOL
(MEASURED)
tDECAY
IOL
TO
OUTPUT
PIN
1.5V
+1.5V
50pF
Figure 15. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Output Enable Time
IOH
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
REV. 0
Figure 17. Equivalent Device Loading for AC Measurements (Including All Fixtures)
–17–
ADSP-21mod970
TIMING PARAMETERS
Parameter
Min
Max
Unit
Timing Requirements:
CLKIN Period
tCKI
tCKIL
CLKIN Width Low
tCKIH
CLKIN Width High
38
15
15
100
ns
ns
ns
Switching Characteristics:
tCKL
CLKOUT Width Low
tCKH
CLKOUT Width High
tCKOH
CLKIN High to CLKOUT High
0.5 tCK – 7
0.5 tCK – 7
0
Clock Signals and Reset
20
ns
ns
ns
Control Signals
Timing Requirements:
tRSP
RESET Width Low
tMS
Mode Setup before RESET High
tMH
Mode Setup after RESET High
5 tCK1
2
5
ns
ns
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(3:0)*
tMS
tMH
RESET
*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 18. Clock Signals
–18–
REV. 0
ADSP-21mod970
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirements:
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
tIFS
tIFH
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25 tCK + 15
0.25 tCK
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
ns
ns
0.25 tCK – 7
0.5 tCK + 6
ns
ns
NOTES
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information
on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 19. Interrupts and Flags
REV. 0
–19–
ADSP-21mod970
TIMING PARAMETERS
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
tBS
BR Setup before CLKOUT Low1
0.25 tCK + 2
0.25 tCK + 17
Switching Characteristics:
tSD
CLKOUT High to xMS, RD, WR Disable
tSDB
xMS, RD, WR Disable to BG Low
tSE
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
tSEC
tSDBH
xMS, RD, WR Disable to BGH Low2
tSEH
BGH High to xMS, RD, WR Enable2
0
0
0.25 tCK – 4
0
0
ns
ns
0.25 tCK + 10
ns
ns
ns
ns
ns
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
tSDBH
tSEH
Figure 20. Bus Request–Bus Grant
–20–
REV. 0
ADSP-21mod970
Parameter
Min
Max
Unit
0.5 tCK – 9 + w
0.75 tCK – 12.5 + w
ns
ns
ns
Memory Read
Timing Requirements:
tRDD
RD Low to Data Valid
tAA
A0–A13, xMS to Data Valid
tRDH
Data Hold from RD High
0
Switching Characteristics:
tRP
RD Pulsewidth
tCRD
CLKOUT High to RD Low
tASR
A0–A13, xMS Setup before RD Low
A0–A13, xMS Hold after RD Deasserted
tRDA
tRWR
RD High to RD or WR Low
0.5 tCK – 5 + w
0.25 tCK – 5
0.25 tCK – 6
0.25 tCK – 3
0.5 tCK – 5
0.25 tCK + 7
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tAA
tRDD
WR
Figure 21. Memory Read
REV. 0
–21–
tRDH
ns
ns
ns
ns
ns
ADSP-21mod970
TIMING PARAMETERS
Parameter
Min
Max
Unit
Memory Write
Switching Characteristics:
Data Setup before WR High
tDW
Data Hold after WR High
tDH
tWP
WR Pulsewidth
tWDE
WR Low to Data Enabled
A0–A13, xMS Setup before WR Low
tASW
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
A0–A13, xMS, Setup before WR Deasserted
tAW
tWRA
A0–A13, xMS Hold after WR Deasserted
tWWR
WR High to RD or WR Low
0.5 tCK – 7 + w
0.25 tCK – 2
0.5 tCK – 5 + w
0
0.25 tCK – 6
0.25 tCK – 7
0.25 tCK – 5
0.75 tCK – 9 + w
0.25 tCK – 3
0.5 tCK – 5
0.25 tCK + 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
tDDR
D
tDW
tWDE
RD
Figure 22. Memory Write
–22–
REV. 0
ADSP-21mod970
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
tSCP
38
4
7
15
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
tSCDE
SCLK High to DT Enable
SCLK High to DT Valid
tSCDV
tRH
TFS/RFSOUT Hold after SCLK High
tRD
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
tSCDH
tTDE
TFS (Alt) to DT Enable
tTDV
TFS (Alt) to DT Valid
SCLK High to DT Disable
tSCDD
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
0.25 tCK
0
15
15
0
0
14
15
15
tCC
tSCK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
tTDE
tTDV
TFSIN
ALTERNATE
FRAME MODE
tRDV
RFSIN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 23. Serial Ports
REV. 0
0.25 tCK + 10
0
SCLK
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
ns
ns
ns
ns
–23–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21mod970
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Address Latch
Timing Requirements:
Duration of Address Latch1, 2
tIALP
tIASU
IAD15–0 Address Setup before Address Latch End2
IAD15–0 Address Hold after Address Latch End2
tIAH
tIKA
IACK Low before Start of Address Latch2, 3
tIALS
Start of Write or Read after Address Latch End1, 2
tIALD
Address Latch Start after Address Latch End1, 2
10
5
2
0
3
2
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD15–0
tIASU
tIAH
tIASU
tIAH
tIALS
RD OR WR
Figure 24. IDMA Address Latch
–24–
REV. 0
ADSP-21mod970
Parameter
Min
Max
Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
tIDH
0
15
5
2
Switching Characteristic:
tIKHW
Start of Write to IACK High
4
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD15–0
tIDH
DATA
Figure 25. IDMA Write, Short Write Cycle
REV. 0
–25–
ns
ns
ns
ns
15
ns
ADSP-21mod970
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
IAD15–0 Data Setup before IACK Low2, 3, 4
tIKSU
tIKH
IAD15–0 Data Hold after IACK Low2, 3, 4
0
0.5 tCK + 10
2
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW
Start of Write to IACK High
1.5 tCK
4
ns
ns
ns
15
ns
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 26. IDMA Write, Long Write Cycle
–26–
REV. 0
ADSP-21mod970
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRK
End of Read after IACK Low2
0
2
Switching Characteristics:
IACK High after Start of Read1
tIKHR
tIKDS
IAD15–0 Data Setup before IACK Low
tIKDH
IAD15–0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
tIRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
tIRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)4
ns
ns
4
0.5 tCK – 7
0
10
0
10
2 tCK – 5
tCK – 5
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS
DATA
IAD15–0
READ
DATA
tIRDV
tIKDD
tIRDH
Figure 27. IDMA Read, Long Read Cycle
REV. 0
–27–
15
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21mod970
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRP
Duration of Read
0
15
Switching Characteristics:
tIKHR
IACK High after Start of Read1
IAD15–0 Data Hold after End of Read2
tIKDH
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
4
0
ns
ns
15
10
0
10
ns
ns
ns
ns
ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIRDE
tIKDH
PREVIOUS
DATA
IAD15–0
tIRDV
tIKDD
Figure 28. IDMA Read, Short Read Cycle
–28–
REV. 0
ADSP-21mod970
304-Ball PBGA Package Pinout
The ADSP-21mod970 package pinout is shown in the table below.
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
GND
PF0_1
PF2_1
FL1_1
D23_1
D21_1
D13_1
D16_1
GND
PF0_2
PF1_2
FL0_2
FL1_2
VDD
VDD
PF0_3
PF1_3
FL0_3
FL1_3
D21
D22
D23
GND
IAD3_1
GND
PF1_1
FL0_1
D22_1
D20_1
D19_1
D15_1
GND
D14_1
BGH_2
PF3_2
FL2_2
VDD
VDD
BGH_3
PF2_3
PF3_3
FL2_3
D20
DT0A
GND
B23
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
IAD1
IAD5_1
IAD0_1
GND
BGH_1
PF3_1
FL2_1
D12_1
D17_1
GND
IAD13_1
IAD15_1
PF2_2
VDD
VDD
VDD
IS_2
CLKOUT_2
PF4_2
DT1_2
EE_2
GND
IAD2
IAD0
IAD6_1
IAD4_1
A0_1
GND
D10_1
D11_1
D9_1
D18_1
GND
IAD14_1
BR_1
BG_1
IACK_1
VDD
VDD
BG_2
BR_2
PF5_2
RESET_2
GND
GND
D22
D23
E1
E2
E3
E4
E20
E21
E22
E23
F1
F2
F3
F4
F20
F21
F22
F23
G1
G2
G3
G4
G20
G21
G22
G23
H1
H2
H3
H4
H20
H21
H22
H23
J1
J2
J3
J4
J20
J21
J22
J23
K1
K2
K3
IAD4
IAD3
IAD8_1
IAD7_1
IAD2_1
IAD1_1
CLKIN
GND
GND
GND
IAD12_1
IAD9_1
IAD10_1
IWR_1
GND
GND
GND
GND
CLKIN_1
IAD11_1
D8_1
IRD_1
IAL
IRD
IWR
GND
RD_1
WR_1
IAL_1
IS_1
CLKOUT_3
RFS0A
DR0A
IS_3
DMS_1
BMS_1
PMS_1
CLKOUT_1
SCLK0A
PF4_3
BG_3
BR_3
D19
PF4_1
IOMS_1
K4
K20
K21
K22
K23
L1
L2
L3
L4
L20
L21
L22
L23
M1
M2
M3
M4
M20
M21
M22
M23
N1
N2
N3
N4
N20
N21
N22
N23
P1
P2
P3
P4
P20
P21
P22
P23
R1
R2
R3
R4
R20
R21
R22
R23
CMS_1
PF5_3
EBG
EBR
EINT
D17
D18
PF5_1
PF7_1
VDD
ERESET
ELIN
ELOUT
D15
D16
PF6_1
BGH_4
VDD
VDD
VDD
VDD
D13
D12
D14
PF1_4
VDD
PF6_3
ECLK
EMS
GND
GND
GND
TFS0_1
DT1_3
PF2_6
RESET_3
EE_3
IAD6
IAD7
IAD5
PF0_4
PF0_6
PF1_6
FL2_6
FL1_6
REV. 0
–29–
ADSP-21mod970
304-Ball PBGA Package Pinout (continued)
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
T1
T2
T3
T4
T20
T21
T22
T23
U1
U2
U3
U4
U20
U21
U22
U23
V1
V2
V3
V4
V20
V21
V22
V23
W1
W2
W3
W4
W20
W21
W22
D10
D9
D11
EE_1
BGH_6
TFS0_3
PF3_6
FL0_6
IAD9
IAD11
IAD8
PF2_4
GND
GND
GND
GND
IAD10
IAD12
DT1_1
PF3_4
GND
GND
GND
GND
D8
CLKOUT_4
RESET_1
IS_4
IS_6
PF7_3
IAD15
W23
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
GND
VDD
VDD
VDD
GND
FL0_4
VDD
FL2_4
CLKOUT_5
GND
IS_5
VDD
TFS0_2
PF6_2
PF0_5
FL0_5
FL2_5
RFS1
SCLK1
GND
GND
BR_5
IAD13
IACK
PF4_4
BG_4
GND
GND
FL1_4
VDD
EE_4
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
PF4_5
GND
PF6_5
VDD
DT1_5
BGH_5
PF7_2
PF1_5
FL1_5
TFS1
DR1
GND
DT1_6
GND
BG_5
IAD14
PF5_4
GND
PF6_4
GND
DT1_4
VDD
RESET_4
PF5_5
GND
PF7_5
VDD
RESET_5
PF4_6
GND
PF3_5
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
PF2_5
CLKOUT_6
RFS0B
GND
SCLK0B
RESET_6
GND
BG_6
GND
BR_4
PF7_4
GND
TFS0_4
VDD
VDD
GND
GND
TFS0_5
VDD
EE_5
PF5_6
GND
PF6_6
PF7_6
DT0B
TFS0_6
GND
DR0B
EE_6
BR_6
GND
ORDERING GUIDE
Part
Number
Ambient
Temperature Range
Processor Clock
Package
Description
Package
Option
ADSP-21mod970-000
0°C to +70°C
26.0 MHz
304-Ball PBGA
B-304
RELATED DOCUMENTS
ADSP-21mod970-110 Multiport Internet Gateway Processor solution.
–30–
REV. 0
REV. 0
CLK
OUT 5
GND
IS 5
–31–
ADSP-21mod970 Pinout
PF0 5
FL0 5
FL2 5
RFS1
SCLK1
GND
4
5
6
7
VDD
8
GND
9
GND
10
TFS0 5
11
VDD
12
EE 5
13
PF5 6
PF4 6
NOTE: THE NUMBER AFTER THE UNDERSCORE IN SIGNAL NAMES CORRESPONDS TO THE MODEM CHANNEL
NUMBER IN THE FUNCTIONAL BLOCK DIAGRAM ON PAGE 1. ANY SIGNAL NAME WITHOUT AN UNDERSCORE
CORRESPONDS TO SIGNALS BEING SHARED AMONG MODEM CHANNELS NUMBER 2–6.
3
VDD
RESET 5
14
GND
GND
15
PF6 6
PF3 5
16
PF7 6
PF2 5
17
18
TFS0 6
RFS0B
CLK
OUT 6
DT0B
DR1
TFS1
19
GND
GND
GND
2
TFS0 4
VDD
FL1 5
1
GND
PF7 5
PF1 5
PF7 4
GND
PF7 2
BR 4
PF5 5
RESET 4
BGH 5
GND
VDD
DT1 5
AC
DT1 4
VDD
AB
GND
PF6 5
PF6 4
GND
GND
PF4 5
PF5 4
GND
EE 4
PF4 4
Y
AA
VDD
BG 4
VDD
FL1 4
GND
VDD
D8
PF6 2
GND
VDD
CLK
OUT 4
IAD10
V
W
GND
BR 5
PF7 3
GND
GND
20
DR0B
21
EE 6
SCLK0B RESET 6
DT1 6
GND
IS 6
GND
IS 4
DT1 1
RESET 1
IAD12
PF3 4
GND
TFS0 3
BGH 6
EE 1
PF2 4
D11
IAD8
D9
IAD11
D10
IAD9
T
U
PF1 6
PF0 6
PF0 4
PF2 6
DT1 3
TFS0 1
GND
IAD5
GND
IAD7
GND
IAD6
TFS0 2
VDD
PF6 3
P
VDD
22
BR 6
GND
BG 5
IAD13
IAD15
GND
GND
PF3 6
23
GND
BG
IAD14
IACK
GND
GND
GND
FL0 6
AC
AB
AA
Y
W
V
U
T
R
P
EE 3
RESET 3
FL1 6
N
FL2 6
M
VDD
L
K
J
EMS
ELOUT
EINT
BR 3
H
G
F
E
D
C
B
A
ECLK
VDD
EBR
ELIN
EBG
BG 3
ERESET
R
VDD
PF1 4
D14
D12
D13
N
FL2 4
VDD
BGH 4
PF6 1
D16
D15
M
(TOP VIEW)
VDD
PF7 1
PF5 1
PF5 3
CMS 1
IOMS 1
D18
PF4 3
IS 3
GND
IWR
DR0A
GND
GND
GND
GND
GND
GND
IAD0
IAD1
IAD3
IAD2
GND
23
GND
IAD4
PF4 1
D8 1
IAL 1
22
D23
GND
GND
D17
VDD
GND
EE_2
D19
FL0 4
DT1 2
RESET 2
SCLK0A
ADSP-21mod970
PF5 2
PF4 2
BR 2
DT0A
PMS 1
L
IS 2
BG 2
D20
21
D22
BMS 1
K
VDD
VDD
CLK
OUT 2
FL2 3
20
D21
CLK
OUT 1
DMS 1
VDD
VDD
PF3 3
PF2 3
19
FL1 3
IRD
J
VDD
IACK 1
18
FL0 3
IRD 1
BG 1
BR 1
BGH 3
17
PF1 3
GND
PF2 2
IAD15 1
VDD
16
PF0 3
RFS0A
WR 1
RD 1
H
IAD13 1
1AD14 1
VDD
15
VDD
CLKIN
GND
GND
FL2 2
14
VDD
IWR 1
D18 1
D17 1
PF3 2
BGH 2
D14 1
GND
13
FL1 2
IAD1 1
D9 1
D15 1
12
FL0 2
11
PF1 2
10
PF0 2
9
GND
IAL
IAD11 1
CLKIN 1
G
IAD2 1
IAD10 1
D12 1
FL2 1
D19 1
D11 1
D20 1
8
D16 1
7
D13 1
CLK
OUT 3
IAD9 1
GND
D10 1
PF3 1
BGH 1
GND
A0 1
6
D21 1
IS 1
IAD7 1
IAD8 1
IAD12 1
F
IAD4 1
D
E
IAD0 1
IAD5 1
IAD6 1
C
5
D23 1
D22 1
PF1 1
GND
IAD3 1
B
4
FL1 1
FL0 1
3
PF2 1
2
PF0 1
1
GND
A
PIN
ADSP-21mod970
ADSP-21mod970
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
1.224 (31.10)
1.220 (31.00) SQ
1.217 (30.90)
TOP VIEW
1.051 (26.70)
1.037 (26.35) SQ
1.024 (26.00)
C3494–2.5–7/99
304-Ball Metric Plastic Ball Grid Array
(B-304)
0.050 (1.27)
BSC
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1.104 (28.04)
1.100 (27.94)
1.096 (27.84)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
BOTTOM VIEW
1.104 (28.04)
1.100 (27.94)
1.096 (27.84)
0.050 (1.27)
BSC
DETAIL A
DETAIL A
0.100 (2.54)
0.092 (2.33)
0.083 (2.12)
0.008 (0.20)
0.035 (0.90)
0.028 (0.70)
SEATING
MAX
0.024 (0.60)
PLANE 0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
BALL DIAMETER
PRINTED IN U.S.A.
NOTE
1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.012 (0.30)
OF THE IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10) OF ITS
IDEAL POSITION RELATIVE TO THE BALL GRID.
3. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
0.024 (0.62)
0.022 (0.56)
0.020 (0.50)
0.048 (1.22)
0.046 (1.17)
0.044 (1.12)
–32–
REV. 0