P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended memory; 64 kB/96 kB OTP with 2 kB/3 kB RAM Rev. 02 — 19 May 2003 Product data 1. General description The P87C51Mx2 represents the first microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2 features 96 kbytes of OTP program memory and 3 kbytes of data SRAM, while the P87C51MB2 has 64 kbytes of OTP and 2 kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs and Serial Peripheral Interface (SPI). Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of program memory and 8 Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits (ASICs). The P87C51Mx2 provides greater functionality, increased performance and overall lower system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for software work-around. The increased program memory enables design engineers to develop more complex programs in a high-level language like C, for example, without struggling to contain the program within the traditional 64 kbytes of program memory. These enhancements also greatly improve C Language efficiency for code size below 64 kbytes. The 51MX core is described in more detail in the 51MX Architecture Reference. 2. Features 2.1 Key features ■ Extended features of the 51MX Core: ◆ 23-bit program memory space and 23-bit data memory space ◆ Linear program and data address range expanded to support up to 8 Mbytes each ◆ Program counter expanded to 23 bits ◆ Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family ■ ■ ■ ■ ■ ■ ◆ New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces 100% binary compatibility with the classic 80C51 so that existing code is completely reusable Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 kbytes (MC2) or 64 kbytes (MB2) of on-chip OTP 3 kbytes (MC2) or 2 kbytes (MB2) of on-chip RAM Programmable Counter Array (PCA) Two full-duplex enhanced UARTs and Serial Peripheral Interface (SPI) communication modules 2.2 Key benefits ■ ■ ■ ■ ■ ■ Increases program/data address range to 8 Mbytes each Enhances performance and efficiency for C programs Fully 80C51-compatible microcontroller Provides seamless and compelling upgrade path from classic 80C51 Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs Supported by wide range of 80C51 development systems and programming tools vendors ■ The P87C51Mx2 makes it possible to develop applications at lower cost and with a reduced time-to-market 2.3 Complete features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Fully static Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 kbytes or 64 kbytes of on-chip OTP 3 kbytes or 2 kbytes of on-chip RAM 23-bit program memory space and 23-bit data memory space Four-level interrupt priority 34 I/O lines (5 ports) Three Timers: Timer0, Timer1 and Timer2 Two full-duplex enhanced UARTs with baud rate generator Framing error detection Automatic address recognition Supports industry-standard Serial Peripheral Interface (SPI) with a baud rate up to 6 Mbits/s Power control modes Clock can be stopped and resumed Idle mode Power down mode with advanced clock control Second DPTR register Asynchronous port reset Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 2 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family ■ Low EMI (inhibit ALE) ■ Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler) 3. Differences between P87C51MX2/02 part and previous revisions of P87C51MX2 The P87C51MX2/02 offers several advantages over the previous generation of P87C51MX2 parts. Right now, SPI module is available, two more general purpose digital pins on P4 are present and additional power control features are implemented (advanced peripheral clock control). New memory interface mode and code size optimization options are available with the use of MXCON register. No changes are necessary when porting and loading code written for existing P87C51MX2 to the new P87C51MX2/02. 4. Ordering information Table 1: Ordering information Type number Memory OTP RAM Temp Range (°C) VDD voltage Frequency Package range VDD = 2.7 VDD = 4.5 Name Description to 5.5 V to 5.5 V Version P87C51MB2BA/02 64 kB 2048 B 0 to +70 2.7 to 5.5 V 0 to 12 MHz 0 to 24 MHz PLCC44 plastic leaded SOT187-2 chip carrier; 44 leads P87C51MC2BA/02 96 kB 3072 B 0 to +70 2.7 to 5.5 V 0 to 12 MHz 0 to 24 MHz PLCC44 plastic leaded SOT187-2 chip carrier; 44 leads © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 3 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 5. Block diagram HIGH PERFORMANCE 80C51 CPU (51 MX CORE) 96kB/64kB CODE EPROM UART 0 internal bus CRYSTAL OR RESONATOR 3kB/2kB DATA RAM BAUD RATE GENERATOR PORT 4 UART 1 PORT 3 SPI PORT 2 TIMER 0 TIMER 1 PORT 1 TIMER 2 PORT 0 CONFIGURABLE I/Os PCA (PROGRAMMABLE COUNTER ARRAY) OSCILLATOR WATCHDOG TIMER 002aaa148 Fig 1. Block diagram. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 4 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 6. Functional diagram MISO SS RXD1 TXD1 Address Bus 8-15 PORT1 P87C51Mx2 PORT2 RXD0 TXD0 INT0 INT1 T0 T1 WR RD PORT 3 Data Bus T2 T2EX ECI CEX0 CEX1 CEX2 CEX3 CEX4 MOSI SPICLK Address Bus 16-22 PORT 4 Address bus 0-7 VSS PORT0 VDD RST XTAL2 EA/VPP XTAL1 PSEN ALE/PROG 002aaa147 Fig 2. Functional diagram. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 5 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 7. Pinning information 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 VDD 1 (NC/VSS) 2 P1.0/T2 3 P1.1/T2EX 4 P1.2/ECI 5 P1.3/CEX0 6 P1.4/CEX1/MOSI 7.1 Pinning P1.5/CEX2/SPICLK 7 39 P0.4/AD4 P1.6/CEX3 8 38 P0.5/AD5 P1.7/CEX4 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RXD0 11 35 EA/VPP P87C51MB2/ P87C51MC2 P4.0/RXD1/MIS0 12 34 P4.1/TXD1/SS P3.1/TXD0 13 33 ALE P3.2/INT0 14 32 PSEN P3.3/INT1 15 31 P2.7/A15 P2.4/A12/A20 28 P2.3/A11/A19 27 P2.2/A10/A18 26 P2.1/A9/A17 25 P2.0/A8/A16 24 (NC/VDD) 23 VSS 22 XTAL1 21 29 P2.5/A13/A21 XTAL2 20 P3.5/T1 17 P3.7/RD 19 30 P2.6/A14/A22 P3.6/WR 18 P3.4/T0 16 002aaa165 Fig 3. Pinning. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 6 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 7.2 Pin description Table 2: Pin description Symbol Pin Type Description P0.0 - P0.7 43 - 36 I/O Port 0: Port 0 is an open drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. P1.0 - P1.7 2-9 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled LOW will source current because of the internal pull-ups. 2 I/O • P1.0, T2 – Timer/Counter 2 external count input/Clock out 3 I • P1.1, T2EX – Timer/Counter 2 Reload/Capture/Direction Control 4 I • P1.2, ECI – External Clock Input to the PCA 5 I/O • P1.3, CEX0 6 I/O • P1.4, CEX1 – Capture/Compare External I/O for PCA module 0 – Capture/Compare External I/O for PCA module 1 (with pull-up on pin) I/O • MOSI – SPI Master Out/Slave In (Selected when SPEN (SPCTL.6) is ‘1’, in which case the pull-up for this pin is disabled) 7 I/O • P1.5, CEX2 I/O • SPICLK – Capture/Compare External I/O for PCA module 2 (with pull-up on pin) – SPI Clock (Selected when SPEN (SPCTL.6) is ‘1’, in which case the pull-up for this pin is disabled) 8 I/O • P1.6, CEX3 – Capture/Compare External I/O for PCA module 3 9 I/O • P1.7, CEX4 – Capture/Compare External I/O for PCA module © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 7 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family Table 2: Pin description…continued Symbol Pin Type Description P2.0 - P2.7 24 - 31 I/O Port 2: Port 2 is a 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 2 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled LOW will source current because of the internal pull-ups. (See Section 10 “Static characteristics”, IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR) or 23-bit addresses (MOVX @EPTR, EMOV). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @ Ri), port 2 emits the contents of the P2 Special Function Register. Note that when 23-bit address is used, address bits A16-A22 will be outputted to P2.0-P2.6 when ALE is HIGH, and address bits A8-A14 are outputted to P2.0-P2.6 when ALE is LOW. Address bit A15 is outputted on P2.7 regardless of ALE. P3.0 - P3.7 11,13 -19 I/O 11 I Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally pulled LOW will source current because of the internal pull-ups. • P3.0, RXD0 – Serial input port 0 13 O • P3.1, TXD0 14 I • P3.2, INT0 – Serial output port 0 – External interrupt 0 15 I • P3.3, INT1 – External interrupt 1 16 I • P3.4, T0 17 I • P3.5, T1 – Timer0 external input – Timer1 external input 18 O • P3.6, WR – External data memory write strobe 19 O • P3.7, RD – External data memory read strobe P4.0 - P4.1 12,34 I/O 12 I Port 4: Port 4 is an 2-bit bidirectional I/O port with internal pull-ups on all pins. Port 4 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 4 pins that are externally pulled LOW will source current because of the internal pull-ups. As inputs, port 4 pins that are externally pulled LOW will source current because of the internal pull-ups. (Note: When SPEN, i.e.,SPCTL.6, is ’1’, the pull-ups at these port pins are disabled.) • P4.0, RXD1 – Serial input port 1 (with pull-up on pin) I/O • MISO – SPI Master In/Slave Out (Selected when SFR bit SPEN (SPCTL.6) is ‘1’, in which case the pull-up for this pin is disabled) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 8 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family Table 2: Pin description…continued Symbol Pin Type 34 O Description • P4.1, TXD1 – Serial output port 1 (with pull-up on pin) I/O • SS – SPI Slave Select (Selected when SPEN (SPCTL.6) is ‘1’, in which case the pull-up for this pin is disabled) RST 10 I Reset: A HIGH on this pin for two machine cycles, while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. ALE 33 O Address Latch Enable: Output pulse for latching the LOW byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1⁄6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR AUXR.0. With this bit is set, ALE will be active only during a MOVX/EMOV/MOVC instruction. PSEN 32 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 35 I External Access Enable/Programming Supply Voltage: EA must be externally held LOW to enable the device to fetch code from external program memory locations. If EA is held HIGH, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. XTAL1 21 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 20 O Crystal 2: Output from the inverting oscillator amplifier. VSS 22 I Ground: 0 V reference. VDD 44 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes. (NC/VSS) 1 I No Connect/Ground: This pin is internally connected to VSS on the P87C51MB2/MC2. If connected externally, this pin must only be connected to the same VSS as at pin 22. (Note: Connecting the second pair of VSS and VDD pins is not required. However, they may be connected in addition to the primary VSS and VDD pins to improve power distribution, reduce noise in output signals, and improve system-level EMI characteristics.) (NC/VDD) 23 I No Connect/Power Supply: This pin is internally connected to VDD on the P87C51MB2/MC2. If connected externally, this pin must only be connected to the same VDD as at pin 44. (Note: Connecting the second pair of VSS and VDD pins is not required. However, they may be connected in addition to the primary VSS and VDD pins to improve power distribution, reduce noise in output signals, and improve system-level EMI characteristics.) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 9 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 8. Functional description 8.1 Memory arrangement P87C51MB2 has 64 kbytes of OTP (MX universal map range: 80:0000-80:FFFF), while P87C51MC2 has 96 kbytes of OTP (MX universal map range: 80:0000-81:7FFF). The P87C51MB2 and P87C51MC2 have 2 kbytes and 3 kbytes of on-chip RAM respectively: Table 3: Memory arrangement Data memory Size (bytes) and MX universal memory map range Type Description P87C51MB2 DATA memory that can be addressed both 128 directly and indirectly; can be used as (7F:0000-7F:007F) stack 128 superset of DATA; memory that can 256 be addressed indirectly (where direct (7F:0000-7F:00FF) address for upper half is for SFR only); can be used as stack 256 superset of DATA/IDATA; memory that 512 can be addressed indirectly using (7F:0000-7F:01FF) Universal Pointers (PR0,1); can be used as stack 512 memory (on-chip ‘External Data’) that 1536 is accessed via the MOVX/EMOV (00:0000-00:05FF) instructions using DPTR/EPTR 2560 IDATA EDATA XDATA P87C51MC2 (7F:0000-7F:001F) (7F:0000-7F:00FF) (7F:0000-7F:01FF) (00:0000-00:09FF) For more detailed information, please refer to the P87C51Mx2 User Manual or the 51MX Architecture Specification. 8.2 Special Function Registers Special Function Register (SFR) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. • SFR bits labeled ‘-’, ‘0’, or ‘1’ can only be written and read as follows: – ‘-’ MUST be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives. – ‘0’ MUST be written with ‘0’, and will return a ‘0’ when read. – ‘1’ MUST be written with ‘1’, and will return a ‘1’ when read. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 10 of 36 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 9397 750 11517 Product data Table 4: Special Function Registers Name Description SFR Addr. Bit functions and addresses MSB Bit address E7 LSB E6 E5 E4 E3 E2 E1 Reset value E0 ACC [1] Accumulator E0H AUXR [2] Auxiliary Function Register 8EH - - - - - - EXTRAM AO 00H[6] AUXR1 [2] Auxiliary Function Register 1 A2H - - - LPEP GF2 0 - DPS 00H[6] F6 F5 F4 F3 F2 F1 F0 00H Bit address F7 B [1] Baud Rate Generator Control 85H[3] 00H BRGR0 [2][5] Baud Rate Generator Rate LOW 86H[3] 00H BRGR1 [2][5] Baud Rate Generator Rate HIGH 87H[3] 00H CCAP0H [2] Module 0 Capture HIGH FAH XXH CCAP1H [2] Module 1 Capture HIGH FBH XXH CCAP2H [2] Module 2 Capture HIGH FCH XXH CCAP3H [2] Module 3 Capture HIGH FDH XXH CCAP4H [2] Module 4 Capture HIGH FEH XXH CCAP0L [2] Module 0 Capture LOW EAH XXH CCAP1L [2] Module 1 Capture LOW EBH XXH CCAP2L [2] Module 2 Capture LOW ECH XXH CCAP3L [2] Module 3 Capture LOW EDH XXH CCAP4L [2] Module 4 Capture LOW EEH CCAPM0 [2] Module 0 Mode DAH - ECOM_0 CAPP_0 CAPN_0 MAT_0 TOG_0 PWM_0 ECCF_0 00H[6] CCAPM1 [2] Module 1 Mode DBH - ECOM_1 CAPP_1 CAPN_1 MAT_1 TOG_1 PWM_1 ECCF_1 00H[6] CCAPM2 [2] Module 2 Mode DCH - ECOM_2 CAPP_2 CAPN_2 MAT_2 TOG_2 PWM_2 ECCF_2 00H[6] CCAPM3 [2] Module 3 Mode DDH - ECOM_3 CAPP_3 CAPN_3 MAT_3 TOG_3 PWM_3 ECCF_3 00H[6] CCAPM4 [2] Module 4 Mode DEH - ECOM_4 CAPP_4 CAPN_4 MAT_4 TOG_4 PWM_4 ECCF_4 00H[6] DE DD DC DB DA D9 D8 CR - CCF4 CCF3 CCF2 CCF1 CCF0 - - - - - - S0BRGS BRGEN 00H[6] XXH Bit address DF CCON [1] [2] PCA Counter Control D8H CH [2] PCA Counter HIGH F9H 00H CL [2] PCA Counter LOW E9H 00H CMOD [2] PCA Counter Mode D9H CF CIDL WDTE - - - CPS1 CPS0 ECF 00H[6] 00H[6] 80C51 8-bit microcontroller family 11 of 36 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. F0H P87C51MB2/P87C51MC2 Rev. 02 — 19 May 2003 B Register BRGCON [2] xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Special Function Registers…continued Description SFR Addr. Bit functions and addresses MSB LSB Reset value DPTR Data Pointer (2 bytes) DPH Data Pointer HIGH 83H 00H DPL Data Pointer LOW 82H 00H EPTR Extended Data Pointer (3 bytes) EPL [2] Extended Data Pointer LOW FCH[3] 00H EPM [2] Extended Data Pointer Middle FDH[3] 00H EPH [2] Extended Data Pointer HIGH FEH[3] 00H 00H Bit address AF IEN0 [1] Interrupt Enable 0 Philips Semiconductors 9397 750 11517 Product data Table 4: A8H EA AE AD AC AB AA A9 A8 EC ET2 ES0/ ET1 EX1 ET0 EX0 00H ES0R Bit address EF Rev. 02 — 19 May 2003 IEN1 [1] Interrupt Enable 1 E8H - EE ED EC EB EA E9 E8 - - - ESPI ES1T ES0T ES1/ BE BD BC BB BA B9 B8 PS0/ PT1 PX1 PT0 PX0 00H PT1H PX1H PT0H PX0H 00H 00H[6] ES1R Bit address BF Interrupt Priority B8H - PPC PT2 IP0H Interrupt Priority 0 HIGH B7H - PPCH PT2H PS0R PS0RH Bit address FF Interrupt Priority 1 F8H - FE FD FC FB FA F9 F8 - - - PSPI PS1T PS0T PS1/ 00H[6] PS1R 12 of 36 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. IP1H Interrupt Priority 1 HIGH F7H - - - - PSPIH PS1TH PS0TH PS1H/ MXCON [2] MX Control Register FFH[3] - - - ECRM EAM1 EAM0 ESMM EIFM 86 85 84 83 82 81 80 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 CEX4 CEX3 CEX2/ CEX1/ CEX0 ECI T2EX T2 SPICLK MOSI 00H[6] PS1RH Bit address 87 P0 [1] Port 0 80H P1 [1] Port 1 90H 00H[6] FFH FFH 80C51 8-bit microcontroller family IP1 [1] PS0H/ P87C51MB2/P87C51MC2 IP0 [1] xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Special Function Registers…continued Name Description SFR Addr. Bit functions and addresses MSB Bit address A7 P2 [1] Port 2 A0H AD15 Bit address B7 P3 [1] Port 3 B0H RD Bit address C7[3] P4 [1] [2] PCON [2] C0H[3] Port 4 Power Control Register 87H SMOD1 LSB A6 A5 A4 A3 A2 A1 A0 AD14/ ADA13/ AD12/ AD11/ AD10/ AD9/ AD8/ AD22 AD21 AD20 AD19 AD18 AD17 AD16 B6 B5 B4 B3 B2 B1 B0 WR T1 T0 INT1 INT0 TxD0 RxD0 C6[3] C5[3] C4[3] C3[3] C2[3] C1[3] C0[3] - - - - - TxD1/ RxD1/ SS MISO PD IDL SMOD0 - POF GF1 GF0 Philips Semiconductors 9397 750 11517 Product data Table 4: Reset value FFH FFH FFH 00H/ 10H[4] Power Control Register A PSW [1] Program Status Word D0H RCAP2H [2] Timer2 Capture HIGH CBH 00H RCAP2L [2] Timer2 Capture LOW CAH 00H S0CON [1] Serial Port 0 Control B5H - Bit address D7 CY Bit address 9F 98H SM0_0/ PCAPD - SPIPD BRGPD T2PD S1PD S0PD D6 D5 D4 D3 D2 D1 D0 AC F0 RS1 RS0 OV F1 P 9E 9D 9C 9B 9A 99 98 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00H 00H FE_0 Serial Port 0 Data Buffer Register 99H xxH S0ADDR Serial Port 0 Address Register A9H 00H S0ADEN Serial Port 0 Address Enable B9H 00H Serial Port 0 Status 8CH[3] S0STAT [2] DBMOD_0 Bit address 87[3] S1CON [1] [2] INTLO_0 CIDIS_0 DBISEL_ FE_0 0 BR_0 OE_0 STINT_0 86[3] 85[3] 84[3] 83[3] 82[3] 81[3] 80[3] SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00H[6] Serial Port 1 Control 80H[3] S1BUF [2] Serial Port 1 Data buffer Register 81H[3] XXH S1ADDR [2] Serial Port 1 Address Register 82H[3] 00H Serial Port 1 Address Enable 83H[3] 00H SM0_1/ 00H FE_1 S1ADEN [2] 80C51 8-bit microcontroller family 13 of 36 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. S0BUF P87C51MB2/P87C51MC2 Rev. 02 — 19 May 2003 PCONA [2] xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Special Function Registers…continued Name Description SFR Addr. Bit functions and addresses LSB Reset value S1STAT [2] Serial Port 1 Status 84H[3] DBMOD_1 INTLO_1 CIDIS_1 DBISEL1 FE_1 BR_1 OE_1 STINT_1 00H[6] SPCTL [2] SPI Control Register E2H SSIG SPEN DORD MSTR CPOL CPHA PSC1 PSC0 00H[6] SPCFG [2] SPI Configuration Register E1H SPIF SPWCOL - - - SPDAT [2] - - - 00H[6] SPI Data E3H 00H SP Stack Pointer (or Stack Pointer LOW Byte When EDATA Supported) 81H 07H SPE [2] Stack Pointer HIGH FBH[3] 00H MSB Bit address 8F 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 CF CE CD CC CB CA C9 C8 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H - - ENT2 TF2DE T2GATE T2PWME T2OE DCEN 00H[6] 88H T2CON [1] [2] Timer2 Control Register C8H T2MOD [2] Timer2 Mode Control C9H TH0 Timer 0 HIGH 8CH 00H TH1 Timer 1 HIGH 8DH 00H TH2 Timer 2 HIGH CDH 00H TL0 Timer 0 LOW 8AH 00H TL1 Timer 1 LOW 8BH 00H TL2 Timer 2 LOW CCH TMOD Timer 0 and 1 Mode 89H WDTRST [2] Watchdog Timer Reset A6H Watchdog Timer Control 8FH[3] WDCON [2] [1] [2] [3] [4] [5] [6] 00H 00H GATE C/T M1 M0 GATE C/T M1 M0 00H FFH - - - - - WDPRE2 WDPRE1 WDPRE0 00H[6] SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Extended SFRs accessed by preceding the instruction with MX escape (opcode A5h). Power on reset is 10H. Other reset is 00H. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any of them is written if BRGEN = 1, result is unpredictable. The unimplemented bits (labeled ‘-’) in the SFRs are X’s (unknown) at all times. ‘1’s should not be written to these bits, as they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read. 80C51 8-bit microcontroller family 14 of 36 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Timer Control Register P87C51MB2/P87C51MC2 Rev. 02 — 19 May 2003 8E TCON [1] Philips Semiconductors 9397 750 11517 Product data Table 4: P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 8.3 Security bits The P87C51Mx2 has security bits to protect users’ firmware codes. With none of the security bits programmed, the code in the program memory can be verified. When only security bit 1 (see Table 5) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. EA is latched on Reset and all further programming of EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. Table 5: EPROM security bits Security Bits[1][2] Bit 1 Bit 2 Bit 3 Protection description 1 U U U No program security features enabled. EEPROM is programmable and verifiable. 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verification is disabled. 4 P P P Same as 3, external execution is disabled. [1] [2] P - programmed. U - unprogrammed. Any other combination of security bits is not defined. 9. Limiting values Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb operating temperature under bias 0 +70 °C Tstg storage temperature range −65 +150 °C V input voltage on EA/VPP pin to VSS 0 +13 input voltage on any other pin to VSS −0.5 VDD+ 0.5 V V II, IO maximum IOL per I/O pin - 20 mA P power dissipation - 1.5 W VI [1] based on package heat transfer, not device power consumption The following applies to the Limiting values: a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Section 10 “Static characteristics” and Section 11 “Dynamic characteristics” of this specification is not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 15 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 10. Static characteristics Table 7: Static characteristics Tamb = 0 °C to +70 °C for commercial, unless otherwise specified; VDD = 2.7 V to 5.5 V unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VIL Input low voltage −0.5 0.2VDD−0.1 V VIH Input high voltage (ports 0, 1, 2, 3, 4, EA) 0.2VDD+0.9 VDD+0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VDD VDD+0.5 V VOL Output low voltage, ports 1, 2, 3, 4[8] VDD = 4.5 V, IOL = 1.6 mA - 0.4 V Output LOW voltage, port 0, ALE, PSEN[7][8] VDD = 4.5 V, IOL = 3.2 mA - 0.4 V Output high voltage, ports 1, VDD = 4.5 V, IOH = −30 A 2, 3, 4 VDD = 2.7 V, IOH = −10 A VDD − 0.7 - V VOH1 Output high voltage (port 0 in VDD = 4.5 V, external bus mode), ALE[9], IOH = −3.2 mA PSEN[3] VDD = 2.7 V, IOH = −3.2 mA VDD − 0.7 - V IIL Logical 0 input current, ports VIN = 0.4 V 1, 2, 3, 4 −1 −75 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, 4[8] - −650 µA - 10 µA mA VOL1 VOH VDD = 2.7 V, IOL = 1.6 mA VDD = 2.7 V, IOL = 3.2 mA 4.5 V < VDD < 5.5 V, - [4] VIN = 2.0 V Input leakage current, port 0 0.45 < VIN < VDD−0.3 IL1 [5] Power supply current ICC Active mode[5] Idle mode[5] Power-down mode or clock stopped (see Figure 16 for conditions) - VDD = 5.5 V - 7 + 2.7 /MHz × fosc VDD = 3.6 V - 4 + 1.3 /MHz × fosc VDD = 5.5 V - 4 + 1.3 /MHz × fosc VDD = 3.6 V - VDD = 5.0 V - VDD = 5.5 V mA 1 + 1.0 /MHz × fosc - µA - 100 µA 20 RRST Internal reset pull-down resistor 40 225 kΩ C10 Pin capacitance[10] (except EA) - 15 pF [1] [2] [3] [4] [5] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), 5 V, unless otherwise stated. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and ports 1, 3 and 4. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading >100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD−0.7 V specification when the address bits are stabilizing. Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V for 4.5 V < VDD < 5.5 V. See Figure 13 through Figure 16 for ICC test conditions. fosc is the oscillator frequency in MHz. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 16 of 36 Philips Semiconductors P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family This value applies to Tamb = 0 °C to +70 °C. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. Under steady state (non-transient) conditions, IOL must be externally limited as follows: a) Maximum IOL per port pin: 15 mA b) Maximum IOL per 8-bit port: 26 mA c) Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. [9] ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. [10] Pin capacitance is characterized but not tested. [6] [7] [8] © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 17 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 11. Dynamic characteristics Table 8: Dynamic characteristics Tamb = 0 to +70 °C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Fig Parameter 2.7 V < VDD < 5.5 V Variable clock[4] 4.5 V < VDD < 5.5 V clock[4] fOSC = 12 MHz[4] Variable Min Max Min Max 0 24 Unit fOSC = 24 MHz[4] Min Max fOSC 4 Oscillator frequency 0 12 tCLCL 4 Clock cycle - - tLHLL 4 ALE pulse width tCLCL−15 - 68 - tCLCL−15 26 - ns tAVLL 4, 5, 6 Address valid to ALE LOW 0.5tCLCL−15 - 8 - 0.5tCLCL−15 - 5 - ns tLLAX 4, 5, 6 Address hold after ALE LOW 0.5tCLCL−25 - 16 - 0.5tCLCL−15 - 5 - ns tLLIV 4 ALE LOW to valid instruction in 121 - 53 ns tLLPL 4 ALE LOW to PSEN LOW 0.5tCLCL−25 - 16 - 0.5tCLCL−12 - 8 - ns tPLPH 4 PSEN pulse width 1.5tCLCL−25 - 100 - 1.5tCLCL−20 - 42 - ns tPLIV 4 PSEN LOW to valid instruction in 1.5tCLCL−45 - 80 - 1.5tCLCL−35 27 ns tPXIX 4 Input instruction hold after PSEN 0 - - 0 - 0 - ns tPXIZ 4 Input instruction float after PSEN - 0.5tCLCL−10 - 31 - 0.5tCLCL−5 - 15 ns tAVIV 4 Address to valid instruction in (non-Extended Addressing Mode) - 2.5tCLCL−35 - 173 - 2.5tCLCL−30 - 74 ns tAVIV1 4 Address (A16-A22) to valid instruction in (Extended Addressing Mode) 1.5tCLCL−44 - 81 - 1.5tCLCL−34 - 28 ns tPLAZ 4 PSEN LOW to address float 16 16 - 8 8 ns - 83 0.5tCLCL−25 0 - - - 41.5 2tCLCL − 30 - Max - MHz - ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data - Min Rev. 02 — 19 May 2003 18 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family Table 8: Dynamic characteristics…continued Tamb = 0 to +70 °C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Fig Parameter 2.7 V < VDD < 5.5 V Variable clock[4] 4.5 V < VDD < 5.5 V fOSC = 12 MHz[4] Variable clock[4] Unit fOSC = 24 MHz[4] Min Max Min Max Min Max Min Max Data Memory tRLRH 5 RD pulse width 3tCLCL−25 - 225 - 3tCLCL−20 - 105 - ns tWLWH 6 WR pulse width 3tCLCL−25 - 225 - 3tCLCL−20 - 105 - ns tRLDV 5 RD LOW to valid data in - 2.5tCLCL−55 - 153 - 2.5tCLCL−40 - 64 ns tRHDX 5 Data hold after RD 0 - 0 - 0 - 0 - ns tRHDZ 5 Data float after RD - tCLCL−20 - 63 - tCLCL−15 - 26 ns tLLDV 5 ALE LOW to valid data in 4tCLCL−50 - 283 - 4tCLCL−35 - 131 ns tAVDV 5 Address to valid data in (non-Extended Addressing Mode) - 4.5tCLCL−40 - 335 - 4.5tCLCL−30 - 157 ns tAVDV1 5 Address (A16-A22) to valid data in (Extended Addressing Mode) - 3.5tCLCL−45 - 246 - 3.5tCLCL−35 - 110 ns tLLWL 5, 6 ALE LOW to RD or WR LOW 1.5tCLCL−5 1.5tCLCL+20 120 145 1.5tCLCL−10 1.5tCLCL+20 52 82 ns tAVWL 5, 6 Address valid to WR or RD LOW (non-Extended Addressing Mode) 2tCLCL−5 - 161 - 2tCLCL−5 - 78 - ns tAVWL1 5, 6 Address (A16-A22) valid to WR or RD LOW (Extended Addressing Mode) tCLCL−10 - 73 - tCLCL−10 - 31 - ns tQVWX 6 Data valid to WR transition 0.5tCLCL−20 - 21 - 0.5tCLCL−15 - 5 - ns tWHQX 6 Data hold after WR 0.5tCLCL−25 - 16 - 0.5tCLCL−11 - 9 - ns tQVWH 6 Data valid to WR HIGH 3.5tCLCL−10 - 281 - 3.5tCLCL−10 - 135 - ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 19 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family Table 8: Dynamic characteristics…continued Tamb = 0 to +70 °C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Fig Parameter 2.7 V < VDD < 5.5 V Variable clock[4] 4.5 V < VDD < 5.5 V fOSC = 12 MHz[4] Variable clock[4] Unit fOSC = 24 MHz[4] Min Max Min Max Min Max Min Max 0 - 0 - 0 - 0 ns 51 0.5tCLCL−11 0.5tCLCL+10 9 30 ns tRLAZ 5 RD LOW to address float - tWHLH 5, 6 RD or WR HIGH to ALE HIGH 0.5tCLCL−20 0.5tCLCL+10 21 External Clock tCHCX 12 HIGH time 33 tCLCL−tCLCX 33 - 16 tCLCL−tCLCX 16 - ns tCLCX 12 LOW time 33 tCLCL−tCHCX 33 - 16 tCLCL−tCHCX 16 - ns tCLCH 12 Rise time - 8 - 8 - 4 - 4 ns tCHCL 12 Fall Time - 8 - 8 - 4 - 4 ns 6tCLCL - 500 - tCLCL−tCLCX - 250 - ns - 406 - tCLCL−tCHCX - 198 - ns Shift Register tXLXL 7 Serial port clock cycle time tQVXH 7 Output data setup 5tCLCL−10 to clock rising edge tXHQX 7 Output data hold after clock rising edge tCLCL−10 - 68 - tCLCL−15 - 26 - ns tXHDX 7 Input data hold after clock rising edge 0 - 0 - 0 - 0 - ns tXHDV 7 Clock rising edge to input data valid 5tCLCL−55 - 361 - 5tCLCL−35 - 173 ns SPI Interface fSPI tSPICYC MHz 8, 9, 10, 11 - - - - - - - - 0 2.0 0 2.0 0 2.0 0 2.0 - - - - - - - - 0 3.0 0 3.0 0 3.0 0 3.0 2.0 MHz (Master) - - - - - - - - 2.0 MHz (Slave) 500 - 500 - 500 - 500 - 3.0 MHz (Master) - - - - - - - - 3.0 MHz (Slave) 333 - 333 - 333 - 333 - Cycle time ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 20 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family Table 8: Dynamic characteristics…continued Tamb = 0 to +70 °C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Fig Parameter 2.7 V < VDD < 5.5 V Variable Min tSPILEAD 10, 11 tSPILAG 10, 11 tSPICLKH 8, 9, 10, 11 tSPICLKL 8, 9, 10, 11 clock[4] Max 4.5 V < VDD < 5.5 V fOSC = 12 MHz[4] Variable Min Max Min clock[4] Max Unit fOSC = 24 MHz[4] Min Max Enable lead time (Slave) ns 2.0 MHz 250 - 250 - 250 - 250 - 3.0 MHz 240 - 240 - 240 - 240 - Enable lag time (Slave) ns 2.0 MHz 250 - 250 - 250 - 250 - 3.0 MHz 240 - 240 - 240 - 240 - SPICLK HIGH time ns Master 340 - 340 - 340 - 340 - Slave 190 - 190 - 190 - 190 - SPICLK LOW time ns Master 340 - 340 - 340 - 340 - Slave 190 - 190 - 190 - 190 - tSPIDSU 8, 9, 10, 11 Data setup time 100 (Master or Slave) - 100 - 100 - 100 - ns tSPIDH 8, 9, 10, 11 Data hold time 100 (Master or Slave) - 100 - 100 - 100 - ns tSPIA 10, 11 Access time (Slave) 120 0 120 0 120 0 120 ns tSPIDIS 10, 11 Disable time (Slave) tSPIDV tSPIOH 8, 9, 10, 11 8, 9, 10, 11 0 ns 2.0 MHz 0 240 - 240 0 240 - 240 3.0 MHz 0 167 - 167 0 167 - 167 Enable to output data valid ns 2.0 MHz - 240 - 240 - 240 - 240 3.0 MHz - 167 - 167 - 167 - 167 0 - 0 - 0 - 0 - Output data hold time © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data ns Rev. 02 — 19 May 2003 21 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family Table 8: Dynamic characteristics…continued Tamb = 0 to +70 °C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Fig Parameter 2.7 V < VDD < 5.5 V Variable tSPIR tSPIF [1] [2] [3] [4] 8, 9, 10, 11 8, 9, 10, 11 clock[4] 4.5 V < VDD < 5.5 V fOSC = 12 MHz[4] Variable clock[4] Unit fOSC = 24 MHz[4] Min Max Min Max Min Max Min Max SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 - 100 - 100 SPI outputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 - 2000 - 2000 Rise time ns Fall time ns SPI outputs (SPICLK, MOSI, MISO) - 100 - 100 - SPI outputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 - 100 - 100 2000 - 2000 Parameters are valid over operating temperature range unless otherwise specified. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 22 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 11.1 Explanation of AC symbols Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A — Address C — Clock D — Input data H — Logic level HIGH I — Instruction (program memory contents) L — Logic level LOW, or ALE P — PSEN Q — Output data R — RD signal t — Time V — Valid W — WR signal X — No longer a valid logic level Z — Float Examples: tAVLL — Time for address valid to ALE LOW tLLPL — Time for ALE LOW to PSEN LOW © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 23 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family tLHLL ALE tLLPL tPLPH tLLIV tPLIV PSEN tAVLL tLLAX PORT 0 tPLAZ tPXIZ tPXIX INSTR IN A0-A7 A0-A7 tAVIV1 tAVIV PORT 2 P2.0-P2.7 OR A8-A15 P2.0-P2.7 OR A8-A15 OR A16-A22,P2.7 002aaa150 Fig 4. External program memory read cycle (extended memory cycle). ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tLLAX tRLAZ tAVLL PORT 0 tRHDZ tRHDX DATA in A0-A7 tAVWL A0-A7 FROM PCL INSTR IN tAVWL1 tAVDV1 tAVDV PORT 2 P2.0-P2.7 OR A8-A15 P2.0-P2.7 OR A8-A15 OR A16-A22,P2.7 002aaa151 Fig 5. External data memory read cycle (non-extended memory cycle). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 24 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family ALE tWHLH PSEN tLLWL tWLWH WR tLLAX tQVWX tAVLL PORT 0 tWHQX tQVWH DATA OUT A0-A7 INSTR IN A0-A7 FROM PCL tAVWL1 tAVWL PORT 2 P2.0-P2.7 OR A8-A15 P2.0-P2.7 OR A8-A15 OR A16-A22,P2.7 002aaa153 Fig 6. External data memory write cycle (non-extended memory cycle). INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 3 4 5 6 7 WRITE TO SBUF tXHDX SET TI tXHDV INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI 002aaa155 Fig 7. Shift register mode timing. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 25 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family SS tCLCL tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKL tSPIR tSPIR tSPICLKL tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in MSB/LSB in tSPIDV MOSI (output) tSPIDV tSPIOH tSPIR tSPIF Master MSB/LSB out Master LSB/MSB out 002aaa156 Fig 8. SPI master timing (CPHA = 0). SS tCLCL tSPIF SPICLK (CPOL = 0) (output) tSPICLKL tSPIF tSPIR tSPICLKH tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH tSPIDV MOSI (output) LSB/MSB in MSB/LSB in tSPIOH tSPIDV tSPIDV tSPIR tSPIF Master MSB/LSB out Master LSB/MSB out 002aaa157 Fig 9. SPI master timing (CPHA = 1). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 26 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family SS tSPIR tSPILEAD tSPIF tSPICLKH SPICLK (CPOL = 0) (input) tSPIF tSPIR tCLCL tSPICLKL tSPIR tSPILAG tSPIR tSPICLKL tSPICLKH SPICLK (CPOL = 1) (input) tSPIOH tSPIA MISO (output) tSPIDV tSPIDIS tSPIDV Slave MSB/LSB out tSPIDSU MOSI (input) tSPIOH tSPIOH tSPIDH Slave LSB/MSB out tSPIDSU tSPIDSU MSB/LSB in Not defined tSPIDH LSB/MSB in 002aaa158 Fig 10. SPI slave timing (CPHA = 0). SS tSPIR tSPILEAD tSPIF tSPICLKH SPICLK (CPOL = 0) (input) tSPIF tSPIR tCLCL tSPICLKL tSPICLKL tSPIR tSPILAG tSPIR tSPICLKH SPICLK (CPOL = 1) (input) tSPIOH tSPIOH tSPIDV tSPIDV tSPIOH tSPIDIS tSPIDV tSPIA MISO (output) Not defined tSPIDSU MOSI (input) Slave LSB/MSB out Slave MSB/LSB out tSPIDH tSPIDSU MSB/LSB in tSPIDSU tSPIDH LSB/MSB in 002aaa159 Fig 11. SPI slave timing (CPHA = 1). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 27 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family VDD -0.5 V 0.45 V 0.7 VDD 0.2 VDD -0.1 V tCHCX tCHCL tCLCX tCLCH tCLCL 002aaa160 Fig 12. External clock drive. VDD VDD ICC RST VDD VDD P0 EA (NC) XTAL2 CLOCK SIGNAL XTAL1 VSS 002aaa161 Fig 13. ICC test condition, active mode (all other pins are disconnected). VDD ICC RST VDD VDD P0 EA (NC) XTAL2 CLOCK SIGNAL XTAL1 VSS 002aaa162 Fig 14. ICC test condition, idle mode (all other pins are disconnected). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 28 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family VDD -0.5 V 0.7 VDD 0.2 VDD -0.1 V 0.45 V tCHCL tCHCX tCLCX tCLCH tCLCL 002aaa163 Fig 15. Clock signal waveform for ICC tests in active and idle modes (tCLCH = tCHCL = 5 ns). VDD ICC RST VDD VDD P0 EA (NC) XTAL2 XTAL1 VSS 002aaa164 Fig 16. ICC test condition, power-down mode (all other pins are disconnected, VDD = 2.0 V to 5.5 V). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 29 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 12. Package outline PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 β 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A A3 D(1) E(1) e eD eE HD bp b1 max. min. 4.57 4.19 mm 0.51 0.180 inches 0.02 0.165 0.53 0.33 0.81 0.66 HE k 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.25 3.05 0.01 0.021 0.032 0.656 0.656 0.05 0.12 0.013 0.026 0.650 0.650 0.63 0.59 0.63 0.59 Lp v w y 1.44 1.02 0.18 0.18 0.1 ZD(1) ZE(1) max. max. 2.16 β 2.16 45 o 0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT187-2 112E10 MS-018 EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 17. SOT187-2. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 30 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended. 13.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 220 °C (SnPb process) or below 245 °C (Pb-free process) – for all the BGA packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 31 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 13.5 Package related soldering information Table 9: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Reflow[2] Wave BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[3] suitable PLCC[4], SO, SOJ suitable suitable LQFP, QFP, TQFP not SSOP, TSSOP, VSO, VSSOP not recommended[6] [1] [2] suitable suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data recommended[4][5] Rev. 02 — 19 May 2003 32 of 36 Philips Semiconductors P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family [3] [4] [5] [6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 33 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 14. Revision history Table 10: Revision history Rev Date 02 20030519 CPCN Description - Product data (9397 750 11517); ECN 853-2426 29927; supersedes Preliminary specification P87C51Mx2_1 of 2001 Apr 06 (9397 750 08199) Modifications: _1 20010406 - • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • • MXCON, IEN1, IP1, IP1H and T2MOD registers updated. PCONA, SPICTL, SPCFG and SPDAT registers added. AC characteristics updated. Preliminary specification (9397 750 08199) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Product data Rev. 02 — 19 May 2003 34 of 36 P87C51MB2/P87C51MC2 Philips Semiconductors 80C51 8-bit microcontroller family 15. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11517 Rev. 02 — 19 May 2003 35 of 36 Philips Semiconductors P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family Contents 1 2 2.1 2.2 2.3 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Complete features . . . . . . . . . . . . . . . . . . . . . . 2 Differences between P87C51MX2/02 part and previous revisions of P87C51MX2 . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 10 Memory arrangement . . . . . . . . . . . . . . . . . . . 10 Special Function Registers . . . . . . . . . . . . . . . 10 Security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Static characteristics. . . . . . . . . . . . . . . . . . . . 16 Dynamic characteristics . . . . . . . . . . . . . . . . . 18 Explanation of AC symbols. . . . . . . . . . . . . . . 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 32 Package related soldering information . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 34 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 35 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 19 May 2003 Document order number: 9397 750 11517