PI49FCT3802/PI49FCT3803 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:5/1:7 Clock Buffer for Networking Applications Product Features Description High Frequency >156 MHz The PI49FCT380x is a 3.3V compatible, high-speed, low-noise non-inverting clock buffer. The key goal in designing the PI6C380x is to target networking applications that require low-skew, lowjitter, and high-frequency clock distribution. Providing output-to-output skew as low as 250ps, the PI49FCT380x is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs. High-speed, low-noise, non-inverting buffer - PI49FCT3802 is 1:5 buffer - PI49FCT3803 is 1:7 buffer Low-skew (<250ps) between any two output clocks Low duty cycle distortion <250ps Low propagation delay <2.5ns 5V Tolerant input Product Pin Description Multiple VDD, GND pins for noise reduction Pin Name 3.3V supply voltage Packages Available: - TSSOP and QSOP Pin Configuration (PI49FCT3802) 1 16 VDD GND 2 15 CLK4 CLK0 3 14 CLK3 4 CLK1 16-Pin L, Q PI49FCT3803 BUF_IN CLK [0:4] GND VDD BUF_IN CLK [0:6] GND VDD D e s cription Input O utputs GND Power Block Diagram (PI49FCT3802) BUF_IN VDD PI49FCT3802 CLK0 CLK1 BUF_IN 13 GND 5 12 CLK2 GND 6 11 VDD NC 7 10 NC VDD 8 9 CLK2 CLK3 GND CLK4 Pin Configuration (PI49FCT3803) Block Diagram (PI49FCT3803) CLK0 BUF_IN 1 16 VDD GND 2 15 CLK6 CLK0 3 14 CLK5 VDD 4 13 GND CLK4 16-Pin L, Q CLK1 CLK1 5 12 GND 6 11 VDD CLK2 7 10 CLK3 VDD 8 9 GND BUF_IN CLK2 CLK3 CLK6 1 PS8559 08/09/01 PI49FCT3802/PI49FCT3803 1:5/1:7 Clock Buffers for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... 65°C to +150°C VDD Voltage ............................................................................. 0.5V to 5.5V Output Voltage ......................................................................... 0.5V to 5.5V Input Voltage ........................................................................... 0.5V to 5.5V DC Output Current ............................................................. 60mA to +60mA Power Dissipation ............................................................................. 500mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range VDD Voltage ................................................................................. 3.3V ± 0.3V Commercial Temperature ........................................................... 0°C to +70°C Industrial Temperature .......................................................... 40°C to +85°C Input Frequency .................................................................... DC to 156 MHz Capacitive Loading ................................................................... 10pF to 50pF DC Electrical Characteristics (Over the Operating Range) M in. Typ.(2) M ax. Guaranteed Logic HIGH Level (Input Pins) 2.0 5.5 Input LOW Voltage Guaranteed Logic LOW Level (Input Pins) 0.5 0.8 IIH Input HIGH Current VDD = Max. VIN = VDD 1 IIL Input LOW Current VDD = Max. VIN = GND 1 VIK Clamp Diode Voltage VDD = Min., IIN = 18mA 0.7 1.2 VOH Output HIGH Voltage VDD = Min., VIN = VIH or VIL IOH = 0.1mA VDD 0.2 IOH = 12mA 2.4(3) 3.0 VOL Output LOW Voltage VDD = Min., VIN = VIH or VIL IOL = 0.1mA 0.2 IOL = 12mA 0.3 0.5 IOH Output HIGH Current VDD = 3.0V, VIN = VIH or VIL, VOUT = 1.5V(4) 45 75 180 IOL Output LOW Current VDD = 3.0V, VIN = VIH or VIL, VOUT = 1.5V(4) 50 92 200 Parame te rs De s cription VIH Input HIGH Voltage VIL Te s t Conditions (1) Units V µA V mA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VDD = 3.3V, +25°C ambient and maximum loading. 3. VOH = VDD 0.6V at rated current. 4. This parameter is determined by device characterization but is not production tested. 5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 2 PS8559 08/09/01 PI49FCT3802/PI49FCT3803 1:5/1:7 Clock Buffers for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Parame te rs Te s t Conditions (1) De s cription M in. Typ.(2) M ax. IDDQ Quiescent Power Supply Current VDD = Max. VIN = GND or VDD 0.1 30 ∆IDD Supply Current per Inputs @ TTL HIGH VDD = Max. VIN = VDD 0.6V(3) 47 300 50 MHz 43 67 MHz 56 80 MHz 66 100 MHz 81 125 MHz 97 156 MHz 121 IDD VDD = 3.6V, No Load Dynamic Supply Current Units µA mA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VDD = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VDD 0.6V); all other inputs at VDD or GND. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. CIN Input Capacitance VIN = 0V 3.0 4 C OUT Output Capacitance VOUT = 0V 6 Units pF Note: 1. This parameter is determined by device characterization but is not production tested. Switching Characteristics (VDD = 3.3V ± 0.3V, TA = 85°C) Parame te rs D e s cription Te s t Conditions (1) M in. Typ. M ax. tR/tF CLK n Rise/Fall Time 0.8V~2.0V CL = 15pF, 125 MHz 0.7 1.0 tPLH tPHL Propagation Delay BUF_IN to CLK n CL = 15pF, 125 MHz 1.0 2.2 2.5 tSK(o)(3) Skew between two outputs of the same package (same transition) CL = 15pF, 125 MHz 110 250 tSK(p)(3) Skew between opposite transitions (tPHL- tPLH) of the same output CL = 15pF, 125 MHz 200 250 tSK(t)(3) Skew between two outputs of different package (4) CL = 15pF, 125 MHz 0.55 Units ns ps ns Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worse cast temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 3 PS8559 08/09/01 PI49FCT3802/PI49FCT3803 1:5/1:7 Clock Buffers for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms Propagation Delay Pulse Skew tSK(P) 3V 3V Input Input 1.5V 0V 0V tPLH 1.5V tPLH tPHL tPHL VOH VOH 2.0V Output Output 1.5V 1.5V 0.8V VOL VOL tR tF tSK(p) = | tPHL – tPLH | Package Skew tSK(T) Output Skew tSK(O) 3V 3V Input Input 1.5V 1.5V 0V 0V tPLH1 tPHLx tPLHx tPHL1 VOH VOH CLKx Package 1 Output 1.5V 1.5V VOL VOL tSK(o) tSK(t) tSK(o) tSK(t) VOH VOH CLKy Package 2 Output 1.5V 1.5V VOL VOL tPLHy tPLH2 tPHLy tSK(o) = tPLHy tPLHx or tPHLy tPHLx tPHL2 tSK(t) = tPLH2 – tPLH1 or tPHL2 – tPHL1 Test Circuits for All Outputs VDD VIN Pulse Generator VOUT D.U.T. CL Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance, should be equal to Zout of the Pulse Generator. 4 PS8559 08/09/01 PI49FCT3802/PI49FCT3803 1:5/1:7 Clock Buffers for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 16-Pin QSOP (Q) Package 16 .008 0.20 MIN. .150 .157 .008 .013 0.20 0.33 3.81 3.99 Guage Plane .010 0.254 1 Detail A .189 .197 4.80 5.00 .041 1.04 REF .015 x 45° 0.38 .008 0.203 REF .053 1.35 .069 1.75 Detail A .008 .012 0.203 0.305 .007 .010 0.178 0.254 0.41 .016 1.27 .050 SEATING PLANE .025 BSC 0.635 0˚-6˚ .016 .035 0.41 0.89 .228 .244 5.79 6.19 .004 0.101 .010 0.254 X.XX DENOTES DIMENSIONS IN MILLIMETERS X.XX 16-Pin TSSOP (L) Package 16 .169 .177 4.3 4.5 1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 0.45 .018 0.75 .030 SEATING PLANE .0256 BSC 0.65 .007 .012 .002 .006 0.09 0.20 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 0.19 0.30 Ordering Information Orde ring Code Package Type PI49FCT3802Q 16- pin 150 mil wide Q SO P PI49FCT3802L 16- pin 173 mil wide TSSO P PI49FCT3803Q 16- pin 150 mil wide Q SO P PI49FCT3803L 16- pin 173 mil wide TSSO P Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8559 08/09/01