XRD87L94 CMOS, 1 MSPS, 12-Bit Analog-to-Digital Converter with Parallel Logic Interface Port ...the analog plus company TM March 1996-3 FEATURES APPLICATIONS 12-Bit ADC with DNL = +1 LSB, INL = +2.5 LSB SNR > 60 dB Sampling Frequency < 1 MHz Single 3.3 V Supply Rail-to-Rail Input Range VREF Range: 1.5 V to VDD CMOS Low Power: 30 mW (typ) 1/4, 1/2 and 3/4 Scale Reference Resistor Taps Three-State Outputs Binary and Two’s Complement Digital Output Mode Latch-Up Proof ESD: 2000 V Minimum Protection Scanners Digital Cameras Instrumentation Medical Imaging Digital Oscilloscopes Spectrum Analysis reference ladder terminals and power supplies allow flexibility for various AIN, VREF, and power supply ranges. GENERAL DESCRIPTION The XRD87L94 is a 1 MSPS 12-bit subranging Analog-to-Digital Converter with DNL = +1 LSB and INL = +2.5 LSB. The XRD87L94 contains an internal track and hold and an analog input bandwidth of 10 MHz. Data is presented at the parallel output port every clock cycle after a 2.5 cycle pipeline delay from sample edge. The digital output port is also equipped with a 3-state function. MINV enables binary and 2’s complement data formatting. Through pins R1-R3, transfer function adjustment can be accommodated. The XRD87L94 operates with a single 3.3 V supply while consuming 30 mW of power (typical). Separate pins for SIMPLIFIED BLOCK DIAGRAM MINV AIN VRT n1 3 R1-R3 n Fine Comp. n1 S/H n2 Coarse Comp. n2 L A T C H 11 m R O M 1 L A T C H 12 12 DB0-DB11 VRB Aperture OE CLK 3 3 AVDD AGND Clock Logic Rev. 1.00 1996 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 XRD87L94 ORDERING INFORMATION Temperature Range Part No. DNL (LSB) INL (LSB) PDIP –40 to +85°C XRD87L94AIP 1 2.5 SOIC (EIAJ) –40 to +85°C XRD87L94AIK 1 2.5 SOIC (Jedec) –40 to +85°C XRD87L94AID 1 2.5 Package Type PIN CONFIGURATIONS DB11 AGND AIN AVDD R2 R3 R1 VREFB VREFT AVDD AGND MINV DB0 DB1 See Packaging Section for Package Dimensions 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DB10 DB9 DB8 DB7 DB6 CLK OE Aperture AGND AVDD DB5 DB4 DB3 DB2 DB11 AGND AIN AVDD R2 R3 R1 VREFB VREFT AVDD AGND MINV DB0 DB1 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DB10 DB9 DB8 DB7 DB6 CLK OE Aperture AGND AVDD DB5 DB4 DB3 DB2 28 Pin SOP (EIAJ, 8.4mm) 28 Pin SOIC (Jedec, 0.300”) 28 Pin PDIP (0.600”) PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION Data Output Bit 11 (MSB) 15 DB2 Data Output Bit 2 AGND Analog Ground 16 DB3 Data Output Bit 3 AIN Analog Input 17 DB4 Data Output Bit 4 4 AVDD Analog Positive Supply 18 DB5 Data Output Bit 5 5 R2 Ref. Resistor Ladder Tap (1/2 VREF) 19 AVDD Digital Positive Supply 6 R3 Ref. Resistor Ladder Tap (3/4 VREF) 20 AGND Digital Negative Supply 7 R1 Ref. Resistor Ladder Tap (1/4 VREF) 21 Aperture Delayed Clock, indicates sample point 1 DB11 2 3 8 VREFB Negative Reference 22 OE Output Enable (Active Low) 9 VREFT Positive Reference 23 CLK Clock 10 AVDD Analog Positive Supply 24 DB6 Data Output Bit 6 11 AGND Analog Ground 25 DB7 Data Output Bit 7 12 MINV Invert MSB (Active High) 26 DB8 Data Output Bit 8 13 DB0 Data Output Bit 0 (LSB) 27 DB9 Data Output Bit 9 14 DB1 Data Output Bit 1 28 DB10 Data Output Bit 10 Rev. 1.00 2 XRD87L94 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: AVDD = DVDD = 3.3 V, FS = 1 MHz (50% Duty Cycle), VREF(+) = 3.0 V, VREF(–) = AGND, TA = 25°C Parameter Symbol Min 25°C Typ Max Units Test Conditions/Comments KEY FEATURES Resolution Sampling Rate FS 12 1 Bits MHz Differential Non-Linearity Integral Non-Linearity DNL INL +1 +2.5 LSB LSB Zero Scale Error Full Scale Error EZS EFS ACCURACY1 +10 –10 Best Fit Line (Max INL – Min INL)/2 LSB LSB REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage3 Ladder Resistance VREF(+) VREF(–) VREF RL 1.5 AGND 1.5 AVDD AVDD 550 V V V Ω Functional ANALOG INPUT Input Bandwidth (–3 dB)4 Input Voltage Range Input Capacitance Sample5 Input Capacitance Convert5 Aperture Delay from Clock Aperture Delay from Aperture Signal BW VIN CIN 3 VREF(–) VREF(+) 50 8 55 0 tAP tAP MHz V p-p pF pF ns ns Aperture pin load 5 pF. Measured at 50% point. DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Leakage Currents 6 CLK, OE, MINV Input Capacitance Clock Timing Clock Period Rise & Fall Time7 “High” Time “Low” Time Duty Cycle VIH VIL IIN tS tR, tF tPWH tPWL 2.5 0.5 0.4 V V 10 5 µA pF 1 15 500 500 50 µs ns ns ns % Functional Functional Functional Functional COUT=15 pF DIGITAL OUTPUTS Logical “1” Voltage Logical “0” Voltage 3-state Leakage Data Enable Delay Data 3-state Delay Data Valid Delay Data Invalid Delay VIN=DGND to DVDD VOH VOL IOZ tDEN tDHZ tDV tDI VDD-0.5 0.5 1 60 60 115 115 Rev. 1.00 3 V V µA ns ns ns ns ILOAD = 1 mA ILOAD = 1 mA VOUT=DGND to DVDD OE = 0 OE = 0 XRD87L94 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Parameter Symbol Min 25°C Typ Max Units Test Conditions/Comments POWER SUPPLIES8 (Tmin to Tmax) Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) VDD IDD 3.3 SNR 60 12 V mA AC PARAMETERS Signal Noise Ratio (N+D) dB FIN = 100 kHz NOTES Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width (VREF/4096) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage. Accuracy is a function of the sampling rate (FS). 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 –3 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 Switched capacitor analog input requires driver with low output resistance. 6 All inputs have diodes to DVDD and DGND. Input(s) OE and MINV have internal pull down(s). Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD. 7 Condition to meet aperture delay specifications (tAP, tAJ). Actual rise/fall time can be less stringent with no loss of accuracy. 8 AGND & DGND pins are connected through the silicon substrate. 1 Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Storage Temperature . . . . . . . . . . . . . . –65 to +150°C VREF(+) & VREF(–) . . . . . . . . . VDD +0.5 to GND –0.5 V Lead Temperature (Soldering 10 seconds) . . . . . . . . . . . . . . . . . . +300°C VIN . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5 V Package Power Dissipation Rating @ 75°C PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . 14mW/°C All Inputs . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5 V All Outputs . . . . . . . . . . . . . . VDD +0.5 to GND –0.5 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 1.00 4 XRD87L94 1/FS tPWL tPWH N+1 CLK N+2 Aperture Pipeline Delay tAP Analog Input VIN N+2 N+1 N N+3 Sampling Points DATA (DB0-DB11) N–3 N–2 N N–1 tDV tDI Figure 1. Timing Diagram with OE = 0 tDV = tAP + tDEN tDI = tAP + tDHz CLK OE tDHZ tDEN DATA (DB0-DB11) High Impedance Figure 2. 3-State Timing Diagram Data 12 Tri-State Buffer 12 OE CLK Delay 12 Aperture Figure 3. Block Diagram of the XRD87L94 Output Rev. 1.00 5 Data Out XRD87L94 OVERVIEW OF THE XRD87L94 PINS & OPERATION NOTES MINV DB11 D OE: Output Enable (Input) D Q Q latch latch EN EN 3-state driver CLK This signal controls the 3-state drivers on the digital outputs DB0 - DB11 as shown in Figure 2. During normal operation, OE should be held low so that all outputs are enabled (NOTE: an internal resistor will pull OE to this level if it is not connected). When OE is driven high, DB0 - DB11 goes into high impedance mode. This control operates asynchronously to the clock and only controls the output drivers. The internal output register will get updated if the clock is running while the outputs are in 3-state mode. The aperture and OE signals are internally combined to enable the output data. If aperture is high, the output data bits are tri-stated, independent of OE. Figure 3. shows the circuit used to tri-state the output. This will reduce the errors introduced by digital output coupling during the AIN sample time. Figure 4. MINV Simplified Logic Circuit VIN Analog Input This part has a switched capacitor type input circuit. This means that the input impedance changes with the phase of the input clock. VIN is sampled at the high to low clock transition. The diagram Figure 5. shows an equivalent input circuit. AVDD 50Ω APERTURE: Aperture Delay Sync (Output) CL 41pF 50Ω VIN This signal is high when the internal sample/hold function is sampling VIN, and goes low when it is in the hold mode (when the ADC is comparing the stored input value to the reference ladder). The value of VIN at the high to low transition of APERTURE is the value that will be digitized. A system can monitor this signal and adjust the CLK to accurately synchronize the sampling point to an external event. The aperture and OE signals are internally combined to enable the output data. If aperture is high, the output data bits are tri-stated, independent of OE. This will reduce the errors introduced by digital output coupling during the AIN sample time. AGND 8pF VRT + VRB + − 2 CL 1.5pF CL CL at PHASE = 1 Figure 5. Equivalent Input Circuit R1, R2, R3: Reference Ladder Taps These taps connect to every 1/4 point along the reference ladder; R1 is 1/4th up from VRB, R3 is 3/4ths up from VRB (or 1/4th down from VRT). Normally these pins should have 0.1 microfarad capacitors to VSS; this helps reduce the INL errors by stabilizing the reference ladder voltages. MINV: Digital Output Format (Input) This signal controls the format of the digital output data bits DB0 – DB11. Normally it is held low so the data is in straight binary format (all 0’s when VIN = VRB; all 1’s when VIN = VRT). If MINV is pulled high then the MSB (DB11) will be inverted. These taps can also be used to alter the transfer curve of the ADC. A 4-segment, piecewise linear, custom transfer curve can be designed by connecting voltage sources to these pins. This may be desirable to make the probability of codes for a certain range of VIN be enhanced or minimized. MINV is meant to be a static digital signal. If it is to change during operation, it should only change when the CLK is low. Changing MINV on the wrong phase of the CLK will not hurt anything, but the effects on the digital outputs will not be seen until the output latch of the output register is enabled. MINV has an internal pull down device. Sometimes this is referred to as probability density function shaping, or histogram shaping. The internal interconnect resistance from each of the tAP pins to the ladder is less than 3Ω. Rev. 1.00 6 XRD87L94 1.6V maximum per tap is recommended for applications above 85°C. Up to 3.2V is allowed for applications under 85°C. V4 DAC4 VRT V3 4095 R3 DAC3 V2 R2 XRD87L94 DAC2 3072 V1 V4 R1 DAC1 DAC MP7226 Digital Code 2048 VRB V3 V2 1024 Only the Ladder detail shown. V1 0 0.5 V 1V VIN 2V Figure 7. A/D with Programmed Ladder Control for Creating a Piecewise Linear Transfer Function 3V Figure 6. A Piecewise Linear Transfer Function Rev. 1.00 7 XRD87L94 PERFORMANCE CHARACTERISTICS Graph 1. INL Graph 2. INL vs. Sampling Frequency Graph 3. DNL Graph 4. DNL vs. Sampling Frequency Graph 5. DNL vs. Reference Voltage Rev. 1.00 8 Graph 1. IDD vs. Sampling Frequency XRD87L94 Figure 8. XRD8794AB Schematic Rev. 1.00 9 XRD87L94 28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) 28 15 E1 1 14 E D Seating Plane A2 A L A1 α C B B1 e INCHES SYMBOL eA eB MILLIMETERS MIN MAX MIN A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.380 1.565 35.05 39.75 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e eA 0.100 BSC 0.600 BSC MAX 2.54 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 α 0° 15° 0° Note: The control dimension is the inch column 15° Rev. 1.00 10 XRD87L94 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) D 28 15 E H 1 14 C A Seating Plane α B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 e 0.050 BSC MAX 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° Note: The control dimension is the millimeter column Rev. 1.00 11 XRD87L94 28 LEAD SMALL OUTLINE (8.4 mm EIAJ SOP) D 28 15 E 1 H 14 C A2 Seating Plane A α e B A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.098 0.114 2.50 2.90 A1 0.004 0.012 0.10 0.30 A2 0.094 0.102 2.40 2.60 B 0.012 0.020 0.30 0.50 C 0.004 0.008 0.10 0.20 D 0.693 0.713 17.60 18.10 E 0.327 0.335 8.30 8.50 e 0.050 BSC MAX 1.27 BSC H 0.453 0.477 11.50 12.10 L 0.028 0.051 0.70 1.30 α 0° 10° 0° 10° Note: The control dimension is the millimeter column Rev. 1.00 12 XRD87L94 Notes Rev. 1.00 13 XRD87L94 Notes Rev. 1.00 14 XRD87L94 Notes Rev. 1.00 15 XRD87L94 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1996 EXAR Corporation Datasheet March 1996 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 16