XRD6406 CMOS 6 MSPS, 10-Bit, High Speed Analog-to-Digital Converter FEATURES · · · · · · · · · · · June 1998-2 APPLICATIONS 10-Bit Resolution Sampling Rate to 6 MSPS DNL = +1 LSB, INL = +2 LSB Internal S/H Function Single 5V Power Supply VIN DC Range: 0V to VDD VREF DC Range: 1V to VDD Low Power: 65mW Three-State Digital Outputs Latch-Up Free Pin Compatible With: MP8784 · Digital Color Copiers · Precision CCDs and Scanners · Digital Radio BENEFITS · · · · GENERAL DESCRIPTION The XRD6406 is a 10-bit, 6 MSPS, Analog-to-Digital Converter for applications that require high speed and high accuracy. Designed using an advanced CMOS process, this part offers excellent performance, low power consumption and latch-up free operation. The XRD6406 uses a subranging architecture to maintain low power consumption at high conversion rates. Our proprietary comparator design achieves a low analog input capacitance. The input circuitry of the XRD6406 includes an on-chip S/H function that allows this part to digitize analog input signals between AGND and AVDD. Simplified Analog Design Rugged Few External Components, no S/H Needed Reduced Board Space The designer can choose the internally generated reference voltages, or provide external reference voltages to the VRB and VRT pins. The internal reference generates 1.0V at VRB and 4V at VRT. Providing external reference voltages allows easy interface to any input signal range between GND and VDD. This also allows the system to cancel zero scale and full scale errors. The Reference Ladder taps (R1 to R3) can be used to externally trim any INL errors. This device operates from a single 5V supply. Power consumption from a 5V supply is typically 65mW at FS=6MHz. SIMPLIFIED BLOCK DIAGRAM AVDD AGND VDD MSB Comparators VRTS VRT R1-R3 DB9 (MSB) Latch Encoder 3 LSB Comparators F/F Latch DB0 (LSB) VRB VRBS S/H VIN Clock Logic CLK OE DVDD DGND Rev. 1.00 E1998 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017 XRD6406 ORDERING INFORMATION Part No. DNL (LSB) INL (LSB) --40 to +85°C XRD6406AIP ¦1 ¦2 --40 to +85°C XRD6406AID ¦1 ¦2 Package Type Temperature Range Plastic Dip SOIC PIN CONFIGURATIONS OE DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 (MSB) CLK See Packaging Section for Package Dimensions 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 (MSB) CLK DGND VRB VRBS R1 AGND VIN AVDD R2 R3 VRT VRTS DVDD 24 Pin PDIP (0.300”) 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DGND VRB VRBS R1 AGND VIN AVDD R2 R3 VRT VRTS DVDD 24 Pin SOIC (Jedec, 0.300”) PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. 13 NAME 1 OE Output Enable 2 DB0 Data Output Bit 0 (LSB) 14 VRTS Top Internal Reference 3 DB1 Data Output Bit 1 15 VRT Top of Reference 4 DB2 Data Output Bit 2 16 R3 3/4 Reference Tap Point 5 DB3 Data Output Bit 3 17 R2 1/2 Reference Tap Point 6 DB4 Data Output Bit 4 18 AVDD Analog Power Supply 7 DB5 Data Output Bit 5 19 VIN Analog Input Voltage 8 DB6 Data Output Bit 6 20 AGND Analog Ground 9 DB7 Data Output Bit 7 21 R1 1/4 Reference Tap Point 10 DB8 Data Output Bit 8 22 VRBS Bottom Internal Reference 11 DB9 Data Output Bit 9 (MSB) 23 VRB Bottom of Reference 12 CLK Clock Input 24 DGND Digital Ground Rev. 1.00 2 DVDD DESCRIPTION Digital Power Supply XRD6406 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: AVDD = DVDD = 5V, FS = 6MHz (50% Duty Cycle), VRT = 4.0, VRB = 1.0, TA = 25°C Parameter Symbol Min FS 10 6 25°C Typ Max Units Test Conditions/Comments KEY FEATURES Resolution Maximum Sampling Rate Bits MHz ACCURACY (A Grade)1 Differential Non-Linearity Integral Non-Linearity DNL INL Zero Scale Error Gain Error EZS EFS +1 +2 10 6 LSB LSB LSB LSB Best Fit Line (Max INL -- Min INL)/2 REFERENCE VOLTAGES Positive Ref. Voltage2,3 Negative Ref. Voltage2,3 Differential Ref. Voltage2,3 Ladder Resistance Ladder Temp. Coefficient2 Top Internal Reference Bottom Internal Reference VRT VRB VREF RL RTCO VRTS VRBS AGND 1.0 AVDD 1400 2000 4 1 AVDD V V V W ppm/°C V V VREF = VRT -- VRB VRT connected to VRTS & VRB connected to VRBS ANALOG INPUT Input Bandwidth (--1 dB)2,4 Input Voltage Range Input Capacitance (Sample)2,5 Input Capacitance (Convert)2,5 Aperture Delay2 Aperture Uncertainty 2 (Jitter) BW VIN CIN VRB tAP tAJ 25 25 7 25 50 VRT 40 12 30 MHz V pF pF ns ps DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage DC Leakage Currents2,6 CLK OE Input Capacitance2 Clock Timing (See Figure 1) Clock Period2 Rise & Fall Time2,7 “High” Pulse Width2,3 “Low” Pulse Width2,3 Duty Cycle2,3 VIH VIL IIN 4 1/FS tR, tF tPWH tPWL 1 V V 5 5 5 mA mA pF 167 2 84 84 50 ns ns ns ns % DIGITAL OUTPUTS Logical “1” Voltage Logical “0” Voltage 3-state Leakage Data Valid Delay Data Enable Delay Data 3-state Delay VIN=DGND to DVDD COUT=15 pF VOH VOL IOZ tDL tDEN tDHZ 4.5 10 40 25 25 Rev. 1.00 3 0.4 45 30 30 V V mA ns ns ns ILOAD = 4mA ISINK = 4mA VOUT=DGND to DVDD XRD6406 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Description Symbol Min VDD IDD 4.5 25°C Typ Max 5 13 5.5 17 Units Conditions POWER SUPPLIES Operating Voltage (AVDD, DVDD)8, 9 Current (AVDD + DVDD) V mA Notes: 1 Tester measures code transitions by dithering the voltage of the analog input (VIN ). The difference between the measured and the ideal code width (VREF /1024) is the DNL error (Figure 3.). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4.). Accuracy is a function of the sampling rate (FS). 2 Guaranteed. Not tested. 3 Specified values guarantee functionality, but INL & DNL specifications may not be met. 4 --1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 See VIN equivalent circuit (Figure 8.). Switched capacitor analog input requires driver with low output resistance. 6 All inputs have diodes to DVDD and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD . 7 Condition to meet aperture delay specifications (tAP, tAJ ). Actual rise/fall time can be less stringent with no loss of accuracy. 8 The AGND & DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane. 9 The AVDD & DVDD pins should be tied together at the package. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V VRT & VRB . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5V All Inputs . . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5V All Outputs . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5V Storage Temperature . . . . . . . . . . . . . . . . . . . --65 to +150°C Package Power Dissipation Rating to 75°C PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . . 14mW/°C Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C Notes 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. 3 VDD refers to AVDD and DVDD . GND refers to AGND and DGND. Rev. 1.00 4 XRD6406 1/FS tPWH tPWL N+1 CLK N+2 Pipeline Delay tAP DATA (DB0-DB9) N+1 N Analog Input VIN N+2 N+3 Sampling Points N -- 3 tDL N -- 2 N -- 1 N Figure 1. XRD6406 Timing Diagram OE tDHZ DATA (DB0-DB9) High Impedance Figure 2. 3-State Timing Diagram Rev. 1.00 5 tDEN N+1 XRD6406 DNL Output Codes LSB Best Fit Line 7 V(N+1) Real Transfer Line Analog Input 6 V(N) 5 N+1 Output Codes EFS INL 4 N Ideal Transfer Line 3 N--1 Code Width (N) = V(N+1) -- V(N) LSB = [ VRT -- VRB ] / 1024 2 LSB 1 DNL(N) = [ V(N+1) -- V(N) ] -- LSB Analog Input (Volt) EZS Figure 3. DNL Measurement Figure 4. INL Error Calculation +5V 0.1mF Analog Input 10mF 10mF 50W C5 C4 C3 C2 10mF 0.1mF Analog Input AVDD VIN DVDD DB9 DB8 DB7 VRTS DB6 DB5 VRT DB4 DB3 R3 XRD6406 DB2 DB1 R2 DB0 R1 VRBS GND CLK 50W N/C V4 C4 Digital Outputs V3 C3 V2 C2 V1 OE VRB C1 +5V C1 Sample Clock N/C AV , DVDD VIN DD DB9 VRTS DB8 DB7 VRT DB6 DB5 R3 DB4 XRD6406 DB3 DB2 R2 DB1 DB0 R1 OE VRB CLK VRBS GND 0.1mF Digital Outputs Sample Clock C1--C5 = 0.1mF C1--C4 = 0.1mF V4 > V3 > V2 > V1 > GND Figure 5. Typical Circuit Connections Figure 6. Creating a Piece Wise Linear Transfer Function Rev. 1.00 6 XRD6406 1023 The digital outputs should not drive long wires or buses. The capacitive coupling and reflections will contribute noise to the conversion. Digital Code 768 VIN Analog Input V4 This part has a switched capacitor type input circuit. This means that the input impedance changes with the phase of the input clock. VIN is sampled at the high to low clock transition. Figure 8. shows an equivalent input circuit. 512 V3 AVDD V2 256 160W V1 CLK VIN 0 1V 2V 3V 4V VIN AGND 5pF VRT + VRB + 2 18pF 100W CLK 1.5pF CLK Figure 8. Equivalent Input Circuit Figure 7. A Piece Wise Linear, Logarithmic Transfer Function RTS & RBS Internal Bias Resistors Two matched resistors are provided on the chip. These resistors can be used to generate on chip reference voltages. Each resistor has a value equal to 1/3 of the reference ladder resistor. By connecting RTS to VRT, and connecting RBS to VRB, the reference ladder will be biased to 1V at VRB and 4V at VRT. APPLICATION NOTES If the internal reference pins VRTS and/or VRBS are not used they should be left unconnected. Signals should not exceed AVDD or DVDD +0.5V or go below DGND or AGND --0.5V. All pins have internal protection diodes that will protect them from short transients (<100ms) outside the supply range. R1 thru R3 Reference Ladder Taps These taps connect to every quarter point along the reference ladder; R1 is 1/4th up from VRB, R3 is 3/4ths up from VRB (or 1/4th down from VRT). Normally these pins should have 0.1 microfarad capacitors to AGND; this helps reduce the INL errors by stabilizing the reference ladder voltages. These taps can also be used to alter the transfer curve of the ADC. A four segment, piecewise linear, custom transfer curve can be designed by connecting voltage sources to these pins. AGND and DGND pins are connected internally through the P-substrate. DC voltage differences between these pins will cause undesirable internal substrate currents. The power supply (AVDD) and reference voltage (VRT & VRB) pins should be decoupled with 0.1mF and 10mF capacitors to AGND, placed as close to the chip as possible. Rev. 1.00 7 XRD6406 PERFORMANCE CHARACTERISTICS Graph 1. XRD6406, DNL @ 5MSPS DVDD = 5V, AVDD = 5V, VRT = 4V, VRB = 1V Graph 2. XRD6406, INL @ 5MSPS DVDD = 5V, AVDD = 5V, VRT = 4V, VRB = 1V Graph 3. XRD6406, DNL @ 5MSPS DVDD = 3V, AVDD = 5V, VRT = 4.5V, VRB = 0.5V Graph 4. XRD6406, INL @ 5MSPS DVDD = 3V, AVDD = 5V, VRT = 4.5V, VRB = 0.5V Rev. 1.00 8 XRD6406 Graph 5. Crossplot Staircase Output CLK = 6MSPS, VREF = 4V Graph 6. XRD6406 Spectral Performance Graph 7. XRD6406 Output Noise Histogram Rev. 1.00 9 XRD6406 24 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 24 13 1 12 E1 E D Seating Plane A2 A L C A1 B e B1 INCHES SYMBOL a eA eB MILLIMETERS MIN MAX MIN A 0.145 0.210 3.68 MAX 5.33 A1 0.015 0.070 0.38 1.78 A2 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.125 1.275 28.58 32.39 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC eB 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 5.08 a 0° 15° 0° 15° Note: The control dimension is the inch column Rev. 1.00 10 XRD6406 24 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) Rev. 1.00 D 24 13 E H 1 12 C A Seating Plane e a B A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.598 0.614 15.20 15.60 E 0.291 0.299 7.40 7.60 e 0.050 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 a 0° 8° 0° 8° Note: The control dimension is the millimeter column Rev. 1.00 11 XRD6406 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. All trademarks and registered trademarks are property of their respective owners. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 12