AD SW06FQ

a
FEATURES
Two Normally Open and Two Normally Closed SPST
Switches with Disable
Switches Can Be Easily Configured as a Dual SPDT or
a DPDT
Highly Resistant to Static Discharge Destruction
Higher Resistance to Radiation than Analog Switches
Designed with MOS Devices
Guaranteed RON Matching: 10% max
Guaranteed Switching Speeds
T ON = 500 ns max
T OFF = 400 ns max
Guaranteed Break-Before-Make Switching
Low “ON” Resistance: 80 V max
Low R ON Variation from Analog Input Voltage: 5%
Low Total Harmonic Distortion: 0.01%
Low Leakage Currents at High Temperature
T A = +1258C: 100 nA max
T A = +858C: 30 nA max
Digital Inputs TTL/CMOS Compatible and Independent
of V+
Improved Specifications and Pin Compatible to
LF-11333/13333
Dual or Single Power Supply Operation
Available in Die Form
Quad SPST JFET
Analog Switch
SW06
FUNCTIONAL BLOCK DIAGRAM
V+
12
3
IN 1
1
2
6
IN 2
LEVEL
SHIFT
8
7
11
IN 3
14
S2
D2
S3
D3
S4
16
15
4
DIS
D1
9
10
IN 4
S1
13
D4
5
GND
V–
GENERAL DESCRIPTION
The SW06 is a four channel single-pole, single-throw analog
switch that employs both bipolar and ion-implanted FET
devices. The SW06 FET switches use bipolar digital logic inputs
which are more resistant to static electricity than CMOS devices.
Ruggedness and reliability are inherent in the SW06 design and
construction technology.
Increased reliability is complemented by excellent electrical
specifications. Potential error sources are reduced by minimizing
“ON” resistance and controlling leakage currents at high temperatures. The switching FET exhibits minimal RON variation
over a 20 V analog signal range and with power supply voltage
changes. Operation from a single positive power supply voltage
is possible. With V+ = 36 V, V– = 0 V, the analog signal range
will extend from ground to +32 V.
PNP logic inputs are TTL and CMOS compatible to allow the
SW06 to upgrade existing designs. The logic “0” and logic “1”
input currents are at microampere levels reducing loading on
CMOS and TTL logic.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
SW06–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V+ = +15 V, V– = –15 V and T = +258C, unless otherwise noted)
A
SW06B
Min Typ Max
SW06F
Min Typ Max
SW06G
Min Typ Max
Parameter
Symbol
Conditions
“ON” RESISTANCE
RON
VS = 0 V, IS = 1 mA
VS = ± 10 V, IS = 1 mA
60
65
80
80
60
65
100
100
RON MATCH BETWEEN SWITCHES
RON Match
VS = 0 V, IS = 100 µA1
5
10
5
20
ANALOG VOLTAGE RANGE
VA
IS = 1 mA2
IS = 1 mA2
+10 +11
–10 –15
+10 +11
–10 –15
+10 +11
–10 –15
V
ANALOG CURRENT RANGE
IA
VS = ± 10 V
10
7
5
mA
∆RON VS. APPLIED VOLTAGE
∆RON
–10 V ≤ VS ≤ 10 V, IS = 1.0 mA
5
15
10
20
10
20
%
SOURCE CURRENT IN
“OFF” CONDITION
IS(OFF)
VS = 10 V, VD = –10 V3
0.3
2.0
0.3
2.0
0.3
10
nA
DRAIN CURRENT IN
“OFF” CONDITION
ID(OFF)
VS = 10 V, VD = –10 V3
0.3
2.0
0.3
2.0
0.3
10
nA
SOURCE CURRENT IN
“ON” CONDITION
IS(ON)+
ID(ON)
VS = VD = ± 10 V
0.3
2.0
0.3
2.0
0.3
10
nA
LOGICAL “1” INPUT VOLTAGE
VINH
Full Temperature Range2, 4
LOGICAL “0” INPUT VOLTAGE
VINL
Full Temperature Range2, 4
0.8
0.8
0.8
V
LOGICAL “1” INPUT CURRENT
IINH
VIN = 2.0 V to 15.0 V5
5
5
10
µA
LOGICAL “0” INPUT
IINL
VIN = 0.8 V
1.5
5.0
1.5
5.0
1.5
10.0
µA
TURN-ON TIME
tON
See Switching Time
Test Circuit4, 6
340
500
340 600
340
700
ns
TURN-OFF TIME
tOFF
See Switching Time
Test Circuit4, 6
200
400
200 400
200
500
ns
BREAK-BEFORE-MAKE TIME
tON–tOFF
Note 7
SOURCE CAPACITANCE
CS(OFF)
VS = 0 V3
CD(OFF)
3
DRAIN CAPACITANCE
3
2.0
50
VS = 0 V
3
15
12
2.0
140
50
100
100
150
150
Ω
20
%
10
2.0
140
50
Units
V
140
ns
7.0
7.0
7.0
pF
5.5
5.5
5.5
pF
15
15
15
pF
CHANNEL “ON” CAPACITANCE
CD(ON)+
CS(ON)
V S = VD = 0 V
“OFF” ISOLATION
ISO(OFF)
VS = 5 V rms, RL = 680 Ω,
CL = 7 pF, f = 500 kHz3
58
58
58
dB
CROSSTALK
CT
VS = 5 V rms, RL = 680 Ω,
CL = 7 pF, f = 500 kHz3
70
70
70
dB
POSITIVE SUPPLY CURRENT
I+
All Channels “OFF”,
DIS = “0”3
5.0
6.0
5.0
9.0
6.0
9.0
mA
NEGATIVE SUPPLY CURRENT
I–
All Channels “OFF”,
DIS = “0”3
3.0
5.0
4.0
7.0
4.0
7.0
mA
GROUND CURRENT
IG
All Channels “ON” or
“OFF”3
3.0
4.0
3.0
4.0
3.0
5.0
mA
–2–
REV. A
SW06
(@ V+ = +15 V, V– = –15 V, –558C ≤ TA ≤ +1258C for SW06BQ, –408C ≤ TA ≤ +858C for
ELECTRICAL CHARACTERISTICS SW06FQ and –408C ≤ T ≤ +858C for SW06GP/GS, unless otherwise noted)
A
Parameter
Symbol
Conditions
SW06B
Min Typ Max
TEMPERATURE RANGE
TA
Operating
–55
“ON” RESISTANCE
RON
VS = 0 V, IS = 1.0 mA
VS = ± 10 V, IS = 1.0 mA
75
80
110
110
75
80
125
125
75
80
VS = 0 V, IS = 100 µA1
6
20
6
25
10
∆RON MATCH BETWEEN SWITCHES RON Match
2
SW06F
Min Typ Max
+125 –25
+85
SW06G
Min Typ Max
Units
0
70
°C
175
175
Ω
%
ANALOG VOLTAGE RANGE
VA
IS = 1.0 mA
IS = 1.0 mA2
+10 +11
–10 –15
+10 +11
–10 –15
ANALOG CURRENT RANGE
IA
VS = ± 10 V
7
5
∆RON WITH APPLIED VOLTAGE
∆RON
–10 V ≤ VS ≤ 10 V, IS = 1.0 mA
SOURCE CURRENT IN
“OFF” CONDITION
IS(OFF)
VS = 10 V, VD = –10 V
TA = Max Operating Temp3, 9
60
30
60
nA
DRAIN CURRENT IN
“OFF” CONDITION
ID(OFF)
VS = 10 V, VD = –10 V
TA = Max Operating Temp3, 9
60
30
60
nA
LEAKAGE CURRENT IN
“ON” CONDITION
IS(ON)+
ID(ON)
VS = VD = ± 10 V
TA = Max Operating Temp3, 9
100
30
60
nA
LOGICAL “1” INPUT CURRENT
IINH
VIN = 2.0 V to 15.0 V5
10
10
15
µA
LOGICAL “0” INPUT CURRENT
IINL
VIN = 0.8 V
4
10
4
15
µA
TURN-ON TIME
tON
See Switching Time
Test Circuit4, 8
440
900
500 900
1000
ns
TURN-OFF TIME
tOFF
See Switching Time
Test Circuit4, 8
300
500
330 500
500
ns
BREAK-BEFORE-MAKE TIME
tON–tOFF
Note 7
70
POSITIVE SUPPLY CURRENT
I+
All Channels “OFF,”
DIS = “0”3
9.0
13.5
13.5
mA
NEGATIVE SUPPLY CURRENT
I–
All Channels “OFF,”
DIS = “0”3
7.5
10.5
10.5
mA
GROUND CURRENT
IG
All Channels “ON” or
“OFF”3
6.0
7.5
7.5
mA
NOTES
1
VS = 0 V, IS = 100 µA. Specified as a percentage of R AVERAGE where: RAVERAGE =
12
10
+10 +11
–10 –15
11
11
mA
12
15
%
10
70
Guaranteed by R ON and leakage tests. For normal operation maximum analog signal voltages should be restricted to less than (V+) –4 V.
Switch being tested ON or OFF as indicated, V INH = 2.0 V or VINL = 0.8 V, per logic truth table.
4
Also applies to disable pin.
5
Current tested at V IN = 2.0 V. This is worst case condition.
6
Sample tested.
7
Switch is guaranteed by design to provide break-before-make operation.
8
Guaranteed by design.
9
Parameter tested only at T A = +125°C for military grade device.
3
Specifications subject to change without notice.
REV. A
–3–
5
50
RON1 + RON2 + RON 3 + RON 4
.
4
2
V
ns
SW06
WAFER TEST LIMITS (@ V+ = +15 V, V– = –15 V, T = +258C, unless otherwise noted)
A
Parameter
Symbol
Conditions
SW06N
Limit
SW06G
Limit
Units
“ON” RESISTANCE
RON
–10 V ≤ VA ≤ 10 V, IS ≤ 1 mA
80
100
Ω max
RON MATCH BETWEEN SWITCHES
RON Match
VA = 0 V, IS ≤ 100 µA
15
20
% max
∆RON VS. VA
∆RON
–10 V ≤ VA ≤ 10 V, IS ≤ 1 mA
10
20
% max
POSITIVE SUPPLY CURRENT
I+
Note 1
6.0
9.0
mA max
NEGATIVE SUPPLY CURRENT
I–
Note 1
5.0
7.0
mA max
GROUND CURRENT
IG
Note 1
4.0
4.0
mA max
ANALOG VOLTAGE RANGE
VA
IS = 1 mA
± 10.0
± 10.0
V min
LOGIC “1” INPUT VOLTAGE
VINH
Note 2
2.0
2.0
V min
LOGIC “0” INPUT VOLTAGE
VINL
Note 2
0.8
0.8
V max
LOGIC “0” INPUT CURRENT
IINL
0 V ≤ VIN ≤ 0.8 V
5.0
5.0
µA max
LOGIC “1” INPUT CURRENT
IINH
2.0 V ≤ VIN ≤ 15 V3
5
5
µA max
ANALOG CURRENT RANGE
IA
VS = ± 10 mV
10
7
mA min
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS (@ V+ = +15 V, V– = –15 V, T = +258C, unless otherwise noted)
A
Parameter
Symbol
Conditions
SW06N
Typical
SW06G
Typical
Units
“ON” RESISTANCE
RON
–10 V ≤ VA ≤ 10 V, IS ≤ 1 mA
60
60
Ω
TURN-ON TIME
tON
340
340
ns
TURN-OFF TIME
tOFF
200
200
ns
DRAIN CURRENT IN
“OFF” CONDITION
ID(OFF)
VS = 10 V, VD = –10 V
0.3
0.3
nA
“OFF” ISOLATION
ISO(OFF)
f = 500 kHz, RL = 680 Ω
58
58
dB
CROSSTALK
CT
f = 500 kHz, RL = 680 Ω
70
70
dB
NOTES
1
Power supply and ground current specified for switch “ON” or “OFF.”
2
Guaranteed by RON and leakage tests.
3
Current tested at V IN = 2.0 V. This is worst case condition.
–4–
REV. A
SW06
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1
Operating Temperature Range
SW06BQ, BRC . . . . . . . . . . . . . . . . . . . –55°C to +125°C
SW06FQ . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
SW06GP, GS . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . +36 V
V+ Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . +36 V
Logic Input Voltage . . . . . . . . . . . (–4 V or V–) to V+ Supply
Analog Input Voltage Range
Continuous . . . . . . . . . . . . . V– Supply to V+ Supply +20 V
Maximum Current Through
Any Pin Including Switch . . . . . . . . . . . . . . . . . . . . . 30 mA
Package Type
uJA2
uJC
Units
16-Pin Hermetic DIP (Q)
16-Pin Plastic DIP (P)
20-Contact LCC (RC)
16-Pin SOL (S)
100
82
98
98
16
39
38
30
°C/W
°C/W
°C/W
°C/W
Model
Temperature
Range
Package
Description
Package
Option
SW06BQ
SW06BRC
SW06FQ
SW06GP
SW06GS
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Cerdip
LCC
Cerdip
Plastic DIP
SOL
Q-16
E-20A
Q-16
N-16
R-16
TRUTH TABLE
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for Cerdip, P-DIP, and LCC packages; θJA is specified for device soldered
to printed circuit board for SO package.
Disable
Input
Logic
Input
Switch State
Channels
Channels
1&2
3&4
0
1 or NC
1 or NC
X
0
1
OFF
OFF
ON
PIN CONNECTIONS
16-Pin DIP (Q or P-Suffix)
16-Pin SOL (S-Suffix)
DICE CHARACTERISTICS
Die Size 0.101 × 0.097 inch, 9797 sq. mils
(2.565 × 2.464 mm, 6320 sq. mm)
SW06BRC/883
LCC Package
(RC-Suffix)
REV. A
–5–
OFF
ON
OFF
SW06–Typical Performance Characteristics
“ON” Resistance vs. Power Supply
Voltage
“ON” Resistance vs. Analog Voltage
RON vs. Temperature
Switch Current vs. Voltage
Leakage Current vs. Analog Voltage
Leakage Current vs. Temperature
Supply Current vs. Temperature
Supply Current vs. Supply Voltage
Switch Capacitance vs. Analog
Voltage
–6–
REV. A
SW06
TON/TOFF Switching Response
Switching Time vs. Analog Voltage
Insertion Loss vs. Frequency
Crosstalk and “OFF” Isolation vs.
Frequency
Power Supply Rejection vs.
Frequency
REV. A
Switching Time vs. Temperature
Total Harmonic Distortion
Overvoltage Characteristics
–7–
SW06–Typical Performance Characteristics (Operating and Single Supply)
“On” Resistance vs. Analog Voltage
Leakage Current vs. VANALOG
Supply Current vs. Supply Voltage
NOTE
These single-supply-operation characteristic curves are valid
when the negative power supply V– is tied to the logic ground
reference pin “GND.” TTL input compatibility is still maintained when “GND” is the same potential as the TTL ground.
tOFF is measured from 50% of logic input waveform to 0.9 VO.
The analog voltage range extends from 0 V to V+ –4 V; the
switch will no longer respond to logic control when VA is within
4 volts of V+.
Switching Time vs. Supply Voltage
Simplified Schematic Diagram (Typical Switch)
–8–
REV. A
SW06
“Off” Isolation Test Circuit
Crosstalk Test Circuit
Switching Time Test Circuit
REV. A
–9–
SW06
Figure 1. Functional Applications of SW06
APPLICATIONS INFORMATION
The single analog switch product configures, by appropriate pin
connections, into four switch applications. As shown in Figure
1, the SW06 connects as a QUAD SPST, a DUAL SPDT, a
DUAL DPST, or a DPDT analog switch. This versatility increases further when taking advantage of the disable input (DIS)
which turns all switches OFF when taken active low.
supplies are OFF. When the V+ and V– supplies are OFF, the
logic inputs present a reverse bias diode loading to active logic
inputs. Input logic thresholds are independent of V+ and V–
supplies making single V+ supply operation possible by simply
connecting GND and V– together to the logic ground supply.
ANALOG VOLTAGE AND CURRENT
ANALOG VOLTAGE
Ion-implantation of the JFET analog switch achieves low ON
resistance and tight channel-to-channel matching. Combining
the low ON resistance and low leakage currents results in a
worst case voltage error figure VERROR @ +125°C = ID(ON) ×
RSD(ON) = 100 nA × 100 Ω = 11 microvolts. This amount of error is negligible considering dissimilar-metal thermally-induced
offsets will be in the 5 to 15 microvolt range.
LOGIC INPUTS
The logic inputs (INX) and disable input (DIS) are referenced
to a TTL logic threshold value of two forward diode drops (1.4 V
at +25°C) above the GND terminal. These inputs use PNP
transistors which draw maximum current at a logic “0” level and
drops to a leakage current of a reverse biased diode as the logic
input voltage raises above 1.4 volts. Any logic input voltage
greater than 2.0 volts becomes logic “1,” less than 0.8 volts becomes logic “0” resulting in full TTL noise immunity not available from similar CMOS input analog switches. The PNP
transistor inputs require such low input current that the SW06
approaches fan-ins of CMOS input devices. These bipolar logic
inputs exceed any CMOS input circuit in resistance to static
voltage and radiation susceptibility. No damage will occur to the
SW06 if logic high voltages are present when the SW06 power
These switches have constant ON resistance for analog voltages
from the negative power supply (V–) to within 4 volts of the
positive power supply. This characteristic shown in the plots results in good total harmonic distortion, especially when compared to CMOS analog switches that have a 20 to 30 percent
variation in ON resistance versus analog voltage. Positive analog
input voltage should be restricted to 4 volts less than V+ assuring the switch remains open circuit in the OFF state. No increase in switch ON resistance occurs when operating at supply
voltages less than ± 15 volts (see plot). Small signals have a 3 dB
down frequency of 70 MHz (see insertion loss versus frequency
plot).
ANALOG CURRENT
The analog switches in the ON state are JFETs biased in their
triode region and act as switches for analog current up to the IA
specification (see plot of IDS vs VDS). Some applications require
pulsed currents exceeding the IA spec. For example, an integrator reset switch discharging a shunt capacitor will produce a
peak current of IA(PEAK) = VCAP/RDS(ON). In this application, it is
best to connect the source to the most positive end of the capacitor, thereby achieving the lowest switch resistance and
–10–
REV. A
SW06
fastest reset times. The switch can easily handle any amount of
capacitor discharge current subject only to the maximum heat
dissipation of the package and the maximum operating junction
temperature from which repetition can be established.
DISABLE NODE
This TTL compatible node is similar to the logic inputs INX but
has an internal 2 µA current source pull-up. If disable is left unconnected, it will assume the logic “1” state, then the state of
the switches is controlled only by the logic inputs INX.
SWITCHING
Switching time tON and tOFF characteristics are plotted versus
VANALOG and temperature. In all cases, tOFF is designed faster
than tON to ensure a break-before-make interval for SPDT and
DPDT applications. The disable input (DIS) has the same
switching times (tON and tOFF) as the logic inputs (INX).
Switching transients occurring at the source and drain contacts
results from ac coupling of the switching FETs gate-to-source
and gate-to-drain coupling capacitance. The switch turn ON
will cause a negative going spike to occur and the turn OFF will
cause a positive spike to occur. These spikes can be reduced by
additional capacitance loading, lower values of RL, or switching
an additional switch (with its extra contact floating) to the opposite state connected to the spike sensitive node.
POWER SUPPLIES
This product operates with power supply voltages ranging from
± 12 to ± 18 volts; however, the specifications only guarantee
device parameters with ± 15 volt ± 5% power supplies. The
power supply sensitive parameters have plots to indicate effects
of supply voltages other than ± 15 volts.
Typical Applications
Operation from Single Positive Power Supply
4-Channel Sample Hold Amplifier
High Off Isolation Selector Switch (Shunt-Series Switch)
REV. A
–11–
SW06
Single Pole Double Throw Selector Switch with Break-Before-Make Interval
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Terminal Leadless Chip Carrier
(RC-Suffix)
E-20A
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.095 (2.41)
0.075 (1.90)
0.358 (9.09) 0.358
(9.09)
0.342 (8.69)
MAX
SQ
SQ
0.005 (0.13) MIN
0.200 (5.08)
BSC
3
19
18 20
4
14
13
0.015 (0.38)
MIN
0.310 (7.87)
0.220 (5.59)
8
1
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.050 (1.27)
BSC
8
9
PIN 1
0.028 (0.71)
0.022 (0.56)
BOTTOM
VIEW
0.080 (2.03) MAX
16
0.100 (2.54) BSC
1
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
16-Lead Cerdip
(Q-Suffix)
Q-16
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
9
0.150
(3.81)
MIN
45° TYP
0.055 (1.40)
0.045 (1.14)
0.200 (5.08)
0.125 (3.18)
0.150 (3.81)
BSC
0.023 (0.58)
0.014 (0.36)
16-Lead Plastic DIP
(P-Suffix)
N-16
1
8
0.022 (0.558)
0.014 (0.356)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.100
(2.54)
BSC
0.070 (1.77) SEATING
0.045 (1.15) PLANE
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
16
9
1
8
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.015 (0.381)
0.008 (0.204)
0.0500
(1.27)
BSC
–12–
0.4193 (10.65)
0.3937 (10.00)
9
0.160 (4.06)
0.115 (2.93)
15°
0°
SEATING
PLANE
0.4133 (10.50)
0.3977 (10.00)
16
PIN 1
0.015 (0.38)
0.008 (0.20)
16-Lead Wide Body SOL
(S-Suffix)
R-16/SOL-16
0.840 (21.33)
0.745 (18.93)
0.210 (5.33)
MAX
0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
0.2992 (7.60)
0.2914 (7.40)
0.088 (2.24)
0.054 (1.37)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
0°
SEATING 0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
REV. A