IH6108 Semiconductor T UCT ROD RODUC P E P T E E A) OL UT OBS UBSTIT HI-0508( , S A E G508 SIBL POS G408, D D April 1999 8-Channel CMOS Analog Multiplexer Features Description • Ultra Low Leakage - ID(OFF) ≤ 100pA (Typ) The IH6108 is a CMOS 1-of-8 multiplexer. The part is a plugin replacement for the DG508A. Three-line decoding is used so that the 8 channels can be controlled by 3 Address inputs; additionally a fourth input is provided for use as a system enable. When the ENABLE input is high (5V), a channel is selected by the three Address inputs, and when low (0V) all channels are off. The 3 Address inputs are TTL and CMOS logic compatible, with a “1” corresponding to any voltage greater than 2.4V. • rDS(ON) < 400Ω Over Full Signal and Temperature Range • Power Supply Quiescent Current Less Than 100µA • ±14V Analog Signal Range • No SCR Latchup • Break-Before-Make Switching • Binary Address Control (3 Address Inputs Control 8 Channels) Part Number Information PART NUMBER • TTL and CMOS Compatible Strobe Control TEMP. RANGE (oC) PKG. NO. PACKAGE • Pin Compatible with DG508A, HI-508 and ADG508A IH6108MJE -55 to 125 16 Ld CERDIP F16.3 • Internal Diode in Series with V+ for Fault Protection IH6108MJE/883B -55 to 125 16 Ld CERDIP F16.3 IH6108CJE 0 to 70 16 Ld CERDIP F16.3 IH6108CPE 0 to 70 16 Ld PDIP E16.3 Pinout Functional Diagram S1 IH6108 (CERDIP, PDIP) TOP VIEW A0 1 16 A1 EN 2 15 A2 V- 3 14 GND S1 4 13 V+ S2 5 12 S5 S3 6 11 S6 S4 7 10 S7 D 8 9 S8 S2 S3 S4 VOUT S5 D ADDRESS DECODER 1 OF 8 S6 ENABLE INPUT S7 S8 A0 A1 A2 EN 3 LINE BINARY ADDRESS INPUT (1 0 1) AND EN AT 5V ABOVE EXAMPLE SHOWS CHANNEL 6 TURNED ON. TRUTH TABLE A2 A1 A0 EN ON SWITCH x x x 0 None 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 NOTE: A0 , A1, A2 Logic “1” = VAH ≥ 2.4V, VENH ≥ 4.5V Logic “0” = VAL ≤ 0.8V. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 12-128 File Number 3156.2 IH6108 Absolute Maximum Ratings Thermal Information VIN (A, EN) to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 15V VS or VD to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V, -36V VS to VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V, 36V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18V Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Current (Analog Source or Drain) . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A CERDIP Package . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER V+ = 15V, V- = -15V, VEN = +5V, Ground = 0V, Unless Otherwise Specified, (Note 4) M SUFFIX (oC) C SUFFIX (oC) TEST CONDITIONS -55 25 125 0 25 70 UNITS 180 VD = +10V, IS = -1.0mA Sequence Each Switch On VAL = 0.8V, VAH = 2.4V 300 300 400 350 350 450 Ω 150 VD = -10V, IS = -1.0mA Sequence Each Switch On VAL = 0.8V, VAH = 2.4V 300 300 400 350 350 450 Ω 20 ∆rDS(ON) = rDS ( ON )MAX –rDS ( ON )MIN ----------------------------------------------------------------------------------- , r ˙ - - - - - - % MEASURED TERMINAL NO TESTS PER TEMP TYP 25oC S to D 8 8 SWITCH rDS(ON) ∆rDS(ON) DS ( ON )AV G VS = ±10V IS(OFF) ID(OFF) ID(ON) 8 0.002 VS = 10V, VD = -10V - ±0.5 ±50 - ±1 ±50 nA 8 0.002 VS = -10V, VD = 10V, VEN = 0.8V - ±0.5 ±50 - ±1 ±50 nA 1 0.03 VD = 10V, VS = -10V, VEN = 0.8V - ±2 ±100 - ±5 ±100 nA 1 0.03 VD = -10V, VS = 10V, VEN = 0.8V - ±2 ±100 - ±5 ±100 nA 8 0.1 VS(ALL) = VD = 10V, Sequence Each Switch On VAL = 0.8V, VAH = 2.4V - ±2 ±100 - ±5 ±100 nA 8 0.1 VS(ALL) = VD = -10V, Sequence Each Switch On VAL = 0.8V, VAH = 2.4V - ±2 ±100 - ±5 ±100 nA A0 , A1 , or A2 Inputs A0 , A1 , A2 3 0.01 VA = 0V - -10 -30 - -10 -30 µA 3 0.01 VA = 14V - 10 30 - 10 30 µA 3 0.01 VEN = 5V, All VA = 0V (Address Pins) - -10 -30 - -10 -30 µA EN 1 0.01 VEN = 0V, All VA = 0V (Address Pins) - -10 -30 - -10 -30 µA S D D INPUT IAN(ON) or IA(on) IAN(OFF) IA(off) IA 12-129 IH6108 Electrical Specifications PARAMETER V+ = 15V, V- = -15V, VEN = +5V, Ground = 0V, Unless Otherwise Specified, (Note 4) (Continued) MEASURED TERMINAL NO TESTS PER TEMP TYP 25oC TEST CONDITIONS M SUFFIX (oC) C SUFFIX (oC) -55 25 0 125 25 70 UNITS DYNAMIC tTRANSITION D 0.3 See Figure 1 - 1 - - - - µs tOPEN D 0.2 See Figure 2 - - - - - - µs tON(EN) D 0.6 See Figure 3 - 1.5 - - - - µs tOFF(EN) D 0.4 See Figure 3 - 1 - - - - µs “OFF” Isolation D 60 VEN = 0V, RL = 200Ω, CL = 3pF, VS = 3VRMS , f = 500kHz - - - - - - dB CS(OFF) S 5 VS = 0V, VEN = 0V, f = 140kHz to 1MHz - - - - - - pF CD(OFF) D 25 VD = 0V,VEN = 0V, f = 140kHz to 1MHz - - - - - - pF D to S 1 VS = 0V, VD = 0V, VEN = 0V, f = 140kHz to 1MHz - - - - - - pF CDS(OFF) SUPPLY Positive Supply Current V+ 1 40 VEN = 5V, All VA = 0V or 5V - - 200 - - 1000 µA Negative Supply Current V- 1 2 VEN = 5V, All VA = 0V or 5V - - 100 - - 1000 µA Positive Standby Current V+ 1 1 VEN = 0V, All VA = 0V or 5V - - 100 - - 1000 µA Negative Standby Current V- 1 1 VEN = 0V, All VA = 0V or 5V - - 100 - - 1000 µA NOTE: 2. See “Enable Input Strobing Levels”, in Application Section. Switching Information VA tr < 100ns tf < 100ns +15V V+ 50Ω EN GND -9V S1 ON ±10V RP -15V +9V ttrans(1-8) -10V S8 ON +9V VOUT +5V +10V VOUT VS1 = +10V VS8 = -10V PROBE D V- 50% ttrans(8-1) ±10V S1 S2 S3 S IH6108 4 S5 A0 S6 A1 S7 A2 S8 VA 3V 0.8V S1 ON +10V ttrans(1-8) CP PROBE IMPEDANCE RP ≥ 1MΩ CP ≤ 30pF VOUT VS1 = -10V VS8 = +10V -10V FIGURE 1. tTRANSITION SWITCHING TEST CIRCUIT AND WAVEFORMS 12-130 -9V ttrans(8-1) S8 ON IH6108 Switching Information (Continued) +15V A2 A1 A0 VA +5V EN 3V S1 S2 THRU S7 IH6108 S8 -2V VOUT 200Ω GND 0.8V 0.8V VS1 = -2V S1 ON VOUT D V- VA tr < 100ns tf < 100ns S8 ON 50% 35pF -15V 50% tOPEN tOPEN FIGURE 2. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TEST CIRCUIT AND WAVEFORMS +15V S1 S2 THRU A0 IH6108 S8 VS1 A2 A1 EN VEN tr < 100ns tf < 100ns 5V 50% 0.8V tEN(OFF) VOUT 0V OUT 10% VOUT VEN 1kΩ GND 35pF 90% -15V tEN(ON) VS1 = -2V FIGURE 3. tON AND tOFF SWITCHING TEST CIRCUIT AND WAVEFORMS IH6108 Application Information ENABLE Input Strobing Levels Using the IH6108 with Supplies Other Than ±15V The ENABLE input on the IH6108 requires a minimum of +4.5V to trigger to the “1” state and a maximum of +0.8V to trigger to the “0” state. If the ENABLE input is being driven from TTL logic, a pull-up resistor of 1k to 3kΩ is required from the gate output to +5V supply. (See Figure 4.) The IH6108 can be used with power supplies ranging from ±6V to ±16V. The switch rDS(ON) will increase as the supply voltages decrease, however, the multiplexer error term (the product of leakage times rDS(ON)) will remain approximately constant since leakage decreases as the supply voltages are reduced. When the EN input is driven from CMOS logic, no pullup is necessary, see Figure 5. The supply voltage of the CD4009 affects the switching speed of the IH6108; the same is true for TTL supply voltage levels. The following chart shows the effect, on ttrans for a supply varying from +4.5V to +5.5V. CMOS OR TTL SUPPLY VOLTAGE TYPICAL TTRANS AT 25oC +4.5V +4.75V +5.00V +5.25V +5.50V 400ns 300ns 250ns 200ns 175ns The throughput rate can therefore be maximized by using a +5V to +5.5V supply for the ENABLE Strobe Logic. The examples shown in Figures 4 and 5 deal with ENABLE strobing when expansion to more than eight channels is required. In these cases the EN terminal acts as a fourth address input. If eight channels or less are being multiplexed, the EN terminal can be directly connected to +5V logic supply to enable the IH6108 at all times. Caution must be taken to ensure that the enable (EN) voltage is at least 0.7V below V+ at all times. If this is not done, the Address input strobing levels will not function properly. This may be achieved quite simply by connecting EN (pin 2) to V+ (pin 13) via a silicon diode as shown in Figure 6. When using this type of configuration, a further requirement must be met: the strobe levels of A0 and A1 must be within 2.5V of the EN voltage in order to define a binary “1” state. For the case shown in Figure 6 the EN voltage is 11.3V which means that logic high at A0 and A1 is +8.8V (logic low continues to be 0.8V). In this configuration the IH6108 cannot be driven by TTL (+5V) or CMOS (+5V) logic. It can be driven by TTL open collector logic or CMOS logic with +12V supplies. If the logic and the IH6108 have common supplies, the EN pin should again be connected to the supply through a silicon diode. In this case, tying EN to the logic supply directly will not work since it violates the 0.7V differential voltage required between V+ and EN, (See Figure 7). A 1µF capacitor can be placed across the diode to minimize switching glitches. 12-131 IH6108 Switching Information +5V A0 1 1kΩ EN 1 14 2 13 -15V 3 12 S1 4 3 4 DM7404N TTL LOGIC 11 5 10 6 9 7 8 +3V 0V 16 A1 15 A2 2 14 IH6108 13 +15V S2 5 12 S5 S3 6 11 S6 S4 7 10 S7 8 9 S8 D VOUT FIGURE 4. ENABLE INPUT STROBING FROM TTL LOGIC +5V 1 16 2 15 3 14 4 CD4009 13 5 12 6 11 7 10 8 9 A0 1 EN 16 A1 15 A2 2 14 GND -15V 3 S1 4 IH6108 13 +15V S2 5 12 S5 S3 6 11 S6 S4 7 10 S7 D 8 9 S8 FIGURE 5. ENABLE INPUT DRIVEN FROM CMOS LOGIC 1N914 A0 1 EN 16 A1 15 A2 2 14 -12V 3 S1 4 IH6108 13 +12V S2 5 12 S5 S3 6 11 S6 S4 7 10 S7 (VOUT) D 8 9 S8 INPUTS INPUTS FIGURE 6. IH6108 CONNECTION DIAGRAM FOR LESS THAN ±15V SUPPLY OPERATION 12-132 IH6108 Switching Information (Continued) 1N914 OR ANY SILICON DIODE A0 EN 1 16 2 15 14 1 16 2 15 -12V 3 3 14 4 13 5 12 12 6 11 6 11 7 10 7 10 8 9 8 9 4 CD4009A 5 13 IH6108 A1 A2 +12V FIGURE 7. IH6108 CONNECTION DIAGRAM WITH ENABLE INPUT STROBING FOR LESS THAN ±15V SUPPLY OPERATION Peak-to-Peak Signal Handling Capability The IH6108 can handle input signals up to ±14V (actually -15V to +14.3V because of the input protection diode) when using the ±15V supplies. The electrical specifications of the IH6108 are guaranteed for ±10V signals, but the specifications have very minor changes for ±14V signals. The notable changes are slightly lower rDS(ON) and slightly higher leakages. TRUTH TABLE +15V -15V EN IH6108 A0 A1 A2 S8 S1 +15V -15V A3 TTL OR CMOS INVERTER VOUT IH6108 EN S16 S9 A3 A2 A1 A0 ON SWITCH 0 0 0 0 S1 0 0 0 1 S2 0 0 1 0 S3 0 0 1 1 S4 0 1 0 0 S5 0 1 0 1 S6 0 1 1 0 S7 0 1 1 1 S8 1 0 0 0 S9 1 0 0 1 S10 1 0 1 0 S11 1 0 1 1 S12 1 1 0 0 S13 1 1 0 1 S14 1 1 1 0 S15 1 1 1 1 S16 NOTE: TTL inverter must have pullup resistor to +5V to drive EN input. FIGURE 8. 1 OF 16 CHANNEL MULTIPLEXER USING TWO IH6108s. OVERVOLTAGE PROTECTION IS MAINTAINED BETWEEN ALL CHANNELS, AS IS BREAK-BEFORE-MAKE SWITCHING. 12-133 IH6108 +5V -15V +15V TTL/CMOS INVERTER A0 A1 TTL/CMOS NOR GATE A3 A2 EN VL IH6108 1 OUT OF 8 MUX GND V- IH5053 A4 S1 S1 1 8 ANALOG INPUTS D1 IN1 A0 A1 A2 EN V+ IN2 IH6108 1 OUT OF 8 MUX D2 S2 S2 9 16 ANALOG INPUTS VOUT A0 A1 A2 EN IH6108 1 OUT OF 8 MUX IH5053 S3 S3 17 24 ANALOG INPUTS IN3 A0 A1 A2 EN D3 IN4 IH6108 1 OUT OF 8 MUX D4 S4 S4 GND LV 25 32 ANALOG INPUTS +5V TRUTH TABLE V+ V- +15V -15V TRUTH TABLE A4 A3 A2 A1 A0 ON SWITCH A4 A3 A2 A1 A0 ON SWITCH 0 0 0 0 0 S1 1 0 0 0 0 S17 0 0 0 0 1 S2 1 0 0 0 1 S18 0 0 0 1 0 S3 1 0 0 1 0 S19 0 0 0 1 1 S4 1 0 0 1 1 S20 0 0 1 0 0 S5 1 0 1 0 0 S21 0 0 1 0 1 S6 1 0 1 0 1 S22 0 0 1 1 0 S7 1 0 1 1 0 S23 0 0 1 1 1 S8 1 0 1 1 1 S24 0 1 0 0 0 S9 1 1 0 0 0 S25 0 1 0 0 1 S10 1 1 0 0 1 S26 0 1 0 1 0 S11 1 1 0 1 0 S27 0 1 0 1 1 S12 1 1 0 1 1 S28 0 1 1 0 0 S13 1 1 1 0 0 S29 0 1 1 0 1 S14 1 1 1 0 1 S30 0 1 1 1 0 S15 1 1 1 1 0 S31 0 1 1 1 1 S16 1 1 1 1 1 S32 NOTE: TTL inverter must have pullup resistor to +5V to drive EN input. FIGURE 9. 1 OF 32 CHANNEL MULTIPLEXER USING FOUR IH6108s, AND TWO IH5053s AS A SUBMULTIPLEXER 12-134 IH6108 Schematic Diagram S1 1) A0’ OR A0’ 2) A1’ OR A1’ 3) A2’ OR A2’ S2 S3 S4 S5 S6 S7 1 2 3 P VADDRESS DECODER V- S8 D VN AX ADDRESS INPUT GND EN AX’ LEVEL SHIFTER AX’ V- INPUT BUFFER AND LEVEL SHIFTER EN GND VV++ V+ VGND FIGURE 10. IH6108 SCHEMATIC DIAGRAM V++ P P P P EN N N N N EN’ P N V- GND FIGURE 11. ENABLE INPUT AND LEVEL SHIFTER 12-135 IH6108 V++ P P AX AX’ N P EN GND V++ AX’ N P N N V- FIGURE 12. ADDRESS INPUT AND LEVEL SHIFTER 12-136