100352 Low Power 8-Bit Buffer with Cut-Off Drivers General Description Features The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100352 outputs are designed to drive a doubly terminated 50Ω transmission line (25Ω load impedance). All inputs have 50 kΩ pull-down resistors. n n n n n n n Cut-off drivers Drives 25Ω load Low power operation 2000V ESD protection Voltage compensated operating range = −4.2V to −5.7V Available to industrial grade temperature range Available to MIL-STD-883 Logic Symbol DS100296-1 Pin Names Description D0–D7 Data Inputs OEN Output Enable Input Q0–Q7 Data Outputs NC No Connect © 1998 National Semiconductor Corporation DS100296 www.national.com 100352 Low Power 8-Bit Buffer with Cut-Off Drivers August 1998 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak DS100296-3 DS100296-2 www.national.com 2 Logic Diagram DS100296-5 Truth Table Inputs Outputs Dn OEN L L L H L H X H Cutoff Qn H = HIGH Voltage Level L = LOW Voltage Level Cutoff = Lower-than-LOW State X = Don’t Care 3 www.national.com Absolute Maximum Ratings (Note 1) ≥2000V ESD (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Above which the useful life may be impaired −65˚C to +150˚C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic +175˚C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) VEE to +0.5V Output Current (DC Output HIGH) −100 mA Case Temperature (TC) Military Supply Voltage (VEE) −55˚C to +125˚C −5.7V to −4.2V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage VOHC Output HIGH Voltage VOLC VOLZ Min Max Units TC −1025 −870 mV 0˚C to +125˚C −1085 −870 mV −55˚C −1830 −1620 mV 0˚C to +125˚C −1830 −1555 mV −55˚C −1035 mV 0˚C to +125˚C −1085 mV −55˚C −1610 mV 0˚C to +125˚C −1555 mV −55˚C −1950 mV 0˚C to +125˚C Output LOW Voltage Cut-Off LOW Voltage −1850 VIH Input HIGH Voltage −1165 −870 −55˚C mV −55˚C to +125˚C Conditions VIN = VIH(Max) or VIL(Min) Notes Loading with 25Ω to −2.0V (Notes 3, 4, 5) VIN = VIH(Min) or VIL(Max) Loading with 25Ω to −2.0V (Notes 3, 4, 5) VIN = VIH(Min),or VIL(Max) OEN = HIGH (Notes 3, 4, 5) Guaranteed HIGH signal for All inputs VIL Input LOW Voltage IIL Input LOW Current IIH IEE −1830 −1475 0.50 Input HIGH Current mV µA −55˚C to +125˚C −55˚C to +125˚C 240 µA 0˚C to + 125˚C VIN = VIL(Min) VEE = −5.7V 340 µA −55˚C VIN = VIH(Max) −55 mA Power Supply Current −55˚C to +125˚C −145 Guaranteed LOW signal for All inputs VEE = 4.2V −150 1, 2, 3, 4 (Notes 3, 4, 5, 6) (Notes 3, 4, 5) (Notes 3, 4, 5) Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V (Notes 3, 4, 5) Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = −55˚C TC = +25˚C TC +125˚C Min Max Min Max Min Max 0.30 2.60 0.50 2.40 0.50 2.70 ns Figures 1, 2 (Notes 7, 8, 10, 11) ns Figures 1, 2 (Notes 7, 8, 9, 11) tPLH Propagation Delay tPHL Dn to Output tPZH Propagation Delay 1.20 4.40 1.40 4.20 1.20 4.40 tPHZ OEN to Output 0.70 3.00 0.70 2.80 0.70 3.20 www.national.com 4 Units Conditions Notes AC Electrical Characteristics (Continued) VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = −55˚C TC = +25˚C TC +125˚C Min Max Min Max Min Max 0.40 2.50 0.40 2.40 0.40 2.70 Units Conditions Figures 1, 2 ns Notes (Note 10) Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9. Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Note 11: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Test Circuitry DS100296-6 Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 25Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms DS100296-7 Note: The output AC measurement point for cut-off propagation delay testing = the 50% voltage point between active VOL and VOH. FIGURE 2. Propagation Delay, Cut-Off and Transition Times 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24-Lead Quad Cerpak (F) NS Package Number W24B 7 www.national.com 100352 Low Power 8-Bit Buffer with Cut-Off Drivers LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.