100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the 100328 transparent. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100328 is designed with FAST ® TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors. n Identical performance to the 100128 at 50% of the supply current n Bi-directional translation n 2000V ESD protection n Latched outputs n FAST TTL outputs n TRI-STATE ® outputs n Voltage compensated operating range = −4.2V to −5.7V n Available to MIL-STD-883 Logic Symbol DS100295-1 Pin Names Description E0–E7 ECL Data I/O T0–T7 TTL Data I/O OE Output Enable Input LE Latch Enable Input DIR Direction Control Input All pins function at 100K ECL levels except for T0–T7. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FAST ® is a registered trademark of Fairchild Semiconductor. © 1998 National Semiconductor Corporation DS100295 www.national.com 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch August 1998 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak DS100295-4 DS100295-2 www.national.com 2 Functional Diagram Truth Table OE L DIR X LE L ECL TTL Port Port LOW Z Notes (Cut-Off) L L H Input Z (Notes 1, 3) L H H LOW Input (Notes 2, 3) (Cut-Off) H L L L L (Notes 1, 4) H L L H H (Notes 1, 4) H L H X Latched (Notes 1, 3) H H L L L (Notes 2, 4) H H L H H (Notes 2, 4) H H H Latched X (Notes 2, 4) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent. DS100295-5 Note: LE, DIR, and OE use ECL logic levels Detail DS100295-6 3 www.national.com Absolute Maximum Ratings (Note 5) Voltage Applied to Output in HIGH State TRI-STATE Output −0.5V to +5.5V Current Applied to TTL Output in LOW State (Max) Twice the Rated IOL (mA) ESD (Note 6) ≥2000V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 7) TTL Input Current (Note 7) −65˚C to +150˚C +175˚C Recommended Operating Conditions −7.0V to +0.5V Case Temperature (TC) Military ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) −0.5V to +6.0V VEE to +0.5V −50 mA −0.5V to +6.0V −30 mA to +5.0 mA −55˚C to +125˚C −5.7V to −4.2V +4.5V to +5.5V Note 5: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 6: ESD testing conforms to MIL-STD-883, Method 3015. Note 7: Either voltage limit or current limit is sufficient to protect inputs. Military Version TTL-to-ECL DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, VTTL = +4.5V to +5.5V Symbol VOH Conditions Parameter Min Max Units TC Output HIGH Voltage −1025 −870 mV 0˚C to −1085 −870 mV −55˚C VIN = VIH (Max) −1830 −1620 mV 0˚C to or VIL (Min) Loading with 50Ω to −2.0V +125˚C VOL Output LOW Voltage Notes (Notes 8, 9, 10) +125˚C −1830 Cutoff Voltage −1555 mV −55˚C −1950 mV 0˚C to −1850 mV +125˚C VOHC Output HIGH Voltage −1035 OE or DIR Low −55˚C mV 0˚C to (Notes 8, 9, 10) +125˚C mV −55˚C VIN = VIH (Min) Loading with −1610 mV 0˚C to or VIL (Max) 50Ω0 to −2.0V −1555 mV −55˚C V −55˚C to −1085 VOLC Output LOW Voltage +125˚C VIH Input HIGH Voltage 2.0 Over VTTL, VEE, TC Range (Notes 8, 9, 10, 11) Over VTTL, VEE, TC Range (Notes 8, 9, 10, 11) VIN = +2.7V (Notes 8, 9, 10) +125˚C VIL Input LOW Voltage 0.8 V −55˚C to +125˚C IIH Input HIGH Current 70 µA −55˚C to 125˚C Breakdown Test 1.0 mA −55˚C to VIN = +5.5V +125˚C IIL Input LOW Current −1.0 mA −55˚C to VIN = +0.5V (Notes 8, 9, 10) IIN = −18 mA (Notes 8, 9, 10) LE Low, OE and DIR High (Notes 8, 9, 10) +125˚C VFCD Input Clamp −1.2 V −55˚C to Diode Voltage IEE +125˚ C VEE Supply Current −55˚C to www.national.com −165 −73 −175 −73 mA +125˚C 4 Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Military Version ECL-to-TTL DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, CL = 50 pF, VTTL = +4.5V to + 5.5V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage Min Max Units 2.5 mV 2.4 TC 0˚C to +125˚C Conditions IOH = −1 mA, VTTL = 4.50V Notes (Notes 8, 9, 10) −55˚C 0.5 mV IOL = 24 mA, VTTL = 4.50V −55˚C +125˚C VIH VIL Input HIGH Voltage Input LOW Voltage −1165 −870 −1830 −1475 mV mV −55˚C Guaranteed HIGH Signal +125˚C for All Inputs −55˚C to +125˚C IIH Input HIGH Current 350 µA 500 IIL Input LOW Current 0.50 0˚C to +125˚C µA −55˚C to +125˚C IOZHT TRI-STATE Current 70 µA Output High IOZLT TRI-STATE Current Output Short-Circuit −1.0 mA (Notes 8, 9, 10) VIN = VIH (Max) VEE = −4.2V (Notes 8, 9, 10) VIN = VIL (Min) VOUT = +2.7V (Notes 8, 9, 10) −55˚C to VOUT = +0.5V (Notes 8, 9, 10) VOUT = 0.0V, VTTL = +5.5V (Notes 8, 9, 10) (Notes 8, 9, 10) +125˚C −150 −60 mA CURRENT ITTL (Notes 8, 9, 10, 11) for All Inputs VEE = −5.7V +125˚C Output Low IOS −55˚C to Guaranteed LOW Signal (Notes 8, 9, 10, 11) VTTL Supply Current −55˚C to +125˚C 75 mA −55˚C to TTL Outputs Low 50 mA +125˚C TTL Output High 70 mA TTL Output in TRI-STATE Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 9: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2 3, 7, and 8. Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 11: Guaranteed by applying specified input condition and testing VOH/VOL. Military Version TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND Symbol Parameter tPLH TN to En tPHL (Transparent) tPLH LE to En TC = −55˚C TC = 25˚C TC = +125˚C Min Max Min Max Min Max 0.8 3.4 1.1 3.6 0.8 3.7 Conditions Notes ns Figures 1, 2 (Notes 12, 13, 14) ns 1.2 3.8 1.4 3.7 1.1 3.8 tPHL tPZH Units ns Figures 1, 2 ns OE to En 0.8 3.6 1.5 4.0 2.0 5.2 ns Figures 1, 2 1.5 4.6 1.6 4.2 1.6 4.3 ns Figures 1, 2 1.6 4.7 1.6 4.3 1.7 4.3 ns Figures 1, 2 (Cutoff to HIGH) tPHZ OE to En (Notes 12, 13, 14) (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) tset Tn to LE 2.5 2.0 2.5 ns Figures 1, 2 thold Tn to LE 2.5 2.0 2.5 ns Figures 1, 2 ns Figures 1, 2 (Note 15) ns Figures 1, 2 (Note 15) tpw(H) Pulse Width LE 2.5 tTLH Transition Time 0.4 tTHL 20% to 80%, 80% to 20% 2.0 2.3 0.5 5 2.5 2.1 0.4 2.4 (Note 15) www.national.com Military Version ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF Symbol Parameter tPLH En to Tn tPHL (Transparent) tPLH LE to Tn TC = −55˚C TC = 25˚C TC = +125˚C Units Conditions Notes 6.3 ns Figures 1, 2 (Notes 12, 13, 14) 7.5 ns Figures 3, 4 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 6 Min Max Min Max Min Max 2.1 6.0 2.0 5.6 2.2 3.1 7.0 3.1 6.5 3.3 tPHL tPZH OE to Tn 3.2 8.0 3.7 8.0 4.0 9.2 tPZL (Enable Time) 3.6 8.0 4.0 8.5 4.3 9.6 tPHZ OE to Tn 3.2 8.5 3.3 8.0 3.5 8.4 tPLZ (Disable Time) 3.0 8.0 3.4 7.5 4.1 10.0 tPHZ DIR to Tn 2.6 7.0 2.6 7.0 2.9 8.0 tPLZ (Disable Time) 2.7 7.0 3.1 7.0 4.0 10.0 tset En to LE 2.5 2.0 2.5 ns Figures 3, 4 thold En to LE 3.0 2.5 3.0 ns Figures 3, 4 tpw(H) Pulse Width LE 2.5 2.0 5.0 ns Figures 3, 4 (Notes 12, 13, 14) (Note 15) (Note 15) Note 12: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 13: Screen tested 100% on each device at +25˚C, temperature only, Subgroup A9. Note 14: Sample tested (Method 5005, Table I) on each mfg. lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 15: Not tested at +25˚C, +125˚C and −55˚C temperature (design characterization data). www.national.com 6 Test Circuitry (TTL-to-ECL) DS100295-7 Note 16: Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope’s 50Ω resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as Rt. Note 17: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note 18: VTTL is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. Note 19: For ECL input pins, the equivelent force/sense circuitry is optional. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) DS100295-9 FIGURE 2. TTL to ECL Transition — Propagation Delay and Transition Times 7 www.national.com Test Circuitry (ECL-to-TTL) DS100295-10 Note 20: Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope’s 50Ω resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as Rt. Note 21: The TTL TRI-STATE pull up switch is connected to +7V only for ZL and LZ tests. Note 22: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note 23: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Switching Waveforms (ECL-to-TTL) DS100295-11 Note 24: DIR is LOW, and OE is HIGH FIGURE 4. ECL-to-TTL Transition — Propagation Delay and Transition Times www.national.com 8 Switching Waveforms (ECL-to-TTL) (Continued) DS100295-14 Note 25: DIR is LOW, LE is HIGH FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times DS100295-15 Note 26: OE is HIGH, LE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 9 www.national.com Applications DS100295-12 FIGURE 7. Applications Diagram — MOS/TTL SRAM Interface Using 100328 ECL–TTL Latched Translator Ordering Information The device number is used to form part of a simplified purchasing code where A package type and temperature range are defined as follows: DS100295-16 www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24-Lead Quad Cerpak (F) NS Package Number W24B 11 www.national.com 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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