Freescale Semiconductor, Inc. Addendum DSP56309UMAD/D Rev. 1, 11/2002 DSP56309 User’s Manual Addendum Freescale Semiconductor, Inc... CONTENTS 1 Introduction ...............1 2 Modified Signal Definitions .................1 3 Operating Mode Register (OMR) Layout and Definition............3 4 SCI Receive Register (SRX) Description .....3 5 Updated Programming Sheets.........................3 1 Introduction This document provides updated information for revision 0 of the DSP56309 User’s Manual (DSP56309UM/D). The updates include the following: • • • • Modified signal definitions New Operating Mode Register (OMR) layout and bit definitions Updated SCI Receive Register (SRX) description Updated OMR and Timer Registers (TLR, TCPR, TCR) programming sheets 2 Modified Signal Definitions Area to Change Change Description Table 2-1, p. 2-3 • Change Ground (GND) to Ground (GND)5. • Add Note 5 as follows: 5. The number of Ground signals listed are for the 144-pin TQFP package. For the 196-ball MAP-BGA package, there are 66 GND connections. Figure 2-1, p. 2-4 • • • • • • Table 2-3, p. 2-7 • Change the note at the end of the table to the following: Note: The subsystem GND signals (GNDQ, GNDA, GNDD, GNDC, GNDH, and GNDS) are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA package, all grounds except GNDP and GNDP1 are connected together inside the package and referenced as GND. Table 2-8, pp. 2-11 to 2-12 • Change BR signal State During Reset, Stop, or Wait to: • Change HA10 to HA10 Change HRW to HRW Change AA0–AA3 to AA0–AA3 Change TMS to TMS Change Grounds: to Grounds4: At the bottom of the figure, add the following note: 4. The GND signals are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA package, all grounds except GNDP and GNDP1 are connected together and referenced as GND. There are 64 GND connections. Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) Change BB signal State During Reset, Stop, or Wait to Ignored input For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modified Signal Definitions Freescale Semiconductor, Inc... Area to Change Change Description Table 2-11, pp. 2-17 to 2-21 • Change the title of the third column to State During Reset1,2. • Add the following notes to the end of the table: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • Change State During Reset or Stop for all signals to Ignored input. • Change the signal description for PB14 to: Port B14—When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed through the HDDR. Table 2-12, pp. 2-22 to 2-25 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the middle paragraph in the signal description. ESSI0 does not support keeper circuits. • For all signals, change PCR0 to PCRC and PRR0 to PRRC. Table 2-13, pp. 2-26 to 2-28 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the middle paragraph in the signal description. ESSI1 does not support keeper circuits. • For all signals, change PCR1 to PCRD and PRR1 to PRRD. Table 2-14, pp. 2-29 to 2-30 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the middle paragraph in the signal description. The SCI does not support keeper circuits. • For all signals, change PCR to PCRE and PRR to PRRE. Table 2-15, p. 2-31 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the middle paragraph in the signal description. The triple timer module does not support keeper circuits. 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Mode Register (OMR) Layout and Definition 3 Operating Mode Register (OMR) Layout and Definition Area to Change Figure 4-3, p. 4-17 Change Description Replace with the following: Stack Control/Status (SCS) 23 22 21 20 19 18 17 Extended Operating Mode (EOM) 16 15 14 13 12 11 10 9 8 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] Chip Operating Mode (COM) 7 6 MS SD 0 0 5 4 3 2 1 0 EBD MD MC MB MA Reset: 0 Freescale Semiconductor, Inc... * 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 * * * * After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA, respectively). SEN—Stack Extension Enable ATE—Address Tracing Enable WRP—Extended Stack Wrap Flag APD—Address Priority Disable MS—Memory Switch Mode SD—Stop Delay EOV—Extended Stack Overflow Flag ABE—Asynch. Bus Arbitration Enable EBD—External Bus Disable EUN—Extended Stack Underflow Flag BRT—Bus Release Timing MD—Operating Mode D XYS—Stack Extension Space Select TAS—TA Synchronize Select MC—Operating Mode C BE—Burst Mode Enable MB—Operating Mode B CDP1—Core-DMA Priority 1 MA—Operating Mode A CDP0—Core-DMA Priority 0 Reserved bit. Read as zero; write to zero for future compatibility Figure 4-3. Operating Mode Register (OMR) 4 SCI Receive Register (SRX) Description Area to Change Section 8.6.4.1, p. 8-20 5 Change Description Change the beginning of the fourth paragraph from “In Synchronous mode” to “In Asynchronous mode”. Updated Programming Sheets Use the following examples to replace Figure D-2 and Figure D-21 in the DSP56309 User’s Manual. 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 2 of 5 Central Processor Asynchronous Bus Arbitration Enable, Bit 13 0 = Synchronization disabled 1 = Synchronization enabled External Bus Disable, Bit 4 0 = Enables external bus 1 = Disables external bus Freescale Semiconductor, Inc... Address Attribute Priority Disable, Bit 14 0 = Priority mechanism enabled 1 = Priority mechanism disabled Stop Delay Mode, Bit 6 0 = Delay is 128K clock cycles 1 = Delay is 16 clock cycles Address Trace Enable, Bit 15 0 = Address Trace mode disabled 1 = Address Trace mode enabled Memory Switch Mode, Bit 7 0 = Memory switching disabled 1 = Memory switching enabled Stack Extension X Y Select, Bit 16 0 = Mapped to X memory 1 = Mapped to Y memory Core-DMA Priority, Bits 9–8 CPD[1:0] Description 00 Compare SR[CP] to active DMA channel priority 01 DMA has higher priority than core 10 DMA has same priority as core 11 DMA has lower priority than core Stack Extension Underflow Flag, Bit 17 0 = No stack underflow 1 = Stack underflow Stack Extension Overflow Flag, Bit 18 0 = No stack overflow 1 = Stack overflow Stack Extension Wrap Flag, Bit 19 0 = No stack extension wrap 1 = Stack extension wrap (sticky bit) Stack Extension Enable, Bit 20 0 = Stack extension disabled 1 = Stack extension enabled Chip Operating Mode, Bits 3–0 Refer to the operating modes table in Chapter 4. Bus Release Timing, Bit 12 0 = Fast Bus Release mode 1 = Slow Bus Release mode Cache Burst Mode Enable, Bit 10 0 = Burst Mode disabled 1 = Burst Mode enabled TA Synchronize Select, Bit 11 0 = Not synchronized 1 = Synchronized 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 *0 *0 *0 8 7 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CPD1 CPD0 MS Operating Mode Register Reset = $00030X; X = latched from levels on Mode pins 6 5 SD *0 4 3 2 1 EBD MD MC MB 0 MA * = Reserved, Program as 0 Figure D-2. Operating Mode Register (OMR) 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... Timer Reload Value Timer Load Register Reset = $xxxxxx, value indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TLR0—X:$FFFF8E Write Only TLR1—X:$FFFF8A Write Only TLR2—X:$FFFF86 Write Only 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register Reset = $xxxxxx, value indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TCPR0—X:$FFFF8D Read/Write TCPR1—X:$FFFF89 Read/Write TCPR2—X:$FFFF85 Read/Write 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register Reset = $000000 TCR0—X:$FFFF8C Read Only TCR1—X:$FFFF88 Read Only TCR2—X:$FFFF84 Read Only Figure D-21. Timer Load, Compare, Count Registers (TLR, TCPR, TCR) 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Updated Programming Sheets 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 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