Freescale Semiconductor, Inc. Addendum DSP56321RMAD/D Rev. 4, 7/2003 DSP56321 Reference Manual Addendum Freescale Semiconductor, Inc... CONTENTS 1 Introduction...............1 2 Modified Signal Definitions.................1 3 Operating Mode Register (OMR) Layout and Definition............2 4 Bus Control Register (BCR) Layout and Definition...................3 5 GPIO Signal Names ..5 6 HDR Address.............5 7 SCI Receive Register (SRX) Description .....5 8 Updated Programming Sheets.........................5 1 Introduction This document provides updated information for revision 0 of the DSP56321 Reference Manual (DSP56321RM/D). The updates include the following: • • • • • • • Modified signal definitions for some external bus control, HI08, ESSI, SCI, and timer signals New Operating Mode Register (OMR) layout and bit definitions New Bus Control Register (BCR) layout and bit definitions Updated GPIO signal names Updated HDR address Updated SCI Receive Register (SRX) description Updated Programming sheets for the OMR, BCR, Address Attribute Registers (AAR[3–0]), and Timer Registers (TLR, TCPR, TCR) 2 Modified Signal Definitions Area to Change What’s New? Rev. 4 adds the following update: • Section 6 updates the listed address for the Host Data Register (HDR). Change Description Figure 2-1, p. 2-2 • Change HA10 to HA10 Table 2-8, pp. 2-5 and 2-6 • Change the title of the third column to State During Reset, Stop, or Wait • Change the TA Signal Description to the following: Transfer Acknowledge—If the DSP56321 is the bus master and there is no external bus activity, or the DSP56321 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait states inserted by the bus control register (BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. For correct operation, the TAS bit must be set in the Operating Mode Register (OMR) to synchronize the TA signal with the internal clock. The current bus cycle completes one clock period after TA is deasserted. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR sets the minimum number of wait states in external bus ‘cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion. • Change BR signal State During Reset, Stop, or Wait to: Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) • Change BB signal State During Reset, Stop, or Wait to Ignored input For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Mode Register (OMR) Layout and Definition Freescale Semiconductor, Inc... Area to Change 3 Change Description Table 2-10, pp. 2-8 to 2-10 • Change the title of the third column to State During Reset1,2. • Add note 1 that states: Note: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the keeper circuit maintains the last output level even if the internal driver is tri-stated. • Change the old note 1 to note 2. • Change State During Reset for all signals to Ignored input. • Change the signal description for PB14 to: Port B14—When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed through the HDDR. Table 2-11, pp. 2-11 to 2-12 Table 2-12, pp. 2-13 to 2-14 Table 2-13, p. 2-15 Table 2-14, p. 2-16 • Delete the Stop column • Change the title for the third column to State During Reset 1,2 Change State During Reset for all signals to Ignored input. Note: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the keeper circuit maintains the last output level even if the internal driver is tri-stated. • Change the old note 1 to note 2. Operating Mode Register (OMR) Layout and Definition Area to Change Figure 4-2, p. 4-10 Change Description • Replace with the following figure: Stack Control/Status (SCS) 23 22 21 20 19 18 17 Extended Operating Mode (EOM) 16 15 MSW[2–1] SEN WRP EOV EUN XYS 14 13 12 11 10 9 8 Chip Operating Mode (COM) 7 6 5 APD ABE BRT TAS BE CDP[1–0] MSW0 SD 4 3 2 1 0 EBD MD MC MB MA Reset: 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 * * * * After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA, respectively). Reserved bit. Read as zero; write to zero for future compatibility Figure 4-2. Operating Mode Register (OMR) Area to Change Table 4-3, p. 4-11 Change Description • Replace the first row in the table to the following two rows: 23 22–21 MSW[2–1] 0 Reserved. Write to 0 for future compatibility. 0 Memory Switch Mode Bits 2, 1 Used with bit 7 (MSW0), the three bits configure the internal memory sizes for Program, X-data, and Y-data memory. See Table 3-1 for details. Notes: 1. 2. To ensure proper operation, place six NOP instructions after the instruction that changes the MSW bits. To ensure proper operation, do not change the MSW bits while the Instruction Cache is enabled (SR[CE] bit is set). 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Bus Control Register (BCR) Layout and Definition Area to Change Change Description Table 4-3, p. 4-11 • For bit 15, change the row contents to the following: 15 0 Reserved. Write to 0 for future compatibility. Area to Change Change Description Table 4-3, p. 4-11 Freescale Semiconductor, Inc... 11 • For bit 11, change the row contents to the following: TAS 0 TA Synchronize Select Selects the synchronization method for the input Port A pin—TA (Transfer Acknowledge). For correct operation if TA is used, TAS must be set to synchronize the TA signal with the internal clock. Area to Change Change Description Table 4-3, p. 4-11 7 4 • For bit 7, change the row contents to the following: MSW0 0 Memory Switch Mode Bit 0 Used with bits 22–21 (MSW[2–1]). See bits 22–21 for details. Bus Control Register (BCR) Layout and Definition Area to Change Figure 4-5, p. 4-20 23 22 BRH Change Description • Replace with the following figure: 21 20 19 18 17 16 15 14 13 12 BBS BDFW4 BDFW3 BDFW2 BDFW1 BDFW0 BA3W2 BA3W1 BA3W0 BA2W2 11 10 9 8 7 6 5 4 3 2 1 0 BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1W0 BA0W4 BA0W3 BA0W2 BA0W1 BA0W0 Reserved bit. Read as zero; write to zero for future compatibility Figure 4-5. Bus Control Register (BCR) Area to Change Table 4-7, p. 4-20 Change Description • For bit 22, change the row contents to the following: 0 22 Area to Change Table 4-7, p. 4-20 to 4-21 Reserved. Write to 0 for future compatibility. Change Description • For bits 20–0, change the row contents to the following: 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Bus Control Register (BCR) Layout and Definition 20–16 BDFW[4–0] 11111 Bus Default Area Wait State Control (31 wait states) Defines the number of wait states (one through 31) inserted into each external access to an area that is not defined by any of the AAR registers. The access type for this area is SRAM only. These bits should not be programmed as zero since SRAM memory access requires at least one wait state. When three through seven wait states are selected, one additional wait state is inserted at the end of the access. When selecting eight or more wait states, two additional wait states are inserted at the end of the access. These trailing wait states increase the data hold time and the memory release time and do not increase the memory access time. Freescale Semiconductor, Inc... 15–13 BA3W[2–0] 111 (7 wait states) Bus Area 3 Wait State Control Defines the number of wait states (1–7) inserted in each external SRAM access to Area 3. Area 3 is the area defined by AAR3. Note: Do not program the value of these bits as zero since SRAM memory access requires at least one wait state. When three through seven wait states are selected, one additional wait state is inserted at the end of the access. This trailing wait state increases the data hold time and the memory release time and does not increase the memory access time. 12–10 BA2W[2–0] 111 (7 wait states) Bus Area 2 Wait State Control Defines the number of wait states (1–7) inserted into each external SRAM access to Area 2. Area 2 is the area defined by AAR2. Note: Do not program the value of these bits as zero, since SRAM memory access requires at least one wait state. When three through seven wait states are selected, one additional wait state is inserted at the end of the access. This trailing wait state increases the data hold time and the memory release time and does not increase the memory access time. 9–5 BA1W[4–0] 11111 Bus Area 1 Wait State Control (31 wait states) Defines the number of wait states (1–31) inserted into each external SRAM access to Area 1. Area 1 is the area defined by AAR1. Note: Do not program the value of these bits as zero, since SRAM memory access requires at least one wait state. When three through seven wait states are selected, one additional wait state is inserted at the end of the access. When selecting eight or more wait states, two additional wait states are inserted at the end of the access. These trailing wait states increase the data hold time and the memory release time and do not increase the memory access time. 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GPIO Signal Names 4–0 BA0W[4–0] 11111 Bus Area 0 Wait State Control (31 wait states) Defines the number of wait states (1–31) inserted in each external SRAM access to Area 0. Area 0 is the area defined by AAR0. Note: Do not program the value of these bits as zero, since SRAM memory access requires at least one wait state. Freescale Semiconductor, Inc... When selecting three through seven wait states, one additional wait state is inserted at the end of the access. When selecting eight or more wait states, two additional wait states are inserted at the end of the access. These trailing wait states increase the data hold time and the memory release time and do not increase the memory access time. 5 GPIO Signal Names Area to Change 6 Change Description Figure 6-2, p. 6-7 • Change HRW to HRW. Figure 6-5, p. 6-8 • Change RXD, TXD, SCLK, PE0, PE1, and PE2 to RXD, TXD, SCLK, PE0, PE1, and PE2, respectively. HDR Address Area to Change Figure 7-9, p. 7-16 Change Description • Replace with the following figure: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 7-9. Host Data Register (HDR) (X:$FFFFC9) 7 SCI Receive Register (SRX) Description Area to Change Section 9.6.4.1, p. 9-24 8 Change Description • Change the beginning of the fourth paragraph from “In Synchronous mode” to “In Asynchronous mode”. Updated Programming Sheets In Table B-1, p. B-2 in the DSP56321 User’s Manual, change the Timers rows to the following: Timers Figure B-20, Timer Prescaler Load Register (TPLR) B-32 Figure B-21, Timer Control/Status Register (TCSR) B-33 Figure B-22, Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) B-34 Use the following examples to replace Figure B-2 (p. B-14), Figure B-7 (p. B-19), Figure B-8 (p. B-20), and Figure B-22 (p. B34). 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 2 of 2 Central Processor Chip Operating Mode, Bits 3–0 Refer to the operating modes table in Chapter 4. Asynchronous Bus Arbitration Enable, Bit 13 0 = Synchronization disabled 1 = Synchronization enabled External Bus Disable, Bit 4 0 = Enables external bus 1 = Disables external bus Freescale Semiconductor, Inc... Address Attribute Priority Disable, Bit 14 0 = Priority mechanism enabled 1 = Priority mechanism disabled Stop Delay Mode, Bit 6 0 = Delay is 128K clock cycles 1 = Delay is 16 clock cycless Stack Extension X Y Select, Bit 16 0 = Mapped to X memory 1 = Mapped to Y memory Stack Extension Underflow Flag, Bit 17 0 = No stack underflow 1 = Stack underflow Core-DMA Priority, Bits 9–8 CPD[1:0] Description 00 Compare SR[CP] to active DMA channel priority 01 DMA has higher priority than core 10 DMA has same priority as core 11 DMA has lower priority than core Stack Extension Overflow Flag, Bit 18 0 = No stack overflow 1 = Stack overflow Stack Extension Wrap Flag, Bit 19 0 = No stack extension wrap 1 = Stack extension wrap (sticky bit) Stack Extension Enable, Bit 20 0 = Stack extension disabled 1 = Stack extension enabled Memory Switch Configuration, Bits 22–21, 7 Refer to the memory configurations in Chapter 3. Cache Burst Mode Enable, Bit 10 0 = Burst Mode disabled 1 = Burst Mode enabled TA Synchronize Select, Bit 11 0 = Not synchronized 1 = Synchronized Bus Release Timing, Bit 12 0 = Fast Bus Release mode 1 = Slow Bus Release mode See Bits 22–21 23 *0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 MSW2 MSW1 SEN WRP EOV EUN XYS *0 8 7 6 APD ABE BRT TAS BE CPD1 CPD0 MSW0 SD Operating Mode Register Reset = $00030X; X = latched from the mode pins at reset 5 *0 4 3 2 1 0 EBD MD MC MB MA * = Reserved, Program as 0 Figure B-2. Operating Mode Register (OMR) 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 1 of 2 Bus Interface Unit Freescale Semiconductor, Inc... NOTE: All BCR bits are read/write control bits. Default Area Wait Control, Bits 20–16 Bus Request Hold, Bit 23 Area 3 Wait Control, Bits 15–13 0 = BR pin is asserted only for attempted or pending access Area 2 Wait Control, Bits 12–10 1 = BR pin is always asserted Area 1 Wait Control, Bits 9–5 Area 0 Wait Control, Bits 4– 0 These read/write control bits define the number of wait states inserted into each external SRAM access to the designated area. The value of these bits should not be programmed as zero. Bits Bit Name # of Wait States Bus State, Bit 21 20–16 BDFW[4–0] 0–31 0 = DSP is not bus master 15–13 BA3W[2–0] 0–7 1 = DSP is bus master 12–10 BA2W[2–0] 0–7 9–5 BA1W[4–0] 0–31 4–0 BA0W[4–0] 0–31 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BRH *0 BBS BDFW[4–0] Bus Control Register (BCR) Reset = $1FFFFF BA3W[2–0] BA2W[2–0] 9 8 7 6 BA1W[4–0] 5 4 3 2 1 0 BA0W[4–0] X:$FFFFFB Read/Write * = Reserved, Program as 0 Figure B-7. Bus Control Register (BCR) 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 2 of 2 Bus Interface Unit Bus Packing Enable, Bit 7 0 = Disable internal packing/unpacking logic 1 = Enable internal packing/unpacking logic Freescale Semiconductor, Inc... Bus Y Data Memory Enable, Bit 5 0 = Disable AA pin and logic during external Y data space accesses 1 = Enable AA pin and logic during external Y data space accesses Bus Address to Compare, Bits 23–12 Bus X Data Memory Enable, Bit 4 0 = Disable AA pin and logic during external X data space accesses 1 = Enable AA pin and logic during external X data space accesses BAC[11–0] = address to compare to the external address in order to decide whether to assert the AA pin Bus Program Memory Enable, Bit 3 0 = Disable AA pin and logic during external program space accesses 1 = Enable AA pin and logic during external program space accesses Bus Number of Address Bits to Compare, Bits 11–8 BNC[3–0] = number of bits (from BAC bits) that are compared to the external address Bus Address Attribute Polarity, Bit 2 0 = AA signal is active low 1 = AA signal is active high (Combinations BNC[3–0] = 1111, 1110, 1101 are reserved.) Bus Access Type, Bits 1–0 BAT[1–0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Reserved SRAM access 10 11 Reserved Reserved 7 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC Address Attribute Registers 3 (AAR3) Address Attribute Registers 2 (AAR2) Address Attribute Registers 1 (AAR1) Address Attribute Registers 0 (AAR0) Reset = $000000 Encoding 00 01 6 *0 5 4 3 2 1 0 BYEN BXEN BPEN BAAP BAT1 BAT0 X:$FFFFF6 Read/Write X:$FFFFF7 Read/Write X:$FFFFF8 Read/Write X:$FFFFF9 Read/Write = Reserved, Program as 0 * Figure B-8. Address Attribute Registers (AAR[3–0]) 8 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... Timer Reload Value Timer Load Register (TLR[0–2]) Reset = $xxxxxx, value is indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TLR0—X:$FFFF8E Write Only TLR1—X:$FFFF8A Write Only TLR2—X:$FFFF86 Write Only 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value TCPR0—X:$FFFF8D Read/Write TCPR1—X:$FFFF89 Read/Write TCPR2—X:$FFFF85 Read/Write Timer Compare Register (TCPR[0–2]) Reset = $xxxxxx, value is indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register (TCR[0–2]) Reset = $000000 TCR0—X:$FFFF8C Read Only TCR1—X:$FFFF88 Read Only TCR2—X:$FFFF84 Read Only Figure B-22. Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) 9 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Updated Programming Sheets 10 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 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