Freescale Semiconductor, Inc. Addendum DSP56301UMAD/D Rev. 3, 5/2003 DSP56301 User’s Manual Addendum Freescale Semiconductor, Inc... CONTENTS 1 Introduction...............1 2 Modified Signal Definitions.................1 3 Operating Mode Register (OMR) Definition...................3 4 DMA Control Register 5–0 (DCR[5–0]) Definition...................4 5 SCI Receive Register (SRX) Description .....5 6 Updated Programming Sheets.........................5 1 Introduction This document provides updated information for revision 3 of the DSP56301 User’s Manual (DSP56301UM/D). The updates include the following: • • • • • Modified signal definitions Updated Operating Mode Register (OMR) bit definition Updated DMA Control Register (DCR) bit definition Updated SCI Receive Register (SRX) description Updated Programming sheets for the OMR, Address Attribute Registers (AAR[3–0]), DMA Control Registers 5–0 (DMR[5–0]), Timer Registers (TLR, TCPR, and TCR), and Host Data Direction and Data Registers (DIRH and DATH) 2 Modified Signal Definitions Area to Change Table 2-1, p. 2-1 • For Notes 1–4, delete the last sentence in each note. • Delete Note 5. Figure 2-1, p. 2-2 • In the figure, change Grounds: to Grounds4: • At the bottom of the figure, add the following: 4. The GND signals are listed for the 208-pin TQFP package. For the 252-ball MAP-BGA package, all grounds except GNDP and GNDP1 are connected together and referenced as GND. Table 2-2, p. 2-4 • Add the following note at the end of the table: Note: The subsystem GND signals (GND Q, GNDA, GNDD , GNDN, GNDH, and GNDS) are listed for the 208-pin TQFP package. For the 252-ball MAP-BGA package, all grounds except GNDP and GNDP1 are connected together inside the package and referenced as GND. Table 2-7, p. 2-6 • Delete the last sentence of the signal description for D[0–23]. The DSP56301 does not have internal keeper circuits. Table 2-8, pp. 2-7 and 2-8 • Change the title of the third column to State During Reset, Stop, or Wait • Change BS signal name to BS • Change BR signal State During Reset, Stop, or Wait to: Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) • Change BB signal State During Reset, Stop, or Wait to Ignored input What’s New? See page 2. The note reference for Table 2-12, signal HP31 changed from 2 to 4. Change Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Modified Signal Definitions Freescale Semiconductor, Inc... Area to Change Change Description Table 2-10, pp. 2-10 to 2-14 • Change the title of the third column to State During Reset1,2. • Add the following notes to the end of the table: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • Change State During Reset for all signals to Ignored input. Table 2-12, pp. 2-20 • For Signal HP31, change the note reference after the sentence “Sustained tri-state bidirectional pin.” from 2 to 4. Table 2-13, pp. 2-23 to 2-24 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the last sentence in the signal description. • For all signals, change PCR0 to PCRC and PRR0 to PRRC. Table 2-14, pp. 2-25 to 2-26 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the last sentence in the signal description. • For all signals, change PCR1 to PCRD and PRR1 to PRRD. Table 2-15, p. 2-27 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the last sentence in the signal description. • For all signals, change PCR to PCRE and PRR to PRRE. Table 2-16, p. 2-28 • Change the title for the third column to State During Reset1,2. • Change State During Reset for all signals to Ignored input. • Add notes that state: Notes: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. • For all signals, delete the last sentence in the signal description. 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Mode Register (OMR) Definition 3 Operating Mode Register (OMR) Definition Area to Change Table 4-4, p. 4-14 7 Change Description For bit 7, identify the correct location of the instruction cache memory space by changing the row contents to the following: MS 0 Memory Switch Mode Allows some internal data memory (X, Y, or both) to become part of the chip internal Program RAM. Freescale Semiconductor, Inc... Notes: 1. 2. 3. Program data placed in the Program RAM/Instruction Cache area changes its placement after the OMR[MS] bit is set (that is, the Instruction Cache always uses the highest internal Program RAM addresses). To ensure proper operation, place six NOP instructions after the instruction that changes the MS bit. To ensure proper operation, do not set the MS bit while the Instruction Cache is enabled (SR[CE] bit is set). 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DMA Control Register 5–0 (DCR[5–0]) Definition 4 DMA Control Register 5–0 (DCR[5–0]) Definition Area to Change Table 4-12, p. 4-33 Freescale Semiconductor, Inc... 15–11 DRS[4–0] 0 Change Description For bits 15–11, identify the correct DMA request sources by changing the row contents to the following: DMA Request Source Encodes the source of DMA requests that trigger the DMA transfers. The DMA request sources may be external devices requesting service through the IRQA, IRQB, IRQC and IRQD pins, triggering by transfers done from a DMA channel, or transfers from the internal peripherals. All the request sources behave as edge-triggered synchronous inputs. DRS[4–0] Requesting Device 00000 External (IRQA pin) 00001 External (IRQB pin) 00010 External (IRQC pin) 00011 External (IRQD pin) 00100 Transfer done from channel 0 00101 Transfer done from channel 1 00110 Transfer done from channel 2 00111 Transfer done from channel 3 01000 Transfer done from channel 4 01001 Transfer done from channel 5 01010 ESSI0 receive data (RDF0 = 1) 01011 ESSI0 transmit data (TDE0 = 1) 01100 ESSI1 receive data (RDF1 = 1) 01101 ESSI1 transmit data (TDE1 = 1) 01110 SCI receive data (RDRF = 1) 01111 SCI transmit data (TDRE = 1) 10000 Timer0 (TCF0 = 1) 10001 Timer1 (TCF1 = 1) 10010 Timer2 (TCF2 = 1) 10011–11011 Reserved 11100 Host slave receive data (SRRQ = 1) 11101 Host master receive data (MRRQ = 1) 11110 Host slave transmit data (STRQ = 1) 11111 Host master transmit data (MTRQ = 1) Peripheral requests 18–21 (DRS[4–0] = 111xx) can serve as fast request sources. Unlike a regular peripheral request in which the peripheral can not generate a second request until the first one is served, a fast peripheral has a full duplex handshake to the DMA, enabling a maximum throughput of a trigger every two clock cycles. This mode is functional only in the Word Transfer mode (that is, DTM = 001 or 101). In the Fast Request mode, the DMA sets an enable line to the peripheral. If required, the peripheral can send the DMA a one cycle triggering pulse. This pulse resets the enable line. If the DMA decides by the priority algorithm that this trigger will be served in the next cycle, the enable line is set again, even before the corresponding register in the peripheral is accessed. 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SCI Receive Register (SRX) Description 5 SCI Receive Register (SRX) Description Area to Change Section 8.6.4.1, p. 8-22 6 Change Description Change the beginning of the fourth paragraph from “In Synchronous mode” to “In Asynchronous mode”. Updated Programming Sheets Freescale Semiconductor, Inc... In Table B-1, p. B-2 in the DSP56L307 User’s Manual, change the Timers rows to the following: Timers Figure B-25, Timer Prescaler Load Register (TPLR) B-37 Figure B-26, Timer Control/Status Register (TCSR) B-38 Figure B-27, Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) B-39 Use the following examples to replace Figure B-2 (p. B-14), Figure B-8 (p. B-20), Figure B-9 (p. B-21), Figure B-27 (p. B-39), and Figure B-28 (p. B-40) in the DSP56301 User’s Manual. 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 2 of 2 Central Processor Asynchronous Bus Arbitration Enable, Bit 13 0 = Synchronization disabled 1 = Synchronization enabled Bus Release Timing, Bit 12 0 = Fast Bus Release mode 1 = Slow Bus Release mode External Bus Disable, Bit 4 0 = Enables external bus 1 = Disables external bus Freescale Semiconductor, Inc... Address Attribute Priority Disable, Bit 14 0 = Priority mechanism enabled 1 = Priority mechanism disabled Stop Delay Mode, Bit 6 0 = Delay is 128K clock cycles 1 = Delay is 16 clock cycles Address Trace Enable, Bit 15 0 = Address Trace mode disabled 1 = Address Trace mode enabled Memory Switch Mode, Bit 7 0 = Memory switching disabled 1 = Memory switching enabled Stack Extension X Y Select, Bit 16 0 = Mapped to X memory 1 = Mapped to Y memory Core-DMA Priority, Bits 9–8 CPD[1:0] Description 00 Compare SR[CP] to active DMA channel priority 01 DMA has higher priority than core 10 DMA has same priority as core 11 DMA has lower priority than core Stack Extension Underflow Flag, Bit 17 0 = No stack underflow 1 = Stack underflow Stack Extension Overflow Flag, Bit 18 0 = No stack overflow 1 = Stack overflow Stack Extension Wrap Flag, Bit 19 0 = No stack extension wrap 1 = Stack extension wrap (sticky bit) Stack Extension Enable, Bit 20 0 = Stack extension disabled 1 = Stack extension enabled 23 22 Cache Burst Mode Enable, Bit 10 0 = Burst Mode disabled 1 = Burst Mode enabled TA Synchronize Select, Bit 11 0 = Not synchronized 1 = Synchronized 21 20 19 18 17 16 15 14 13 12 11 10 9 *0 *0 *0 Chip Operating Mode, Bits 3–0 Refer to the operating modes table in Chapter 4. 8 7 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CPD1 CPD0 MS Operating Mode Register Reset = $00030X; X = latched from levels on Mode pins 6 5 SD *0 4 3 2 EBD MD MC 1 0 MB MA * = Reserved, Program as 0 Figure B-2. Operating Mode Register (OMR) 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Bus Interface Unit Bus Packing Enable, Bit 7 0 = Disable internal packing/unpacking logic 1 = Enable internal packing/unpacking logic Freescale Semiconductor, Inc... Bus Y Data Memory Enable, Bit 5 0 = Disable AA pin and logic during external Y data space accesses 1 = Enable AA pin and logic during external Y data space accesses Bus Address to Compare, Bits 23–12 Bus X Data Memory Enable, Bit 4 0 = Disable AA pin and logic during external X data space accesses 1 = Enable AA pin and logic during external X data space accesses BAC[11–0] = address to compare to the external address in order to decide whether to assert the AA pin Bus Program Memory Enable, Bit 3 0 = Disable AA pin and logic during external program space accesses 1 = Enable AA pin and logic during external program space accesses Bus Number of Address Bits to Compare, Bits 11–8 BNC[3–0] = number of bits (from BAC bits) that are compared to the external address Bus Address Attribute Polarity, Bit 2 0 = AA/RAS signal is active low 1 = AA/RAS signal is active high (Combinations BNC[3–0] = 1111, 1110, 1101 are reserved.) Bus Access Type, Bits 1–0 BAT[1–0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Reserved SRAM access 10 11 DRAM access Reserved 7 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC Address Attribute Registers 3 (AAR3) Address Attribute Registers 2 (AAR2) Address Attribute Registers 1 (AAR1) Address Attribute Registers 0 (AAR0) Reset = $000000 Encoding 00 01 6 *0 5 4 3 2 1 0 BYEN BXEN BPEN BAAP BAT1 BAT0 X:$FFFFF6 Read/Write X:$FFFFF7 Read/Write X:$FFFFF8 Read/Write X:$FFFFF9 Read/Write = Reserved, Program as 0 * Figure B-8. Address Attribute Registers (AAR[3–0]) 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Programmer: Application: Sheet 1 of 1 DMA Address Mode, Bits 9–4 Non-Three-Dimensional Addressing Modes (D3D=0) DAM[2–0] = source DAM[5–3] = Destination DMA Interrupt Enable, Bit 22 0 = Disables DMA Interrupt 1 = Enables DMA interrupt DMA Transfer Mode, Bits 21–19 Freescale Semiconductor, Inc... DTM[2:0] Triggered By DE Cleared Transfer Mode 000 001 request request yes yes block transfer word transfer 010 011 request DE yes yes line transfer block transfer 100 101 request request no no block transfer word transfer 110 111 reserved reserved DMA Channel Priority, Bits 18–17 DPR[1:0] Channel Priority 00 01 Priority level 0 (lowest) Priority level 1 10 11 Priority level 2 Priority level 3 (highest) DAM[5–3] DAM[2–0] 000 001 010 011 100 101 110–111 DAM[5–3] 000 001 010 011 100 101 110 111 DRS[4:0] DAM [1–0] 00 01 10 11 External (IRQA, IRQB, IRQC, IRQD) 00100–01001 Transfer done from channel 0,1,2,3,4,5 01010–01011 ESSI0 Receive, Transmit Data 01100–01101 ESSI1 Receive, Transmit Data 01110–01111 SCI Receive, Transmit Data 10000–10010 Timer0, Timer1, Timer2 10011–11011 Reserved 11100–11101 Host Slave/Master Receive Data 11110–11111 Host Slave/Master Transmit Data DTM[2–0] Offset Register Selection DOR0 DOR1 DOR2 DOR3 None None Addressing Mode 2D 2D 2D 2D No update Postincrement-by-1 3D 3D Offset Selection DOR0 DOR1 DOR2 DOR3 None None DOR[0–1] DOR[2–3] Counter DCO Layout Mode C DCOH[23–12] DCOM[11–6] DCOL[5–0] Mode D DCOH[23–18] DCOM[17–6] DCOL[5–0] Mode E DCOH[23–18] DCOM[17–12] DCOL[11–0] — Reserved Requesting Device 00000–00011 DMA Destination Space, Bits 3–2 DSS[1:0] 00 DPR[1–0] DCON DMA Control Registers (DCR5–DCR0) Reset = $000000 DMA Destination Memory X Memory Space 01 10 Y Memory Space P Memory Space 11 Reserved DMA Source Space, Bits 1–0 DSS[1:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DIE Counter Mode B B B B A A Addressing Mode Offset Selection Source: 3D Source: DOR[0–1] Destination: Defined by DAM[5–3] Source: Defined by DAM[5–3] Destination: 3D Destination: DOR[2–3] 1 DMA Request Source, Bits 15–11 Addressing Mode 2D 2D 2D 2D No update Postincrement-by-1 reserved Three-Dimensional Addressing Modes (D3D=1) DAM2 0 DMA Continuous Mode Enable, Bit 16 0 = Disables continuous mode 1 = Enables continuous mode DE DMA Three-Dimensional Mode, Bit 10 0 = Three-Dimensional mode disabled 1 = Three-Dimensional mode enabled DMA Channel Enable, Bit 23 0 = Disables channel operation 1 = Enables channel operation DRS[4–0] D3D 9 8 7 DMA Source Memory 00 01 X Memory Space Y Memory Space 10 11 P Memory Space Reserved 6 5 4 DAM[5–0] 3 2 DDS[1–0] 1 0 DSS[1–0] X:$FFFFD8, X:$FFFFDC, X:$FFFFE0, X:$FFFFE4, X:$FFFFE8, X:$FFFFEC Read/Write Figure B-9. DMA Control Registers 5–0 (DCR[5–0]) 8 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... Timer Reload Value Timer Load Register (TLR[0–2]) Reset = $xxxxxx, value indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TLR0—X:$FFFF8E Write Only TLR1—X:$FFFF8A Write Only TLR2—X:$FFFF86 Write Only 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register Reset = $xxxxxx, value is indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TCPR0—X:$FFFF8D Read/Write TCPR1—X:$FFFF89 Read/Write TCPR2—X:FFFF85 Read/Write 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register Reset = $000000 TCR0—X:$FFFF8C Read Only TCR1—X:$FFFF88 Read Only TCR2—X:$FFFF84 Read Only Figure B-27. Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) 9 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 1 of 4 Freescale Semiconductor, Inc... GPIO Port B (HI32) 23 22 21 20 19 18 17 16 DIR23 DIR22 DIR21 DIR20 DIR19 DIR18 DIR17 DIR16 15 14 13 12 11 10 9 8 DIR15 DIR14 DIR13 DIR12 DIR11 DIR10 DIR9 DIR8 7 6 5 4 3 2 1 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 DSP Host Port GPIO Direction Register (DIRH) Reset: $000000 X:$FFFFCE Read/Write 23 22 21 20 19 18 17 16 DAT23 DAT22 DAT21 DAT20 DAT19 DAT18 DAT17 DAT16 15 14 13 12 11 10 9 8 DAT15 DAT14 DAT13 DAT12 DAT11 DAT10 DAT9 DAT8 7 6 5 4 3 2 1 0 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 DSP Host Port GPIO Data Register (DATH) Reset: $000000 X:$FFFFCF Read/Write DATH and DIRH Functionality DATx DIRx GPIO Pin1 Non-GPIO Pin1 0 Read-only bit. The value read is the binary value of the pin. The corresponding pin is configured as an input. Read-only bit. Does not contain significant data. 1 Read/write bit. The value written is the same as the value read. The corresponding pin is configured as an output, and is driven with the data written to DATx. Read/write bit. The value written is the same as the value read. Note: 1. Defined by the selected mode Figure B-28. Host Data Direction and Host Data Registers (DIRH, DATH) 10 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Updated Programming Sheets 11 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. HOW TO REACH US: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. 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