HFC - S active ISDN Microprocessor (ARM7 based) Preliminary Data Sheet: July 2002 Copyright 1994 - 2002 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by patent or other rights. Cologne Chip products are not designed, intended, or authorized for use in any application intended to support or sustain life, or for any other application in which the failure of the Cologne Chip product could create a situation where personal injury or death may occur. Cologne Chip Cologne Chip AG Eintrachtstrasse 113 D - 50668 K¨oln Germany Tel.: +49 (0) 221 / 91 24-0 Fax: +49 (0) 221 / 91 24-100 http://www.CologneChip.com http://www.CologneChip.de [email protected] 2 of 173 Preliminary Data Sheet July 2002 Contents 1 2 3 General description 15 1.1 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4 Address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CPU, memory and bus interface 2.1 ARM7 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 External bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.2 Asynchronous memory interface (Flash, SRAM, external peripherals) . . . . 31 2.2.3 SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 Boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clocks, timer and interrupt 3.1 3.2 3.3 4 29 39 Clocks of the HFC-S active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.1 Clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.2 Clock frequency selection and clock switching (system clock ). . . . . . 41 3.1.3 Clock frequency selection and clock switching (USB clock) . . . . . . . . . 42 3.1.4 USB clock generation from OSC 1 . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timer modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.1 Timer 1 and Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.2 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.3 PWM counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt processing of the HFC-S active . . . . . . . . . . . . . . . . . . . . . . . 54 3.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.3.2 Register description of the main interrupt controller . . . . . . . . . . . . . . 57 ISDN related modules 61 4.1 FSC-PLL module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1.1 FSC source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.1.2 Functional description of the FSC-PLL . . . . . . . . . . . . . . . . . . . . 63 4.1.3 The constructed FSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 July 2002 Preliminary Data Sheet 3 of 173 4.2 4.3 4.4 4.5 5 S/T-HDLC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.3 State matrices for NT and TE . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.4 Binary organisation of the frame . . . . . . . . . . . . . . . . . . . . . . . . 94 4.2.5 S/T interface circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PCM highway module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.2 Switching buffer mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3.3 Time slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.3.4 Peripheral frame synchronization signals . . . . . . . . . . . . . . . . . . . 100 4.3.5 Enabling a PCM highway . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.3.6 Disabling a PCM highway . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Switching unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.4.1 Source index registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.4.2 Destination codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.4.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 CODEC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.5.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.5.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Interfaces 127 5.1 5.2 5.3 General purpose input and output pins (GPIO) . . . . . . . . . . . . . . . . . . . . . 127 5.1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 UART module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.2.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 USB module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 A HFC-S active package dimensions 159 B Power supply and ground distribution 160 B.1 Digital supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 B.2 Analog supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 C Multiplexer control logic of the PLL 1 block 161 D Examples circuitry for HFC-S active 162 4 of 173 Preliminary Data Sheet July 2002 G General Remarks to Notations 1. Numerical values have different notations for various number systems, e.g. the hexadecimal value 0xC9 is binary ’11001001’ and in decimal notation 201. 2. The first letter of registers and their bit (resp. bitmap) names indicates the typ: ‘R . . . ’ is a register, ‘A . . . ’ is an array-register, ‘V . . . ’ is a bit or bitmap value and ‘M . . . ’ is its bitmap mask, i.e. all bits of the bitmap are set to ’1’. July 2002 Preliminary Data Sheet 5 of 173 List of Figures 1 HFC-S active application overview . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 HFC-S active block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Address space of HFC-S active . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 HFC-S active pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Connecting external memory components to the HFC-S active . . . . . . . . . . . . 31 6 External bus interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 SDRAM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Clock distribution in the HFC-S active . . . . . . . . . . . . . . . . . . . . . . . . 40 9 Programmable PLL 1 block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Programmable PLL 2 block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 Internal structure of the 16 bit Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . 48 12 Internal structure of the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . 49 13 Internal structure of the PWM counter . . . . . . . . . . . . . . . . . . . . . . . . . 49 14 Interrupt control structure of HFC-S active . . . . . . . . . . . . . . . . . . . . . . 55 15 Overview of the FSC signal source selection of the FSC-PLL . . . . . . . . . . . . . 62 16 Overview of the internal structure of the FSC-PLL . . . . . . . . . . . . . . . . . . 63 17 Principle of the phase correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18 Programmable phase position for the FSC signal . . . . . . . . . . . . . . . . . . . . 65 19 Data path configuration options for the S/T-HDLC module . . . . . . . . . . . . . . 70 20 HDLC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 21 FIFO pointer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 22 Frame structure at reference point S and T . . . . . . . . . . . . . . . . . . . . . . . 94 23 The scheme of the PCM highway interface . . . . . . . . . . . . . . . . . . . . . . . 99 24 PCM timing with the configuration shown in table 33 (1st line) . . . . . . . . . . . . 101 25 PCM timing with the configuration shown in table 33 (2nd line) . . . . . . . . . . . 101 26 PCM timing with the configuration shown in table 33 (3rd line) . . . . . . . . . . . . 101 27 Data distribution in the HFC-S active system . . . . . . . . . . . . . . . . . . . . . 117 28 Simplified representation for the primary GPIO[15:0] functionality . . . . . . . . . . 127 29 Logic levels of the UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 30 USB input scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 31 HFC-S active package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 159 32 Clock switching behaviour of PLL multiplexer . . . . . . . . . . . . . . . . . . . . . 161 33 Clock switching behaviour of divider multiplexer . . . . . . . . . . . . . . . . . . . 161 6 of 173 Preliminary Data Sheet July 2002 List of Tables 1 Overview of primary / secondary function pins and committed registers . . . . . . . . 20 3 Overview of the HFC-S active external bus interface pins . . . . . . . . . . . . . . 30 4 Overview of the HFC-S active external bus interface registers . . . . . . . . . . . . 31 5 Recommended values for waitstates programming . . . . . . . . . . . . . . . . . . . 34 6 Overview of the HFC-S active clock pins . . . . . . . . . . . . . . . . . . . . . . . 39 7 Overview of the HFC-S active clock registers . . . . . . . . . . . . . . . . . . . . . 39 8 Suitable values for CNT 1A programming . . . . . . . . . . . . . . . . . . . . . . . 39 9 Suitable values for PLL 2 programming . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Suitable values for CNT 1B programming . . . . . . . . . . . . . . . . . . . . . . . 40 11 Suitable values for PLL 1 programming (DIV 1 disabled) . . . . . . . . . . . . . . . 42 12 Overview of the HFC-S active timer pins . . . . . . . . . . . . . . . . . . . . . . . 47 13 Overview of the HFC-S active timer registers . . . . . . . . . . . . . . . . . . . . . 47 14 Overview of the HFC-S active interrupt pins . . . . . . . . . . . . . . . . . . . . . 54 15 Overview of the HFC-S active interrupt registers . . . . . . . . . . . . . . . . . . . 54 16 Bit numbering of the interrupt sub-controller . . . . . . . . . . . . . . . . . . . . . . 55 17 Bit names of the interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 18 Overview of the HFC-S active FSC-PLL pins . . . . . . . . . . . . . . . . . . . . . 61 19 Overview of the HFC-S active FSC-PLL registers . . . . . . . . . . . . . . . . . . 61 20 Overview of the HFC-S active S/T-HDLC pins . . . . . . . . . . . . . . . . . . . . 69 21 Overview of the HFC-S active S/T-HDLC registers . . . . . . . . . . . . . . . . . . 69 22 Control field organization of the HDLC mode . . . . . . . . . . . . . . . . . . . . . 71 23 Bitmap description of the FIFO transmit status . . . . . . . . . . . . . . . . . . . . . 76 24 Bitmap description of the FIFO receive status (B1- and B2-channel) . . . . . . . . . 76 25 Bitmap description of the FIFO receive status (D-channel) . . . . . . . . . . . . . . 77 26 Activation / deactivation layer 1 for finite state matrix for NT . . . . . . . . . . . . . 92 27 Activation / deactivation layer 1 for finite state matrix for TE . . . . . . . . . . . . . 93 28 S/T module part numbers and manufacturers (part 1) . . . . . . . . . . . . . . . . . 95 29 S/T module part numbers and manufacturers (part 2) . . . . . . . . . . . . . . . . . 96 30 Overview of the HFC-S active PCM highway pins . . . . . . . . . . . . . . . . . . 97 31 Overview of the HFC-S active PCM highway registers . . . . . . . . . . . . . . . . 97 32 Name mapping between PCM interface pins and IOM-2 abbreviations . . . . . . . . 98 33 Configuration settings for the timing examples in figures 24 to 26 . . . . . . . . . . . 101 34 Overview of the HFC-S active switching unit registers . . . . . . . . . . . . . . . . 117 35 Source registers of the switching unit . . . . . . . . . . . . . . . . . . . . . . . . . . 118 36 Destination codes of the switching unit . . . . . . . . . . . . . . . . . . . . . . . . . 119 37 Overview of GPIO functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 38 Baud rate programming values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 July 2002 Preliminary Data Sheet 7 of 173 39 Bitmap description of the UART transmit FIFO status . . . . . . . . . . . . . . . . . 143 40 Bitmap description of the UART receive FIFO status . . . . . . . . . . . . . . . . . 143 41 Overview of the HFC-S active USB pins . . . . . . . . . . . . . . . . . . . . . . . 145 42 Overview of the HFC-S active USB registers . . . . . . . . . . . . . . . . . . . . . 145 43 Power supply and ground pins of the digital subsystems . . . . . . . . . . . . . . . . 160 44 Power supply and ground pins of the mixed signal subsystems . . . . . . . . . . . . 160 8 of 173 Preliminary Data Sheet July 2002 List of Registers (sorted by name) The first letter of the register names indicates the typ: ‘R . . . ’ is a register, ‘A . . . ’ is an arrayregister. The index of array-registers is either the FIFO, channel or slot which has to be specified in the appropriate register. July 2002 Address Width 0x00080040 0x000D000C 0x000B01E0 0x000D0004 0x000D0008 0x000D0000 0x00080028 0x00080000 0x00080008 0x00090030 0x00090034 0x00090028 0x00090014 0x00090024 0x00080030 0x00090020 0x00080034 0x00090018 0x0009001C 0x0008002C 0x000B0210 0x000B0204 0x000B00C0 0x000B0120 0x000B0020 0x000B01E8 0x000B0100 0x000B0000 0x000B0208 0x000B00E0 0x000B0160 0x000B0060 0x000B01EC 0x000B0140 0x000B0040 0x000B020C 0x000B01C0 0x000B01A0 0x000B00A0 0x000B01F0 0x000B0180 0x000B0080 0x00080004 0x0008000C 0x00080038 0x000B0200 0x000B01F4 16 32 32 32 32 32 32 16 16 32 32 16 32 32 32 32 16 32 32 32 32 16 32 32 32 32 32 32 16 32 32 32 32 32 32 16 32 32 32 32 32 32 16 16 8 8 16 Name R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R CNT1B CFG CODEC CTRL CODEC IDX CODEC RX CODEC RX8 CODEC TX DIV1 CFG FIQ CTRL FIQ STATUS FSC CFG FSC CONST FSC IRQ GPIO CFG GPIO CTRL1 GPIO CTRL2 GPIO IN1 GPIO IN2 GPIO IRQ CTRL GPIO OUT GPO CTRL HW SL CNT HW1 CTRL HW1 IDX HW1 RX CUR HW1 RX LAST HW1 TS EN HW1 TX CUR HW1 TX NEXT HW2 CTRL HW2 IDX HW2 RX CUR HW2 RX LAST HW2 TS EN HW2 TX CUR HW2 TX NEXT HW3 CTRL HW3 IDX HW3 RX CUR HW3 RX LAST HW3 TS EN HW3 TX CUR HW3 TX NEXT IRQ CTRL IRQ STATUS OSC CFG PCM CFG PFS0 CFG Preliminary Data Sheet Mode r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Page 46 125 121 123 124 123 45 57 59 67 68 66 129 131 133 130 130 129 130 132 116 111 120 105 103 107 105 103 113 120 106 104 107 106 104 115 120 107 105 108 106 104 58 60 45 110 108 9 of 173 10 of 173 Address Width 0x000B01F6 0x000B01F8 0x000B01FA 0x00080020 0x00080024 0x0009000C 0x00080010 0x000C0038 0x000C0028 0x000C00F0 0x000C001C 0x000C00F4 0x000C0014 0x000C000C 0x000C0048 0x000C003C 0x000C0030 0x000C00F8 0x000C0020 0x000C00FC 0x000C0000 0x000C00DC 0x000C0044 0x000C00C4 0x000C00C8 0x000C00CC 0x000C0040 0x000C0010 0x000C0018 0x000C0034 0x000C0100 0x000C004C 0x000C0024 0x000C0104 0x000C0108 0x000B01E4 0x000C00C0 0x000C0008 0x000C00D0 0x000C0004 0x000C00C0 0x00090004 0x00090010 0x0009002C 0x00090000 0x000A0010 0x000A0020 0x000A0024 0x000A0028 0x000A002C 0x000A0020 0x000A0000 0x000A0004 0x000A0008 0x000A000C 16 16 16 32 32 32 16 16 32 8 32 8 32 32 32 16 32 8 32 8 32 8 8 8 8 8 16 16 16 32 8 16 32 8 8 16 8 32 8 32 8 32 32 32 32 16 32 8 8 32 32 32 32 32 32 Name R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R PFS1 CFG PFS2 CFG PFS3 CFG PLL1 CFG PLL2 CFG PWM CFG SDRAM CTRL ST B1 CRC ST B1 RX FIFO ST B1 RX ST B1 TX FIFO ST B1 TX ST B12 IRQ EN ST B12 IRQ STATUS ST B12 STATUS ST B2 CRC ST B2 RX FIFO ST B2 RX ST B2 TX FIFO ST B2 TX ST CFG ST CLK CTRL ST CTRL ST CTRL1 ST CTRL2 ST CTRL3 ST D CRC ST D FIFO STATUS ST D IRQ EN ST D RX FIFO ST D RX ST D STATUS ST D TX FIFO ST D TX ST E RX ST IDX ST RD STATES ST RX STATUS ST SQ MF ST TX STATUS ST WR STATES TIMER CFG1 TIMER CFG2 TIMER PRELD TIMER UART BAUD UART CFG UART CLR UART ECHO UART IRQ CFG UART PREVIEW UART RX1 UART RX2 UART RX3 UART RX4 Preliminary Data Sheet Mode r/w r/w r/w r/w r/w r/w r/w, r r/w r/w r r/w w r/w r/w r r/w r/w r r/w w r/w w r/w w w w r/w r/w r/w r/w r r r/w w r r/w r r r/w, r, w r w r/w r/w r/w r/w w w w r/w r/w r r r r r Page 108 109 109 44 44 52 36 81 80 90 79 90 78 77 84 82 81 90 79 90 72 89 83 87 88 88 82 78 78 81 91 84 80 91 91 121 85 74 89 74 86 51 53 50 50 138 139 140 140 144 142 140 141 141 142 July 2002 July 2002 Address Width 0x000A0024 0x000A0000 0x000A0004 0x000A0008 0x000A000C 0x000E0000 0x000E0004 0x000E0008 0x0008003C 0x000E000C 0x000E0014 0x000E0010 0x000E0018 0x000E0038 0x000E0034 0x000E0044 0x000E0058 0x000E005C 0x000E0030 0x000E004C 0x000E003C 0x000E0028 0x000E0024 0x000E0040 0x000E0050 0x000E0054 0x000E0020 0x000E0048 0x000E002C 0x00090008 0x00080018 0x0008001C 32 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 32 32 8 8 8 8 8 8 8 32 8 8 8 32 32 32 Name Mode Page R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R r w w w w r/w r/w, r r/w r/w, r r r r/w r/w r/w w r/w, r r/w r/w r/w r/w r r/w r r/w, r r r/w r/w r/w r r/w r/w r/w 143 137 137 137 138 147 148 148 147 149 150 150 151 154 153 155 157 158 153 156 154 152 151 155 157 157 151 156 152 51 37 38 UART STATUS UART TX1 UART TX2 UART TX3 UART TX4 USB ADDR USB CFG USB CTRL USB DRV USB EV1 USB EV2 USB EVMSK1 USB EVMSK2 USB ICMD USB IDATA USB IEP EN USB IEP EV USB IEP EVMSK USB IEP SEL USB IEP STALL USB ISTATUS USB OCMD USB ODATA USB OEP EN USB OEP EV USB OEP EVMSK USB OEP SEL USB OEP STALL USB OSTATUS WD WS1 WS2 Preliminary Data Sheet 11 of 173 List of Registers (sorted by address) The first letter of the register names indicates the typ: ‘R . . . ’ is a register, ‘A . . . ’ is an arrayregister. The index of array-registers is either the FIFO, channel or slot which has to be specified in the appropriate register. 12 of 173 Address Width 0x00080000 0x00080004 0x00080008 0x0008000C 0x00080010 0x00080018 0x0008001C 0x00080020 0x00080024 0x00080028 0x0008002C 0x00080030 0x00080034 0x00080038 0x0008003C 0x00080040 0x00090000 0x00090004 0x00090008 0x0009000C 0x00090010 0x00090014 0x00090018 0x0009001C 0x00090020 0x00090024 0x00090028 0x0009002C 0x00090030 0x00090034 0x000A0000 0x000A0000 0x000A0004 0x000A0004 0x000A0008 0x000A0008 0x000A000C 0x000A000C 0x000A0010 0x000A0020 0x000A0020 0x000A0024 0x000A0024 0x000A0028 0x000A002C 0x000B0000 0x000B0020 16 16 16 16 16 32 32 32 32 32 32 32 16 8 8 16 32 32 32 32 32 32 32 32 32 32 16 32 32 32 32 16 32 16 32 16 32 16 16 32 32 32 8 8 32 32 32 Name Mode Page R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R r/w r/w r/w r/w r/w, r r/w r/w r/w r/w r/w r/w 57 58 59 60 36 37 38 44 44 45 132 133 130 45 147 46 50 51 51 52 53 129 129 130 130 131 66 50 67 68 140 137 141 137 141 137 142 138 138 142 139 143 140 140 144 103 103 FIQ CTRL IRQ CTRL FIQ STATUS IRQ STATUS SDRAM CTRL WS1 WS2 PLL1 CFG PLL2 CFG DIV1 CFG GPO CTRL GPIO CTRL2 GPIO IN2 OSC CFG USB DRV CNT1B CFG TIMER TIMER CFG1 WD PWM CFG TIMER CFG2 GPIO CFG GPIO IRQ CTRL GPIO OUT GPIO IN1 GPIO CTRL1 FSC IRQ TIMER PRELD FSC CFG FSC CONST UART RX1 UART TX1 UART RX2 UART TX2 UART RX3 UART TX3 UART RX4 UART TX4 UART BAUD UART PREVIEW UART CFG UART STATUS UART CLR UART ECHO UART IRQ CFG HW1 TX NEXT HW1 RX LAST Preliminary Data Sheet r r/w r/w, r r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r w r w r w r w w r w r w r/w r/w r/w r/w July 2002 July 2002 Address Width 0x000B0040 0x000B0060 0x000B0080 0x000B00A0 0x000B00C0 0x000B00E0 0x000B0100 0x000B0120 0x000B0140 0x000B0160 0x000B0180 0x000B01A0 0x000B01C0 0x000B01E0 0x000B01E4 0x000B01E8 0x000B01EC 0x000B01F0 0x000B01F4 0x000B01F6 0x000B01F8 0x000B01FA 0x000B0200 0x000B0204 0x000B0208 0x000B020C 0x000B0210 0x000C0000 0x000C0004 0x000C0008 0x000C000C 0x000C0010 0x000C0014 0x000C0018 0x000C001C 0x000C0020 0x000C0024 0x000C0028 0x000C0030 0x000C0034 0x000C0038 0x000C003C 0x000C0040 0x000C0044 0x000C0048 0x000C004C 0x000C00C0 0x000C00C0 0x000C00C4 0x000C00C8 0x000C00CC 0x000C00D0 0x000C00DC 0x000C00F0 0x000C00F4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 32 32 32 16 16 16 16 8 16 16 16 32 32 32 32 32 16 32 16 32 32 32 32 32 32 16 16 16 8 32 16 8 8 8 8 8 8 8 8 8 Name R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R HW2 TX NEXT HW2 RX LAST HW3 TX NEXT HW3 RX LAST HW1 IDX HW2 IDX HW1 TX CUR HW1 RX CUR HW2 TX CUR HW2 RX CUR HW3 TX CUR HW3 RX CUR HW3 IDX CODEC IDX ST IDX HW1 TS EN HW2 TS EN HW3 TS EN PFS0 CFG PFS1 CFG PFS2 CFG PFS3 CFG PCM CFG HW1 CTRL HW2 CTRL HW3 CTRL HW SL CNT ST CFG ST TX STATUS ST RX STATUS ST B12 IRQ STATUS ST D FIFO STATUS ST B12 IRQ EN ST D IRQ EN ST B1 TX FIFO ST B2 TX FIFO ST D TX FIFO ST B1 RX FIFO ST B2 RX FIFO ST D RX FIFO ST B1 CRC ST B2 CRC ST D CRC ST CTRL ST B12 STATUS ST D STATUS ST RD STATES ST WR STATES ST CTRL1 ST CTRL2 ST CTRL3 ST SQ MF ST CLK CTRL ST B1 RX ST B1 TX Preliminary Data Sheet Mode r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r w w w w r/w, r, w w r w Page 104 104 104 105 120 120 105 105 106 106 106 107 120 121 121 107 107 108 108 108 109 109 110 111 113 115 116 72 74 74 77 78 78 78 79 79 80 80 81 81 81 82 82 83 84 84 85 86 87 88 88 89 89 90 90 13 of 173 14 of 173 Address Width 0x000C00F8 0x000C00FC 0x000C0100 0x000C0104 0x000C0108 0x000D0000 0x000D0004 0x000D0008 0x000D000C 0x000E0000 0x000E0004 0x000E0008 0x000E000C 0x000E0010 0x000E0014 0x000E0018 0x000E0020 0x000E0024 0x000E0028 0x000E002C 0x000E0030 0x000E0034 0x000E0038 0x000E003C 0x000E0040 0x000E0044 0x000E0048 0x000E004C 0x000E0050 0x000E0054 0x000E0058 0x000E005C 8 8 8 8 8 32 32 32 32 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 32 32 Name Mode Page R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R r w r w r r/w r r r/w r/w r/w, r r/w r r/w r r/w r/w r r/w r r/w w r/w r r/w, r r/w, r r/w r/w r r/w r/w r/w 90 90 91 91 91 123 123 124 125 147 148 148 149 150 150 151 151 151 152 152 153 153 154 154 155 155 156 156 157 157 157 158 ST B2 RX ST B2 TX ST D RX ST D TX ST E RX CODEC TX CODEC RX CODEC RX8 CODEC CTRL USB ADDR USB CFG USB CTRL USB EV1 USB EVMSK1 USB EV2 USB EVMSK2 USB OEP SEL USB ODATA USB OCMD USB OSTATUS USB IEP SEL USB IDATA USB ICMD USB ISTATUS USB OEP EN USB IEP EN USB OEP STALL USB IEP STALL USB OEP EV USB OEP EVMSK USB IEP EV USB IEP EVMSK Preliminary Data Sheet July 2002 General description 1 General description 1.1 System overview The HFC-S active is a single-chip solution for ISDN telecommunication applications. The device is designed for the following applications: ISDN telephones with / without data port ISDN PABX and ISDN POTS terminal adapters ISDN USB terminal adapters ISDN RS 232 terminal adapters various other ISDN applications by using external peripherals (e.g. ISDN LAN router) USB RS232 PCM Highway S/T-ISDN Interface TE / NT Mode HFC-S active ISDN Microprocessor Flash SRAM SDRAM Peripherals (3.3V QFP 160) LCD-Display Handsfree 1 2 3 4 5 6 7 8 9 * 0 # Handset Keypad Figure 1: HFC-S active application overview July 2002 Preliminary Data Sheet 15 of 173 General description 1.2 Features The HFC-S active contains a powerful 32 bit ARM7 RISC controller with a 32 bit address space operating at up to 61.440 MHz under worst case commercial conditions. Internal 16 kbyte SRAM (zero wait states) Supports 8 / 16 bit SRAM / Flash and 16 bit external SDRAM memory Advanced SDRAM controller with minimum wait states (full column burst mode) 5 independent external address spaces with software programmable wait state generation Full I.430 ITU S/T ISDN support in TE and NT mode Integrated ISDN S/T-controller with B- and D-channel HDLC support 6 independent read and write HDLC-controllers for B1-, B2- and D-channel B1-, B2- and D-channel transparent mode independently selectable Integrated FIFOs with 64 byte per channel and direction 2 integrated audio CODECs for the connection of analog devices (e.g. phone, fax, answering machine in PABX applications or handset in telephone applications) 3 independently programmable PCM highways with programmable switching unit between the 3 x 32 PCM highway channels (time slots), the B1- and B2-channels of the S/T-interface and the 2 CODECs Integrated high speed RS 232 interface (UART) with programmable data rate from 1.2 kbaud to 230.4 kbaud (theoretical maximum data rate: 1/8 of the system frequency ) ROM code for UART boot option integrated Full speed 12 Mbps Universal Serial Bus (USB) interface integrated compliant to USB specification 1.1 with – – – – – – – 4 input data endpoints with 64 byte FIFO each 4 output data endpoints with 64 byte FIFO each Bidirectional control endpoint with 16 byte FIFO per direction On-chip USB transceiver Control, interrupt and bulk transfer types Bidirectional half-duplex link Serial bus interface engine with packet decoding / generation, CRC generation and checking, NRZI encoding / decoding and bit-stuffing 2 programmable 16 bit timers with 8 bit prescaler with interrupt capability 10 bit programmable pulse width modulator (PWM) with interrupt capability Watchdog timer with interrupt capability and reset generation capability Up to 31 GPIO pins, 16 of these with interrupt capability Flexible and efficient interrupt processing for all system modules 3.3 V CMOS technology operation temperature range 0 Æ C . . . 70 Æ C PQFP 160 case 16 of 173 Preliminary Data Sheet July 2002 General description 1.3 Functional description The HFC-S active is an ISDN telecommunication microprocessor system on a single chip (SoC). It is based on a powerful 32 bit ARM7 RISC processor with 16 bit and 32 bit instruction set. This industrial standard processor includes on-chip debugging facilities (embedded ICE). The HFC-S active includes a 16 kbyte high speed memory, a S/T interface with layer 1 and layer 2 functions for the D-, B1- and B2-channel, a full speed USB-interface and a standard RS 232 interface. The CPU can boot from external Flash or from the RS 232 interface. The following block diagram illustrates the powerful architecture of the HFC-S active. HFC - S active 2x HDLC D-Channel TM D-transmit D-receive ARM7 TDMI CPU (32 Bit) JTAG Debug FIFOs B2-receive PCM30 PCM30 PCM30 PCM30 PCM30 Peripheral Bus (32 Bit) CODEC G. 711 USB a/b GPIO e.g. Keypad, LC-Display PWM PWM Output UART RS232 CODEC G. 711 External Bus Interface SDRAM, Flash, SRAM (16 Bit Data, 22 Bit Address) PCM30 B1-receive B2-transmit USB S/ T 4x HDLC B-Channel B1-transmit Bridge ROM 6x 64 Byte System Bus (32 Bit) SRAM (4K x 32) S/TController a/b Figure 2: HFC-S active block diagram The integrated CODECs allow the connection to telephone hand-sets or POTS ports e.g. for PABX applications. The CODECs have a programmable power-down mode. A processor controlled power management is supported. The programmable PLL allows to vary the system clock speed in the range from 12.288 MHz to 61.440 MHz. 1.4 Address space The HFC-S active has an internal 4 k x 32 SRAM (16 kbyte) with the address range from 0x00000 to 0x3FFF. The address area 0x00000 to 0x0001F is reserved for exception handlers like shown in figure 3. The remaining SRAM can be used by application programs. The internal ROM is divided into two sections: An 8 kbyte ROM which contains the first level boot loader and the 512 kbyte I/O area where the HFC-S active registers are located. External SRAM, FLASH, SDRAM and peripherals are located at the address areas shown in figure3. All other addresses are not used with the HFC-S active. July 2002 Preliminary Data Sheet 17 of 173 General description 32 bit adress: 0 x 0000 0000 0 x 0000 001C adress space System Handler SRAM 16 KB 0 x 0000 3FFC 0 x 0000 4000 14 Bit not used 16 KB 0 x 0000 3FFC 0 x 0000 4000 not used 32 KB 0 x 0000 FFFF 0 x 0000 4000 not used 64 KB 0 x 0000 FFFF 0 x 0000 4000 ROM 0 x 0002 1FFC 0 x 0002 2000 not used 0 x 0003 FFFC 0 x 0004 0000 8 KB 120 KB 13 Bit 128 KB ext. SRAM 0 x 0007 FFFF 0 x 0008 0000 0 x 000F FFFF 0 x 0010 0000 256 KB Adr_Sys Adr_Low_Lev Adr_Uart Adr_PCM_HW Adr_S0_HDLC Adr_Codec Adr_USB not Used 0 x 0000 8000 - 0 x 0000 8FFC 0 x 0000 9000 - 0 x 0000 9FFC 0 x 0000 A000 - 0 x 0000 AFFC 0 x 0000 B000 - 0 x 0000 BFFC 0 x 0000 C000 - 0 x 0000 CFFC 0 x 0000 D000 - 0 x 0000 DFFC 0 x 0000 E000 - 0 x 0000 EFFC 0 x 0000 F000 - 0 x 0000 FFFC 18 Bit I/O 8x64 KB = 512 KB 8x16 Bit 19 Bit ext. peripherals 0 x 001F FFFF 0 x 0020 0000 1 MB 20 Bit 2 MB 21 Bit ext. Flash 2 0 x 003F FFFF 0 x 0040 0000 ext. Flash 1 0 x 007F FFFF 0 x 0080 0000 4 MB 22 Bit 8 MB 23 Bit ext. SDRAM 0 x 00FF FFFF 0 x 0100 0000 not used 0 x FFFF FFFC Figure 3: Address space of HFC-S active 18 of 173 Preliminary Data Sheet July 2002 General description 1.5 Pin description 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GPIO[7] / PFS[3] GPIO[8] / WD GPIO[9] / FSC_TE GPIO[10] / ?? GPIO[11] / ?? GPIO[12] / STCLOCK GND VCC TxD / GPIO[25] RxD / GPIO[24] FSC2 / NRTS BSCK2 / NCTS GND VCC SDO2 / GPIO[23] SDI2 / GPIO[22] FSC1 / GPIO[21] BSCK1 / GPIO[20] SDO1 / GPIO[19] SDI1 / GPIO[18] PFS0 PFS1 PFS2 PFS3 FSC0 BSCK0 SDO0 SDI0 VCC GND GPIO[13] GPIO[14] / DK_REP GPIO[15] / EOFT GPIO[16] GPIO[17] / CLK_OUT ADJ_LEV R1 LEV_R1 LEV_R2 R2 Pins with primary / secondary function are marked in figure 4. Table 1 shows an overview of these pins. The initial value of the register bits select always the primary function. The bit value has to be toggled to switch to the secondary function of the corresponding pin. HFC-S active ISDN Processor Cologne Chip week code 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TX1_LO TX2_LO TX2_HI NTX_EN TX1_HI GPI[0] DN DP GND VCC DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DQMU / NBE[1] GND CLK_SD CKE_SD VCC DATA[0] DATA[1] GND DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DQML / NBE[0] NOE NWE_SD NCAS NRAS NWE VCC GND GPIO[0] / CARRY1 NRES XNTRST XTDI XTMS XTCLK XTDO NTESTMODE ADR[20] / GPO[2] ADR[21] / GPO[3] ADR[17] ADR[18] / GPO[0] ADR[19] / GPO[1] ADR[11] ADR[12] ADR[13] ADR[14] GND ADR[15] ADR[16] VCC ADR[4] ADR[5] GND ADR[6] ADR[7] ADR[8] ADR[9] VCC GND ADR[10] ADR[3] ADR[2] ADR[1] ADR[0] /CS5 /CS4 /CS3 /CS2 /CS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GPIO[6] / PFS[2] 121 GPIO[5] / PFS[1] 122 XTALOUT12 123 XTALIN12 124 GND 125 GND 126 GND 127 FILTER_PLL12 128 VCC_PLL12 129 VDDD_PLL12 130 VCC_CODEC2 131 REFH2 132 REFL2 133 GND 134 APOSTOUT2 135 VREFOUT2 136 AMODIN2 137 AINFB2 138 VCC 139 GND 140 AINFB1 141 AMODIN1 142 VREFOUT1 143 APOSTOUT1 144 GND 145 REFH1 146 REFL1 147 VCC_CODEC1 148 VDDD_PLL12_288 149 VCC_PLL12_288 150 TER_PLL12_288 151 GND 152 GND 153 GND 154 XTALIN_12_288 155 XTALOUT_12_288 156 GPIO[4] / PFS[0] 157 GPIO[3] / ?? 158 GPIO[2] / PWM_OUT 159 GPIO[1] / CARRY[2] 160 Figure 4: HFC-S active pinout July 2002 Preliminary Data Sheet 19 of 173 General description Table 1: Overview of primary / secondary function pins and committed registers Pin number Primary function Secondary function Register name Bit name 1 CARRY1 GPIO0 R GPIO CTRL1 V GPIO0 TI1 9 A20 GPO2 R GPO CTRL V GPO2 EN 10 A21 GPO3 R GPO CTRL V GPO3 EN 12 A18 GPO0 R GPO CTRL V GPO0 EN 13 A19 GPO1 R GPO CTRL V GPO1 EN 86 CLK OUT GPIO17 R GPIO CTRL2 V GPIO17 CNT1B 88 EOFT GPIO15 R GPIO CTRL1 V GPIO15 EOFT 89 DK REP GPIO14 R GPIO CTRL1 V GPIO14 DKREP 90 DK EN GPIO13 R GPIO CTRL1 V GPIO13 DKEN 101 SDI1 GPIO18 R GPIO CTRL2 V GPIO18 EN 102 SDO1 GPIO19 R GPIO CTRL2 V GPIO19 EN 103 BCLK1 GPIO20 R GPIO CTRL2 V GPIO20 EN 104 FSC1 GPIO21 R GPIO CTRL2 V GPIO21 EN 105 SDI2 GPIO22 R GPIO CTRL2 V GPIO22 EN 106 SDO2 GPIO23 R GPIO CTRL2 V GPIO23 EN 109 BCLK2 /CTS R GPIO CTRL2 V NCTS EN 110 FSC2 /RTS R GPIO CTRL2 V NRTS EN 111 RXD GPIO24 R GPIO CTRL2 V GPIO24 EN 112 TXD GPIO25 R GPIO CTRL2 V GPIO25 EN 115 CLK ST GPIO12 R GPIO CTRL1 V GPIO12 CNT1A 116 CLK EXT GPIO11 R GPIO CTRL1 V GPIO11 CNT1B GPIO10 R GPIO CTRL1 V GPIO10 FSC CONST 117 118 FSC TE GPIO9 R GPIO CTRL1 V GPIO9 FSC ST 119 WDT GPIO8 R GPIO CTRL1 V GPIO8 WD 120 PFS3 GPIO7 R GPIO CTRL1 V GPIO7 PFS3 121 PFS2 GPIO6 R GPIO CTRL1 V GPIO6 PFS2 122 PSF1 GPIO5 R GPIO CTRL1 V GPIO5 PFS1 157 PFS0 GPIO4 R GPIO CTRL1 V GPIO4 PFS0 GPIO3 R GPIO CTRL1 V GPIO3 FSC 158 159 PWM OUT GPIO2 R GPIO CTRL1 V GPIO2 PWM 160 CARRY2 GPIO1 R GPIO CTRL1 V GPIO1 TI2 20 of 173 Preliminary Data Sheet July 2002 General description Pin 1 Function Name I/O Description 1st function 2nd function CARRY1 GPIO0 O I/O timer 1 carry signal general purpose put / output in- LVCMOS 2 /RES I chip reset (active low) LVCMOS 3 /XTRST I test reset (active low) LVCMOS (PU) 4 XTDI I test data input LVCMOS (PU) 5 XTMS I test mode select LVCMOS (PU) 6 XTCLK I test clock LVCMOS (PU) 7 XTDO O test data output 8 DVCC 4 (SL) 2 (tri) digital power supply 9 1st function 2nd function A20 GPO2 O O external address bus general purpose output 8 8 10 1st function 2nd function A21 GPO3 O O external address bus general purpose output 8 8 A17 O external address bus 8 11 12 1st function 2nd function A18 GPO0 O O external address bus general purpose output 8 8 13 1st function 2nd function A19 GPO1 O O external address bus general purpose output 8 8 14 A11 O external address bus 8 15 A12 O external address bus 8 16 A13 O external address bus 8 17 A14 O external address bus 8 18 DGND 19 A15 O external address bus 8 20 A16 O external address bus 8 21 DVCC 22 A4 O external address bus 8 23 A5 O external address bus 8 24 DGND 25 A6 O external address bus 8 26 A7 O external address bus 8 27 A8 O external address bus 8 digital ground digital power supply digital ground (continued on next page) July 2002 Preliminary Data Sheet 21 of 173 General description (continued from previous page) Pin Function Name I/O Description 28 A9 29 DVCC digital power supply 30 DGND digital ground 31 A10 O external address bus 8 32 A3 O external address bus 8 33 A2 O external address bus 8 34 A1 O external address bus 8 35 A0 O external address bus 8 36 /CS5 O chip select for external SDRAM (active low) 8 37 /CS4 O chip select for external peripherals (active low) 8 38 /CS3 O chip select for external Flash 2 (active low) 8 39 /CS2 O chip select for external Flash 1 (active low) 8 40 /CS1 O chip select for external SRAM (active low) 8 41 DGND digital ground 42 DVCC digital power supply 43 /WE O write strobe for external asynchronous memories (active low) O 44 /RAS O row address strobe for the external SDRAM (active low) 8 45 /CAS O column address strobe for the external SDRAM (active low) 8 46 /WE SD O write strobe for the SDRAM (active low) 8 47 /OE O output enable for external asynchronous memories (active low) 8 48 DQML O low byte write mask for SDRAM 8 49 D7 I/O external data bus LVCMOS 8 50 D6 I/O external data bus LVCMOS 8 51 D5 I/O external data bus LVCMOS 8 O external address bus 8 (continued on next page) 22 of 173 Preliminary Data Sheet July 2002 General description (continued from previous page) Pin Function Name I/O Description 52 D4 I/O external data bus LVCMOS 8 53 D3 I/O external data bus LVCMOS 8 54 D2 I/O external data bus LVCMOS 8 55 DGND 56 D1 I/O external data bus LVCMOS 8 57 D0 I/O external data bus LVCMOS 8 58 DVCC 59 CKE SD O clock enable for SDRAM 8 60 CLK SD O clock for SDRAM 8 61 DGND 62 DQMU 63 D8 I/O external data bus LVCMOS 8 64 D9 I/O external data bus LVCMOS 8 65 D10 I/O external data bus LVCMOS 8 66 D11 I/O external data bus LVCMOS 8 67 D12 I/O external data bus LVCMOS 8 68 D13 I/O external data bus LVCMOS 8 69 D14 I/O external data bus LVCMOS 8 70 D15 I/O external data bus LVCMOS 8 71 DVCC digital power supply 72 DGND digital ground 73 USB+ I/O differential (positive) USB port USB USB 74 USB- I/O differential (negative) USB port USB USB 75 GPI0 I general purpose input pin 76 TX1 HI O transmit port (high) for the S/T interface S/T 77 /TX EN O transmit enable port S/T 78 TX2 HI O transmit port (high) for the S/T interface S/T 79 TX2 LO O transmit port (low) for the S/T interface S/T digital ground digital power supply digital ground O high byte write mask for SDRAM 8 LVCMOS (PD) (continued on next page) July 2002 Preliminary Data Sheet 23 of 173 General description (continued from previous page) Pin Function Name I/O Description 80 TX1 LO O transmit port (low) for the S/T interface 81 R2 I receive port for the S/T interface S/T 82 LEV R2 I level detect for R2 S/T 83 LEV R1 I Level detect for R1 S/T 84 R1 I receive port for the S/T interface S/T 85 ADJ LEV 86 1st function 2nd function 87 88 89 90 S/T adjust level control for the S/T interface S/T CLK OUT GPIO17 O I/O system clock general purpose put / output pin in- LVCMOS 4 (SL) GPIO16 I/O general purpose put / output pin in- LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) 1st function EOFT 2nd function GPIO15 I/O 1st function DK REP O 2nd function GPIO14 I/O 1st function DK EN O 2nd function GPIO13 I/O O EOFT signal of the S/T interface general purpose input / output pin DK REP signal of the S/T interface general purpose input / output pin DK EN signal of the S/T interface general purpose input / output pin 91 DGND digital ground 92 DVCC digital power supply 93 SDI0 I serial data input for PCM highway 1 94 SDO0 O serial data output for PCM highway 1 2 (tri) 95 BCLK0 O bit clock for PCM highway 1 2 (tri) 96 FSC0 I/O frame sync signal for PCM highway 1 97 PFS3 O peripheral frame sync signal 2 98 PFS2 O peripheral frame sync signal 2 LVCMOS LVCMOS 2 (tri) (continued on next page) 24 of 173 Preliminary Data Sheet July 2002 General description (continued from previous page) Pin I/O 99 PFS1 O peripheral frame sync signal 2 100 PFS0 O peripheral frame sync signal 2 1st function SDI1 I 2nd function GPIO18 serial data input for PCM highway 2 general purpose input / output 1st function SDO1 2nd function GPIO19 I/O 1st function BCLK1 O 2nd function GPIO20 I/O 1st function FSC1 I/O 2nd function GPIO21 I/O 1st function SDI2 2nd function GPIO22 1st function SDO2 2nd function GPIO23 102 103 104 105 106 I/O O I I/O O I/O Description Name 101 Function serial data output for PCM highway 2 general purpose input / output bit clock for PCM highway 2 general purpose input / output frame sync signal for PCM highway 2 general purpose input / output serial data input for PCM highway 3 general purpose input / output serial data output for PCM highway 3 general purpose input / output 107 DVCC digital power supply 108 DGND digital ground 109 110 111 112 1st function BCLK2 O 2nd function /CTS I 1st function FSC2 I/O 2nd function /RTS O 1st function RXD I 2nd function GPIO24 1st function TXD 2nd function GPIO25 113 DVCC I/O O I/O bit clock for PCM highway 2 CTS signal (UART) LVCMOS 2 LVCMOS 2 LVCMOS 2 (tri) LVCMOS 2 LVCMOS 2 (tri) LVCMOS 2 LVCMOS 2 (tri) LVCMOS 2 LVCMOS 2 LVCMOS 2 LVCMOS 2 (tri) LVCMOS 2 LVCMOS 2 (tri) frame sync signal for PCM highway 3 RTS signal (UART) serial receive (UART) general purpose put / output data serial transmit (UART) general purpose put / output data 2 (tri) LVCMOS 2 LVCMOS 2 in- in- digital power supply (continued on next page) July 2002 Preliminary Data Sheet 25 of 173 General description (continued from previous page) Pin Function 116 117 118 119 120 121 122 I/O DGND 114 115 Name Description digital ground 1st function 2nd function CLK ST GPIO12 1st function CLK EXT 2nd function GPIO11 I/O 1st function 2nd function GPIO10 O I/O 1st function FSC TE O 2nd function GPIO9 I/O 1st function WDT 2nd function GPIO8 I/O 1st function PFS3 O 2nd function GPIO7 I/O 1st function PFS2 O 2nd function GPIO6 I/O 1st function PSF1 O 2nd function GPIO5 I/O O I/O O O S/T clock general purpose put / output in- clock for external devices ( ) general purpose input / output general purpose put / output in- FSC TE signal of the S/T interface general purpose input / output carry signal of the watchdog timer general purpose input / output peripheral frame sync 3 signal with interrupt capability general purpose input / output peripheral frame sync 2 signal with interrupt capability general purpose input / output peripheral frame sync 1 signal with interrupt capability general purpose input / output 123 XTALOUT2 O Output for the USB quartz oscillator 124 XTALIN2 I Input for the USB quartz oscillator 125 DGND digital ground 126 AGND analog / digital power 127 AGND analog ground 128 C PLL2 PLL filter capacitance 129 AVCC PLL2 analog power supply LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) LVCMOS 4 (SL) XTAL XTAL sub-bias analog analog (continued on next page) 26 of 173 Preliminary Data Sheet July 2002 General description (continued from previous page) Pin Function Name I/O Description 130 DVCC PLL2 digital power supply 131 AVCC CODEC2 analog power supply 132 REFH1 analog 133 REFL1 analog 134 AGND 135 APOSTOUT1 analog 136 VREFOUT1 analog 137 AMODIN1 138 AINFB1 139 DVCC CODEC digital power supply 140 DGND digital ground 141 AINFB0 142 AMODIN0 143 VREFOUT0 analog 144 APOSTOUT0 analog 145 AGND 146 REFH0 147 REFL0 148 AVCC CODEC1 analog power (+3.3V) 149 DVCC PLL1 digital power supply 150 AVCC PLL1 analog power supply 151 C PLL1 152 AGND analog ground 153 AGND analog / digital power 154 DGND digital ground 155 XTALIN1 156 XTALOUT1 157 analog ground (0.0V) analog analog analog analog analog ground (0.0V) analog analog analog analog sub-bias XTAL XTAL 1st function PFS0 O 2nd function GPIO4 I/O peripheral frame sync 0 signal with interrupt capability general purpose input / output LVCMOS 4 (SL) (continued on next page) July 2002 Preliminary Data Sheet 27 of 173 General description (continued from previous page) Pin Function Name I/O 158 1st function 2nd function GPIO3 O I/O 1st function 2nd function PWM OUT GPIO2 O I/O 1st function 2nd function CARRY2 GPIO1 O I/O 159 160 Description general purpose put / output in- LVCMOS 4 (SL) PWM output general purpose put / output in- LVCMOS LVCMOS 4 (SL) 4 (SL) Timer 2 carry signal general purpose put / output in- LVCMOS 4 (SL) Legend: SL: slew rate controlled output pad OD: open drain output pad tri: tristate output pad PU: pullup resistor integrated in input pad 28 of 173 Preliminary Data Sheet July 2002 CPU, memory and bus interface 2 CPU, memory and bus interface 2.1 ARM7 CPU The HFC-S active is based on the ARM7 TDMI processor core revision 1b 1 , which is a member of the Advanced RISC Machines (ARM) family of general purpose 32 bit microprocessors. The ARM7 TDMI offers high performance at a very low power consumption and cost. The ARM7 architecture is based on Reduced Instruction Set Computer (RISC) principles. The instruction set and related decode mechanisms are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory system can operate continuously. Typically, while one instruction is being executed, its successor is being decoded and a third instruction is being fetched from memory. The ARM7 memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic. These control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs. The HFC-S actives ARM7 CPU including its bus interface is fixed to little endian mode. Misaligned memory access should always be avoided. The internal memory and external asynchronous memory round down to the next aligned address. The SDRAM controller replaces an unaligned access by several memory accesses, but at page boundaries there might be unexpected results. The access to not used memory areas returns undefined values. More about the ARM7 TDMI CPU can be looked up on the following WWW sites: http://www.arm.com/Documentation/UserMans/PDF/ARM7TDMI.html 2.2 External bus interface 2.2.1 Overview The HFC-S active contains a versatile interface for external memories. Up to four external memory components can be connected at the same time and one additional address region is reserved for external peripheral chips or I/O expansions. The external memory bus is 16 bit wide and allows to connect 8 bit and 16 bit memory components or external peripheral devices, except the SDRAM which has always 16 bit bus width. The software can set the number of waitstates and the bus width (8 / 16 bit) for each address area individually. Five chip select signals are generated for the following purposes: 1 SDRAM of up to 4 M x 16 (8 Mbyte / 64 Mbit) 1 Flash of up to 4 M x 8 or 2 M x 16 (4 Mbyte / 32 Mbit) 1 Flash of up to 2 M x 8 or 1 M x 16 (2 Mbyte / 16 Mbit) 1 ARM7 TDMI is a registered trademark of ARM Ltd. July 2002 Preliminary Data Sheet 29 of 173 CPU, memory and bus interface Table 3: Overview of the HFC-S active external bus interface pins ( : Primary function) Number Name Number Description Name Description 35 A0 57 D0 34 A1 56 D1 33 A2 54 D2 32 A3 53 D3 22 A4 52 D4 23 A5 51 D5 25 A6 50 D6 26 A7 49 D7 27 A8 63 D8 28 A9 64 D9 31 A10 65 D10 14 A11 66 D11 15 A12 67 D12 16 A13 68 D13 17 A14 69 D14 19 A15 70 D15 20 A16 11 A17 47 /OE 12 A18 output enable for external asynchronous memories (active low) 13 A19 43 /WE 9 A20 10 A21 write strobe for external asynchronous memories (active low) 60 CLK SD clock for SDRAM 40 /CS1 chip select for external SRAM (active low) 59 CKE SD clock enable for SDRAM 39 /CS2 chip select for external Flash 1 (active low) 46 /WE SD write strobe for the SDRAM (active low) 38 /CS3 chip select for external Flash 2 (active low) 45 /CAS column address strobe for the external SDRAM (active low) 37 /CS4 chip select for external peripherals (active low) 44 /RAS row address strobe for the external SDRAM (active low) 36 /CS5 chip select for external SDRAM (active low) 62 DQMU high byte write mask for SDRAM 48 DQML low byte write mask for SDRAM external address bus external data bus 1 SRAM of up to 256 k x 8 or 128 k x 16 (256 kbyte / 2 Mbit) 1 area for external peripherals of up to 1 M x 8 or 512 k x 16 (1 Mbyte / 8 Mbit) Table 3 shows all pins of the HFC-S active which are in the context of chapter 2.2. For applications requiring more external SRAM memory, the areas for SRAM and external peripherals can be swapped by swapping the chip select signals (allowing 1 Mbyte of SRAM). 30 of 173 Preliminary Data Sheet July 2002 CPU, memory and bus interface Table 4: Overview of the HFC-S active external bus interface registers 0x0008001C R WS2 38 0x00080010 R SDRAM CTRL 36 A[11:0] A[18:0] DQ[15:0] DQ[15:0] 16 DATA[15:0] A[16:0] A A[15:0] D[15:0] D SRAM 64k x 16 e.g. TC55V1664B CS 128k x 8 e.g. 29LV010B DQMU DQML Flash 2 DQML 512k x 16 e.g. 29LV800B DQ[7:0] DQMU /Be1 UB UB /Be0 LB OE WE LB OE WE /CK Chip Select Generator Asynchr. Memory Interface [15:0] [16:0] [11:0] Addr. Mapper Addr. Counter Data Lane Ctrl. 22 ADR[21:0] [7:0] /Be0 Flash 1 SDRAM Controller /CAS /RAS SDRAM CLK CKE WE CAS RAS CLK_SD CKE_SD /WE_SD /OE /WE OE WE OE WE CS CS CS I/O ... e.g. I/O Expansion 37 [18:0] R WS1 /Be1 ARM7 Page 0x00080018 1M x 16 e.g. MB 81F161622B HFC-S active memory interface Name Any Peripherals Address CS /Cs5 /Cs2 /Cs3 /Cs1 /Cs4 Figure 5: Connecting external memory components to the HFC-S active (example) Flash memory, SRAM and external peripherals can be connected via the asynchronous memory interface which is described in section 2.2.2. The SDRAM needs additional control signals. A detailled description of the SDRAM controller can be found in section 2.2.3. Figure 5 shows an example schematic with the connection of one SDRAM, one 16 bit Flash, one 8 bit Flash and one SRAM to the HFC-S active. Due to the used RAM sizes which are smaller than the maximum sizes, the shown address ranges are underutilized in this example. The SDRAM address is a 12 bit multiplexed signal for alternate row and column address. 2.2.2 Asynchronous memory interface (Flash, SRAM, external peripherals) 8 / 16 bit bus width options The asynchronous memory interface generates /OE and /WE signals at the pins 47 and 43 that allow direct interfacing to external Flash, SRAM and peripheral devices. July 2002 Preliminary Data Sheet 31 of 173 CPU, memory and bus interface For all external components except the SDRAM (which is always 16 bit wide), a bus width of 8 bit or 16 bit can be selected individually. 32 bit, 16 bit and 8 bit read and write access is fully supported on 16 bit memories as well as on 8 bit memories. If the access size is greater than the memory size, the internal logic of HFC-S active will perform 2 or 4 memory access cycles with automatic address incrementing and data lane selection. External 16 bit memories should be connected to the external address bus bits A[n:0] as the internal ARM7 address bits A[n+1:1] are shifted down by one bit by the internal logic for each access to an external 16 bit memory. This allows an optimum usage of the address signals. When writing an 8 bit data byte to a 16 bit memory, data qualifier signals2 (DQMU, DQML at pins 62, 48) are generated to mask the 8 data bits that should not be written. Waitstates programming The number of waitstates can be selected individually for each external component, except the SDRAM (which always operates at the maximum frequency) in order to comply with the different timing of the memory components and peripherals. For a selected number of waitstates, the access time for one memory access cycle will be ARM7 clock periods. If the ARM7 access size is greater than the memory size, the total access time will be 2 or 4 times the access time for a single memory access cycle because 2 or 4 memory accesses are performed. The total number of clock cycles used for a memory access can be determined as follows (for waitstates selected): clock cycles, a 16 bit access on an 8 bit memory takes clock cycles (2 memory accesses of 8 bit), a 32 bit access on an 8 bit memory takes clock cycles (4 memory accesses of 8 bit), an 8 bit access on a 16 bit memory takes clock cycles, a 16 bit access on a 16 bit memory takes clock cycles, a 32 bit access on a 16 bit memory takes clock cycles (2 memory accesses of 16 bit), a register access (32 bit) takes clock cycles, an 8 bit access on an 8 bit memory takes a 32 bit access on the internal SRAM and ROM is always performed without wait states. Some internal modules of the HFC-S active have also a wait states programming register. The internal SRAM, the S/T interface, The CODECs and the USB interface have indepent waitstates bitmaps in the register R WS2, while all other modules have the same waitstates value. Larger waitstates values might be useful to reduce the CPU load. External bus interface timing The example in figure 6 shows a 16 bit read access on an external 8 bit Flash component with 2 waitstates, followed by a 16 bit write access to the same external 8 bit Flash component with 2 waitstates. Please note that the total access time is 6 clock cycles in this case (access 2 words of 8 bit; 2 waitstates = 3 clock cycles for each access). For a high performance system, a Flash with 16 bit data bus and 0 waitstates could be used (if available), allowing a single cycle access. 2 DQM: Data I/O Mask, DQMU: Upper byte of Data I/O Mask, DQML: Lower byte of Data I/O Mask 32 of 173 Preliminary Data Sheet July 2002 CPU, memory and bus interface 16 bit - read from 8-bit Flash 1 2 waitstates 16 bit - write to 8-bit Flash 2 Flash pause 2 waitstates 2 waitstates 2 waitstates CLK Addr1 ADR Addr1 +1 Addr2 Addr2 +1 Data from HFC-S active Data from HFC-S active NOE NWE Data from memory DATA Data from memory NCS2 NCS3 Figure 6: External bus interface timing diagram (example with 2 programmed waitstates cycles) Avoiding bus contention (Flash pause) As some Flash devices have a very long data bus release time (/OE high to output HIGH-Z), a pause (delay) can be programmed in order to avoid bus contention on the bidirectional external data bus (bitmap V WS FLASH DL in register R WS1). In figure 6, this pause is 2 clock cycles. It can be programmed in the range of 0 . . . 3 cycles. The delay is only inserted between a read access cycle from the external Flash and a write access to any external memory and only when it is necessary to avoid bus contention. For example, if the two clock cycles following the Flash read are used for internal memory access, no delay is inserted. In the case of one internal cycle between a Flash read and a Flash write, only one wait cycle will be inserted in the case that a number of 2 cycles has been selected. It is recommended to use the waitstates shown in table 5. 2.2.3 SDRAM controller The HFC-S active has an advanced SDRAM controller which supports all SDRAMs with max. 8 MByte capacity, 16 bit data bus, and CAS 3 latency = 2. The main feature of the SDRAM controller is the full column burst mode. The full column burst mode is controlled by the SEQ signal of the ARM7 CPU indicating sequential memory access 3 CAS: Column Address Strobe July 2002 Preliminary Data Sheet 33 of 173 CPU, memory and bus interface Table 5: Recommended values for waitstates programming Register Bitmap Recommended Value R WS2 R WS2 R WS1 V WS ST V WS CODEC V WS PCM not less than R WS2 V WS USB not less than R WS2 V WS SRAM V WS GEN should always be 0 R WS1 V V V V WS WS WS WS FLASH1 FLASH2 EXTIO SRAM ½ ½ depends on the access time of the external memory / peripheral devices operations. This feature increases the software performance by typically, if the program is running from the external SDRAM. The SDRAM controller is clock-controlled by the system clock (ARM7 clock). After a system reset the SDRAM controller initialization sequence starts automatically. At the end of the initialization process the V SDRAM RDY bit of the register R SDRAM CTRL is automatically set to 1. The software has to take care that no access on the external bus is carried out during the SDRAM initialization. The software can switch the SDRAM to a power down mode to reduce the power consumption of the ISDN application by setting V SDRAM EN in the R SDRAM CTRL register. SDRAM interface timing The SDRAM interface timing is shown in figure 7. CLK NRAS t ras_cas 1 clock period NCAS ADR Row Address Column Address Column Address Column Address Column Address Figure 7: SDRAM interface timing 34 of 173 Preliminary Data Sheet July 2002 CPU, memory and bus interface 2.3 Boot loader The First Level Boot Loader is a small programm at ROM address 0x20000 which will always be started after a system reset. It decides about the boot program address. 1. If there is the magic number 0x46352413 found at address 0x00040000 (FLASH bank 1), the boot program is expected from address 0x00040004 and will be startet at once. The magic number is not a valid instruction code. 2. If the magic number is not found, the HFC-S active waits for seriell data at the RS 232 port with a fixed baud rate of Note, that the system clock is always equal to the quartz frequency at this time. The received data is stored from address 0x00000400 (internal SRAM) and is started afterwards. 3. If there are no seriell data for one second, the boot loader terminates the wait loop and starts the program from address 0x00040000. Note, that in this case there is no magic number at the beginning of the FLASH bank 1. July 2002 Preliminary Data Sheet 35 of 173 CPU, memory and bus interface 2.4 Register description R SDRAM CTRL (read / write, read) 0x00080010 SDRAM control register Bits Reset Name Description M SDRAM MO Shows the setting of the SDRAM mode register (reserved) Must be set to 0 Value 11..0 0x27 12 13 0 V SDRAM RDY Indicates the end of the SDRAM initialization ’0’ = SDRAM not ready ’1’ = SDRAM ready 14 0 V SDRAM EN Activates the SDRAM controller ’0’ = power up ’1’ = power down 15 0 V BURST EN Activates the full column burst mode ’0’ = disabled ’1’ = enabled Note: Word accesses have to be word aligned on the page boundary. 36 of 173 Preliminary Data Sheet July 2002 CPU, memory and bus interface R WS1 (read / write) 0x00080018 1st waitstates register and bus width control for the external bus interface Bits Reset Name Description Value 3..0 2 V WS FLASH1 Sets the waitstates for the external Flash bank 1 ( clock cycles) 7..4 0xF V WS FLASH2 Sets the waitstates for the external Flash bank 2 ( clock cycles) 11..8 0xF V WS EXTIO Sets the waitstates for the external peripherals ( clock cycles) (reserved) 15..12 19..16 0xF V WS SRAM Sets the waitstates for the external SRAM ( clock cycles) 24..20 0x0F V WS PCM Sets the waitstates for the PCM highway ( clock cycles) 25 0 V FLASH1 WORD Sets the data bus width for the external Flash bank 1 ’0’ = 8 bit ’1’ = 16 bit 26 0 V FLASH2 WORD Sets the data bus width for the external Flash bank 2 ’0’ = 8 bit ’1’ = 16 bit 27 1 V EXTIO WORD Sets the data bus width for the external peripherals ’0’ = 8 bit ’1’ = 16 bit 28 0 V SRAM WORD Sets the data bus width for the external SRAM ’0’ = 8 bit ’1’ = 16 bit 30..29 0 V WS FLASH DL Sets the delay between Flash read access and write access (0 . . . 3 clock cycles) 31 July 2002 (reserved) Preliminary Data Sheet 37 of 173 CPU, memory and bus interface R WS2 (read / write) 0x0008001C 2nd waitstates register Bits Reset Name Description Value 4..0 0x02 V WS ST Sets the waitstates for the S/T HDLC module ( clock cycles) 8..5 0 V WS SRAM Sets the waitstates for the internal SRAM ( clock cycles) 11..9 0 V WS GEN Sets the waitstates for all other interfaces ( clock cycles) 17..12 0x00 V WS USB Sets the waitstates for the USB interface ( clock cycles) 21..18 0 V WS CODEC Sets the waitstates for the CODEC ( clock cycles) 31..22 38 of 173 (reserved) Preliminary Data Sheet July 2002 Clocks, timer and interrupt 3 Clocks, timer and interrupt 3.1 Clocks of the HFC-S active Table 6: Overview of the HFC-S active clock pins (all primary function) Number Name Description CLK OUT system clock 115 CLK ST S/T clock 116 CLK EXT clock for external devices ( ) 86 Table 7: Overview of the HFC-S active clock registers Address 3.1.1 Name Page 0x00080020 R PLL1 CFG 44 0x00080024 R PLL2 CFG 44 0x00080028 R DIV1 CFG 45 Address Name Page 0x00080038 R OSC CFG 45 0x00080040 R CNT1B CFG 46 Clock distribution The HFC-S active contains a versatile clock distribution circuit including two crystal oscillators, two PLLs, a clock divider and two modulo counters for the generation of several, individually programmable clock frequencies from one or two external crystals. Section 3.1.4 shows a circuitry example which needs only one external crystal to put all subsystems into operation. Figure 8 illustrates, how the functional blocks of the HFC-S active clock distribution work together. As the crystal frequencies are not prescribed, frequency values are only pointed out where they are fixed by specification requirements. Table 8: Suitable values for CNT 1A programming System clock Table 9: Suitable values for PLL 2 programming CNT 1A Crystal PLL 2 frequency M N frequency P M S 12.288 MHz 1 1 8.000 MHz 4 64 1 24.576 MHz 1 2 12.000 MHz 7 64 1 36.864 MHz 1 3 12.288 MHz 14 117 1 49.152 MHz 1 4 16.000 MHz 10 64 1 61.440 MHz 1 5 24.576 MHz 30 117 1 Programmable system clock ×Ý× : The crystal which is connected to the OSC 1 block is used as a reference for the programmable frequency of the ARM7 CPU and some other subsystems like shown in figure 8. By using the PLL 1 and the divider DIV 1, the input frequency can be July 2002 Preliminary Data Sheet 39 of 173 Clocks, timer and interrupt CNT1B MOD counter FOUT FIN OSC1 PLL1 6 P 8 M M N 8 M 8 N P M 6 OSC2 8 7.68 MHz or 12.288 MHz or 24.576 MHz fSYS DIV1 2 S external devices ARM 7 Bus Interface Clocks Timers Interrupt FSC PLL GPIO UART CNT1A 10 N MOD counter FOUT FIN EN fEXT M N S 2 fISDN M N M N 8 M 8 N 12.288 MHz fUSB PLL2 48.000 MHz CODEC ISDN - S/T PCM - HW Switching Unit USB Figure 8: Clock distribution in the HFC-S active Table 10: Suitable values for CNT 1B programming System clock frequency frequency M N 7.680 MHz 5 8 12.288 MHz 1 1 24.576 MHz 2 1 7.680 MHz 5 16 12.288 MHz 1 2 24.576 MHz 1 1 7.680 MHz 5 24 12.288 MHz 1 3 24.576 MHz 2 3 7.680 MHz 5 32 12.288 MHz 1 4 24.576 MHz 2 1 7.680 MHz 1 8 12.288 MHz 1 5 24.576 MHz 2 5 12.288 MHz 24.576 MHz 36.864 MHz 49.152 MHz 61.440 MHz 40 of 173 CNT 1B Preliminary Data Sheet July 2002 Clocks, timer and interrupt scaled up or down flexibly over a very wide frequency range from some kHz to 49.152 MHz. A detailed describtion of the generation is given in section 3.1.2. 12.288 MHz clock for ISDN related peripheral modules: Some peripheral modules of the HFC-S active like shown in figure 8 have to operate at a fixed frequency due to fixed data rate requirements. In order to allow interfacing to the ARM7 CPU, the clock skew between and the ARM7 clock has to be nearly zero. As the clock phase of the PLL output relative to the PLL input is uncontrollable, the original crystal frequency cannot be used to derive a clock signal for these modules. These hardware limitations have been solved by implementing the programmable modulo counter CNT 1A. Some examples and the matching counter parameters are listed in table8 4 . The clock jitter of the modulo counter CNT 1A is max. in clock period. For an input frequency with an integer , the clock jitter is zero as the modulo counter behaves like a divider. 7.68 MHz / 12.288 MHz / 24.576 MHz clock for external S/T transceivers ICs: Besides the usage of additional, external Cologne Chip ISDN S/T controllers (such like HFC-S mini), the HFC-S active also supports the use of simple ISDN transceiver ICs with lower functional integration. For the connection of such external S/T transceiver ICs to the HFC-S active, a synchronization frequency of 7.68 MHz, 12.288 MHz or 24.576 MHz is required. The modulo counter CNT 1B has been implemented to generate this frequency. Tabel 10 shows some suitable programming parameters for several system frequencies. Due to the sophisticated dual slope design of this counter, the clock jitter of the output frequency is only max. in clock period. For an input frequency with an integer , the clock jitter is zero. 48.000 MHz clock for USB controller: The crystal which is connected to the OSC 2 block is only used to generate a frequency of 48.000 MHz needed for the USB controller. Crystals of different frequencies can be used to generate as the PLL is programmable. A detailed describtion of the generation is given in section 3.1.3. 3.1.2 Clock frequency selection and clock switching (system clock ) The PLL block includes a crystal oscillator, the programmable PLL 1 and the programmable divider DIV 1. The PLL requieres an external capacitor of 820 pF. The frequency scaling ratio of the PLL and the divider can be selected by parameters as shown in figure9. In addition, the PLL can be turned off (V PLL1 PWRDN=1) to save energy. The PLL and the divider can be selected or bridged by multiplexers individually. One multiplexer can select the PLL output (V PLL1 SEL = 1) or the original oscillator frequency (V PLL1 SEL = 0). As the clock phase of the PLL output relative to the PLL input is uncontrollable, the multiplexer is synchronized to the clock signals to avoid short clock pulses (spikes). For detailed timing information see appendix C. For bridging the programmable divider after the PLL, a second multiplexer can select the divider output (V DIV1 SEL = 1) or the PLL multiplexer output (V DIV1 SEL = 0). Suitable parameters for the PLL 1 block and DIV 1 block are given in table 11. Most PLL output frequencies can be achieved with various PLL parameter sets. It is recommended to select the shown PLL parameters to ensure a stable operation. 4 Typically, for both counters CNT 1A and CNT 1B there are several parameter sets which result in the same output frequency. In these cases one should prefer small values for M and N. July 2002 Preliminary Data Sheet 41 of 173 820pF Filter 0 PLL1 FIN FOUT 0 DIV1 FOUT FIN 1 1 OSC1 PWRDN = FOUT (M + 8) 2S (P + 2) 6 P 8 M FIN 2 S = 1 2 (N + 1) 10 N DIV1_SEL FIN PLL1_SEL FOUT ARM7 system clock (fsys ) Clocks, timer and interrupt Figure 9: Programmable PLL 1 block Table 11: Suitable values for PLL 1 programming (DIV 1 disabled) Crystal desired frequency system clock P M S 12.288 MHz 5 78 24.576 MHz 5 36.864 MHz 8.000 MHz 12.000 MHz 12.288 MHz PLL 1 Crystal desired frequency system clock P M S 3 12.288 MHz 19 121 3 78 2 24.576 MHz 19 121 2 7 75 1 36.864 MHz 21 98 1 49.152 MHz 5 78 1 49.152 MHz 19 121 1 61.440 MHz 9 161 1 61.440 MHz 23 184 1 12.288 MHz 14 123 3 12.288 MHz 16 64 3 24.576 MHz 14 123 2 24.576 MHz 16 64 2 36.864 MHz 12 78 1 36.864 MHz 16 46 1 49.152 MHz 14 123 1 49.152 MHz 16 64 1 61.440 MHz 15 166 1 61.440 MHz 16 82 1 12.288 MHz 7 64 3 24.576 MHz 7 64 2 36.864 MHz 7 46 1 49.152 MHz 7 64 1 61.440 MHz 7 82 1 16.000 MHz 24.576 MHz PLL 1 As the system clock is also the input signal for the modulo counters CNT 1A and CNT 1B, possible system clock frequencies are restricted by the requiered counter output frequencies. 3.1.3 Clock frequency selection and clock switching (USB clock) The PLL 2 block includes a crystal oscillator and the programmable PLL 2 (see fig. 10). The PLL requieres an external capacitor of 820 pF. For details of the PLL and PLL multiplexer please refer to 42 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt 820pF 48 MHz USB clock (fUSB ) the previous section. Some practicable crystal frequencies and the matching PLL 2 parameters are shown in table 9. Filter 0 PLL2 FIN FOUT 1 OSC2 FIN OSC2_EN PWRDN = (M + 8) 2S (P + 2) 6 P 8 M 2 S PLL1_SEL FOUT Figure 10: Programmable PLL 2 block In addition to the PLL 2 block, the crystal oscillator OSC 2 can be turned off (V OSC2 EN = 0) to save energy. A multiplexer allows to switch the OSC 2 signal directly to the output with the setting V PLL2 SEL = 0. 3.1.4 USB clock generation from OSC 1 The USB clock can be derived from the OSC 1 crystal, if the second crystal connected to OSC 2 shall be saved. As there is no internal signal path between OSC 1 and OSC 2 resp. and , the OSC 1 output (pin XTALOUT1) must be connected to OSC 2 input (pin XTALIN2). Some exmaples of practicable PLL 2 parameters are given in Table 9. July 2002 Preliminary Data Sheet 43 of 173 Clocks, timer and interrupt 3.1.5 Register description R PLL1 CFG (read / write) 0x00080020 Configuration register for the PLL 1 (system clock) Bits Reset Name Description Value 7..0 0x00 V PLL1 M multiplier M for PLL 1 (range 0 . . . 255) 13..8 0x00 V PLL1 P divider P for PLL 1 (range 0 . . . 63) 15..14 0 V PLL1 S divider S for PLL 1 (range 0 . . . 3) 25..16 0x000 V DIV1 N divider N for DIV 1 (range 0 . . . 1023) 26 1 V PLL1 PWRDN set the PLL 1 in power down mode ’0’ = power on ’1’ = power down (reserved) 31..27 R PLL2 CFG (read / write) 0x00080024 Configuration register for the PLL 2 (USB clock) Bits Reset Name Description Value 7..0 0x00 V PLL2 M multiplier M for PLL 2 (range 0 . . . 255) 13..8 0x00 V PLL2 P divider P for PLL 2 (range 0 . . . 63) 15..14 0 V PLL2 S divider S for PLL 2 (range 0 . . . 3) (reserved) 25..16 26 1 31..29 44 of 173 sets the PLL 2 in power down mode ’0’ = power on ’1’ = power down (reserved) 27 28 V PLL2 PWRDN 0 V PLL2 SEL selects the PLL 2 ’0’ = inactive ’1’ = active (reserved) Preliminary Data Sheet July 2002 Clocks, timer and interrupt R DIV1 CFG (read / write) 0x00080028 Configuration register for the predivider of the system clock generation Bits Reset Name Description Value 7..0 1 V CNT1A M multiplier for the modulo-counter CNT 1A (range 0 . . . 255) 15..8 1 V CNT1A N divider for the modulo-counter CNT 1A (range 1 . . . 255) 16 0 V PLL1 SEL selects the PLL 1 ’0’ = inactive ’1’ = active 17 0 V DIV1 SEL selects the divider DIV 1 ’0’ = inactive ’1’ = active (reserved) 31..18 R OSC CFG (read / write) 0x00080038 Configuration register for the USB clock and the USB signal receiver Bits Reset Name Description V OSC2 EN enables the oscillator OSC 2 ’0’ = off ’1’ = on Value 0 0 (reserved) 1 2 1 V USB SREC OFF enables the USB pad single-ended receiver ’0’ = enabled ’1’ = disabled 3 1 V USB OFF enables the USB pad differential receiver ’0’ = enabled ’1’ = disabled 7..4 July 2002 (reserved) Preliminary Data Sheet 45 of 173 Clocks, timer and interrupt R CNT1B CFG (read / write) Configuration register for the Bits Reset 0x00080040 clock generation with the modulo counter CNT 1B Name Description Value 7..0 0x01 V CNT1B M multiplying value of the counter CNT 1B (range 1 . . . 255) 15..8 0x01 V CNT1B N divider of the counter CNT 1B (range 1 . . . 255) Note: N must be greater or equal than M. 46 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt 3.2 Timer modules Table 12: Overview of the HFC-S active timer pins (all primary function) Number Name Description CARRY1 timer 1 carry signal 119 WDT carry signal of the watchdog timer 159 PWM OUT PWM output 160 CARRY2 Timer 2 carry signal 1 Table 13: Overview of the HFC-S active timer registers Address Name Page Address Name Page 0x00090000 R TIMER 50 0x00090024 R GPIO CTRL1 0x0009002C R TIMER PRELD 50 0x00080000 R FIQ CTRL 57 0x00090004 R TIMER CFG1 51 0x00080004 R IRQ CTRL 58 0x00090008 R WD 51 0x00080008 R FIQ STATUS 59 0x0009000C R PWM CFG 52 0x0008000C R IRQ STATUS 60 0x00090010 R TIMER CFG2 53 131 The HFC-S active has 4 independent programable timers with interrupt capability: Timer 1 and Timer 2 for general usage, a PWM counter for a simple digital to analog conversion, and a watchdog timer. The PWM counter can also be used as a timer for other purposes. A detailed description of the timers is given in the following sections. 3.2.1 Timer 1 and Timer 2 The HFC-S active has two independent programmable 16 bit timers with interrupt capabilities and 8 bit prescaler. The counters accumulate on the ARM7 system clock. The carry signals of the 16 bit timers can be mapped on the pins 1 and 160 (see tab. 12). Figure 11 illustrates the internal structure of the 16 bit Timer 1. Timer 1 and Timer 2 are constructed identically. Each timer can be set to a 16 bit value by writing the value to the register R TIMER. This value is decremented with the clock signal July 2002 V TI1 PREDIV V TI2 PREDIV Preliminary Data Sheet 47 of 173 Clocks, timer and interrupt 8 Bit M_TI1_PREDIV R_TIMER_CFG1 16 Bit 16 Bit f TI1 pre scaler MUX fSYS 1 M_T1 16 R_TIMER 0 M_TI1_PRELD 16 R_TIMER_PRELD 16 0x0000 = 1 Bit V_TI1_OFF 16 R_TIMER_CFG1 1 -1 IRQ PIN160 + Figure 11: Internal structure of the 16 bit Timer 1 An Timer 1 interrupt occurs when V TI1 (resp. V TI2 for Timer 2) of the register R TIMER reaches the value 0. Additionally, the Timer 1 zero-signal can be mapped to the pin 1 (resp. pin 160 for Timer 2) if V GPIO0 TI1 (resp. V GPIO1 TI2) of the register R GPIO CTRL1 is set to 1. Reaching the value 0, the timer automatically reloads the predefined value of the register R TIMER PRELD. The periodically interrupt signal has the frequency V TI1 PRELD V TI2 PRELD V TI1 PREDIV V TI1 PRELD V TI2 PREDIV V TI2 PRELD The Timer 1 stops with V TI1 OFF (resp. V TI2 OFF for Timer 2) of the register R TIMER CFG1 is set to 1. 3.2.2 Watchdog timer The 16 bit watchdog counter generates a global reset when elapsing. To prevent an HFC-S active reset the watchdog counter has to be reset by the software periodically. This can be carried out in two different ways. By setting the V WD RES bit in the R TIMER CFG1 register or by programming the watchdog counter value R WD directly. For critical system operation the watchdog counter can generate a pre-reset interrupt signal to warn the software of the coming global reset. The threshold value of the pre-reset interrupt signal can be set by the V WD LEV bits in the register R TIMER CFG2. 3.2.3 PWM counter The PWM counter can be used to produce a pulse width modulated signal for a simple digital to analog conversion. Therefore, the counter is periodically incremented. Reaching the value 0x0000 generates an interrupt, if enabled in the register R TIMER CFG2. The pulse width can be set with a resolution of 10 bit (bitmap V PWM PWIDTH of the register R PWM CFG). The PWM signal is 0 for V PWM V PWM PWIDTH and 1 otherwise. The generated PWM signal can be mapped on the GPIO[2] pin (see GPIO register R GPIO CTRL1). 48 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt 12 Bit 1 Bit M_WD_PREDIV V_WD_RESET 1 R_Timer_CFG1 fWDT pre scaler MUX 17 Bit fSYS M_WD_VALUE 16 R_WD_TIMER carry 17 R_Timer_CFG1 0x0000 17 17 1 Bit + V_WD_OFF R_TIMER_CFG1 +1 Reset (WDT) = 17 Bit V_WD_IRQ M_WD_LEVEL R_TIMER_CFG2 Figure 12: Internal structure of the watchdog timer The PWM counter is clocked by the system clock and has a 12 bit prescaler (bitmap V PWM PREDIV of the register R PWM CFG) to control the counter frequency. If the PWM counter isn’t used for pulse width modulation, it can be used as a 10 bit counter with interrupt functionality. Therefore, the software has to write the initial value to the PWM counter register R PWM CFG in the interrupt service routine. 12 Bit M_PWM_PREDIV R_PWM_CFG 10 Bit fSYS pre scaler f PWM M_PWM R_PWM_CFG +1 10 + = IRQ b³ a 10 GPIO 0x000 a 10 Bit M_PWM_PWIDTH R_PWM_CFG b Figure 13: Internal structure of the PWM counter July 2002 Preliminary Data Sheet 49 of 173 Clocks, timer and interrupt 3.2.4 Register description R TIMER (read / write) 0x00090000 Counter register for timer 1 and timer 2 Bits Reset Name Description Value 15..0 0xFFFF V TI1 counter value of timer 1 (count down counter) 31..16 0xFFFF V TI2 counter value of timer 2 (count down counter) R TIMER PRELD (read / write) 0x0009002C Preload value register for timer 1 and timer 2 Bits Reset Name Description Value 15..0 0x0000 V TI1 PRELD Preload value for timer 1. The timer is loaded with this preload value if it has counted to zero. 31..16 0x0000 V TI2 PRELD Preload value for timer 2. The timer is loaded with this preload value if it has counted to zero. 50 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt R TIMER CFG1 (read / write) 0x00090004 Timer control register: predivider for timer 1 and timer 2 and watchdog timer Bits Reset Name Description Value 7..0 0xBB V TI1 PREDIV predivider value for timer 1 15..8 0x00 V TI2 PREDIV predivider value for timer 2 27..16 0x0BB V WD PREDIV predivider value for the watchdog timer 28 0 V TI1 OFF stop timer 1 ’0’ = run ’1’ = stop 29 0 V TI2 OFF stop timer 2 ’0’ = run ’1’ = stop 30 0 V WD OFF stop the watchdog timer ’0’ = run ’1’ = stop 31 0 V WD RES resets the watchdog timer to zero, this bit is set back automatically ’0’ = no reset ’1’ = reset R WD (read / write) 0x00090008 Counter register for the watchdog timer Bits Reset Name Description Value 15..0 31..16 July 2002 0x0000 V WD VALUE Counter value of the watchdog timer (count-up counter) The carry signal of the watchdog counter generates the watchdog reset signal (reserved) Preliminary Data Sheet 51 of 173 Clocks, timer and interrupt R PWM CFG (read / write) 0x0009000C PWM counter control register for PWM pulse generation. The output signal can be mapped on the pins GPIO[0] and GPIO[1] (see primary GPIO description). Bits Reset Name Description Value 9..0 0x000 V PWM PWM counter value (count-up counter) 19..10 0x001 V PWM PWIDTH sets the pulse width of the PWM counter 31..20 0x000 V PWM PREDIV prescaler for the PWM counter 52 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt R TIMER CFG2 (read / write) 0x00090010 Timer interrupt status and control register Bits Reset Name Description Value 0 0 V TI1 IRQ shows the status for timer 1 interrupt (An interrupt is generated if the timer has counted to zero. Writing a zero to this bit resets the interrupt request.) ’0’ = no interrupt request ’1’ = interrupt request 1 0 V TI2 IRQ shows the status for timer 2 interrupt (An interrupt is generated if the timer has counted to zero. Writing a zero to this bit resets the interrupt request.) ’0’ = no interrupt request ’1’ = interrupt request 2 0 V WD IRQ shows the status for the watchdog interrupt (Writing a zero to this bit resets the interrupt request.) ’0’ = no interrupt request ’1’ = interrupt request 3 0 V PWM IRQ shows the status for PWM interrupt (Writing a zero to this bit resets the interrupt request.) ’0’ = no interrupt request ’1’ = interrupt request 4 0 V TI1 EN enables the timer 1 interrupt ’1’ = interrupt enable ’0’ = interrupt disable 5 0 V TI2 EN enables the timer 2 interrupt ’1’ = interrupt enable ’0’ = interrupt disable 6 0 V WD EN enables the watchdog interrupt ’1’ = interrupt enable ’0’ = interrupt disable 7 0 V PWM EN enables the PWM interrupt ’1’ = interrupt enable ’0’ = interrupt disable 23..8 0x8000 V WD LEV 31..24 July 2002 Sets the threshold value for the generation of the interrupt signal. When the watchdog counter reaches the threshold value, a watchdog interrupt signal is generated to give the CPU the possibility to reset the watchdog counter in an interrupt service routine. (reserved) Preliminary Data Sheet 53 of 173 Clocks, timer and interrupt 3.3 Interrupt processing of the HFC-S active Table 14: Overview of the HFC-S active interrupt pins (all primary function) Number 1 88 Name Description CARRY1 timer 1 carry signal EOFT EOFT signal of the S/T interface Number 89 DK REP DK REP signal of the S/T interface 90 DK EN DK EN signal of the S/T interface 115 CLK ST S/T clock 116 CLK EXT clock for external devices ( ) FSC TE FSC TE signal of the S/T interface 117 118 Name Description 119 WDT carry signal of the watchdog timer 120 PFS3 peripheral frame sync 3 signal with interrupt capability 121 PFS2 peripheral frame sync 2 signal with interrupt capability 122 PSF1 peripheral frame sync 1 signal with interrupt capability 157 PFS0 peripheral frame sync 0 signal with interrupt capability 159 PWM OUT PWM output 160 CARRY2 Timer 2 carry signal 158 Table 15: Overview of the HFC-S active interrupt registers Address Name Page Address Name Page 0x00080000 R FIQ CTRL 57 0x00090028 R FSC IRQ 0x00080004 R IRQ CTRL 58 0x00090014 R GPIO CFG 129 0x00080008 R FIQ STATUS 59 0x00090018 R GPIO IRQ CTRL 129 0x0008000C R IRQ STATUS 60 0x000C000C R ST B12 IRQ STATUS 77 0x000E0004 R USB CFG 148 0x000C0014 R ST B12 IRQ EN 78 0x000A002C R UART IRQ CFG 144 0x000C0018 R ST D IRQ EN 78 0x00090010 R TIMER CFG2 3.3.1 66 53 Functional description The ARM7 CPU has two levels of interrupt processing. One interrupt level is the fast interrupt (FIQ) and the other interrupt level is the normal interrupt (IRQ). The HFC-S active has a hierarchically organized interrupt controlling system. Every module listed in 16 has an own interrupt controller (called sub-controller). Every module interrupt can be programmed as a FIQ (fast interrupt) or as an IRQ (normal interrupt). Figure 14 illustrates the interrupt architecture of the HFC-S active. 54 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt ... ... ... 1 1 ... 1 1 1 ... 10 1 10 Bit Main Interrupt Controller Bit 1 .. .. .. .. .. .. Bit 9 Bit 0 Bit 0 .. .. .. .. .. .. Bit 1 10 Bit 0 Bit.. 1 . Bit 9 10 Bit 1 R_IRQ_STATUS 10 Bit 9 ... 1 1 10 Bit R_FIQ_STATUS Bit 0 Bit .. 1 . Bit 9 10 Bit .. .. .. .. .. .. .. .. .. .. .. .. R_FIQ_CTRLI sub - controller 0..9 Module Interrupt Controller 10 10 . .. .. . R_IRQ_CTRL Figure 14: Interrupt control structure of HFC-S active Table 16: Bit numbering of the interrupt sub-controller IRQ / FIQ bit number Sub-controller 0 USB module 1 UART module 2 Timer module 3 FSC PLL module 4 GPIO module 5 PFS 0 of FSC-PLL module, 6 PFS 1 of FSC-PLL module, 7 PFS 2 of FSC-PLL module, 8 PFS 3 of FSC-PLL module, 9 S/T-HDLC module The main interrupt controller has 10 interrupt sources coming from the 10 sub-controllers. All interrupts are maskable in the main controller and in the sub-controllers. When an interrupt has occurred, the software must read the corresponding interrupt status register (fast interrupt or normal interrupt) of the main controller to detect the module which generated the interrupt request. After this the software has to read the interrupt status register of the corresponding module. The interrupt request must be set back by writing a zero value to the interrupt status register of the module. July 2002 Preliminary Data Sheet 55 of 173 Clocks, timer and interrupt Table 17: Bit names of the interrupt registers IRQ / FIQ R FIQ CTRL R IRQ CTRL R FIQ STATUS R IRQ STATUS 0 V FIQ USB EN V IRQ USB EN V FIQ USB V IRQ USB 1 V FIQ UART EN V IRQ UART EN V FIQ UART V IRQ UART 2 V FIQ TI EN V IRQ TI EN V FIQ TI V IRQ TI 3 V FIQ PLL EN V IRQ PLL EN V FIQ PLL V IRQ PLL 4 V FIQ GPIO EN V IRQ GPIO EN V FIQ GPIO V IRQ GPIO 5 V FIQ PFS0 EN V IRQ PFS0 EN V FIQ PFS0 V IRQ PFS0 6 V FIQ PFS1 EN V IRQ PFS1 EN V FIQ PFS1 V IRQ PFS1 7 V FIQ PFS2 EN V IRQ PFS2 EN V FIQ PFS2 V IRQ PFS2 8 V FIQ PFS3 EN V IRQ PFS3 EN V FIQ PFS3 V IRQ PFS3 9 V FIQ ST EN V IRQ ST EN V FIQ ST V IRQ ST bit number 56 of 173 Register Preliminary Data Sheet July 2002 Clocks, timer and interrupt 3.3.2 Register description of the main interrupt controller R FIQ CTRL (read / write) 0x00080000 Interrupt control register to control the FIQ sources ’1’ = enable ’0’ = disable Bits Reset Name Description Value 0 0 V FIQ USB EN Enables the FIQ for the USB module 1 0 V FIQ UART EN Enables the FIQ for the UART module 2 0 V FIQ TI EN Enables the FIQ for the Timer module 3 0 V FIQ PLL EN Enables the FIQ for the FSC PLL module 4 0 V FIQ GPIO EN Enables the FIQ for the GPIO module 5 0 V FIQ PFS0 EN Enables the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 6 0 V FIQ PFS1 EN Enables the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 7 0 V FIQ PFS2 EN Enables the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 8 0 V FIQ PFS3 EN Enables the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 9 0 V FIQ ST EN Enables the FIQ for the S/T module 15..10 (reserved) (See table 17 on page 56 to identify the modules and bit names.) July 2002 Preliminary Data Sheet 57 of 173 Clocks, timer and interrupt R IRQ CTRL (read / write) 0x00080004 Interrupt control register to control the IRQ sources ’1’ = enable ’0’ = disable Bits Reset Name Description Value 0 0 V IRQ USB EN Enables the IRQ for the USB module 1 0 V IRQ UART EN Enables the IRQ for the UART module 2 0 V IRQ TI EN Enables the IRQ for the Timer module 3 0 V IRQ PLL EN Enables the IRQ for the FSC PLL module 4 0 V IRQ GPIO EN Enables the IRQ for the GPIO module 5 0 V IRQ PFS0 EN Enables the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 6 0 V IRQ PFS1 EN Enables the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 7 0 V IRQ PFS2 EN Enables the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 8 0 V IRQ PFS3 EN Enables the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 9 0 V IRQ ST EN Enables the IRQ for the S/T module 15..10 (reserved) (See table 17 on page 56 to identify the modules and bit names.) 58 of 173 Preliminary Data Sheet July 2002 Clocks, timer and interrupt R FIQ STATUS (read / write) 0x00080008 Interrupt status register for the FIQ sources ’1’ = interrupt request ’0’ = no interrupt request The interrupt status register represents the status of each module. When the request of the corresponding module is set back by the software (in the module interrupt status register) the status entry is set back automatically. The FIQ status is only shown if the corresponding module interrupt is enabled in the register R FIQ CTRL. Bits Reset Name Description Value 0 0 V FIQ USB Status of the FIQ for the USB module 1 0 V FIQ UART Status of the FIQ for the UART module 2 0 V FIQ TI Status of the FIQ for the Timer module 3 0 V FIQ PLL Status of the FIQ for the FSC PLL module 4 0 V FIQ GPIO Status of the FIQ for the GPIO module 5 0 V FIQ PFS0 Status of the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 6 0 V FIQ PFS1 Status of the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 7 0 V FIQ PFS2 Status of the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 8 0 V FIQ PFS3 Status of the FIQ for the peripheral frame sync signal (PCM highway-Interface) module 9 0 V FIQ ST Status of the FIQ for the S/T module 15..10 (reserved) (See table 17 on page 56 to identify the modules and bit names.) July 2002 Preliminary Data Sheet 59 of 173 Clocks, timer and interrupt R IRQ STATUS (read / write) 0x0008000C Interrupt status register for the IRQ sources ’1’ = interrupt request ’0’ = no interrupt request The interrupt status register represents the status of each module. If the request of the corresponding module is set back by the software (in the module interrupt status register) the status entry is set back automatically. The IRQ status is only shown if the corresponding module interrupt is enabled in the register R IRQ CTRL. Bits Reset Name Description Value 0 0 V IRQ USB Status of the IRQ for the USB module 1 0 V IRQ UART Status of the IRQ for the UART module 2 0 V IRQ TI Status of the IRQ for the Timer module 3 0 V IRQ PLL Status of the IRQ for the FSC PLL module 4 0 V IRQ GPIO Status of the IRQ for the GPIO module 5 0 V IRQ PFS0 Status of the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 6 0 V IRQ PFS1 Status of the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 7 0 V IRQ PFS2 Status of the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 8 0 V IRQ PFS3 Status of the IRQ for the peripheral frame sync signal (PCM highway-Interface) module 9 0 V IRQ ST Status of the IRQ for the S/T module 15..10 (reserved) (See table 17 on page 56 to identify the modules and bit names.) 60 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4 ISDN related modules 4.1 FSC-PLL module Table 18: Overview of the HFC-S active FSC-PLL pins (primary function pins marked with ) Number Name Description 96 FSC0 frame sync signal for PCM highway 1 97 PFS3 peripheral frame sync signal 98 PFS2 peripheral frame sync signal 99 PFS1 peripheral frame sync signal 100 PFS0 peripheral frame sync signal 104 FSC1 frame sync signal for PCM highway 2 110 FSC2 frame sync signal for PCM highway 3 118 FSC TE FSC TE signal of the S/T interface 120 PFS3 peripheral frame sync 3 signal with interrupt capability 121 PFS2 peripheral frame sync 2 signal with interrupt capability 122 PSF1 peripheral frame sync 1 signal with interrupt capability 157 PFS0 peripheral frame sync 0 signal with interrupt capability 117 158 Table 19: Overview of the HFC-S active FSC-PLL registers Address Name Page Address Name Page 0x00080000 R FIQ CTRL 57 0x00090034 R FSC CONST 0x00080004 R IRQ CTRL 58 0x000B0204 R HW1 CTRL 111 0x00080008 R FIQ STATUS 59 0x000B0208 R HW2 CTRL 113 0x0008000C R IRQ STATUS 60 0x000B020C R HW3 CTRL 115 0x00080030 R GPIO CTRL2 133 0x000B01F4 R PFS0 CFG 108 0x00090014 R GPIO CFG 129 0x000B01F6 R PFS1 CFG 108 0x00090024 R GPIO CTRL1 131 0x000B01F8 R PFS2 CFG 109 0x00090028 R FSC IRQ 66 0x000B01FA R PFS3 CFG 109 0x00090030 R FSC CFG 67 68 The FSC-PLL5 is one of the central modules of the HFC-S active. It is responsible for the generation of the ISDN frame synchronization pulse. The FSC signal is the central clock of 8 kHz for ISDN telephone network, generated by the central office. The ISDN controller, the PCM highways and the CODEC interface work on this synchronization signal. The main task of the FSC-PLL is to eliminate jitter of the external frame synchronization clock by 5 FSC: frame synchronization clock July 2002 Preliminary Data Sheet 61 of 173 ISDN related modules means of the higher resolution of the system clock. 4.1.1 FSC source selection The source signal for the synchronization clock is selectable by the software. If no FSC clock is generated from a source module (PCM highway, S/T-HDLC or a peripheral device connected to GPIO0 . . . GPIO15), the FSC-PLL is free-running. 1 Bit V_FSC_EDGE R_FSC_CFG 0 PCM - Highway 1 2 FSC 0..2 4 5 6 S/T - Interface 8 kHz S/T - FSC 1 divider 8 kHz GPIO - FSC 0 MUX 8 kHz 8 kHz EFSC GPIO data: 8 kHz or 512 kHz or 1024 kHz or 1536 kHz ... MUX GPIO[0]..[15] FSC - PLL 8 kHz IFSC 3 PCM - Highway Controller CODEC Controller 4 4 Bit 3 Bit M_FSC_GPIO_SEL M_FSC_SOURCE R_GPIO_CFG R_FSC_CFG S/T - HDLC Controller Figure 15: Overview of the FSC signal source selection of the FSC-PLL Figure 15 illustrates the FSC source selection. The bitmap V FSC SRC of the register R FSC CFG offers three possibilities for the FSC source: 1. FSC0, FSC1 or FSC2 of the PCM highway, 2. FSC TE of the S/T interface, 3. and one GPIO pin out of GPIO0. . . GPIO15. The GPIO pin can be selected with the bitmap V FSC GPIO SEL of the register R GPIO CFG. As the GPIO synchronization signal can be a multiple of 8 kHz, a programmable 10 bit divider must generate the required signal frequency , i.e. V FSC PREDIV where V FSC PREDIV is a bitmap of the register R GPIO CFG and . In contrast to this, the S/T interface and the PCM highway work always on a 8 kHz synchronization signal. The selected signal is called EFSC (external frame sync clock). The FSC-PLL accepts this signal and generates the internal frame syncronization clock (IFSC) which is used from the PCM highway, the CODECs and the S/T controller. 62 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4.1.2 Functional description of the FSC-PLL The FSC-PLL generates the internal FSC from the external FSC which is passed to the PCM highway controller, the CODEC interface and the S/T controller. The FSC-PLL module offers a very variable adjustment. Figure 16 illustrates the configuration possibilities. Three main parts perform the FSCPLL functionality – the PLL counter, the PLL phase alignment and the FSC adjustment – and are described in the following paragraphs. IFSC f sys 1 Bit V_FSC_CONSTRUCT MUX R_FSC_CFG 0 1 13 Bit 13 Bit M_FSC_POS_EDGE R_FSC_CFG FSC construction logic 13 13 Bit M_FSC_NEG_EDGE M_FSC_VAR_MODE_DATA 13 R_FSC_CFG 13 R_FSC_CFG ÷2 8 kHz = 8 kHz phase correction logic EFSC Q Q clock 3 Bit M_FSC_PPC reset 1 3 Bit in out MUX 3 MUX FSC counter R_FSC_CFG M_FSC_NPC 8 kHz CFSC 3 13 13 R_FSC_CFG + +1 Figure 16: Overview of the internal structure of the FSC-PLL PLL counter The FSC-PLL counter is a 13 bit count-up counter which is clocked by . To generate the CFSC signal (see figure 16), the PSC counter must receive its reset signal every 125 s. Therefore the counter end value has to be programmed by V FSC VARMODE DATA in the register R FSC CFG. This value must not be greater than 8191. Furtheron, it is necessary to set (reserved) = 1 in the register R FSC CFG. With each counter clock, the value of the FSC-PLL counter is incremented with a value which depends on the phase detection result which is described in the next paragraph. Reaching its end value, the counter restarts with zero. July 2002 Preliminary Data Sheet 63 of 173 ISDN related modules PLL phase alignment The FSC-PLL phase detection has two input signals of 8 kHz. The CFSC has to syncronize with EFSC, and in addition to this, it must suppress the EFSC jitter. If no phase shift is needed, the FSC-PLL counter will always be incremented by 1. A phase offset between EFSC and CFSC causes a different increment with a positive or a negative value. These values can be programmed in the range 0 . . . 7 with the bitmaps V FSC PPC resp. V FSC NPC (two complement) in the register R FSC CFG. The phase correction may be performed with every pulse of the FSC or only every th pulse. This is put into action with the bitmap V FSC CORT of the register R FSC CFG. Only the rising edge of the FSC is involved with the phase correction. 125 µs 125 µs CFSC EFSC internal FSC minimal phase correction 1/f sys per 8 kHz pulse external FSC Figure 17: Principle of the phase correction If a phase deviation is recognized, the FSC-PLL corrects the phase difference in the corresponding direction. The phase correction is carried out in both directions. The maximum phase jump per clock period (125 s) is programmable. The resolution of the phase jump depends on the clock frequency . The minimum phase jump per 125 s is 16.27 ns (at ). The FSC-PLL module generates an interrupt (if enabled) every 125 s. The interrupt source can be the internal FSC signal generated by the FSC-PLL module or / and the four peripheral FSC signals (see R FSC IRQ description). 4.1.3 The constructed FSC The FSC-PLL has a constant phase shift (delay) of three system clock periods with reference to the external FSC signal due to the synchronization logic. In case that the constant phase delay leads to disadvantages for the external devices (e.g. PCM CODECs), the FSC-PLL module offers a programmable phase position. Within the contruction logic block, the phase position of the rising and falling edges are independently programmable with a resolution of 13 bit each (bitmaps V FSC POS EDGE and V FSC NEG EDGE of the register R FSC CONST) like shown in figure 18. The periodically FSC contruction starts with the rising edge of the FSC output from the phase correction logic block (called PLL-FSC). A 13 bit counter is incremented with clock beginning at zero. Simultaneously the constructed FSC is put to high. If the counter reaches the value of V FSC NEG EDGE (register R FSC CONST), the constructed FSC changes to low. A counter value equal to V FSC POS EDGE (same register) sets the signal back to high. If this condition is not reached before the next rising edge of the PLL-FSC, this is 64 of 173 Preliminary Data Sheet July 2002 ISDN related modules 125 µs 62.5 µs PLL - FSC constructed FSC t fall t rise Figure 18: Programmable phase position for the FSC signal done as well. A neutral constructed FSC which is identical with the PLL-FSC is achieved with V FSC NEG EDGE for a falling edge after 62.5 s and V FSC POS EDGE V FSC NEG EDGE for a rising edge after 125 s. Note, that the rising edge is not influenced with greater values or if it is zero. A falling edge shift is configured with V FSC NEG EDGE where needs a bitmap value . If the neutral rising edge is located at V FSC POS EDGE with , the shift . The neutral rising edge can also be seen at . Then V FSC POS EDGE within the range . Finally, an inverted constructed FSC is achieved with V FSC NEG EDGE and V FSC POS EDGE July 2002 Preliminary Data Sheet 65 of 173 ISDN related modules 4.1.4 Register description R FSC IRQ (read / write) 0x00090028 Interrupt status and enable register for the FSC interrupts enable bits 0 . . . 4: ’0’ = interrupt disable, ’1’ = interrupt enable status bits 6 . . . 10: ’1’ = interrupt, ’0’ = no interrupt (Writing ’0’ sets back the interrupt request) Bits Reset Name Description Value 0 0 V FSC IRQ interrupt enable register for the internal FSC signal 1 0 V PFSC0 IRQ interrupt enable register for the internal peripheral FSC signal PFS0 2 0 V PFSC1 IRQ interrupt enable register for the peripheral FSC signal PFS1 3 0 V PFSC2 IRQ interrupt enable register for the peripheral FSC signal PFS2 4 0 V PFSC3 IRQ interrupt enable register for the peripheral FSC signal PFS3 (reserved) 5 6 0 V FSC IRQ STATUS interrupt status register for the internal FSC signal. The interrupt request is set back with ’0’. 7 0 V PFSC0 IRQ STATUS interrupt status register for the internal peripheral FSC signal (PFS0) 8 0 V PFSC1 IRQ STATUS interrupt status register for the internal peripheral FSC signal (PFS1) 9 0 V PFSC2 IRQ STATUS interrupt status register for the internal peripheral FSC signal (PFS2) 10 0 V PFSC3 IRQ STATUS interrupt status register for the internal peripheral FSC signal (PFS3) 15..11 66 of 173 (reserved) Preliminary Data Sheet July 2002 ISDN related modules R FSC CFG (read / write) 0x00090030 FSC-PLL configuration register for programmable phase positioning of the internal FSC signal Bits Reset Name Description Value 2..0 0 (reserved) 5..3 2 V FSC PPC sets the phase jump for the positive phase correction ’0’ = no phase correction ’1’ = phase correction 1 clock cycle ... ’7’ = phase correction 7 clock cycle 8..6 7 V FSC NPC sets the phase jump for the negative phase correction (two complement representation: ’000’ = 0, ’001’ = -7, ’010’ = -6, . . . , ’111’ = -1) 9 0 V FSC EDGE sets clock edge for synchronization ’0’=falling ’1’= rising 12..10 0 V FSC CORT sets the number of frame sync pulses in with a phase correction is carried out ’0’ = the phase correction is done within every 125 s ’1’ = the phase correction is done within every 250 s ... ’7’ = the phase correction is done within every 1000 s 15..13 0 V FSC SRC selects the source signal for the FSC-PLL ’000’ = source is GPIO ’001’ = source is S/T module ’100’ = source is FSC0 (PCM highway) ’101’ = source is FSC1 (PCM highway) ’110’ = source is FSC2 (PCM highway) Note: other values deactivate the source 16 0 V FSC CONST enables the variable phase positioning of the internal FSC signal ’0’ = off ’1’ = on 29..17 0x600 V FSC VARMODE DATA Prescaler for the FSC signal in variable mode of the FSC signal generation. In this mode the FSC-PLL can be adjust to every system programmed system frequency. (reserved) 30 31 July 2002 0 (reserved) must be set to ’1’ Preliminary Data Sheet 67 of 173 ISDN related modules R FSC CONST (read / write) 0x00090034 FSC construct register for programmable phase position. Bits Reset Name Description Value 12..0 0x0000 V FSC POS EDGE value for rising clock position ’1111000000000’ = 7680 for 61.440 MHz ’1100000000000’ = 6144 for 49.152 MHz ’1001000000000’ = 4608 for 36.864 MHz ’0110000000000’ = 3072 for 24.576 MHz ’0011000000000’ = 1536 for 12.288 MHz 25..13 0x0000 V FSC NEG EDGE value for falling clock position ’1111000000000’ = 7680 for 61.440 MHz ’1100000000000’ = 6144 for 49.152 MHz ’1001000000000’ = 4608 for 36.864 MHz ’0110000000000’ = 3072 for 24.576 MHz ’0011000000000’ = 1536 for 12.288 MHz 31..26 (reserved) 68 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4.2 S/T-HDLC controller Table 20: Overview of the HFC-S active S/T-HDLC pins Name Description 81 R2 receive port for the S/T interface transmit enable port 82 LEV R2 level detect for R2 TX2 HI transmit port (high) for the S/T interface 83 LEV R1 Level detect for R1 84 R1 79 TX2 LO transmit port (low) for the S/T interface receive port for the S/T interface 85 ADJ LEV 80 TX1 LO transmit port (low) for the S/T interface adjust level control for the S/T interface Number Number Name Description 76 TX1 HI transmit port (high) for the S/T interface 77 /TX EN 78 Table 21: Overview of the HFC-S active S/T-HDLC registers Address Name Page Address Name Page 0x000C0000 R ST CFG 72 0x000C0048 R ST B12 STATUS 84 0x000C0004 R ST TX STATUS 74 0x000C004C R ST D STATUS 84 0x000C0008 R ST RX STATUS 74 0x000C00C0 R ST WR STATES 86 0x000C000C R ST B12 IRQ STATUS 77 0x000C00C0 R ST RD STATES 85 0x000C0010 R ST D FIFO STATUS 78 0x000C00C4 R ST CTRL1 87 0x000C0014 R ST B12 IRQ EN 78 0x000C00C8 R ST CTRL2 88 0x000C0018 R ST D IRQ EN 78 0x000C00CC R ST CTRL3 88 0x000C001C R ST B1 TX FIFO 79 0x000C00D0 R ST SQ MF 89 0x000C0020 R ST B2 TX FIFO 79 0x000C00DC R ST CLK CTRL 89 0x000C0024 R ST D TX FIFO 80 0x000C00F0 R ST B1 RX 90 0x000C0028 R ST B1 RX FIFO 80 0x000C00F4 R ST B1 TX 90 0x000C0030 R ST B2 RX FIFO 81 0x000C00F8 R ST B2 RX 90 0x000C0034 R ST D RX FIFO 81 0x000C00FC R ST B2 TX 90 0x000C0038 R ST B1 CRC 81 0x000C0100 R ST D RX 91 0x000C003C R ST B2 CRC 82 0x000C0104 R ST D TX 91 0x000C0040 R ST D CRC 82 0x000C0108 R ST E RX 91 0x000C0044 R ST CTRL 83 4.2.1 Functional description The S/T-HDLC module is an ISDN S/T-HDLC Basic Rate Interface (BRI). The S/T-HDLC interface and the PCM highway form a functional unit for ISDN telecommunication applications. Additionally, the CODEC interface can be involved in the data flow via the ARM7 CPU. July 2002 Preliminary Data Sheet 69 of 173 ISDN related modules Various options of the S/T-HDLC module allow a very flexible use of the module. The integrated HDLC controller for D-, B1- and B2-channel permits the construction of HDLC frames with an arbitrary length. The HDLC-frames of the B1- and B2-channel can be sent to the S/T interface or to the switching unit. The S/T-HDLC module supports 32 bit data access only, that means always 4 byte are processed together. The clock frequency is fixed to 12.288 MHz. 1 Bit 1 Bit V_ST_B1_SRC V_ST_B1_FIFO_EN R_ST_CFG R_ST_CFG 8 Bit 0 1 R_ST_B1_RX 3 1 1 4 MUX 2 8 Bit MUX R_ST_B1_TX 5 TX 0 S/T 8 Bit TX FIFO RX 0 RX FIFO R_ST_B1_RX_FIFO 11 9 10 6 1 7 0 MUX 8 Bit MUX R_ST_B1_TX_FIFO 8 TX 1 PCM RX 1 Bit V_HDLC_B1_SRC R_ST_CFG Figure 19: Data path configuration options for the S/T-HDLC module (only shown for the B1-channel) Figure 19 illustrates the configuration options of the S/T-HDLC module. Data sources and destinations are selectable from the ARM7 CPU (directly or via FIFO), the PCM highway (via switching unit), or the S/T interface (via switching unit). It is also possible to transmit data to the S/T interface without FIFO buffering. In this case the CPU has to ensure the timing constraints. For the CRC generation the standard check sum CCITT-16 ( illustrates the composition of a HDLC frame. Octet Number Octet Number Bit Order 1 Flag 01111110 2 N+1 3 Data 1 Data 2 01234567 01234567 ... Data N 01234567 01234567 CRC calculation N+2 CRC- High-Byte 76543210 N+3 CRC- Low-Byte 76543210 ) is used. Figure 20 N+4 Flag 01111110 16 12 5 CRC-Check sum CCITT-16: x + x +x +1 bit stuffing Figure 20: HDLC frame format 70 of 173 Preliminary Data Sheet July 2002 ISDN related modules Table 22: Control field organization of the HDLC mode Bit Transmit Receive 0 Start HDLC frame with byte 0 Byte 0 is beginning of the HDLC frame 1 Start HDLC frame with byte 1 Byte 1 is beginning of the HDLC frame 2 Start HDLC frame with byte 2 Byte 2 is beginning of the HDLC frame 3 reserved reserved 4 Stop HDLC frame with byte 0 Byte 0 is end of the HDLC frame 5 Stop HDLC frame with byte 1 Byte 1 is end of the HDLC frame 6 Stop HDLC frame with byte 2 Byte 2 is end of the HDLC frame 7 reserved CRC of the HDLC frame is correct Byte 3 Byte 2 Byte 1 Byte 0 0 FIFO write pointer 1 . . FIFO read pointer . 14 15 3 2 1 0 byte count Figure 21: FIFO pointer structure The HDLC controller of the S/T-HDLC interface has a 64 byte FIFO for each channel (B1, B2 and D) and each direction. The FIFOs can be used in transparent mode and in HDLC mode. They are organized in blocks of 16 x 32 bit. In HDLC mode the fourth byte of the FIFO is interpreted as a control field for data flow controlling. Table 22 illustrates the control field structure for transmit and receive direction. Figure 21 shows the pointer structure of the FIFO. July 2002 Preliminary Data Sheet 71 of 173 ISDN related modules 4.2.2 Register description R ST CFG (read / write) 0x000C0000 S/T-HDLC configuration register Bits Reset Name Description Value 0 0 V ST B1 SRC selects the source for the data on the B1-channel ’0’ = ARM7 CPU ’1’ = PCM highway 1 0 V ST B2 SRC selects the source for the data on the B2-channel ’0’ = ARM7 CPU ’1’ = PCM highway 3..2 0 V ST B1 TX MODE sets the sending data mode for the B1-channel ’00’ = transparent mode ’10’ = HDLC mode without CRC generation ’11’ = HDLC mode with CRC-16 generation 5..4 0 V ST B1 RX MODE sets the receiving data mode for the B1-channel ’00’ = transparent mode ’10’ = HDLC mode without CRC generation ’11’ = HDLC mode with CRC-16 generation 6 1 V ST B1 RX FIFO STATUS resets the B1 receive FIFO pointer 7 0 V ST B1 TX MSB sets the bit direction for the sending data in the B1-channel ’0’ = LSB first ’1’ = MSB first 8 1 V ST B1 RX MSB sets the bit direction for the receiving data in the B1-channel ’0’ = LSB first ’1’ = MSB first 9 1 V ST B1 RX LSB sets the format for the raw data in the B1 receive FIFO ’0’ = original (MSB first) ’1’ = mirrored (LSB first) 11..10 0 V ST B2 TX MODE sets the sending data mode for the B2-channel ’00’ = transparent mode ’10’ = HDLC mode without CRC generation ’11’ = HDLC mode with CRC-16 generation 13..12 0 V ST B2 RX MODE sets the receiving data mode for the B2-channel ’00’ = transparent mode ’10’ = HDLC mode without CRC generation ’11’ = HDLC mode with CRC-16 generation 14 1 V ST B2 RX FIFO STATUS resets the B2 receive FIFO pointer 15 0 V ST B2 TX MSB sets the bit direction for the sending data in the B2-channel ’0’ = LSB first ’1’ = MSB first 72 of 173 Preliminary Data Sheet July 2002 ISDN related modules Bits Reset Name Description Value 16 1 V ST B2 RX MSB sets the bit direction for the receiving data in the B2-channel ’0’ = LSB first ’1’ = MSB first 17 1 V ST B2 RX FIFO LSB sets the format for the raw data in the B2 receive FIFO ’0’ = original (MSB first) ’1’ = mirrored (LSB) 19..18 0 V ST D TX MODE sets the sending data mode for the D-channel ’00’ = transparent mode ’10’ = HDLC mode without CRC generation ’11’ = HDLC mode with CRC-16 generation 21..20 0 V ST D RX MODE sets the receiving data mode for the D-channel ’00’ = transparent mode ’10’ = HDLC mode no CRC generation ’11’ = HDLC mode with CRC-16 generation 22 1 V ST D RX FIFO STATUS resets the D receive FIFO pointer 23 0 V ST D TX MSB sets the bit direction for the sending data on the B2-channel ’0’ = LSB first ’1’ = MSB first 24 1 V ST D RX MSB sets the bit direction for the receiving data on the B2-channel ’0’ = LSB first ’1’ = MSB first 25 1 V ST D RX FIFO LSB sets the format for the raw data in the B2 receive FIFO ’0’ = original (MSB) ’1’ = mirrored (LSB) 26 1 V ST B1 FIFO EN activates the sending FIFO for the B1-channel ’0’ = inactive ’1’ = active 27 1 V ST B2 FIFO EN activates the sending FIFO for the B2-channel ’0’ = inactive ’1’ = active 28 1 V ST D FIFO EN activates the sending FIFO for the D-channel ’0’ = inactive ’1’ = active 29 1 V ST LOOP sets all FIFOs in internal loop mode (for test only) 30 0 V HDLC B1 SRC B1 receives data from S/T or PCM interface ’0’ = S/T ’1’ = PCM interface 31 0 V HDLC B2 SRC B2 receives data from S/T or PCM interface ’0’ = S/T ’1’ = PCM interface July 2002 Preliminary Data Sheet 73 of 173 ISDN related modules R ST TX STATUS (read only) 0x000C0004 FIFO status register for transmit channels Bits Reset Name Description Value 3..0 0 V B1 TX FIFO WRPTR displays FIFO write pointer of B1-channel transmitter 7..4 0 V B1 TX FIFO RDPTR displays FIFO read pointer of B1-channel transmitter 11..8 0 V B2 TX FIFO WRPTR displays FIFO write pointer of B2-channel transmitter 15..12 0 V B2 TX FIFO RDPTR displays FIFO read pointer of B2-channel transmitter 19..16 0 V D TX FIFO WRPTR displays FIFO write pointer of D-channel transmitter 23..20 0 V D TX FIFO RDPTR displays FIFO read pointer of D-channel transmitter 25..24 0 V B1 TX CNT displays FIFO byte counter of B1-channel transmitter 27..26 0 V B2 TX CNT displays FIFO byte counter of B2-channel transmitter 29..28 0 V D TX CNT displays FIFO byte counter of D-channel transmitter (reserved) 31..30 R ST RX STATUS (read only) 0x000C0008 FIFO status register for receive channels Bits Reset Name Description Value 3..0 0 V B1 RX FIFO WRPTR displays FIFO write pointer of B1-channel receiver 7..4 0 V B1 RX FIFO RDPTR displays FIFO read pointer of B1-channel receiver 11..8 0 V B2 RX FIFO WRPTR displays FIFO write pointer of B2-channel receiver 15..12 0 V B2 RX FIFO RDPTR displays FIFO read pointer of B2-channel receiver 19..16 0 V D RX FIFO WRPTR displays FIFO write pointer of D-channel receiver 23..20 0 V D RX FIFO RDPTR displays FIFO read pointer of D-channel receiver 25..24 0 V B1 RX CNT displays FIFO byte counter of B1-channel receiver 27..26 0 V B2 RX CNT displays FIFO byte counter of B2-channel receiver 29..28 0 V D TX CNT displays FIFO byte counter of D-channel receiver 31..30 74 of 173 (reserved) Preliminary Data Sheet July 2002 ISDN related modules July 2002 Preliminary Data Sheet 75 of 173 ISDN related modules Table 23: Bitmap description of the FIFO transmit status Bit Bit number name Description 0 empty indicates that the transmit FIFO is empty 1 full 2 overflow indicates an overflow in the transmit FIFO (data has not been sent) 3 underflow indicates an underflow in the transmit FIFO (in transparent mode: old data has been sent, in HDLC mode: 0xFF has been sent) 4 abort 5 HDLC mode indicates that the transmit FIFO is full indicates abort of HDLC frame in transmit channel indicates that the transmitted data is an HDLC frame Table 24: Bitmap description of the FIFO receive status (B1- and B2-channel) Bit Bit number name Description 0 empty indicates that the receive FIFO is empty 1 full 2 overflow indicates an overflow in the receive FIFO (data has not been written into the FIFO) 3 underflow indicates an underflow in the receive FIFO (in transparent mode: old data has been written, in HDLC mode: 0xFF has been written) 4 abort 5 CRC OK 6 HDLC mode 7 align error indicates an error in the HDLC data stream of the receive channel (data is not byte aligned) 8 lost error indicates that data has been lost in receive channel 76 of 173 indicates that the receive FIFO is full indicates abort of HDLC frame in receive channel indicates correct CRC checksum of receive channel indicates that a HDLC frame was received Preliminary Data Sheet July 2002 ISDN related modules Table 25: Bitmap description of the FIFO receive status (D-channel) Bit Bit number name Description 0 empty indicates that the receive FIFO is empty 1 full 2 overflow indicates an overflow in the receive FIFO (data has not been written into the FIFO) 3 underflow indicates an underflow in the receive FIFO (in transparent mode: old data has been written, in HDLC mode: 0xFF has been written) 4 abort 5 CRC OK 6 HDLC mode 7 align error 8 repeat 9 lost error indicates that the receive FIFO is full indicates abort of HDLC frame in receive channel indicates correct CRC checksum of receive channel indicates that a HDLC frame was received indicates an error in the HDLC data stream of the receive channel (data is not byte aligned) indicates a request to repeat the last HDLC frame in receive channel indicates that data has been lost in receive channel R ST B12 IRQ STATUS (read / write) 0x000C000C Interrupt status register for S/T-HDLC B1- and B2-channels Bits Reset Name Description Value 5..0 0 V B1 TX FIFO STATUS indicates the B1-channel transmit FIFO status 14..6 0 V B1 RX FIFO STATUS indicates the B1-channel receive FIFO status (reserved) 15 21..16 0 V B2 TX FIFO STATUS indicates the B2-channel transmit FIFO status 30..22 0 V B2 RX FIFO STATUS indicates the B1-channel transmit FIFO status 31 (reserved) (see table 23 and 24 for bitmap explanation) July 2002 Preliminary Data Sheet 77 of 173 ISDN related modules R ST D FIFO STATUS (read / write) 0x000C0010 Interrupt status register for S/T-HDLC D-channel Bits Reset Name Description Value 5..0 0 V D TX FIFO STATUS indicates the D-channel transmit FIFO status 15..6 0 V D RX FIFO STATUS indicates the D-channel receive FIFO status (see table 23 and 25 for bitmap explanation) R ST B12 IRQ EN (read / write) 0x000C0014 Interrupt enable register for S/T-HDLC B1- and B2-channels ’0’ = disable interrupt ’1’ = enable interrupt Bits Reset Name Description Value 5..0 0 V B1 TX IRQ EN enables the B1 transmit interrupts 14..6 0 V B1 RX IRQ EN enables the B1 receive interrupts (reserved) 15 21..16 0 V B2 TX IRQ EN enables the B2 transmit interrupts 30..22 0 V B2 RX IRQ EN enables the B2 receive interrupts (reserved) 31 (see table 23 and 24 for bitmap explanation) R ST D IRQ EN (read / write) 0x000C0018 Interrupt enable register for S/T-HDLC D-channel ’0’ = disable interrupt ’1’ = enable interrupt Bits Reset Name Description Value 5..0 0 V D TX IRQ EN enables the D-channel transmit interrupts 15..6 0 V D RX IRQ EN enables the D-channel receive interrupts (see table 23 (page 76) and 25 (page 77) for bitmap explanation) 78 of 173 Preliminary Data Sheet July 2002 ISDN related modules R ST B1 TX FIFO (read / write) 0x000C001C Write address of B1-channel transmitter FIFO (Organization: 16 x 32 bit = 64 bytes) In transparent mode 4 bytes of data are written simultaneously. In HDLC mode 3 bytes of data and 1 control byte (byte 3) are written simultaneously. Bits Reset Name Description Value 7..0 0x00 V B1 TX FIFO BYTE0 B1-channel transmit data byte 0 15..8 0 V B1 TX FIFO BYTE1 B1-channel transmit data byt 1 23..16 0 V B1 TX FIFO BYTE2 B1-channel transmit data byte 2 31..24 0x00 V B1 TX FIFO BYTE3 in transp. mode: B1-channel transmit data byte 3 in HDLC mode: HDLC control byte R ST B2 TX FIFO (read / write) 0x000C0020 Write address of B2-channel transmitter FIFO (Organization: 16 x 32 bit = 64 bytes) In transparent mode 4 bytes of data are written simultaneously. In HDLC mode 3 bytes of data and 1 control byte (byte 3) are written simultaneously. Bits Reset Name Description Value 7..0 0 V B2 TX FIFO BYTE0 B2-channel transmit data byte 0 15..8 0x00 V B2 TX FIFO BYTE1 B2-channel transmit data byte 1 23..16 0x00 V B2 TX FIFO BYTE2 B2-channel transmit data byte 2 31..24 0x00 V B2 TX FIFO BYTE3 in transp. mode: B2-channel transmit data byte 3 in HDLC mode: HDLC control byte July 2002 Preliminary Data Sheet 79 of 173 ISDN related modules R ST D TX FIFO (read / write) 0x000C0024 Write address of D-channel transmitter FIFO (Organization: 16 x 32 bit = 64 bytes) In transparent mode 4 bytes of data are written simultaneously. In HDLC mode 3 bytes of data and 1 control byte (byte 3) are written simultaneously. Bits Reset Name Description Value 7..0 0 V D TX FIFO BYTE0 D-channel transmit data byte 0 15..8 0 V D TX FIFO BYTE1 D-channel transmit data byte 1 23..16 0x00 V D TX FIFO BYTE2 D-channel transmit data byte 2 31..24 0x00 V D TX FIFO BYTE3 in transp. mode: D-channel transmit data byte 3 in HDLC mode: HDLC control byte R ST B1 RX FIFO (read / write) 0x000C0028 Read address of B1-channel receiver FIFO (Organization: 16 x 32 bit = 64 bytes) In transparent mode 4 bytes of data are read simultaneously. In HDLC mode 3 bytes of data and 1 control byte (byte 3) are read simultaneously. Bits Reset Name Description Value 7..0 0 V B1 RX FIFO BYTE0 B1-channel receiver data byte 0 15..8 0 V B1 RX FIFO BYTE1 B1-channel receiver data byte 1 23..16 0 V B1 RX FIFO BYTE2 B1-channel receiver data byte 2 31..24 0x00 V B1 RX FIFO BYTE3 in transp. mode: B1-channel receive data byte 3 in HDLC mode: HDLC control byte 80 of 173 Preliminary Data Sheet July 2002 ISDN related modules R ST B2 RX FIFO (read / write) 0x000C0030 Read address of B2-channel receiver FIFO (Organization: 16 x 32 bit = 64 bytes) In transparent mode 4 bytes of data are read simultaneously. In HDLC mode 3 bytes of data and 1 control byte (byte 3) are read simultaneously. Bits Reset Name Description Value 7..0 0 V B2 RX FIFO BYTE0 B2-channel receiver data byte 0 15..8 0 V B2 RX FIFO BYTE1 B2-channel receiver data byte 1 23..16 0 V B2 RX FIFO BYTE2 B2-channel receiver data byte 2 31..24 0 V B2 RX FIFO BYTE3 in transp. mode: B2-channel receive data byte 3 in HDLC mode: HDLC control byte R ST D RX FIFO (read / write) 0x000C0034 Read address of D-channel receiver FIFO (Organization: 16 x 32 bit = 64 bytes) In transparent mode 4 bytes of data are read simultaneously. In HDLC mode 3 bytes of data and 1 control byte (byte 3) are read simultaneously. Bits Reset Name Description Value 7..0 0x00 V D RX FIFO BYTE0 D-channel receiver data byte 0 15..8 0x00 V D RX FIFO BYTE1 D-channel receiver data byte 1 23..16 0x00 V D RX FIFO BYTE2 D-channel receiver data byte 2 31..24 0x00 V D RX FIFO BYTE3 in transp. mode: D-channel receive data byte 3 in HDLC mode: HDLC control byte R ST B1 CRC (read / write) 0x000C0038 Register for soft CRC of B1-channel If selected, the CRC has to be calculated by the software and stored into this register before the start of the HDLC frame. Bits Reset Name Description Value 15..0 July 2002 0x0000 V ST B1 CRC value of the CRC for the B1-channel Preliminary Data Sheet 81 of 173 ISDN related modules R ST B2 CRC (read / write) 0x000C003C Register for soft CRC of B2-channel If selected, the CRC has to be calculated by the software and stored into this register before the start of the HDLC frame. Bits Reset Name Description Value 15..0 0x0000 V ST B2 CRC R ST D CRC value of the CRC for the B2-channel (read / write) 0x000C0040 Register for soft CRC of D-channel If selected, the CRC has to be calculated by the software and stored into this register before the start of the HDLC frame. Bits Reset Name Description Value 15..0 82 of 173 0x0000 V ST D CRC value of the CRC for the D-channel Preliminary Data Sheet July 2002 ISDN related modules R ST CTRL (read / write) 0x000C0044 FIFO control register Bits Reset Name Description Value 0 1 V B1 TX FIFO STOP stops the B1-channel transmit FIFO ’0’ = run ’1’ = stop If the FIFO is active but stopped, 0xFF will be transmitted. 1 1 V B2 TX FIFO STOP stops the B2-channel transmit FIFO ’0’ = run ’1’ = stop If the FIFO is active but stopped, 0xFF will be transmitted. 2 1 V B2 TX FIFO STOP stops the B2-channel transmit FIFO ’0’ = run ’1’ = stop If the FIFO is active but stopped, 0xFF will be transmitted. 3 1 V D TX FIFO STOP stops the D-channel transmit FIFO ’0’ = run ’1’ = stop If the FIFO is active but stopped, 0xFF will be transmitted. 4 1 V B1 TX FIFO RDY resets the B1-channel transmit FIFO ’0’ = reset ’1’ = operation 5 1 V B2 TX FIFO RDY resets the B2-channel transmit FIFO ’0’ = reset ’1’ = operation 6 1 V D TX FIFO RDY resets the D-channel transmit FIFO ’0’ = reset ’1’ = operation 7 1 V ST RDY resets the S/T module ’0’ = reset ’1’ = operation 8 July 2002 (reserved) Preliminary Data Sheet 83 of 173 ISDN related modules R ST B12 STATUS (read only) 0x000C0048 Status register for S/T-HDLC B1- and B2-channels Represents the current status of the S/T-HDLC module Bits Reset Name Description Value 5..0 0x00 V B1 TX STATUS indicates the B1-channel transmit FIFO status 14..6 0x000 V B1 RX STATUS indicates the B1-channel transmit FIFO status (reserved) 15 21..16 0 V B2 TX STATUS indicates the B2-channel transmit FIFO status 30..22 0 V B2 RX STATUS indicates the B2-channel receive FIFO status (reserved) 31 (see table 23 (page 76) and 24 (page 76) for bitmap explanation) R ST D STATUS (read only) 0x000C004C Status register for S/T-HDLC D-channel Represents the current status of the S/T-HDLC module Bits Reset Name Description Value 5..0 0x00 V D TX STATUS indicates the D-channel transmit FIFO status 15..6 0x000 V D RX STATUS indicates the D-channel transmit FIFO status (see table 23 (page 76) and 25 (page 77) for bitmap explanation) 84 of 173 Preliminary Data Sheet July 2002 ISDN related modules R ST RD STATES (read only) 0x000C00C0 Status register for S/T module state machine Bits Reset Name Description Value 3..0 0 V ST STATE binary value of actual state (NT: Gx, TE: Fx) 4 0 V FR SYNC frame synchronization ’0’ = not synchronized ’1’ = synchronized 5 0 V T2 EXP ’1’ = timer T2 expired (NT mode only) 6 0 V INFO0 ’1’ = receiving INFO0 7 0 V G2 G3 ’0’ = no operation ’1’ = allows transition from G2 to G3 in NT mode This bit is automatically cleared after the transition and has no function in TE mode. Note: For bit 5 details see table 26 on page 92 July 2002 Preliminary Data Sheet 85 of 173 ISDN related modules R ST WR STATES (write only) 0x000C00C0 Status register for S/T module state machine Bits Reset Name Description Value 3..0 0 V ST SET STATE binary value of the new state (NT: Gx, TE: Fx) (bit 4 must also be set to load the state) 4 0 V ST LD STATE ’1’ loads the prepared state (bit 3 . . . 0) and stops the state machine. This bit needs to be set for a minimum period of 5.21 s and must be cleared by software. ’0’ enables the state machine (bits 3 . . . 0 are ignored). After writing an invalid state, the state machine goes to deactivated state (G1, F2). 6..5 0 V ST ACT ’00’ = no operation ’01’ = no operation ’10’ = start deactivation ’11’ = start activation These bits are automatically cleared after activation/deactivation. 7 0 V SET G2 G3 ’0’ no operation ’1’ in NT mode allows transition from G2 to G3. This bit is automatically cleared after the transition and has no function in TE mode. G Important ! The state machine is stuck to ’0’ after a reset. Writing a ’0’ to bit 4 restarts the state machine. In this state the HFC-S active sends no signal on the S/T line and it is not possible to activate it by incoming INFOx. NT mode: The NT state machine does not change automatically from G2 to G3 if the TE side sends INFO3 frames. This transition must be activated each time by setting bit 7 of the R ST WR STATES register or by setting bit 0 of the R ST CTRL2 register. Fix the NT state machine to state G3 when activated (by writing 13h into this register). This prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data. 86 of 173 Preliminary Data Sheet July 2002 ISDN related modules R ST CTRL1 (write only) 0x000C00C4 1st control register of the S/T module Bits Reset Name Description Value 0 0 V B1 EN ’0’ = B1 send data disabled (permanent 1 sent in activated states) ’1’ = B1 send data enabled 1 0 V B2 EN ’0’ = B2 send data disabled (permanent 1 sent in activated states) ’1’ = B2 send data enabled 2 0 V ST MODE S/T interface mode ’0’ = TE mode ’1’ = NT mode 3 0 V D PRIO D-channel priority ’0’ = high priority 8/9 ’1’ = low priority 10/11 4 0 V SQ EN S/Q bit transmission ’0’ = S/Q bit disabled ’1’ = S/Q bit and multiframe enabled 5 0 V 96KHZ ’0’ = normal operation ’1’ = send 96 kHz transmit test signal (alternating zeros) 6 0 V TX LO TX2 LO and TX1 LO line setup This bit must be configured depending on the used S/T module and circuitry to match the pulse mask test. ’0’ = capacitive line mode ’1’ = non capacitive line mode 7 0 V ST STOP Power down ’0’ = power up, oscillator active ’1’ = power down, oscillator stopped Note: This bit is not cleared by a soft reset. July 2002 Preliminary Data Sheet 87 of 173 ISDN related modules R ST CTRL2 (write only) 0x000C00C8 2nd control register of the S/T module Bits Reset Name Description Value 0 0 V G2 G3 EN force automatic transition from G2 to G3 without setting bit V SET G2 G3 of the R ST WR STATES 1 0 (reserved) must be ’0’ 2 0 V D HI D reset ’0’ = normal operation ’1’ = D bits are forced to ’1’ 3 0 V E IGNO D U enable ’0’ = normal operation ’1’ = D-channel always sends enabled regardless of the received E bit 4 0 V E LO force E to ’0’ (NT mode) ’0’ = normal operation ’1’ = E bit is forced to ’0’ 6..5 0 (reserved) must be ’00’ 7 0 V B12 SWAP ’0’ = normal operation ’1’ = swap B1- and B2-channel in the S/T interface R ST CTRL3 (write only) 0x000C00CC 3rd control register for the S/T module Bits Reset Name Description Value 0 0 V B1 RX HI B1-channel receive enable ’0’ = B1 receive bits are forced to ’1’ ’1’ = normal operation 1 0 V B2 RX HI B2-channel receive enable ’0’ = B2 receive bits are forced to ’1’ ’1’ = normal operation 7..2 88 of 173 (reserved) Preliminary Data Sheet July 2002 ISDN related modules R ST SQ MF (read / write, read, write) 0x000C00D0 S/Q multiframe register for S/T module Bits Reset Name Description Value 3..0 0 V ST SQ TE mode: S bits (bit 3 = S1, . . . , bit 0 = S4) NT mode: Q bits (bit 3 = Q1, bit 0 = Q4) 4 0 V MF RX RDY ’1’ a complete S or Q multiframe has been received Reading this register clears this bit. 6..5 0 (reserved) 7 0 V MF TX RDY ’1’ ready to send a new S or Q multiframe Writing to this register clears this bit. R ST CLK CTRL (write only) 0x000C00DC Clock control register for S/T module The register is not initialized with a ’0’ after reset. It should be initialized as follows before activating the TE/NT state machine: TE mode: 0x0D . . . 0x0F NT mode: 0x6C Bits Reset Name Description V ST CLK DELAY TE: 4 bit delay value to adjust the 2 bit time between receive and transmit direction. The delay of the external S/T interface circuit can be compensated. The lower the value the smaller the delay between receive and transmit direction Value 3..0 NT: Data sample point. The lower the value the earlier the input data is sampled. The steps are 163 ns. 6..4 V ST SAMPLE 7 (reserved) July 2002 NT mode only early edge input data shaping Low pass characteristic of extended bus configurations can be compensated. The lower the value the earlier input data pulse is sampled. No compensation means a value of 6 (’110’). Step size is 163 ns. Preliminary Data Sheet 89 of 173 ISDN related modules R ST B1 RX (read only) 0x000C00F0 Receive register for the B1-channel data. This register is updated all 125 s (FSC pulse) by hardware. Bits Reset Name Description V ST B1 RX B1-channel data Value 7..0 0xFF R ST B1 TX (write only) 0x000C00F4 Transmit register for the B1-channel data. This register is automatically updated all 125 s (FSC pulse) with data from the FIFO or from the switching unit or can be updated by the CPU if these data streams are not configured. Bits Reset Name Description V ST B1 TX B1-channel data Value 7..0 0x00 R ST B2 RX (read only) 0x000C00F8 Receive register for the B2-channel data. This register is updated all 125 s (FSC pulse) by hardware. Bits Reset Name Description V ST B2 RX B2-channel data Value 7..0 0xFF R ST B2 TX (write only) 0x000C00FC Transmit register for the B2-channel data. This register is automatically updated all 125 s (FSC pulse) with data from the FIFO or from the switching unit or can be updated by the CPU if these data streams are not configured. Bits Reset Name Description V ST B2 TX B2-channel data Value 7..0 90 of 173 0x00 Preliminary Data Sheet July 2002 ISDN related modules R ST D RX (read only) 0x000C0100 Receive register for the D-channel data. This register is updated all 125 s (FSC pulse) by hardware. Bits Reset Name Description Value (reserved) 5..0 7..6 3 V ST D RX R ST D TX D-channel data (write only) 0x000C0104 Transmit register for the D-channel data. This register is automatically updated all 125 s (FSC pulse) with data from the FIFO or from the switching unit or can be updated by the CPU if these data streams are not configured. Bits Reset Name Description Value (reserved) 5..0 7..6 0 V ST D TX R ST E RX D-channel data (read only) 0x000C0108 Receive register for the E-channel data. This register is updated all 125 s (FSC pulse) by hardware. Bits Reset Name Description Value (reserved) 5..0 7..6 July 2002 3 M ST E RX E-channel data Preliminary Data Sheet 91 of 173 ISDN related modules 4.2.3 State matrices for NT and TE S/T interface activation / deactivation layer 1 for finite state matrix for NT Table 26: Activation / deactivation layer 1 for finite state matrix for NT Pending State name: State number: INFO sent: Pending Reset Deactivate activation Active deactivation G0 G1 G2 G3 G4 INFO 0 INFO 0 INFO 2 INFO 4 INFO 0 Event: State machine release G2 (Note 3) Activate request Deactivate request G2 G2 G2 (Note 1) (Note 1) (Note 1) — Start timer T2 Start timer T2 G4 G4 Expiry T2 (Note 2) — — — — G1 Receiving INFO 0 — — — G2 G1 Receiving INFO 1 — G2 — / — G3 — — G2 — (Note 1) Receiving INFO 3 — / (Note 1, 4) Lost framing — / / Legend: — No state change / Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons Impossible by the definition of the physical layer service Notes: Note 1: Timer 1 (T1) is not implemented in the HFC-S active and must be implemented in software. Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32 ms ( implies that a TE has to recognize INFO 0 and to react on it within this time. ). This Note 3: After reset the state machine is fixed to G0. Note 4: Bit V SET G2 G3 of the R ST WR STATES register must be set to allow this transition. 92 of 173 Preliminary Data Sheet July 2002 ISDN related modules Activation / deactivation layer 1 for finite state matrx for TE State name: Reset Sensing Deactivated Awaiting signal Identifying input Synchronized Activated Lost framing Table 27: Activation / deactivation layer 1 for finite state matrix for TE State number: F0 F2 F3 F4 F5 F6 F7 F8 INFO 0 INFO 0 INFO 0 INFO 1 INFO 0 INFO 3 INFO 3 INFO 0 F2 / / / / / / / INFO sent: Event: State machine release (Note 1) Activate request, receiving any signal — F5 — — receiving INFO 0 — F4 — — Expiry T3 (Note 5) — / — F3 F3 F3 — — Receiving INFO 0 — F3 — — — F3 F3 F3 Receiving any signal — — — F5 — / / — — F6 F6 F6 F6 — F6 F6 — F7 F7 F7 F7 F7 — F7 — / / / / F8 F8 — (Note 2) Receiving INFO 2 (Note 3) Receiving INFO 4 (Note 3) Lost framing (Note 4) Legend: — No state change / Impossible situation Impossible by the definition of the layer 1 service Notes: Note 1: After reset the state machine is fixed to F 0. Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined wether it is INFO 2 or INFO 4. Note 3: Bit- and frame-synchronisation achieved. Note 4: Loss of Bit- or frame-synchronisation. Note 5: Timer 3 (T3) is not implemented in the HFC-S active and must be implemented in software. July 2002 Preliminary Data Sheet 93 of 173 ISDN related modules 4.2.4 Binary organisation of the frame The frame structures on the S/T interface are different for each direction of transmission. Both structures are illustrated in figure 22. 48 bits in 250 microseconds NT to TE 0 1 0 D L . F L . B1 B1 B1 B1 B1 B1 B1 B1 E D A FA N B2 B2 B2 B2 B2 B2 B2 B2 E D M B1 B1 B1 B1 B1 B1 B1 B1 E D S B2 B2 B2 B2 B2 B2 B2 B2 E D L . F L . 2 bits offset TE to NT D L . F L . B1 B1 B1 B1 B1 B1 B1 B1 L . D L . FA L . B2 B2 B2 B2 B2 B2 B2 B2 L . D L . B1 B1 B1 B1 B1 B1 B1 B1 L . D L . B2 B2 B2 B2 B2 B2 B2 B2 L . D L . F L . t DC balanced parts of different TEs (see note) Figure 22: Frame structure at reference point S and T Legend: Code Explanation Code Explanation F Framing bit N Bit set to a binary value (NT to TE) L D.C. balancing bit B1 Bit within B1-channel D D-channel bit B2 Bit within B2-channel E D-echo-channel bit A Bit used for activation F Auxiliary framing bit S S-channel bit M Multiframing bit G Note ! Lines demarcate those parts of the frame that are independently d.c.-balanced. The F bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is enabled (see R ST CTRL1 register). The nominal 2 bit offset is as seen from the TE. The offset can be adjusted with the R ST CLK CTRL register in TE mode. The corresponding offset at the NT may be greater due to delay in the interface cable and varies by configuration. HDLC B-channel data start with the LSB, PCM B-channel data start with the MSB. 94 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4.2.5 S/T interface circuitry In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the HFC-S active needs some additional circuitry, which are shown in appendixD (see page 162). A list of suitable S/T modules is given in the tables28 and 29. Furtheron, an actual list of S/T modules is always available on the web site www.CologneChip.com. Table 28: S/T module part numbers and manufacturers (part 1) S/T module part number Manufacturer APC 56624-1 APC 40495S (SMD) S-Hybrid modules with receiver and transmitter circuitry included: APC 5568-3V APC 5568-5V APC 5568DS-3V APC 5568DS-5V Advanced Power Components United Kingdom Phone: Fax: URL: +44 1634-290588 +44 1634-290591 http://www.apcisdn.com FEE GmbH FE 8131-55Z transformers: PE-64995 PE-64999 PE-65795 (SMD) PE-65799 (SMD) PE-68995 PE-68999 T5006 (SMD) T5007 (SMD) S -modules: T5012 T5034 T5038 transformers: SM TC-9001 SM ST-9002 SM ST-16311F S -modules: July 2002 SM TC-16311 SM TC-16311A Singapore Phone: Fax: +65 741-5277 +65 741-3013 Bangkok Phone: Fax: +662 718-0726-30 +662 718-0712 Germany Phone: Fax: +49 6106-82980 +49 6106-829898 Pulse Engineering, Inc. United States Phone: Fax: URL: +1-619-674-8100 +1-619-674-8262 http://www.pulseeng.com Sun Myung Korea Phone: Fax: URL: +82-348-943-8525 +82-348-943-8527 http://www.sunmyung.com Preliminary Data Sheet 95 of 173 ISDN related modules Table 29: S/T module part numbers and manufacturers (part 2) S/T module part number Manufacturer UMEC GmbH transformers UT21023 S -modules: UT 20795 (SMD) UT 21624 UT 28624 A Germany Phone: Fax: +49 7131-7617-0 +49 7131-7617-20 Taiwan Phone: Fax: +886-4-359-009-6 +886-4-359-012-9 United States Phone: Fax: URL: +1-310-326-707-2 +1-310-326-705-8 http://www.umec.de all devices T 6040. . . transformers: S -modules: . . . 3-L4021-X066 . . . 3-L4025-X095 . . . 3-L5024-X028 . . . 3-L4096-X005 . . . 3-L5032-X040 VAC GmbH Germany . . . 7-L5026-X010 (SMD) . . . 7-L5051-X014 . . . 7-M5051-X032 . . . 7-L5052-X102 (SMD) . . . 7-M5052-X110 . . . 7-M5052-X114 Phone: Fax: URL: +49 6181/ 38-0 +49 6181/ 38-2645 http://www.vacuumschmelze.de Valor Electronics, Inc. transformers: ST5069 S -modules: PT5135 ST5201 ST5202 Asia Phone: Fax: +852 2333-0127 +852 2363-6206 North America Phone: Fax: +1 800 31VALOR +1 619 537-2525 Europe Phone: Fax: URL: +44 1727-824-875 +44 1727-824-898 http://www.valorinc.com Vogt electronic AG 543 76 009 00 Germany 503 740 010 0 (SMD) 96 of 173 Phone: Fax: URL: Preliminary Data Sheet +49 8591/ 17-0 +49 8591/ 17-240 http://www.vogt-electronic.com July 2002 ISDN related modules 4.3 PCM highway module Table 30: Overview of the HFC-S active PCM highway pins (primary function for pins marked with ) Number Name Description serial data input for PCM highway 1 101 SDI1 serial data input for PCM highway 2 SDO0 serial data output for PCM highway 1 102 SDO1 serial data output for PCM highway 2 95 BCLK0 bit clock for PCM highway 1 103 BCLK1 96 FSC0 frame sync signal for PCM highway 1 bit clock for PCM highway 2 104 FSC1 frame sync signal for PCM highway 2 105 SDI2 serial data input for PCM highway 3 106 SDO2 serial data output for PCM highway 3 109 BCLK2 bit clock for PCM highway 2 110 FSC2 frame sync signal for PCM highway 3 Number Name Description 93 SDI0 94 97 PFS3 peripheral frame sync signal 98 PFS2 peripheral frame sync signal 99 PFS1 peripheral frame sync signal 100 PFS0 peripheral frame sync signal Table 31: Overview of the HFC-S active PCM highway registers ( : The bit V CODEC ST is part of the Switching Unit, see section 4.4) Address 4.3.1 Name Page Address Name Page 0x000B0000 R HW1 TX NEXT 103 0x000B01A0 R HW3 RX CUR 107 0x000B0020 R HW1 RX LAST 103 0x000B01F4 R PFS0 CFG 108 0x000B0040 R HW2 TX NEXT 104 0x000B01F6 R PFS1 CFG 108 0x000B0060 R HW2 RX LAST 104 0x000B01F8 R PFS2 CFG 109 0x000B0080 R HW3 TX NEXT 104 0x000B01FA R PFS3 CFG 109 CFG 110 0x000B00A0 R HW3 RX LAST 105 0x000B0200 R PCM 0x000B0100 R HW1 TX CUR 105 0x000B0204 R HW1 CTRL 111 0x000B0120 R HW1 RX CUR 105 0x000B0208 R HW2 CTRL 113 0x000B0140 R HW2 TX CUR 106 0x000B020C R HW3 CTRL 115 0x000B0160 R HW2 RX CUR 106 0x000B0210 R HW SL CNT 116 0x000B0180 R HW3 TX CUR 106 Overview The PCM highway module provides three PCM highway interfaces with a data rate of up to 2.048 Mbit/s each. This allows the connection with external PCM or IOM-2 compatible devices (see table32 for name mapping) or to cascade the HFC-S active for advanced applications. The data stream of the July 2002 Preliminary Data Sheet 97 of 173 ISDN related modules Table 32: Name mapping between HFC-S active PCM interface pins and the corresponding IOM-2 abbreviations (DCL = data clock, FSC = frame synchronization clock, DD = data downstream, DU = data upstream) HFC-S active IOM-2 name name Description BCLKx DCL Bus clock output FSCx FSC Frame clock output (always 8 kHz) SDOx DD Data output SDIx DU Data input PCM highway interface is divided into 32 time slots (channels). Each time slot can receive and transmit 1 byte per FSC pulse (125 s). Only with the maximum PCM data rate it is possible to use all 32 time slots. With lower data rates, the number of available time slots is reduces accordingly. The three interfaces receive the bit and frame clock signals from the internal FSC-PLL of the HFC-S active, so that the PCM highways always work synchronously to the S/T module and the CODEC module. The following parameters of the PCM highways are programmable to allow a flexible operation: Bit rate 256 kbit/s . . . 2.048 Mbit/s Used time slots for transmission Single or double clocking Phase position and pulse length of the frame synchronization signals PFS0 . . . PFS3 Open drain output for 5 V compatibility6 The characteristic of turn around cycles The three PCM highways can be controlled completely independent, so every parameter can be set for each PCM highway individually. The standard mode of the PCM highway interface is usually the master mode. In master mode, bit clocks (pins BCLK0, BCLK1 and BCLK2) and the frame synchronization signals (FSC0, FSC1 and FSC2) are driven by the HFC-S active. In slave mode the FSC and BCLK signals are driven by an external device (e.g. an other HFC-S active in master mode). Due to the possibility to configure each PCM highway individually to master or slave mode, it is possible to build cascaded networks with HFC-S active chips. By the means of high level protocols it is possible to build ISDN networks with arbitrary complexity and topology. If a highway is not used its SDI pin must have a defined potential. Highway 3 shares its pins with the internal UART, so only one of these interfaces can be used at a time. 4.3.2 Switching buffer mechanism The data transfer between the PCM highways and the ARM7 CPU is carried out via a switching buffer mechanism. Figure 23 illustrates the scheme of the PCM data flow. 6 . . . via external pull-up resistor to a 5 V source. In this case the pin SDO0 (resp. SDO1, SDO2) have to be switched to high-Z. This is achieved with the register R HW1 TS EN (resp. R HW2 TS EN, R HW3 TS EN) for each time slot independently. The input ports of the PCM highways are 5 V tolerant. 98 of 173 Preliminary Data Sheet July 2002 ISDN related modules CPU write to buffer FSC (8kHz) read from buffer SRAM 32 x 8 Bit SDI serial / parallel - converter write to buffer LOGIC receive buffer 1 swap buffers SRAM 32 x 8 Bit receive buffer 2 SRAM 32 x 8 Bit SDO parallel / serial - converter read from buffer LOGIC transmit buffer 1 swap buffers SRAM 32 x 8 Bit transmit buffer 2 Figure 23: The scheme of the PCM highway interface The receive and transmit buffers exist in duplicate each. So the ARM7 CPU can access one buffer pair while the PCM interface operates on the other buffer pair at the same time without the risk of collisions. As an instance of the PCM highway 1, at every FSC pulse (8 kHz) the HFC-S active exchanges the R HW1 TX CUR buffer with R HW1 TX NEXT buffer (resp. R HW1 RX CUR with R HW1 RX LAST for receive direction) automatically. So the ARM7 CPU can always write to the register R HW1 TX NEXT and read from R HW1 RX LAST while the PCM highway interface writes to R HW1 TX CUR and reads from R HW1 RX CUR at the same time. If required, the switching buffer functionality can be disabled by software. In this case the software must ensure a collision-free data handling as both, the PCM highway and the ARM7 CPU, write to R HW1 TX CUR and read from R HW1 RX CUR. The PCM highway transmit buffer is implemented as a single port RAM. Therefore three waitstates must be programmed in the corresponding waitstates register at least, to assure a proper data exchange between the CPU and the PCM highway interface. The waitstates must be adjusted to the clock frequency ratio of the CPU and the PCM highway. 4.3.3 Time slot configuration The number of available time slots depends on the selected PCM data rate. This can be cofigured for each PCM interface independentliy, e.g. for the PCM highway 1 with the bitmap V HW1 BR of the register R HW1 CTRL. Four data rates are available and the number of time slots is After HFC-S active reset all time slots are switched off. The time slots can be activated by writing a ’1’ to the appropriate bit of the registers R HW1 TS EN, R HW2 TS EN or R HW1 TS EN. Additionally, time slots can be assigned to the S/T interface and the CODECs. This functionallity is part of the HFC-S actives Switching Unit (see section 4.4). July 2002 Preliminary Data Sheet 99 of 173 ISDN related modules 4.3.4 Peripheral frame synchronization signals The first PCM highway has four freely programmable peripheral frame synchronization outputs PFS0. . . PFS3. By the peripheral FSC signals each time slot can be selected for the external peripheral devices (e.g. additional external CODEC). The start position and the length of the PFSC is programmable (see R PFS0 CFG. . . R PFS3 CFG register description). 4.3.5 Enabling a PCM highway Before a PCM highway can be used some initial settings must be done7 . 1. The system frequency in the interface control register R PCM CFG must be specified. 2. The PCM highway control register read / writeust be configured: PCM data rate (bit V HW1 BR) Single- or double-bit clocking on BCLK0 output (bit V HW1 DCLK) Rising or falling edge of transmit and receive date (bits V HW1 TX EDGEand V HW1 RX EDGE) Number of turn around cycles (bitmap V BCLK0 WAIT), V SD0 WAITmust be set to ’1’ if turn around cycles are greater than zero Master or slave mode of the PCM highway (bit V HW1 MASTER) V HW1 SDO0 EN = ’1’ if the PCM highway has to run with a permanently data stream on SDO0, with V HW1 SDO0 EN = ’0’ certain time slots can be enabled or disabled independently. In this functional setting there are further configuration options, i.e. a switching unit allows to connect the HFC-S active CODESCs und S/T interface to arbitrary time slots (see section 4.4). Switching buffer enable or disable (bit V HW1 BUFF OFF) 3. The switching buffers must be initialized, i.e. the registers R HW1 TX CUR and R HW1 TX NEXT should get meaningful contents. 4. For the PCM highway 1 only, the peripheral FSC registers R PFS0 CFG . . . R PFS3 CFG have to be initialized. 5. The bit clock BCLK0 has to be enabled by setting V HW1 BCLK EN = ’1’. 6. Finally, V HW1 FSC0 EN = ’1’ enables the FSC0 clock signal. After this bit has been set the BCLK0 signal is started after the next FSC pulse. Changes to the system frequency, data rate and bit clock take effect immediately and may not be done while the highway is enabled. The figures 24 to 26 show some timing examples for different highway settings which are listed in table 33. 7 This section describes the highway 1 settings and is valid for the other two PCM highways in the same way. 100 of 173 Preliminary Data Sheet July 2002 ISDN related modules Table 33: Configuration settings for the timing examples in figures 24 to 26 V HW1 DCLK V HW1 TX EDGE V HW1 RX EDGE V SD0 WAIT V BCLK0 WAIT 24 ’0’ (single) ’0’ (rising edge) ’0’ (falling edge) ’1’ (enable) ’001’ (1 wait cycle) 25 ’0’ (single) ’0’ (rising edge) ’1’ (rising edge) ’1’ (enable) ’011’ (3 wait cycles) 26 ’1’ (double) ’1’ (falling edge) ’1’ (rising edge) ’0’ (disable) ’xxx’ (no wait cycles) Figure BSCK FSC SDO TS 0 - 1. Bit SDI 1. Bit TS 0 - 2. Bit 2. Bit TS 0 - 3. Bit TS 0 - 4. Bit 3. Bit TS 0 - 5. Bit 4. Bit 5. Bit TS = Timeslot Figure 24: PCM timing with the configuration shown in table 33 (1st line) BSCK FSC SDO TS 0 - 1. Bit SDI TS 0 - 2. Bit 1. Bit TS 0 - 3. Bit 2. Bit TS = Timeslot Figure 25: PCM timing with the configuration shown in table 33 (2nd line) BSCK FSC SDO SDI TS 0 - 1. Bit 1. Bit TS 0 - 2. Bit 2. Bit TS 0 - 3. Bit TS 0 - 4. Bit 3. Bit 4. Bit TS 0 - 5. Bit 5. Bit TS = Timeslot Figure 26: PCM timing with the configuration shown in table 33 (3rd line) July 2002 Preliminary Data Sheet 101 of 173 ISDN related modules G Note ! Exemplary for the PCM highway 1, the bit clock BCLK0 is required for the data transfer and must be enabled first. If both V HW1 BCLK EN and V HW1 FSC0 EN of the register R HW1 CTRL are set at the same time, the operation is as follows: 1. After the 1st FSC pulse the bit clock BCLK0 (. . . BCLK2) will be enabled. 2. After the 2nd FSC pulse also the data transfer on the highway will be enabled. (This note is valid for the other two PCM highways in the same way.) 4.3.6 Disabling a PCM highway To ensure a proper data transfer halt, the PCM highway should be disabled in two steps (described for PCM highway 1, also valid for the other two PCM highways): 1. Setting V HW1 FSC0 EN = 0 the data transfer will be disabled after the next FSC pulse. The bit clock BCLK0 will remain available. 2. Setting V HW1 BCLK EN = 0 the bit clock BCLK0 will be stopped immediately. If the first point is not executed before the second one, the data transmisson may be stopped right in the middle of a byte! 102 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4.3.7 Register description R HW1 TX NEXT (read / write) 0x000B0000 Base address of the PCM Highway 1 next send register The send buffer operates as a switching buffer. So the CPU can write to the next transmit buffer and the hardware can send the current data without any collisions. At every FSC pulse (8 kHz) the HFC-S active changes the R HW1 TX NEXT buffer to R HW1 TX CUR buffer automatically. If required, the switching buffer functionality can be disabled by software. The PCM highway transmit buffer is implemented as a single port RAM. Therefore three waitstates must be programmed in the corresponding waitstates register at least, to assure a proper data exchange between the CPU and the PCM highway interface. The waitstates must be adjusted to the clock frequency ratio of the CPU and the PCM highway. The transmit buffer RAM supports 8 / 16 / 32 bit access. Bits Reset Name Description V HW1 TX NEXT the access to address 0x000B0000 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW1 RX LAST (read / write) 0x000B0020 Base address of the PCM Highway 1 last receive register. Bits Reset Name Description V HW1 RX LAST the access to address 0x000B0020 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 July 2002 0 Preliminary Data Sheet 103 of 173 ISDN related modules R HW2 TX NEXT (read / write) 0x000B0040 Base address of the PCM Highway 2 next send register The send buffer operates as a switching buffer. So the CPU can write to the next transmit buffer and the hardware can send the current data without any collisions. At every FSC pulse (8 kHz) the HFC-S active changes the R HW2 TX NEXT buffer to R HW2 TX CUR buffer automatically. If required the switching buffer functionality can be disabled by software. Bits Reset Name Description V HW2 TX NEXT the access to address 0x000B0040 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW2 RX LAST (read / write) 0x000B0060 Base address of the PCM Highway 2 last receive register Bits Reset Name Description V HW2 RX LAST the access to address 0x000B0060 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW3 TX NEXT (read / write) 0x000B0080 Base address of the PCM Highway 3 next send register The send buffer operates as a switching buffer. So the CPU can write to the next transmit buffer and the hardware can send the current data without any collisions. At every FSC pulse (8 kHz) the HFC-S active changes the R HW3 TX NEXT buffer to R HW3 TX CUR buffer automatically. If required the switching buffer functionality can be disabled by software. Bits Reset Name Description V HW3 TX NEXT the access to address 0x000B0080 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 104 of 173 0 Preliminary Data Sheet July 2002 ISDN related modules R HW3 RX LAST (read / write) 0x000B00A0 Base address of the PCM Highway 3 last receive register. Bits Reset Name Description V HW3 RX LAST the access to address 0x000B00A0 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW1 TX CUR (read / write) 0x000B0100 Base address of the PCM highway 1 current send register. The hardware prevent the collision automatically. By writing to this register the software has to take care of the consistence of the data. This register must be used, if the switching buffer is disabled. Bits Reset Name Description V HW1 TX CUR the access to address 0x000B0100 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW1 RX CUR (read / write) 0x000B0120 Base address of the PCM highway 1 current receive register. The hardware prevent the collision automatically. By writing to this register the software has to take care of the consistence of the data. This register must be used, if the switching buffer is disabled. Bits Reset Name Description V HW1 RX CUR the access to address 0x000B0120 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 July 2002 0 Preliminary Data Sheet 105 of 173 ISDN related modules R HW2 TX CUR (read / write) 0x000B0140 Base address of the PCM highway 2 current send register. The hardware prevent the collision automatically. By writing to this register the software has to take care of the consistence of the data. This register must be used, if the switching buffer is disabled. Bits Reset Name Description V HW2 TX CUR the access to address 0x000B0140 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW2 RX CUR (read / write) 0x000B0160 Base address of the PCM highway 2 current receive register. The hardware prevent the collision automatically. By writing to this register the software has to take care of the consistence of the data. This register must be used, if the switching buffer is disabled. Bits Reset Name Description V HW2 RX CUR the access to address 0x000B0160 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW3 TX CUR (read / write) 0x000B0180 Base address of the PCM highway 3 current send register. The hardware prevent the collision automatically. By writing to this register the software has to take care of the consistence of the data. This register must be used, if the switching buffer is disabled. Bits Reset Name Description V HW3 TX CUR the access to address 0x000B0180 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 106 of 173 0 Preliminary Data Sheet July 2002 ISDN related modules R HW3 RX CUR (read / write) 0x000B01A0 Base address of the PCM highway 3 current receive register. The hardware prevent the collision automatically. By writing to this register the software has to take care of the consistence of the data. This register must be used, if the switching buffer is disabled. Bits Reset Name Description V HW3 RX CUR the access to address 0x000B01A0 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 R HW1 TS EN (read / write) 0x000B01E8 Time slot enable register The bit number is equal to the timslot number. ’0’ = port SDO is high-Z ’1’ = time slot is active Bits Reset Name Description Value 31..0 0x00000000 V HW1 TS EN R HW2 TS EN enable register of highway 1 time slots for transmission (read / write) 0x000B01EC Time slot enable register The bit number is equal to the timslot number. ’0’ = port SDO is high-Z ’1’ = time slot is active Bits Reset Name Description Value 31..0 July 2002 0x00000000 V HW2 TS EN enable register of highway 2 time slots for transmission Preliminary Data Sheet 107 of 173 ISDN related modules R HW3 TS EN (read / write) 0x000B01F0 Time slot enable register The bit number is equal to the timslot number. ’0’ = port SDO is high-Z ’1’ = time slot is active Bits Reset Name Description Value 31..0 0x00000000 V HW3 TS EN R PFS0 CFG enable register of highway 3 time slots for transmission (read / write) 0x000B01F4 Control register for the frame synchronization signal on PFS0 port Bits Reset Name Description V PFS0 START defines the start position of the PFS0 signal Value 8..0 0 Note: The value refers to the number of clock cycles of the BCLK signal. 15..9 0 V PFS0 LEN defines the length of the PFS0 signal Note: The value refers to the number of clock cycles of the BCLK signal. R PFS1 CFG (read / write) 0x000B01F6 Control register for the frame synchronization signal on PFS1 port Bits Reset Name Description V PFS1 START defines the start position of the PFS1 signal Value 8..0 0 Note: The value refers to the number of clock cycles of the BCLK signal. 15..9 0 V PFS1 LEN defines the length of the PFS1 signal Note: The value refers to the number of clock cycles of the BCLK signal. 108 of 173 Preliminary Data Sheet July 2002 ISDN related modules R PFS2 CFG (read / write) 0x000B01F8 Control register for the frame synchronization signal on PFS2 port Bits Reset Name Description V PFS2 START defines the start position of the PFS2 signal Value 8..0 0 Note: The value refers to the number of clock cycles of the BCLK signal. 15..9 0 V PFS2 LEN defines the length of the PFS2 signal Note: The value refers to the number of clock cycles of the BCLK signal. R PFS3 CFG (read / write) 0x000B01FA Control register for the frame synchronization signal on PFS3 port Bits Reset Name Description V PFS3 START defines the start position of the PF3 signal Value 8..0 0 Note: The value refers to the number of clock cycles of the BCLK signal. 15..9 0 V PFS3 LEN defines the length of the PFS3 signal Note: The value refers to the number of clock cycles of the BCLK signal. July 2002 Preliminary Data Sheet 109 of 173 ISDN related modules R PCM CFG (read / write) 0x000B0200 Control register for PCM highway interface configuration. Bits Reset Name Description V PCM CLK defines the operating frequency of the PCM highway interfaces Value 2..0 0 Coding: ’000’ 12.288 MHz ’001’ 24.576 MHz ’010’ 36.864 MHz ’100’ 61.440 MHz Note: The PCM highway interface gets the external (12.288 MHz) system clock always. At 12.288 MHz system frequency these bits should be left on zero. 3 7..4 110 of 173 0 V CODEC ST enables the coupling between S/T and CODECs ’0’ = disable ’1’ = enable (reserved) Preliminary Data Sheet July 2002 ISDN related modules R HW1 CTRL (read / write) 0x000B0204 Control register for PCM Highway 1 Bits Reset Name Description Value 0 0 V HW1 BCLK EN enables the clock signal on BCLK0 (bit clock) port ’0’ =off ’1’ = on 1 0 V HW1 FSC0 EN enables the frame synchronization signal on FSC0 port ’0’ = off ’1’ = on 2 0 V HW1 EN enables the switching unit for the PCM Highway 1 ’0’ = off ’1’ = on 4..3 0 V HW1 BR defines the transmission rate on the PCM Highwa 1 Coding: ’00’ 2048 kBit/s ’01’ 768 kBit/s ’10’ 512 kBit/s ’11’ 256 kBit/s 5 0 V HW1 DCLK enables the double clocking mode on PCM Highway 1 ’0’ = single clock ’1’ = double clock 6 0 V HW1 TX EDGE defines the output edge of sending data ’0’ = rising edge ’1’ = falling edge 7 0 V HW1 RX EDGE defines the sampling edge of receiving data ’0’ = falling edge ’1’ = rising edge 8 0 V SD0 WAIT enables turn around cycles (wait cycles between FSC and first data bit) on SDO0 port ’0’ = disable ’1’ = enable 11..9 0 V BCLK0 WAIT defines the number of turn around cycles in BCCK0 clock units (’000’ = 0 and so on) 12 0 V HW1 MASTER Defines the mode for PCM Highway 1. In slave mode the port FSC0 and BCLK0 are not driven by the HFC-S active (high-Z). ’0’ = slave ’1’ = master 13 0 V HW1 SDO0 EN Enables permanently the SDO0 Port of the PCM Highway 1. If enable the entry in the R HW1 TS EN has no influence. ’0’ = disable ’1’ = enable July 2002 Preliminary Data Sheet 111 of 173 ISDN related modules Bits Reset Name Description V HW1 BUFF OFF disables the switching buffer for the PCM Highway 1 ’1’ = off ’0’ = on Value 14 0 15 112 of 173 (reserved) Preliminary Data Sheet July 2002 ISDN related modules R HW2 CTRL (read / write) 0x000B0208 Control register for PCM Highway 2 Bits Reset Name Description Value 0 0 V HW2 BCLK EN enables the clock signal on BCLK1 (bit clock) port ’0’ = off ’1’ = on 1 0 V HW2 FSC1 EN enables the frame synchronization signal on FSC1 port ’0’ = off ’1’ = on 2 0 V HW2 EN enables the switching unit for the PCM Highway 2 ’0’ = off ’1’ = on 4..3 0 V HW2 BR defines the transmission rate on the PCM Highway 2 Coding: ’00’ 2048 kBit/s ’01’ 768 kBit/s ’10’ 512 kBit/s ’11’ 256 kBit/s 5 0 V HW2 DCLK enables the double clocking mode on PCM Highway 2 ’0’ = single clock ’1’ = double clock 6 0 V HW2 TX EDGE defines the output edge of sending data ’0’ = rising edge ’1’ = falling edge 7 0 V HW2 RX EDGE defines the sampling edge of receiving data ’0’ = falling edge ’1’ = rising edge 8 0 V SD1 WAIT enables turn around cycles (wait cycles between FSC and first data bit) on SDO1 port ’0’ = disable ’1’ = enable 11..9 0 V BCLK1 WAIT defines the number of turn around cycles in BCCK1 clock units (’000’ = 0 and so on) 12 0 V HW2 MASTER Defines the mode for PCM Highway 2. In slave mode the port FSC1 and BCK1 are not driven by the HFC-S active (high-Z). ’0’ = slave ’1’ = master 13 0 V HW2 SDO1 EN Enables permanently the SDO1 Port of the PCM Highway 2. If enabled, the entry in the R HW2 TS EN has no influence. ’0’ = disable ’1’ = enable July 2002 Preliminary Data Sheet 113 of 173 ISDN related modules Bits Reset Name Description V HW2 BUFF OFF disables the switching buffer for the PCM Highway 2 ’1’ = off ’0’ = on Value 14 0 15 114 of 173 (reserved) Preliminary Data Sheet July 2002 ISDN related modules R HW3 CTRL (read / write) 0x000B020C Control register for PCM Highway 3 Bits Reset Name Description Value 0 0 V HW3 BCLK EN Enables the clock signal on BCLK2 (bit clock) port. ’0’ = off ’1’ = on 1 0 V HW3 FSC2 EN enables the frame synchronization signal on FSC2 port ’0’ = off ’1’ = on 2 0 V HW3 EN enables the switching unit for the PCM Highway 3 ’0’ = off ’1’ = on 4..3 0 V HW3 BR defines the transmission rate on the PCM Highway 3 Coding: ’00’ 2048 kBit/s ’01’ 768 kBit/s ’10’ 512 kBit/s ’11’ 256 kBit/s 5 0 V HW3 DCLK enables the double clocking mode on PCM Highway 3 ’0’ = single clock ’1’ = double clock 6 0 V HW3 TX EDGE defines the output edge of sending data ’0’ = rising edge ’1’ = falling edge 7 0 V HW3 RX EDGE defines the sampling edge of receiving data ’0’ = falling edge ’1’ = rising edge 8 0 V SD2 WAIT enables turn around cycles (wait cycles between FSC and first data bit) on SDO2 port ’0’ = disable ’1’ = enable 11..9 0 V BCLK2 WAIT defines the number of the coupling turn around cycles in BCCK1 clock units (’000’ = 0 and so on) 12 0 V HW3 MASTER Defines the mode for PCM Highway 3. In slave mode the port FSC2 and BCLK2 are not driven by the HFC-S active (high-Z). ’0’ = slave ’1’ = master 13 0 V HW3 SD2 EN Enables permanently the SDO2 Port of the PCM Highway 2. If enabled the entry in the R HW3 TS EN has no influence. ’0’ = disable ’1’ = enable July 2002 Preliminary Data Sheet 115 of 173 ISDN related modules Bits Reset Name Description V HW3 BUFF OFF disables the switching buffer for the PCM Highway 3 ’1’ = off ’0’ = on Value 14 0 (reserved) 15 R HW SL CNT (read only) 0x000B0210 Slot count register for the PCM highways Bits Reset Name Description 4..0 V HW1 SL Number of the current time slot of highway 1 5 V HW1 BUFF buffer position of highway 1 switching buffer 7..6 (reserved) 12..8 V HW2 SL Number of the current time slot of highway 2 13 V HW2 BUFF buffer position of highway 2 switching buffer 15..14 (reserved) 20..16 V HW3 SL Number of the current time slot of highway 3 21 V HW3 BUFF buffer position of highway 3 switching buffer 31..22 (reserved) Value 116 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4.4 Switching unit Table 34: Overview of the HFC-S active switching unit registers Address Name Page Address Name Page 0x000B00C0 R HW1 IDX 120 0x000B01E4 R ST IDX 121 0x000B00E0 R HW2 IDX 120 0x000B01E8 R HW1 TS EN 107 0x000B01C0 R HW3 IDX 120 0x000B01EC R HW2 TS EN 107 0x000B01E0 R CODEC IDX 121 0x000B01F0 R HW3 TS EN 108 The switching unit is a data distribution modul which can connect the PCM highways, the S/T interface and the CODEC module directly without keeping the ARM7 CPU busy. An overview of the data distribution is shown in figure 27. Alternative data streams can be processed via the CPU. switching unit PCM highway interface S/T interface ARM7 CPU CODEC interface Figure 27: Data distribution in the HFC-S active system 4.4.1 Source index registers The data coupling can be established between the 32 PCM time slots of each highway, the two CODECs (in compressed or linear data mode, one or two bytes each) and the B1- and B2-channels of the S/T interface. So there are data sources as listes in table 35. Each data source is implemented as an index register. Table 35 shows base addresses and index values for 32 bit (resp. 16 bit for the S/T interface) accesses. Alternatively, all registers can be accessed by word and byte access, e.g. address 0x000B00D1 to access time slot 17 of PCM highway 1. 4.4.2 Destination codes For each data source the destination must be specified. The destination code is a 8 bit value. Table36 shows all defined values. These have to be written into the data source index registers. July 2002 Preliminary Data Sheet 117 of 173 ISDN related modules Table 35: Source registers of the switching unit (TS = time slot, high (resp. low) = higher (resp. lower) byte of the CODECs 1 and 2) Data source Source index register Byte 3 Byte 2 Byte 1 Byte 0 0x000B00C0 0x00 TS 3 TS 2 TS 1 TS 0 0x04 TS 7 TS 6 TS 5 TS 4 0x08 TS 11 TS 10 TS 9 TS 8 0x0C TS 15 TS 14 TS 13 TS 12 0x10 TS 19 TS 18 TS 17 TS 16 0x14 TS 23 TS 22 TS 21 TS 20 0x18 TS 25 TS 24 TS 23 TS 24 0x1C TS 31 TS 30 TS 29 TS 28 0x000B00E0 0x00 TS 3 TS 2 TS 1 TS 0 0x04 TS 7 TS 6 TS 5 TS 4 0x08 TS 11 TS 10 TS 9 TS 8 0x0C TS 15 TS 14 TS 13 TS 12 0x10 TS 19 TS 18 TS 17 TS 16 0x14 TS 23 TS 22 TS 21 TS 20 0x18 TS 25 TS 24 TS 23 TS 24 0x1C TS 31 TS 30 TS 29 TS 28 0x000B01C0 0x00 TS 3 TS 2 TS 1 TS 0 0x04 TS 7 TS 6 TS 5 TS 4 0x08 TS 11 TS 10 TS 9 TS 8 0x0C TS 15 TS 14 TS 13 TS 12 0x10 TS 19 TS 18 TS 17 TS 16 0x14 TS 23 TS 22 TS 21 TS 20 0x18 TS 25 TS 24 TS 23 TS 24 0x1C TS 31 TS 30 TS 29 TS 28 high 2 low 2 high 1 low 1 – – B2 B1 (base address index) 32 time slots of PCM highway 1 32 time slots of PCM highway 2 32 time slots of PCM highway 3 CODEC R HW1 IDX R HW2 IDX R HW3 IDX R CODEC IDX 0x000B01E0 S/T interface R ST IDX 0x000B01E4 118 of 173 Preliminary Data Sheet July 2002 ISDN related modules Table 36: Destination codes of the switching unit (TS = time slot, high (resp. low) = higher (resp. lower) byte of the CODECs 1 and 2) HFC-S active module Data destination Destination code PCM highway 1 32 time slots ( ) 0x00 (range 0x00 . . . 0x1F) PCM highway 2 32 time slots ( ) 0x20 (range 0x20 . . . 0x3F) PCM highway 3 32 time slots ( ) 0x40 (range 0x40 . . . 0x5F) CODEC 1 low 1 0x60 high 1 0x61 low 2 0x62 high 2 0x63 B1 0x64 B2 0x65 ‘disable code’ 0x80 CODEC 2 S/T interface – July 2002 Preliminary Data Sheet 119 of 173 ISDN related modules 4.4.3 Register description R HW1 IDX (read / write) 0x000B00C0 Base address of the index register for the PCM highway 1. The values written to this 32 byte register define the destination for the PCM data of each time slot. Bits Reset Name Description V HW1 IDX the access to address 0x000B00C0 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 Note: Values to be written into this register are shown in table 36 R HW2 IDX (read / write) 0x000B00E0 Base address of the index register for the PCM highway 2. The values written to this 32 byte register define the destination for the PCM data of each time slot. Bits Reset Name Description V HW2 IDX the access to address 0x000B00E0 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 Note: Values to be written into this register are shown in table 36 R HW3 IDX (read / write) 0x000B01C0 Base address of the index register for the PCM highway 3. The values written to this 32 byte register define the destination for the PCM data of each time slot. Bits Reset Name Description V HW3 IDX the access to address 0x000B01C0 selects the time slots in byte 0 . . . byte 3 ( ) Value 31..0 0 Note: Values to be written into this register are shown in table 36 120 of 173 Preliminary Data Sheet July 2002 ISDN related modules R CODEC IDX (read / write) 0x000B01E0 Index register of the CODECs Bits Reset Name Description Value 7..0 0 V CODEC1L Lower byte for data coupling between CODEC and time slots of the PCM highways. The lower byte of the CODEC is used for the -law or -law mode of the CODEC. In linear mode two time slots have to be used for 14 bit CODEC data (lower byte, higher byte). 15..8 0 V CODEC1H higher byte for data coupling between CODEC and time slots of the PCM highways 23..16 0 V CODEC2L lower byte for data coupling between CODEC and time slots of the PCM highways. The lower byte of the CODEC is used for the -law or -law mode of the CODEC. In linear mode two time slots have to be used for 14 bit CODEC data (lower byte, higher byte). 31..24 0 V CODEC2H higher byte for data coupling between CODEC and time slots of the PCM highways R ST IDX (read / write) 0x000B01E4 Index register for the B1- and B2-channels of the S/T interface Bits Reset Name Description Value 7..0 0 V ST B1 coupling between B1-channel and time slots of the PCM highways 15..8 0 V ST B2 coupling between B2-channel and time slots of the PCM highways July 2002 Preliminary Data Sheet 121 of 173 ISDN related modules 4.5 CODEC module 4.5.1 Functional description The HFC-S active has two sigma delta audio CODECs for speech and telephony applications. Each CODEC contains both digital IIR / FIR filters and smoothing filters. The normal input and output channels have - / a-law format with 38 dB signal-to-noise distortion ratio. The digital data format for input and output data of this device can be 8 bit companded data (a-law, -law) or 14 bit linear data which can be easily selected by the CODEC control register. An on-chip voltage reference circuit is included to allow single supply operation. 122 of 173 Preliminary Data Sheet July 2002 ISDN related modules 4.5.2 Register description R CODEC TX (read / write) 0x000D0000 Codec transmit register Bits Reset Name Description data for CODEC 1 If companded data (a-law/-law) is selected, only bits 7 . . . 0 are used. Value 13..0 0 V CODEC1 TX 15..14 0 (reserved) 29..16 0 V CODEC2 TX 31..30 0 (reserved) R CODEC RX data for CODEC 2 If companded data (a-law/-law) is selected, only bits 7 . . . 0 are used. (read only) 0x000D0004 Codec linear mode receive register Bits Reset Name Description V CODEC1 RX data from CODEC 1 (valid in linear mode only) (reserved) reserved V CODEC2 RX data from CODEC 2 (valid in linear mode only) (reserved) reserved Value 13..0 0 15..14 29..16 31..30 July 2002 0 Preliminary Data Sheet 123 of 173 ISDN related modules R CODEC RX8 (read only) 0x000D0008 Codec compand mode receive register Bits Reset Name Description V CODEC1 RX8 data from CODEC 1 (valid in compand mode only) Value 7..0 0 (reserved) 15..8 23..16 31..24 124 of 173 0 V CODEC2 RX8 data from CODEC 2 (valid in compand mode only) (reserved) reserved Preliminary Data Sheet July 2002 ISDN related modules R CODEC CTRL (read / write) 0x000D000C Codec control register Bits Reset Name Description Value 0 0 V CODEC1 TX LIN select CODEC 1 transmit mode ’0’ = 8 bit companded ’1’ = 14 bit linear 1 0 V CODEC2 TX LIN select CODEC 2 transmit mode ’0’ = 8 bit companded ’1’ = 14 bit linear 2 0 V CODEC1 RX LIN select CODEC 1 receive mode ’0’ = 8 bit companded ’1’ = 14 bit linear 3 0 V CODEC2 RX LIN select CODEC 2 receive mode ’0’ = 8 bit companded ’1’ = 14 bit linear 4 0 V PCM CODEC1 use data from PCM highway as transmit data for CODEC 1 ’0’ = data from registers ’1’ = data from PCM highway 5 0 V PCM CODEC2 use data from PCM highway as transmit data for CODEC 2 ’0’ = data from registers ’1’ = data from PCM highway 6 0 V CODEC1 CODEC2 use receive data from CODEC 1 as transmit data for CODEC 2 ’0’ = inactive ’1’ = active 7 0 V CODEC2 CODEC1 use receive data from CODEC 2 as transmit data for CODEC 1. ’0’ = inactive ’1’ = active 8 0 V CODEC1 MUTE Codec 1 analog mute ’1’ = mute ’0’ = normal operation 9 0 V CODEC2 MUTE Codec 2 analog mute ’1’ = mute ’0’ = normal operation 10 0 V CODEC1 LOOP Codec 1 analog loopback ’1’ = loopback ’0’ = normal operation 11 0 V CODEC2 LOOP Codec 2 analog loopback ’1’ = loopback ’0’ = normal operation 12 0 V CODEC1 ADC OFF Codec 1 ADC power down ’1’ = power down ’0’ = normal operation July 2002 Preliminary Data Sheet 125 of 173 ISDN related modules Bits Reset Name Description Value 13 0 V CODEC2 ADC OFF Codec 2 ADC power down ’1’ = power down ’0’ = normal operation 14 0 V CODEC1 DAC OFF Codec 1 DAC power down ’1’ = power down ’0’ = normal operation 15 0 V CODEC2 DAC OFF Codec 2 DAC power down ’1’ = power down ’0’ = normal operation 16 0 V CODEC1 ALAW Codec 1 a-law/-law select, applies only when 8 bit companded data is selected ’1’= a-law ’0’ = -law 17 0 V CODEC2 ALAW Codec 2 a-law/-law select, applies only when 8 bit companded data is selected ’1’ = a-law ’0’ = -law (reserved) must be set to 0x00 25..18 26 0 V CODEC1 RES controls reset signal of CODEC 1 ’1’ = reset ’0’ = normal operation 27 0 V CODEC2 RES controls reset signal of CODEC 2 ’1’ = reset ’0’ = normal operation 28 0 V CODEC1 INV invert data bits 6 . . . 0 for G.711 conformity in a-law mode, this bit should be set to ’1’ in a-law mode, else ’0’ 29 0 V CODEC2 INV invert data bits 6 . . . 0 for G.711 conformity in a-law mode, this bit should be set to ’1’ in a-law mode, else ’0’ 30 0 V CODEC1 INV7 invert data bit 7 for G.711 conformity in -law mode, this bit should be set to ’1’ in -law mode, else ’0’ 31 0 V CODEC2 INV7 invert data bit 7 for G.711 conformity in -law mode, this bit should be set to ’1’ in -law mode, else ’0’. 126 of 173 Preliminary Data Sheet July 2002 Interfaces 5 Interfaces 5.1 General purpose input and output pins (GPIO) 5.1.1 Functional description The HFC-S active has up to 31 GPIO pins: : 16 bidirectional GPIO pins with interrupt capabilities GPIO[15:0] GPIO[25:16] : 10 bidirectional GPIO pins GPI[0] : 1 GPI pin (input only) GPO[3:0] : 4 GPO pins (output only) 19 of these GPIOs are always mapped to package pins. The other 12 GPIOs can be mapped to other function pins when the primary function of those pins is not needed. It is possible to select the function (primary function / GPIO function) for each pin individually. 16 Bit M_GPIO_DIR R_GPIO_CTRL1 16 16 Bit M_GPIO_OUT R_GPIO_OUT 16 16 I/O - Pin 16 Bit M_GPIO_MSK R_GPIO_OUT 16 Bit M_GPIO_IN Bit 0 R_GPIO_IN IRQ Bit 1 .. ... .. .. .. . Bit15 .. .. .. .. .. .. .. . 16 EDGE DETECTOR Bit15 Bit 1 Bit 0 .. . .. . Bit15 Bit 1 Bit 0 16 Bit M_GPIO_IRQ_EDGE R_GPIO_IRQ_CTRL 16 16 16 Bit 16 Bit M_GPIO_IRQ_EN M_GPIO_IRQ R_GPIO_CFG R_GPIO_IRQ_CTRL Figure 28: Simplified representation for the primary GPIO[15:0] functionality The direction of most GPIOs is individually configurable by the software. Each port of GPIO[15:0] can be used as an input signal for the FSC-PLL synchronization. With these pins it is possible to output some internal signals (like time pulses, PWM pulses, FSC, watchdog pulse) on the GPIO ports. The interrupt capability of the GPIO[15:0] pins is also valid on these pins if the primary function is selected. The bits of the data out register for GPIO[15:0] are maskable, i.e. that each bit can be set by the software without influence on any other bit. The edge for the GPIO interrupt is programmable for each bit of GPIO[15:0] and each GPIO interrupt can be enabled or disabled. July 2002 Preliminary Data Sheet 127 of 173 Interfaces Table 37: Overview of GPIO functions (DIR = signal direction input / output) Pin Primary function DIR GPIO function DIR 1 CARRY1 (timer 1 carry signal) O GPIO0 I/O 9 A20 (external address bus) O GPO2 O 10 A21 (external address bus) O GPO3 O 12 A18 (external address bus) O GPO0 O 13 A19 (external address bus) O GPO1 O GPI0 I 75 86 CLK OUT (system clock ) O 87 GPIO17 I/O GPIO16 I/O 88 EOFT (EOFT signal of the S/T interface) O GPIO15 I/O 89 DK REP (DK REP signal of the S/T interface) O GPIO14 I/O 90 DK EN (DK EN signal of the S/T interface) O GPIO13 I/O 101 SDI1 (serial data input for PCM highway 2) I GPIO18 I/O 102 SDO1 (serial data output for PCM highway 2) O GPIO19 I/O 103 BCLK1 (bit clock for PCM highway 2) O GPIO20 I/O 104 FSC1 (frame sync signal for PCM highway 2) I/O GPIO21 I/O 105 SDI2 (serial data input for PCM highway 3) I GPIO22 I/O 106 SDO2 (serial data output for PCM highway 3) O GPIO23 I/O 111 RXD (serial receive data (UART)) I GPIO24 I/O 112 TXD (serial transmit data (UART)) O GPIO25 I/O 115 CLK ST (S/T clock ) O GPIO12 I/O 116 CLK EXT (clock for external devices ( )) O GPIO11 I/O () O GPIO10 I/O 117 118 FSC TE (FSC TE signal of the S/T interface) O GPIO9 I/O 119 WDT (carry signal of the watchdog timer) O GPIO8 I/O 120 PFS3 (peripheral frame sync 3 signal with interrupt capability) O GPIO7 I/O 121 PFS2 (peripheral frame sync 2 signal with interrupt capability) O GPIO6 I/O 122 PSF1 (peripheral frame sync 1 signal with interrupt capability) O GPIO5 I/O 157 PFS0 (peripheral frame sync 0 signal with interrupt capability) O GPIO4 I/O () O GPIO3 I/O 158 159 PWM OUT (PWM output) O GPIO2 I/O 160 CARRY2 (Timer 2 carry signal) O GPIO1 I/O 128 of 173 Preliminary Data Sheet July 2002 Interfaces 5.1.2 Register description R GPIO CFG (read / write) 0x00090014 Configuration register for the primary GPIOs (interrupt and prescaler for FSC source) Bits Reset Name Description Value 15..0 0x0000 V GPIO IRQ EN interrupt enable register for each GPIO[15:0] pin each bit ’1’ = interrupt enable ’0’ = interrupt disable 25..16 0x000 V FSC PREDIV predivider for the external FSC signal of GPIO[15:0] for the FSC-PLL synchronization The external FSC signal can be a multiple of 8 kHz 29..26 0 V FSC GPIO SEL Selects the GPIO port as source for the FSC synchronization One of 16 ports is selected (reserved) 31..30 R GPIO IRQ CTRL (read / write) 0x00090018 GPIO[15:0] interrupt control and status register Bits Reset Name Description Value 15..0 0x0000 V GPIO IRQ shows the interrupt status for each GPIO interrupt (writing a zero value sets back the interrupt request) 31..16 0x0000 V GPIO IRQ EDGE selects the trigger edge for each GPIO interrupt ’1’ = rising edge ’0’ = falling edge July 2002 Preliminary Data Sheet 129 of 173 Interfaces R GPIO OUT (read / write) 0x0009001C GPIO[15:0] data output register Bits Reset Name Description Value 15..0 0x0000 V GPIO OUT sets the value (level) on each GPIO port. It takes one clock cycle to switch output data to this register. 31..16 0xFFFF V GPIO OUTMSK Sets the mask for the data output value Only a ’1’ in the mask allows new setting in the V GPIO OUT bitmap. ’1’ = on ’0’ = off R GPIO IN1 (read only) 0x00090020 GPIO[15:0] data input register Bits Reset Name Description Value 15..0 0x0000 V GPIO IN1 represents the input status of the GPIO port. (reserved) 31..16 R GPIO IN2 (read only) 0x00080034 GPIO[25:16] and GPI[0] data input register Bits Reset Name Description 9..0 V GPIO IN2 represents the input status of the GPIO[25:16] port. 10 V GPI IN represents the input status of the GPI[0] port. Value 130 of 173 Preliminary Data Sheet July 2002 Interfaces R GPIO CTRL1 (read / write) 0x00090024 GPIO[15:0] output enable register and port mapping Setting a bit of bitmap [31:16] disables the corresponding bit in V GPIO DIR (’0’ = disable, ’1’ = enable) Bits Reset Name Description Value 15..0 0x0000 V GPIO DIR controls the direction for each GPIO ’1’ = output ’0’ = input 16 0 V GPIO0 TI1 enables timer 1 carry signal on GPIO 0 17 0 V GPIO1 TI2 enables timer 2 carry signal on GPIO 1 18 0 V GPIO2 PWM enables PWM signal on GPIO 2 19 0 V GPIO3 FSC enables internal FSC signal on GPIO 3 20 0 V GPIO4 PFS0 enables internal PFS0 (peripheral frame sync) signal on GPIO 4 21 0 V GPIO5 PFS1 enables internal PFS1 (peripheral frame sync) signal on GPIO 5 22 0 V GPIO6 PFS2 enables internal PFS2 (peripheral frame sync) signal on GPIO 6 23 0 V GPIO7 PFS3 enables internal PFS3 (peripheral frame sync) signal on GPIO 7 24 0 V GPIO8 WD enables watchdog carry signal on GPIO 8 25 0 V GPIO9 FSC ST enables the FSC TE (S/T-Interface) signal on GPIO 9 26 0 V GPIO10 FSC CONST enables the constructed FSC signal on GPIO 10 27 0 V GPIO11 CNT1B enables signal on GPIO 11 28 0 V GPIO12 CNT1A enables internal S/T interface clock (12.288/2 MHz) signal on GPIO 12 29 0 V GPIO13 DKEN enables the internal DK EN signal of the S/T interface on GPIO 13 30 0 V GPIO14 DKREP enables the internal DK REP signal of the S/T interface on GPIO 14 31 0 V GPIO15 EOFT enables the internal EOFT signal of the S/T interface on GPIO 15 July 2002 Preliminary Data Sheet 131 of 173 Interfaces R GPO CTRL (read / write) 0x0008002C GPO[3:0] control register Bits Reset Name Description Value 3..0 0 V GPO DATA 4 bit output value for GPO[3:0] (applies only when the corresponding bit of V GPO0 EN . . . V GPO3 EN is set) 4 0 V GPO0 EN selects function of pin ADDR[18] ’1’ = secondary function GPO[0] ’0’ = ADDR[18] 5 0 V GPO1 EN selects function of pin ADDR[19] ’1’ = secondary function GPO[1] ’0’ = ADDR[19] 6 0 V GPO2 EN selects function of pin ADDR[20] ’1’ = secondary function GPO[2] ’0’ = ADDR[20] 7 0 V GPO3 EN selects function of pin ADDR[21] ’1’ = secondary function GPO[3] ’0’ = ADDR[21] 31..8 132 of 173 (reserved) Preliminary Data Sheet July 2002 Interfaces R GPIO CTRL2 0x00080030 () GPIO[25:16] output control register and port mapping Bits Reset Name Description Value 9..0 0x000 V GPIO DATA 10 bit output value on GPIO[25:16] 19..10 0x000 V GPIO EN enable for GPIO[25:16] ’1’ = data output ’0’ = ’HIGH-Z’ Note: Enable must be set for primary and secondary function to obtain output functionality. 20 0 V GPIO18 EN selects function of pin SDI1 ’1’ = secondary function GPIO[18] ’0’ = SDI1 21 0 V GPIO19 EN selects function of pin SDO1 ’1’ = secondary function GPIO[19] ’0’ = SDO1 22 0 V GPIO20 EN selects function of pin BCLK1 ’1’ = secondary function GPIO[20] ’0’ = BCLK1 23 0 V GPIO21 EN selects function of pin FSC1 ’1’ = secondary function GPIO[21] ’0’ = FSC1 24 0 V GPIO22 EN selects function of pin SDI2 ’1’ = secondary function GPIO[22] ’0’ = SDI2 25 0 V GPIO23 EN selects function of pin SDO2 ’1’ = secondary function GPIO[23] ’0’ = SDO2 26 0 V GPIO24 EN selects function of pin RxD ’1’ = secondary function GPIO[24] ’0’ = RxD 27 0 V GPIO25 EN selects function of pin TxD ’1’ = secondary function GPIO[25] ’0’ = TxD 28 0 V NCTS EN selects function of pin BCLK2 ’1’ = secondary function NCTS ’0’ = BCLK2 29 0 V NRTS EN selects function of pin FSC2 ’1’ = secondary function NRTS ’0’ = FSC2 30 0 V GPIO17 CNT1B enables the clock output on GPIO[17] ’1’ = clock on GPIO17 ’0’ = GPIO[17] 31 July 2002 (reserved) Preliminary Data Sheet 133 of 173 Interfaces 5.2 UART module 5.2.1 Functional description The HFC-S active contains an Universal Asynchronous Receiver / Transmitter (UART) module with 8 byte FIFO for both directions. The complete logic is on chip to minimize system overhead and to maximize system efficiency. The UART module performs a serial-to-parallel conversion on data characters received from a peripheral device (e.g. PC) or a modem, and parallel-to-serial conversion on data characters received from the ARM7 CPU. The ARM7 CPU can read the complete status of the UART module at any time during the functional operation. The reported status information includes the type and condition of the transfer operations being performed by the UART module as well as any error conditions (parity, overrun, framing or break interrupt). The UART module includes a programmable baud rate generator that is capable of dividing the timing reference clock input to achieve a baud rate V UART BAUD within the scope V UART BAUD = 1 . . . 216. The UART has complete handshake control capability and a processor interrupt system. Interrupts can be programmed to the users requirements which minimizes the CPU time required to handle the communications link. The UART module is always running on system clock speed . Features: Transmitter and receiver are each buffered with 8 byte FIFOs to reduce the number of interrupts. Adds or removes standard asynchronous communication bits (start, stop and parity) to or from the serial data. Independently controlled interrupts for transmit, receive, line status and FIFO status Programmable baud rate generator divides the system clock Handshake control functions (CTS, RTS) with enable / disable functionality Fully programmable serial interface characteristics – – – – 5-, 6-, 7- or 8-bit characters Even, odd or no-parity bit generation and detection 1-, 1/2- or 2-stop bit generation Baud rate generation (up to 6 Mbaud) Complete status reporting capabilities Internal diagnostic capabilities: – Loop back controls for communications link fault isolation – Break, parity, overrun and framing error simulation Fully prioritized interrupt system controls The physical UART interface operates with 3.3 V input and output voltage levels. For the connection to a RS 232 interface an external line driver (e.g. MAX 560) is required. The polarity of the RXD and TXD ports are programmable to active low or active high logic levels. Figure29 illustrates the signal form (voltage level) depending on the output mode. 134 of 173 Preliminary Data Sheet July 2002 Interfaces Table 38: Baud rate programming values ( : rounded value) Baud rate 110 1200 4800 19200 57600 230400 921600 July 2002 V UART BAUD Baud rate V UART BAUD 12.288 MHz 13964 12.288 MHz 5120 24.576 MHz 27927 24.576 MHz 10240 36.864 MHz 41891 36.864 MHz 15360 49.152 MHz 55855 49.152 MHz 20480 61.440 MHz 69818 61.440 MHz 25600 12.288 MHz 1280 12.288 MHz 640 24.576 MHz 2560 24.576 MHz 1280 36.864 MHz 3840 36.864 MHz 1920 49.152 MHz 5120 49.152 MHz 2560 61.440 MHz 6400 61.440 MHz 3200 12.288 MHz 320 12.288 MHz 160 24.576 MHz 640 24.576 MHz 320 36.864 MHz 960 36.864 MHz 480 49.152 MHz 1280 49.152 MHz 640 61.440 MHz 1600 61.440 MHz 800 12.288 MHz 80 12.288 MHz 40 24.576 MHz 160 24.576 MHz 80 36.864 MHz 240 36.864 MHz 120 49.152 MHz 320 49.152 MHz 160 61.440 MHz 400 61.440 MHz 200 300 2400 9600 38400 12.288 MHz 27 12.288 MHz 13 24.576 MHz 53 24.576 MHz 27 36.864 MHz 80 36.864 MHz 40 49.152 MHz 107 49.152 MHz 53 61.440 MHz 133 61.440 MHz 67 12.288 MHz 7 12.288 MHz 3 24.576 MHz 13 24.576 MHz 7 36.864 MHz 20 49.152 MHz 115200 460800 36.864 MHz 10 27 49.152 MHz 13 61.440 MHz 33 61.440 MHz 17 12.288 MHz 2 24.576 MHz 3 36.864 MHz 5 49.152 MHz 7 61.440 MHz 8 Preliminary Data Sheet 135 of 173 Interfaces Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Parity Bit Stop Bit 3.3V HFC-S active driver level 0V +12 V external driver level (RS232 / V.24) low 0V -12 V high Figure 29: Logic levels of the UART interface 136 of 173 Preliminary Data Sheet July 2002 Interfaces 5.2.2 Register description R UART TX1 (write only) 0x000A0000 Transmit register of the UART interface (Register value cannot be read back) Note: The R UART RX1 register is located on the same address Bits Reset Name Description V UART TX1 Basic transmit register. The software should write this register only for transmitting. Value 8..0 0x000 (reserved) 15..9 R UART TX2 (write only) 0x000A0004 Transmit register of the UART interface (Register value cannot be read back) Note: The R UART RX2 register is located on the same address Bits Reset Name Description V UART TX2 2nd transmit register This register can be used for multiple transmission (multiple write command) Value 8..0 0x000 (reserved) 15..9 R UART TX3 (write only) 0x000A0008 Transmit register of the UART interface (Register value cannot be read back) Note: The R UART RX3 register is located on the same address Bits Reset Name Description V UART TX3 3rd transmit register This register can be used for multiple transmission (multiple write command) Value 8..0 15..9 July 2002 0x000 (reserved) Preliminary Data Sheet 137 of 173 Interfaces R UART TX4 (write only) 0x000A000C Transmit register of the UART interface (Register value cannot be read back) Note: The R UART RX4 register is located on the same address Bits Reset Name Description V UART TX4 4th transmit register This register can be used for multiple transmission (multiple write command) Value 8..0 0x000 (reserved) 15..9 R UART BAUD (write only) 0x000A0010 Register for baud rate settings Bits Reset Name Description Value 15..0 138 of 173 0x001B V UART BAUD Programmable baud rate ×Ý× UART baud rate V UART BAUD Preliminary Data Sheet July 2002 Interfaces R UART CFG (write only) 0x000A0020 Configuration register for the UART module Note: The R UART PREVIEW register is located on the same address Bits Reset Name Description Value 1..0 0 V UART STB defines the length of the stop bit ’0x’ = 1 stop bit ’10’ = 1.5 stop bits ’11’ = 2 stop bits 4..2 0 V UART PAR defines the parity mode of the parity bit ’000’ = no parity bit ’001’ = even parity ’010’ = odd parity ’011’ = mark ’100’ = space 9..5 0x08 V UART LEN defines the word length of the data (e.g. ’0111’ = 7 bit) 10 0 V UART CTS CTS signal ’0’= CTS not used ’1’= CTS used 14..11 6 V RX HWA Sets the high water mark for interrupt generation of received data. An interrupt is generated when the number of received bytes is equal to this value. 18..15 1 V UART TX LWA Sets the low water mark for interrupt generation of transmit data. An interrupt is generated when the number of the transmit FIFO data is equal to this value. 19 0 V UART TX POL defines polarity of the TxD output ’0’ = non inverted ’1’ = inverted 20 0 V UART RX POL defines polarity of the RxD input ’0’ = non inverted ’1’ = inverted 31..21 July 2002 (reserved) Preliminary Data Sheet 139 of 173 Interfaces R UART CLR (write only) 0x000A0024 Clears the UART FIFOs Note: The R UART STATUS register is located on the same address Bits Reset Name Description V UART CLR clears the UART FIFO Value 0 0 (reserved) 7..1 R UART ECHO (read / write) 0x000A0028 Sets the UART into an echo mode The received data is transmitted by the hardware immediately Bits Reset Name Description V UART ECHO enables the UART echo mode ’0’ = hardware echo off ’1’ = hardware echo on Value 0 0 (reserved) 7..1 R UART RX1 (read only) 0x000A0000 Receive register of the UART interface Note: The R UART TX1 register is located on the same address Bits Reset Name Description V UART RX1 Basic receive register The software should read this register only for receiving Value 8..0 0x000 (reserved) 15..9 19..16 0 V UART TX1 FIFO number of bytes in the transmit FIFO 23..20 0 V UART RX1 FIFO number of bytes in the receive FIFO 24 0 V UART PERR1 parity error information of V UART RX1 ’0’ = no parity error ’1’ = parity error 31..25 140 of 173 (reserved) Preliminary Data Sheet July 2002 Interfaces R UART RX2 (read only) 0x000A0004 Receive register of the UART interface Note: R UART TX2 register is located on the same address Bits Reset Name Description V UART RX2 2nd receive register This register can be used for multiple receiving (multiple read command) Value 8..0 0x000 (reserved) 15..9 19..16 0 V UART TX2 FIFO number of bytes in the transmit FIFO 23..20 0 V UART RX2 FIFO number of bytes in the receive FIFO 24 0 V UART PERR2 parity error information of V UART RX2 ’0’ = no parity error ’1’ = parity error (reserved) 31..25 R UART RX3 (read only) 0x000A0008 Receive register of the UART interface Note: R UART TX3 register is located on the same address Bits Reset Name Description V UART RX3 3rd receive register This register can be used for multiple receiving (multiple read command) Value 7..0 0x00 (reserved) 15..8 19..16 0 V UART TX3 FIFO number of bytes in the transmit FIFO 23..20 0 V UART RX3 FIFO number of bytes in the receive FIFO 24 0 V UART PERR3 parity error information of V UART RX3 ’0’ = no parity error ’1’ = parity error 31..25 July 2002 (reserved) Preliminary Data Sheet 141 of 173 Interfaces R UART RX4 (read only) 0x000A000C Receive register of the UART interface Note: R UART TX4 register is located on the same address Bits Reset Name Description V UART RX4 Fourth receive register This register can be used for multiple receiving (multiple read command) Value 7..0 0x00 (reserved) 15..8 19..16 0 V UART TX4 FIFO number of bytes in the transmit FIFO 23..20 0 V UART RX4 FIFO number of bytes in the receive FIFO 24 0 V UART PERR4 parity error information of V UART RX4 ’0’ = no parity error ’1’ = parity error (reserved) 31..25 R UART PREVIEW (read only) 0x000A0020 Previous status register for the UART module, for preview the next FIFO data Note: The R UART CFG register is located on the same address Bits Reset Name Description V UART PREVIEW shows the next data in the receive FIFO Value 8..0 0x000 (reserved) 15..9 19..16 0 V UART TX0 FIFO number of bytes in the transmit FIFO 23..20 0 V UART RX0 FIFO number of bytes in the receive FIFO 24 0 V UART PERR0 parity error information of V UART PREVIEW ’0’ = no parity error ’1’ = parity error 31..25 142 of 173 (reserved) Preliminary Data Sheet July 2002 Interfaces Table 39: Bitmap description of the UART transmit FIFO status Bit Bit number name Description 0 status number of words in the transmit FIFO 1 low water 2 empty low water mark of the transmit FIFO has been reached transmit FIFO is empty (last byte sent) Table 40: Bitmap description of the UART receive FIFO status Bit Bit number name Description 0 status words received in the FIFO 1 high water 2 full 3 parity error parity error in the receive FIFO 4 echo error echo error 5 break 6 overflow hiwh water mark of the receive FIFO has been reached receive FIFO is full Hardware echo error (TxD and RxD at the same time) overflow of the receive FIFO (data lost) R UART STATUS (read only) 0x000A0024 Interrupt Status register for the UART module Note: The R UART CLR register is located on the same address Bits Reset Name Description Value 3..0 0 V UART TX FIFO Number of bytes in the transmit FIFO 7..4 0 V UART RX FIFO Number of bytes in the receive FIFO 10..8 0 V UART TX STATUS status of send data (data sent out) 17..11 0 V UART RX STATUS status of receive data (data received) 32..18 (reserved) Note: see table 39 (page 143) and 40 (page 143) for bit identification of V UART TX STATUS and V UART RX STATUS July 2002 Preliminary Data Sheet 143 of 173 Interfaces R UART IRQ CFG (read / write) 0x000A002C Interrupt status and configuration register for the UART interface. Bits Reset Name Description Value 2..0 0 V UART TX IRQ STATUS interrupt status of send data (data sent out) 9..3 0x00 V UART RX IRQ STATUS interrupt status of receive data (data received) 12..10 0 V UART TX FIQ EN enables fast interrupts for data transmit 19..13 0x00 V UART RX FIQ EN enables fast interrupts for data receive 22..20 0 V UART TX IRQ EN enables interrupts for transmit data 29..23 0 V UART RX IRQ EN enables interrupts for receive data 31..30 (reserved) Note: see table 39 (page 143) and 40 (page 143) for bit identification of V UART TX IRQ STATUS and V UART RX IRQ STATUS 144 of 173 Preliminary Data Sheet July 2002 Interfaces 5.3 USB module G Note ! Please contact our support team if you want to use the USB interface. Table 41: Overview of the HFC-S active USB pins Number Name Description 73 USB+ differential USB port (positive) 74 USB- differential USB port (negative) Table 42: Overview of the HFC-S active USB registers Address Name Page Address Name Page 0x0008003C R USB DRV 147 0x000E0030 R USB IEP SEL 153 0x000E0000 R USB ADDR 147 0x000E0034 R USB IDATA 153 0x000E0004 R USB CFG 148 0x000E0038 R USB ICMD 154 0x000E0008 R USB CTRL 148 0x000E003C R USB ISTATUS 154 0x000E000C R USB EV1 149 0x000E0040 R USB OEP EN 155 0x000E0010 R USB EVMSK1 150 0x000E0044 R USB IEP EN 155 0x000E0014 R USB EV2 150 0x000E0048 R USB OEP STALL 156 0x000E0018 R USB EVMSK2 151 0x000E004C R USB IEP STALL 156 0x000E0020 R USB OEP SEL 151 0x000E0050 R USB OEP EV 157 0x000E0024 R USB ODATA 151 0x000E0054 R USB OEP EVMSK 157 0x000E0028 R USB OCMD 152 0x000E0058 R USB IEP EV 157 0x000E002C R USB OSTATUS 152 0x000E005C R USB IEP EVMSK 158 The HFC-S active has a complete Universal Serial Bus (USB) interface which is compatible with the USB specification 1.1. The on-chip USB transceiver permits the direct connection to the physical USB interface (e.g. computers with USB interface). Four endpoints excluding endpoint 0 are implemented for transmit and receive direction. The endpoints 1 . . . 4 have an FIFO depth of 64 byte for each direction, whereas endpoint 0 has an 16 byte FIFO for transmit and receive each. The HFC-S active USB module supports control, interrupt and bulk transfer types. Figure 30 illustrated the input and output driver circuitry of the USB interface. The receivers can be switched off with V USB OFF = 1 (register R OSC CFG). The differential and single ended data can be monitored in the named register bits of the register R USB DRV. July 2002 Preliminary Data Sheet 145 of 173 Interfaces 1 Bit V_USB_DREC_OFF R_OSC_CFG Differential Receiver 1 Bit USB + V_USB_RXD R_USB_DRV USB 1 Bit V_USB_SREC_OFF R_OSC_CFG Single Ended Receiver 1 Bit V_USB_RXDP R_USB_DRV Single Ended Receiver 1 Bit V_USB_RXDN R_USB_DRV Figure 30: USB input scheme 146 of 173 Preliminary Data Sheet July 2002 Interfaces 5.3.1 Register description R USB DRV (read / write, read) 0x0008003C USB driver control register Bits Reset Name Description V USB WAK Generates a wakeup signal 1 V USB RXD Represents the state of the RXD port 2 V USB RXDP Represents the state of the RXDP port 3 V USB RXDN Represents the state of the RXDN port 7..4 (reserved) Value 1 0 R USB ADDR (read / write) 0x000E0000 USB device address Bits Reset Name Description V USB ADDR After power-on-reset the device works on the default address 0. The software has to set the new address after the status stage following a SET ADDRESS request directed to the USB device. Value 6..0 7 July 2002 0x00 (reserved) Preliminary Data Sheet 147 of 173 Interfaces R USB CFG (read / write, read) 0x000E0004 USB mode configuration register Bits Reset Name Description Value 0 0 V USB IRQ POL Defines the interrupt polarity (0 = active low, 1 = active high) 1 0 V USB IRQ EN Interrupt output enable ’1’ = Enable the interrupt output. If one or more event bits of the R USB EV1 register are set before enabling the interrupt, an interrupt will also occure after setting this bit. V USB VER Represents the version of the USB module 7..2 R USB CTRL (read / write) 0x000E0008 USB control register Bits Reset Name Description Value 0 0 V USB RESU Force resume Setting this bit forces a K state on the data lines driven for 12 ms. If this bit is set immediately after a suspend condition, the resume will not start earlier than 5 ms after this suspend state. 1 0 V USB AT Node attached When set to 0, the data lines will held on low to simulate a disconnected device. After initialisation of the microcontroller this bit should be set to 1 to force the recognition of a connect. 2 0 V USB SUSP Suspend mode This bit must be set before entering the suspend state. Any bus activity starts the resume sequence and the bit will be cleared after its completion automatically. If no resume is performed, the bit must be cleared manually by the microcontroller. 7..3 148 of 173 (reserved) Preliminary Data Sheet July 2002 Interfaces R USB EV1 (read only) 0x000E000C 1st USB event register Bits Reset Name Description V USB EV2 Event on the 2nd USB event register ’1’ = A change in the R USB EV2 register occurred. This leads to an interrupt if the corresponding bit in the R USB EVMSK2 register is set. Value 0 0 (reserved) 1 2 0 V USB ZOF ZERO OUT function ’1’ = An OUT token with an empty DATA1 packet was received on EP0. In this special case the FIFO is not blocked. (reserved) 3 4 0 V USB IEV IN event function ’1’ = A bit in the R USB IEP EV register changed to ’1’ and the corresponding bit in the R USB IEP EVMSK register is set. This shows, that an event on an IN endpoint occurred and leads to an interrupt if the corresponding bit in the R USB EVMSK1 register is set. 5 0 V USB OEV OUT event function ’1’ = A bit in the R USB OEP EV register changed to ’1’ and the corresponding bit in the R USB OEP EVMSK register is set. This shows, that an event on an OUT endpoint occurred and leads to an interrupt if the corresponding bit in the R USB EVMSK1 register is set. 7..6 July 2002 (reserved) Preliminary Data Sheet 149 of 173 Interfaces R USB EVMSK1 (read / write) 0x000E0010 Mask for the 1st USB event register Bits Reset Name Description V USB EVMSK2 EVENT2 mask Value 0 0 (reserved) 1 0 2 V USB ZOFMSK ZERO OUT function mask (reserved) 3 4 0 V USB IEVMSK IN event function mask 5 0 V USB OEVMSK OUT event function mask (reserved) 7..6 R USB EV2 (read only) 0x000E0014 2nd USB event register Bits Reset Name Description Value 0 0 V USB RES USB reset ’1’ = An USB reset is recognized at the data lines. 1 0 V USB SUSP Suspend ’1’ = No data traffic was seen for 3 ms. The firmware should enter the suspend state if this event occures. 2 0 V USB RESU Resume ’1’ = A resume state at the data lines was detected. 3 0 V USB RWAK Remote wakeup ’1’ = A remote wakeup signal was detected. The bit can only be set, if the corresponding mask bit is set and the suspend mode is enabled using the V USB SUSP bit of the R USB CTRL register. If remote wakeup capability is enabled, the device must send a resume (setting bit V USB RESU of the R USB CTRL register) to wakeup the entire bus. 4 0 V USB RDY Resume completed ’1’ = A resume is completed by the host with a low-speed EOP 7..5 150 of 173 (reserved) Preliminary Data Sheet July 2002 Interfaces R USB EVMSK2 (read / write) 0x000E0018 Mask for the 2nd USB event register Bits Reset Name Description Value 0 0 V USB RESMSK USB reset mask 1 0 V USB SUSPMSK Suspend mask 2 0 V USB RESUMSK Resume mask 3 0 V USB RWAKMSK Remote wakeup mask 4 0 V USB RDYMSK Resume completed mask (reserved) 7..5 R USB OEP SEL (read / write) 0x000E0020 OUT endpoint select register Bits Reset Name Description V USB OEP SEL Writing the appropriate endpoint number allows the access to the mapped FIFO control and data registers (range 0 . . . 4). Value 3..0 0 (reserved) 7..4 R USB ODATA (read only) 0x000E0024 Data OUT register Bits Reset Name Description 7..0 V USB ODATA The FIFO data of the selected endpoint can be read out by reading this register times ( = value of V USB OCNT in the V USB OCNT register) 10..8 (reserved) Value July 2002 Preliminary Data Sheet 151 of 173 Interfaces R USB OCMD (read / write) 0x000E0028 OUT command register Bits Reset Name Description 0 V USB FLUSH Flush OUT FIFO The FIFO must be flushed by the microcontroller by setting this bit to ’1’. 7..1 (reserved) Value G Important ! If the bit V USB FLUSH is not set, the FIFO is blocked and the USB module will respond with a NAK handshake to OUT tokens. Because SETUP tokens dont have to be NAKed, the USB module will not respond to these tokens if the FIFO is blocked and the USB host will recognize a timeout. R USB OSTATUS (read only) 0x000E002C OUT status register Bits Reset Name Description Value 6..0 0 V USB OCNT OUT count Shows the number of received bytes residing in the output FIFO of the selected endpoint (EP0: range 0 . . . 16, EP1. . . 4: range 0 . . . 64). 7 0 V USB SETUP SETUP token received 1 = A SETUP transfer occurred on the endpoint 0. 152 of 173 Preliminary Data Sheet July 2002 Interfaces R USB IEP SEL (read / write) 0x000E0030 IN endpoint select register Bits Reset Name Description V USB IEP SEL Writing the appropriate endpoint number allows the access to the mapped FIFO control and data registers (range 0 . . . 4)). Value 2..0 0 (reserved) 7..3 R USB IDATA (write only) 0x000E0034 Data IN register Bits Reset Name Description V USB IDATA Data written to this register will enter the input FIFO selected by the R USB IEP SEL register. The pointers for the FIFO will be automatically incremented with every write cycle and will be resetted if the input FIFO was flushed. The number of bytes contained in a FIFO is visible in the R USB ISTATUS register. Value 7..0 July 2002 Preliminary Data Sheet 153 of 173 Interfaces R USB ICMD (read / write) 0x000E0038 IN command register Bits Reset Name Description Value 0 0 V USB IFLUSH Flush IN FIFO The FIFO will be flushed automatically after a successful transmission of data to the host and receiving the appropriate ACK handshake. The FIFO can be flushed manually by setting this bit. The full- or empty-status of the FIFO can be evaluated by reading this bit. 1 0 V USB IN EN In transfer enable Setting this bit enables the USB module to sent the contents of the FIFO after the next IN token to this endpoint. The bit is cleared by hardware after a successful transmission. Any necessary retries caused by missing or destroyed handshake tokens will be done automatically. (reserved) 7..2 R USB ISTATUS (read only) 0x000E003C IN status register Bits Reset Name Description V USB ICNT IN count Shows the actual number of bytes in the selected input FIFO (EP0: range 0 . . . 16, EP1. . . 4: range 0 . . . 64). V USB TOG IN toggle value Shows the actual toggle value of the DATA PID for the transfer (0 = DATA0 packet, 1 = DATA1 packet). The toggle value will be generated automatically. Value 6..0 7 154 of 173 0 Preliminary Data Sheet July 2002 Interfaces R USB OEP EN (read / write, read) 0x000E0040 OUT endpoint enable register If a bit is set, the device will respond to an OUT token addressed to the corresponding endpoint. If the corresponding endpoint FIFO is empty, the following data packet will be received and an ACK token will be sent in the handshake phase. Otherwise a NAK handshake will be sent to force a retry by the host. This register should be modified according to the endpoint layout chosen with the SET CONFIGURATION request. Bits Reset Name Description 0 V USB OEP0 EN Endpoint 0 This bit is set automatically after detection of an USB Reset 4..1 V USB OEP EN Endpoints 1 . . . 4 7..5 (reserved) Value R USB IEP EN (read / write, read) 0x000E0044 IN endpoint enable register If a bit is set, the function will respond to an IN token addressed to the corresponding endpoint. If the corresponding endpoint FIFO contains data and is enabled, the FIFO contents will be sent, otherwise a NAK handshake will be sent. This register should be modified according to the endpoint layout chosen with the SET CONFIGURATION request. Bits Reset Name Description 0 V USB IEP0 EN Endpoint 0 This bit is set automatically after detection of an USB Reset 4..1 V USB IEP EN Endpoints 1 . . . 4 7..5 (reserved) Value July 2002 Preliminary Data Sheet 155 of 173 Interfaces R USB OEP STALL (read / write) 0x000E0048 OUT endpoint stall register If a bit is set, the corresponding endpoint will always sent a STALL token during the handshake phase of an OUT transfer. SETUP transfers on control endpoint EP0 can not be stalled. The bit EP0 works only for OUT tokens on EP0 but not for SETUP tokens! (For example the OUT data stage after a SET DESCRIPTOR request) The bit for control endpoint EP0 will be automatically resetted after detection of a valid SETUP token. A bit of this register can only be set after the corresponding bit in the R USB OEP EN register was set, otherwise the bit will stuck at zero. Bits Reset Name Description V USB OEP STALL Enable OUT endpoint stall (range: 0 . . . 4) Value 4..0 0x00 (reserved) 7..5 R USB IEP STALL (read / write) 0x000E004C IN endpoint stall register If a bit is set, the corresponding endpoint will always sent a STALL token after the data phase of an IN transfer. The bit for control endpoint EP0 will be automatically resetted after detection of a valid SETUP token. A bit of this register can only be set after the corresponding bit in the R USB IEP EN register was set, otherwise the bit will stuck at zero. Bits Reset Name Description V USB IEP STALL Endpoints 0 . . . 4 Value 4..0 7..5 156 of 173 0x00 (reserved) Preliminary Data Sheet July 2002 Interfaces R USB OEP EV (read only) 0x000E0050 OUT endpoint event register The bits are set, when an OUT transfer on the corresponding endpoint is completed. Any set of a bit will force a set of the V USB OEV bit in the R USB EV1 register when the corresponding bit in the R USB OEP EVMSK register is set. All bits are cleared on read. Bits Reset Name Description V USB OEP EV Endpoits 0 . . . 4 Value 4..0 0x00 (reserved) 7..5 R USB OEP EVMSK (read / write) 0x000E0054 Mask of the OUT endpoint event register Bits Reset Name Description V USB OEP EVMSK Endpoints 0 . . . 4 Value 4..0 0x00 (reserved) 7..5 R USB IEP EV (read / write) 0x000E0058 IN endpoint event register The bits are set, when an IN transfer on the corresponding endpoint is completed. Any set of a bit will force a set of the V USB IEV bit in the R USB EV1 register when the corresponding bit in the R USB IEP EVMSK register is set. All bits are cleared on read. Bits Reset Name Description V USB IEP EV Endpoints 0 . . . 4 Value 4..0 7..5 July 2002 0x00 (reserved) Preliminary Data Sheet 157 of 173 Interfaces R USB IEP EVMSK (read / write) 0x000E005C Mask of the IN endpoint event register Bits Reset Name Description 4..0 V USB IEP EVMSK Endpoints 0 . . . 5 7..5 (reserved) Value 158 of 173 Preliminary Data Sheet July 2002 package dimensions HFC-S active package dimensions A 0.65 BSC 31.20 ± 0.25 28.00 ± 0.10 31.20 ± 0.25 28.00 ± 0.10 0.30 ± 0.08 M 0~7 0.25 MIN 0.15 + 0.08 - 0.04 3.40 ± 0.25 4.07 MAX 0.12 (1.325) 0.73 ~ 1.03 0.10 Unit: mm Figure 31: HFC-S active package dimensions July 2002 Preliminary Data Sheet 159 of 173 Power supply and ground distribution B Power supply and ground distribution B.1 Digital supply pins All ditigal power supply pins and digital ground pins listed in table 43 should be connected to the 3.3 V system supply voltage respectively to ground. Table 43: Power supply and ground pins of the digital subsystems Category Pin name Pin numbers digital ground DGND 18, 24, 30, 41, 55, 61, 72, 91, 108, 114 digital power supply DVCC 8, 21, 29, 42, 58, 71, 92, 107, 113 B.2 Analog supply pins Table 44: Power supply and ground pins of the mixed signal subsystems PLL 1 PLL 2 CODEC 1 CODEC 2 Category pin number (name) pin number (name) pin number (name) pin number (name) digital power supply 149 (DVCC PLL1) 130 (DVCC PLL2) digital ground 154 (DGND) 125 (DGND) analog power supply 150 (AVCC PLL1) 129 (AVCC PLL2) 148 (AVCC CODEC1) 131 (AVCC CODEC2) analog ground 152 (AGND) 153 (AGND) 126 (AGND) 127 (AGND) 145 (AGND) 134 (AGND) 160 of 173 Preliminary Data Sheet 139 (DVCC CODEC) 140 (DGND) July 2002 PLL 1 multiplexer control logic C Multiplexer control logic of the PLL 1 block The PLL and the divider can be selected or bridged by multiplexers individually. One multiplexer can select the PLL output (V PLL1 SEL = 1) or the original oscillator frequency (V PLL1 SEL = 0). As the clock phase of the PLL output relative to the PLL input is uncontrollable, it is not possible to use a normal asynchronous multiplexer for this purpose. A normal multiplexer could generate very short clock pulses (spikes) during switching, resulting in misbehavior of the ARM7 CPU or flipflops in the circuit. Instead, a special logic has been developed to control a multiplexer in a way that it will switch from one input to zero level before switching to the other input, switching only when the individual input is at zero level (see fig. 32). FIN FOUT 15 SEL_PLL (register) MUX control input 0 2 1 MUX output MUX switches off at next negative edge of old frequency. MUX switches on after 15 negative edges of old frequency. Figure 32: Clock switching behaviour of PLL multiplexer The result is a multiplexer output waveform which contains no spikes or dynamic hazards, even though a pause in the output waveform is unavoidable for a versatile multiplexer that can also be used for switching between clock frequencies differing by a large factor. FIN FOUT SEL_DIV (register) MUX control input MUX output = ARM7 clock MUX switches at next negative edge of FIN if (FOUT = 0). Figure 33: Clock switching behaviour of divider multiplexer As the phase relationship between the divider input and the divider output is well defined in this case, the multiplexer can be controlled so that it switches directly from one input to the other at a time when both inputs are at zero level as shown in the diagram above. July 2002 Preliminary Data Sheet 161 of 173 Examples circuitry D Examples circuitry for HFC-S active The following pages show the Cologne Chip evaluation board circuitry of the HFC-S active. 162 of 173 Preliminary Data Sheet July 2002 July 2002 Preliminary Data Sheet D C B A TX1_HI /TX_EN R2 LEV_R2 LEV_R1 R1 ADJ_LEV 1 1 RE1 R9 GND RG1 R1 RA2 RA1 / T X 2 _ LO R6 +3.3V RC2 RB2 RB1 RC1 Q5 C5 Q3 Q2 R7 R3 2 R11 R10 GND RF1 +3.3V 2 RF2 Q4 C4 Q6 GND RD2 Q1 R4 D2 D1 RD1 R8 GND / T X 1 _ LO R5 GND RG2 RE2 GND 3 D5 D3 GND TX2_HI AWAKE C3 3 D4 R2 +3.3V TRANS TR1B REC TR1A 4 Date: Size A4 Title TX+ TP JP26 RX+ TP JP25 4 TRANS1 TRANS2 REC1 REC2 ISDN_ST1 Friday, March 08, 2002 Document Number ST Interface Sheet HFC-S active Eval Board (c) 2001 by CC AG TX- TP JP27 RX- TP JP24 5 5 6 of 6 Rev 1.0 D C B A Examples circuitry 163 of 173 Preliminary Data Sheet D C B Cod2_in Cod2_out 1 GND GND VCCA_c1 R54 0 GND Q12 n.b. R59 GND 0 2 4 3 2 1 JP23 3 Cod1_in GNDA_c1 4k7 R60 4k7 R52 R56 n.b. 1k R58 GNDA_c2 RJ11 Cod1_out R50 GND Q9 100k GND R61 GND GND 4 Date: Size A4 Title n.b. 0 GND C27 100µ 4 3 2 1 JP22 RJ11 Wednesday, February 27, 2002 Document Number Codec Sheet HFC-S active Eval Board (c) 2001 by CC AG R62 Q10 10 R48 R46 100µ 10 R44 Q8 +3.3V 10 1k 4k7 R55 n.b. R53 0 GND C26 D15 BAV99 1k R42 +3.3V 4 R45 10 R43 Q7 +3.3V 3 R49 Q11 R57 4k7 R51 VCCA_c2 100k R47 D14 BAV99 1k R41 +3.3V 2 + 164 of 173 + A 1 5 5 1 of 6 Rev 1.0 D C B A Examples circuitry July 2002 Preliminary Data Sheet D C B 1 9 # 0 * 6 5 8 4 3 7 2 1 Tast3x4 JP14 G H J K D E F 2 2 R30 1k R31 1k R32 1k R34 1k R29 1k R28 1k 3 3 V1 LCD2x16 D7 D6 D5 D4 D3 D2 D1 D0 E R/W RS VLED VP GND R33 GND 100k July 2002 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A 1 GPIO5 GPIO6 GPIO7 GPIO8 GPIO4 GPIO2 GPIO16 GPIO3 4 Date: Size A4 Title 4 1k5 R64 22k R63 GND 100n C28 +5V GND Wednesday, February 27, 2002 Document Number LCD and Keyboard Sheet HFC-S active Eval Board (c) 2001 by CC AG GND +5V 5 5 2 of 6 Rev 1.0 D C B A Examples circuitry 165 of 173 166 of 173 Preliminary Data Sheet D C B A Vin POW2X1 Masse Vin JP17 POW2X1 2 1 2 1 1k5 680 JP16 R68 R67 GND gn gn Masse GND D17 +5V D16 +3.3V VCC 1 L4 L3 GND Vin GND 100n C16 VCC 100n C17 C20 100µ GND + Vin 100n C18 2 0.33R R37 2 7 8 1 6 GND TC Cll SWE MC34063A Ipk DRC SWC Vin U4 GND 4 3 5 2 100n C22 +5V GND 10µ C23 GND + IN LM1117 U5 470p C19 GND 3 3 GND 3 GND GND 1 +5V 1 ZD D10 OUT OUT GND 4 2 1k2 R36 10µ C24 R35 3k6 GND + GND 220µ L2 100n C25 470µ C21 GND + 4 Date: Size A4 Title +5V +3.3V 4 Friday, March 08, 2002 Sheet HFC-S active Eval Board (c) 2001 by CC AG Document Number Power +3.3V +5V GND 5 5 4 JP37 JP36 JP35 JP34 JP33 JP32 of 6 +3.3V +5V GND Rev 1.0 D C B A Examples circuitry July 2002 Preliminary Data Sheet D C B A TxD3 RTS3 RxD3 CTS3 RxD2 TxD2 CTS2 RTS2 RxD1 TxD1 CTS_1 RTS_1 GND 1 +5V ? ? JP11 4 3 2 1 R19 ? R15 C+ C1C2+ C2V+ V- R1IN T1OUT R2IN T2OUT U2 12 11 9 10 8 7 6 9 R1OUT T1IN R2OUT T2IN 1 3 4 5 2 6 13 14 8 7 RRX+ RRX- RTX+ RTX- MAX232 MAX1485 H/F U3 R1OUT T1IN R2OUT T2IN R18 +5V 12 11 9 10 R21 10k R20 10k GND C15 C13 4 6 1 3 1 3 4 5 2 6 13 14 8 7 20F001N P3 P4 P1 P2 L1 JP13 JP12 C14 +5V + MAX232 C+ C1C2+ C2V+ V- R1IN T1OUT R2IN T2OUT U1 2 R1 R2 R3 R4 5 + + C10 C8 C11 12 10 9 7 5 C12 GND 2 + + July 2002 + 1 GND GND C29 C9 +5V + 5 4 3 2 1 + + GND RJ45 1 2 3 4 5 6 7 8 J1 R17 100 R X D+ TXD+ R16 100 1 2 3 4 5 6 7 8 9 8 7 6 9 8 7 6 sub_d_9_ma 5 4 3 2 1 JP7 C7 C6 5 4 3 2 1 GND 9 8 7 6 9 8 7 6 9 8 7 6 9 8 7 6 3 sub_d_9_fe 5 4 3 2 1 sub_d_9_fe 5 4 3 2 1 JP10 5 4 3 2 1 JP6 3 R X D- TXD- 4 Date: Size A4 Title 4 LED2 LED0 LED1 USB_B V+USB D+ DGNDUSB ST1 13 12 11 10 9 8 7 6 5 4 3 2 1 25 24 23 22 21 20 19 18 17 16 15 14 GND +5V JP9 D6 D7 Friday, March 08, 2002 Document Number Connector Sheet rt ge gn R14 27 27 R13 25 24 23 22 21 20 19 18 17 16 15 14 D8 sub_d_25 13 12 11 10 9 8 7 6 5 4 3 2 1 JP8 HFC-S active Eval Board (c) 2001 by CC AG SLCT PE BUSY /ACK PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 /STROBE 5 5 5 of R24 2k4 R23 2k4 R22 2k4 1k5 R12 +3.3V GND 6 Rev 1.0 +5V DPUSB DNUSB /SLCTIN /INIT /ERR /AUFDX D C B A Examples circuitry + 167 of 173 168 of 173 Preliminary Data Sheet D C B A XTDO /RESET /XNTRST XTDI XTMS XTCLK SDO2 FSC1 SDO1 FSC2 SDO2 FSC1 SDO1 PFS0 PFS2 FSC0 SDO0 BSCK2 CTS_1 FSC2 RTS_1 +3.3V GND +3.3V 1 1 3 5 7 9 11 13 15 17 19 CON2X10 GND +3.3V 10k 10k 2 4 6 8 10 12 14 16 18 20 GND SDI2 BSCK1 SDI1 R66 JP31 2 4 6 8 10 BSCK2 SDI2 BSCK1 SDI1 PFS1 PFS3 BSCK0 SDI0 R65 SDI1 SDO1 FSC1 BSCK1 CON2X5 JP21 +5V +5V CON2X10 2 4 6 8 10 12 14 16 18 20 GND 1 3 5 7 9 1 3 5 7 9 11 13 15 17 19 JP18 +3.3V CTS1 RTS1 GND +3.3V JP20 JP19 1 1 2 3 4 DIP4 IN1 IN2 IN3 IN4 JP29 OUT1 OUT2 OUT3 OUT4 8 7 6 5 2 GPIO12 +3.3V GND CON2X1 JP30 GND DS6 DS4 DS2 DS0 RTS3 TxD3 /RI_B /ACK BUSY /ERR /RXRDY_B GPIO5 GPIO7 GPIO9 GPIO16 TxD1 RTS1 SDO2 FSC1 SDO1 PFS0 PFS2 FSC0 SDO0 AWAKE R1 LEV_R2 / T X 1 _ LO TX2_HI TX1_HI DNUSB 2 /NTTEST 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 JP1 0R R69 +3.3V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 A3_ST A1_ST A11_ST A13_ST A10_ST A8_ST /CS3_ST /CS1_ST /MR XTDI XTCLK GPIO3 DS7 DS5 DS3 DS1 CTS3 /DTR_B /DCD_B /DSR_B PE SLCT RxD3 GPIO6 GPIO8 GPIO10 GPIO12 RxD1 CTS1 SDI2 BSCK1 SDI1 PFS1 PFS3 BSCK0 SDI0 ADJ_LEV LEV_R1 R2 / T X 2 _ LO /TX_EN GP_USB DPUSB GND 3 3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 JP2 /RESET DS0 DS2 DS4 DS6 A0_ST A2_ST A4_ST /CS2_ST /CS4_ST A6_ST A8_ST A10_ST A12_ST GPIO12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 /RESET 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 +5V 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 +3.3V CON2X15 JP15 Taster JP28 GND +5V GND 4 Date: Size A4 Title A2_ST A0_ST A12_ST A6_ST A9_ST A7_ST /CS4_ST /CS2_ST /RESET GPIO4 GPIO2 GPIO0 /XNTRST XTMS XTDO DS1 DS3 DS5 DS7 A1_ST A3_ST A5_ST /CS1_ST /CS3_ST A7_ST A9_ST A11_ST A13_ST 4 750 R39 750 R38 Cod2_out Cod2_in Cod1_out Cod1_in Wednesday, February 27, 2002 Document Number Connector 2 Sheet 5 3 JP5 JP4 CON1X4 1 2 3 4 of 6 GPIO10 GPIO9 CON1X4 1 2 3 4 VCCA_c2 GNDA_c2 LED_SMD D12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 VCCA_c1 GNDA_c1 JP3 LED_SMD D11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 HFC-S active Eval Board (c) 2001 by CC AG +3.3V /INIT /STROBE /SLCTIN PD2 PD4 PD6 RDOUT RxD2 /TXRDY_A /DTR_A /DSR_A CTS2 /RI_A RTX+ RRX+ LED1 /WR /RD A 4 _ ST 5 Rev 1.0 A5_ST RTS2 TxD2 /CS_A /DCD_A RTXRRXLED0 LED2 /AUFDX PD0 PD1 PD3 PD5 PD7 /CS_P /TXRDY_B D C B A Examples circuitry July 2002 July 2002 CKE_SD VLK_SD NWE NRAS NCAS NWE_SD NOE DQML DQMU Preliminary Data Sheet D C NCS1 NCS2 NCS3 NCS4 NCS5 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Memory B A ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 ADR21 U3A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 57 56 54 53 52 51 50 49 63 64 65 66 67 68 69 70 59 60 43 44 45 46 47 48 62 40 39 38 37 36 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 35 34 33 32 22 23 25 26 27 28 31 14 15 16 17 19 20 11 12 13 9 10 1 1 /NOE DQML DQMU /NWE /NCS1 /NCS2 /NCS3 /NCS4 /NCS5 R5 22R R6 22R /NCS2 /NOE /NWE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 26 28 11 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 22R R4 22R R3 D[0:15] A[0:21] RB BYTE RP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15A-1 29W160/320 E G W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 U4 /NRAS /NCAS /NWE_SD CKE_SD CLK_SD +3.3V D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 /RESET 2 22R R2 15 47 12 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 2 /NCS5 CLK_SD 19 38 16 17 18 20 21 A12 A13 /NWE_SD /NCAS /NRAS 23 24 25 26 29 30 31 32 33 34 22 35 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 /NCS4 /RESET /NOE /NWE A17 A18 A19 A21 A21 A3 A2 A1 A0 A4 A5 K4S641632D CS CLK WE CAS RAS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 U5 3 39 37 15 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 6 4 5 1 2 3 1 19 2 3 4 5 6 7 8 9 A[0:21] UDQM CKE LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 3 18 17 16 15 14 13 12 11 15 14 13 12 11 10 9 7 DQMU CKE_SD DQML Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 74HCT138 G1 G2A G2B A B C U9 74HC541 G1 G2 A1 A2 A3 A4 A5 A6 A7 A8 U10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 /NCS4 /NOE D7 D6 D5 D4 D3 D2 D1 D0 AEN_RE /CS_A /CS_B /CS_P /CS1_ST /CS2_ST /CS3_ST /CS4_ST A3_ST A2_ST A1_ST A0_ST A4_ST A5_ST /RD /WR 19 1 2 3 4 5 6 7 8 9 B1 B2 B3 B4 B5 B6 B7 B8 4 Date: Size A4 Title 74LVT245 G DIR A1 A2 A3 A4 A5 A6 A7 A8 U7 4 1 19 2 3 4 5 6 7 8 9 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 74HC541 G1 G2 A1 A2 A3 A4 A5 A6 A7 A8 U11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 DT[0:7] A11_ST A12_ST A13_ST A6_ST A7_ST A8_ST A9_ST A10_ST Wednesday, January 16, 2002 Document Number Memory Sheet 5 2 HFC-S active system board (c) 2001 by Cologne Chip AG A21 A21 A12 A11 A13 A6 A7 A8 A9 A10 18 17 16 15 14 13 12 11 5 of 5 Rev 1.0 D C B A Examples circuitry 169 of 173 170 of 173 Preliminary Data Sheet D C B A 1 CODEC AINFB2 AMODIN2 VREFOUT2 APOSTOUT2 REFH2 REFL2 AINFB1 AMODIN1 VREFOUT1 APOSTOUT1 REFH1 REFL1 U3D 1 138 137 136 135 132 133 141 142 143 144 146 147 GNDA_c2 GNDA_c1 C12 Spule Spule C55 L4 L3 C14 VCCA_c1 VCCA_c2 C56 39k R24 2 C15 39k R1 C11 2 R26 10R 12k R25 10R R27 12k R23 GNDA_c2 C59 GNDA_c1 C60 C58 C54 C57 C53 3 Cod2_out Cod2_in Cod1_out Cod1_in 3 /NTTEST /XNTRST XTDI XTMS XTCLK XTDO /RESET GND GND Spule L6 Spule L5 8 3 4 5 6 7 2 GNDA_c1 GNDA_c2 Control NTESTMODE XNTRST XTDI XTMS XTCLK XTDO NRES U3E 4 Date: Size Title 151 156 155 128 123 124 1n C26 GNDA_c2 JP6 CON1X4 JP7 CON1X4 1 2 3 4 VCCA_c2 GNDA_c1 1 2 3 4 VCCA_c1 GNDA_p1 GNDA_p2 1n C25 100 R22 22p C27 12.288MHz Q2 5 Tuesday, March 26, 2002 Document Number Codec / PLL Sheet 4 5 of 22p C28 22p C29 GND HFC-S active system board (c) 2001 by Cologne Chip AG Cod2_out Cod2_in Cod1_out Cod1_in FIL_PLL12_288 XTALOUT12_288 XTALIN12_288 FIL_PLL12 XTALOUT12 XTALIN12 4 5 Rev 1.0 D C B A Examples circuitry July 2002 July 2002 1 14 53 52 55 27 28 29 30 31 32 33 34 51 50 49 2 RDOUT INIT AUTOFDX STROBE SLCTIN INT P Powered by 5V ST16C552 CLK IOR IOW RESET D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 B B B B B B A A A A A A PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RTS DTR TX TXRDY RXRDY INT RTS DTR TX TXRDY RXRDY INT 63 76 75 74 77 78 72 71 70 69 68 67 66 65 25 24 23 58 3 79 37 38 39 35 19 64 RDOUT INIT /AUFDX /STROBE /SLCTIN GPIO14R PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 /RTS_B /DTR_B TX_B /TXRDY_B /RXRDY_B GPIO11R GPIO15R /RTS_A /DTR_A TX_A /TXRDY_A 3 GPIO1 DT[0:7] A[0:21] AEN_RE 10k R16 GND DT0 DT1 DT2 DT3 DT4 DT5 DT6 DT7 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 34 35 96 4 3 2 1 100 99 98 97 36 37 38 39 40 41 42 43 95 94 93 92 91 90 88 87 5 7 8 9 10 11 12 13 15 16 18 19 20 21 22 23 24 25 26 27 U1 Preliminary Data Sheet 4 Date: Size Title RTL8019AS AEN IOCHRDY IOCS16B INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 4 30 29 32 31 33 65 50 51 60 61 62 63 54 53 56 55 49 48 59 58 45 46 64 75 76 85 84 82 81 80 79 78 77 74 73 72 71 69 68 67 66 GND /NWE /NOE 20MHz Q3 LED0 LED1 LED2 10k R7 +5V 200 R10 10k R9 +5V 4k7 R8 +3.3V RRXRTX+ RTX- RRX+ GPIO0 HFC-S active system board (c) 2001 by Cologne Chip AG IOWB IORB SMEMWB SMEMRB RSTDRV JP X1 X2 LEDBNC LED0 LED1 LED2 CD+ CDRX+ RXTX+ TXTPIN+ TPINTPOUT+ TPOUT- AUI BCSB EECS BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 5 of 5 Rev 1.0 B A Tuesday, March 26, 2002 Document Number Ethernet / Connector Sheet 5 3 D DT0 DT1 DT2 DT3 DT4 DT5 DT6 DT7 A0 A1 A2 ERROR SLCT BUSY PE ACK BIDEN CSP ENIRQ CTS B DSR B DCD B RI B RX B CSB CTS A DSR A DCD A RI A RX A CSA 3 D GPIO17 /NOE /NWE /RESET +5V 5 7 8 9 10 11 54 59 26 15 18 16 4 13 44 47 45 46 57 48 2 C DT[0:7] A[0:21] /CS_P /ERR SLCT BUSY PE /ACK /CTS_B /DSR_B /DCD_B /RI_B RX_B /CS_B /CTS_A /DSR_A /DCD_A /RI_A RX_A /CS_A U8 C B A 1 Examples circuitry 171 of 173 172 of 173 Preliminary Data Sheet D C B VSS GNDA_p1 GNDA_p2 A GND 1 GNDA_c1 GNDA_c2 145 134 18 24 30 41 55 61 72 91 108 114 125 126 127 152 153 154 140 1 POWER GNDA_c1 GNDA_c2 GND GND GND GND GND GND GND GND GND GND GND GNDA_p2 GNDA_p2 GNDA_p1 GNDA_p1 GND GND U3F VCCA_C1 VCCA_C2 VDD_12_288_a VDD_12_288_d VCC_12_a VDD_12_d VCC VCC VCC VCC VCC VCC VCC VCC VCC 2 GNDA_c2 100n C8 Spule VCCA_c2 VCCA_c1 148 131 150 149 129 130 21 29 42 58 71 92 107 113 139 L1 2 0R +3.3V L7 +3.3V +3.3V n.b. C51 GNDA_c2 + 0R L8 +3.3V GNDA_c1 100n C9 Spule L2 +3.3V n.b. C52 GNDA_c1 + GND GND 100n C31 +5V 33n 33n 3 C36 C35 33n C37 33n C38 GND +5V GND LED 33n C41 LED D2 650 1k5 D1 R15 +3.3V 33n C40 GNDA_p1 R14 33n C39 0R GNDA_p2 0R GNDA_p2 100n C34 L9 GND 100n C33 L10 GNDA_p1 100n C32 3 VCC +3.3V 33n C21 GND 100n C16 + 4 Date: Size Title 100n C44 100n C17 4 10µ C42 100n C45 100n C19 33n 33n C7 100n 100n C6 C22 C20 + 10µ C43 VSSQ 33n C2 VDDQ 100n C23 Tuesday, March 26, 2002 Document Number Power Sheet 33n C3 SDRAM 100n C24 5 5 HFC-S active system board (c) 2001 by Cologne Chip AG GND 33n C1 +3.3V 100n C18 5 of 5 33n C4 Rev 1.0 33n C5 D C B A Examples circuitry July 2002 July 2002 Preliminary Data Sheet D C B A IO R17 R18 73 74 75 /MR /RESET 1 n.b. R28 PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 PCM6 PCM7 RXD TXD CTS RTS 111 112 109 110 93 94 95 96 97 98 99 100 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 1 1 160 159 158 157 122 121 120 119 118 117 116 115 90 89 88 87 86 101 102 103 104 105 106 GPIO2 SDI0 SDO0 BSCK FSC0 PFS3 PFS2 PFS1 PFS0 USB+ USBUSB_con RXD TXD CTS RTS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 U3C 4 3 1 TPS3820 WDI MR RESET U6 DPUSB DNUSB GP_USB A3_ST A1_ST A11_ST A13_ST A10_ST A8_ST /CS3_ST /CS1_ST /MR XTDI XTCLK /NTTEST DT[0:7] /RTS_B TX_B /RI_B /ACK BUSY /ERR /RXRDY_B DT6 DT4 DT2 DT0 R1 LEV_R2 /TX1_LO TX2_HI TX1_HI DNUSB GPIO5 GPIO7 GPIO9 GPIO16 TXD RTS GPIO23 GPIO21 GPIO19 PCM7 PCM5 PCM3 PCM1 GPIO13 2 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 DT[0:7] JP1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 GPIO3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 JP2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GPIO4 GPIO2 GPIO0 GPIO[0:23],RXD,TXD,CTS,RTS,PCM[0:7] GND 2 DT7 DT5 DT3 DT1 ADJ_LEV LEV_R1 R2 /TX2_LO TX_EN GP_USB DPUSB +5V +3.3V /CTS_B /DTR_B /DCD_B /DSR_B PE SLCT RX_B GPIO6 GPIO8 GPIO10 GPIO12 RXD CTS GPIO22 GPIO20 GPIO18 PCM6 PCM4 PCM2 PCM0 GPIO11 GPIO15 GPIO14 3 A2_ST A0_ST A12_ST A6_ST A9_ST A7_ST /CS4_ST /CS2_ST /RESET /XNTRST XTMS XTDO GPIO7 GPIO6 GPIO5 3 n.b. R21 10k GND R20 10k +3.3V 6 5 3 7 U12 OSCI VDD 10k R13 VSS OSCO PCF8583 A0 INT SCL SDA 10k 10k R19 +3.3V R12 R11 4 2 1 8 4 Date: Size A4 Title GND +3.3V_B ? QUARZ Q4 C48 +3.3V_B ISDN 10µ C49 GND + +3.3V_B INIT /STROBE /SLCTIN PD2 PD4 PD6 RDOUT RX_A /TXRDY_A /DTR_A /DSR_A /CTS_A /RI_A RTX+ RRX+ LED1 /WR /RD A4_ST R2 LEV_R2 LEV_R1 R1 ADJ_LEV TX1_HI NTX_EN TX2_HI TX2_LO TX1_LO U3B 100n C50 81 82 83 84 85 76 77 78 79 80 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 22p C46 GND JP4 Tuesday, March 26, 2002 Document Number Connect Sheet 1 5 22p C47 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 5 HFC-S active system board (c) 2001 by Cologne Chip AG GPIO11R GPIO15R GPIO14R GPIO0 GPIO2 GPIO1 GPIO17 4 of 5 Rev 1.0 R2 LEV_R2 LEV_R1 R1 ADJ_LEV TX1_HI TX_EN TX2_HI /TX2_LO /TX1_LO A5_ST /RTS_A TX_A /CS_A /DCD_A RTXRRXLED0 LED2 /AUFDX PD0 PD1 PD3 PD5 PD7 /CS_P /TXRDY_B D C B A Examples circuitry 173 of 173