ETC HFC-E1

Cologne
Chip
HFC - E1
ISDN HDLC FIFO controller
with
Primary Rate Interface (E1)
Data Sheet
October 2003
Cologne
Chip
HFC-E1
Revision History
Date
Remarks
October 2003
The data sheet has completely been revised. Information was added to the chapters Data
flow, E1 interface, PCM interface, Multiparty audio conferences, DTMF controller, BERT,
Clock, reset, interrupt, timer and watchdog and GPIO. Sample circuitries are revised in chapter
Universal external bus interface. Programming examples are revised in chapter Data Flow
for SM, CSM, FSM and the subchannel processor. Restrictions are described on EEPROM
programming and Auxiliary interface.
March 2003
First edition.
Cologne Chip AG
Eintrachtstrasse 113
D - 50668 Köln
Germany
Tel.: +49 (0) 221 / 91 24-0
Fax: +49 (0) 221 / 91 24-100
http://www.CologneChip.com
http://www.CologneChip.de
[email protected]
Copyright 1994 - 2003 Cologne Chip AG
All Rights Reserved
The information presented can not be considered as assured characteristics. Data can change without notice.
Parts of the information presented may be protected by patent or other rights.
Cologne Chip products are not designed, intended, or authorized for use in any application
intended to support or sustain life, or for any other application in which the failure of the
Cologne Chip product could create a situation where personal injury or death may occur.
2 of 306
Data Sheet
October 2003
Contents
1 General description
23
1.1
System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
1.3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.3.1
Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.3.2
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2 Universal external bus interface
2.1
2.2
2.3
2.4
2.5
47
Common features of all interface modes . . . . . . . . . . . . . . . . . . . . . . . .
49
2.1.1
EEPROM programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
2.1.2
EEPROM circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
2.1.3
Register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
2.1.4
RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
2.2.1
PCI command types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
2.2.2
PCI access description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
2.2.3
PCI configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
2.2.4
PCI connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
ISA Plug and Play interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
2.3.1
IRQ assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
2.3.2
ISA Plug and Play registers . . . . . . . . . . . . . . . . . . . . . . . . . .
60
2.3.3
ISA connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
PCMCIA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
2.4.1
Attribute memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
2.4.2
PCMCIA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
2.4.3
PCMCIA connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . .
67
Parallel processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
2.5.1
Parallel processor interface modes . . . . . . . . . . . . . . . . . . . . . . .
69
2.5.2
Signal and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . .
69
October 2003
Data Sheet
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Chip
HFC-E1
2.5.2.1
8 bit processors in mode 2 (Motorola) and mode 3 (Intel) . . . . .
71
2.5.2.2
16 bit processors in mode 2 (Motorola) and mode 3 (Intel) . . . . .
74
2.5.2.3
8 bit processors in mode 4 (Intel, multiplexed) . . . . . . . . . . .
78
2.5.2.4
16 bit processors in mode 4 (Intel, multiplexed) . . . . . . . . . .
80
2.5.2.5
32 bit processors in mode 4 (Intel, multiplexed) . . . . . . . . . .
82
Examples of processor connection circuitries . . . . . . . . . . . . . . . . .
86
Serial processor interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
2.6.1
SPI read and write access . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
2.6.2
SPI connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
2.7.1
Write only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
2.7.2
Read only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
2.5.3
2.6
2.7
3 HFC-E1 data flow
3.1
3.2
3.3
3.4
Data flow concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
3.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
3.1.2
Term definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
3.2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
3.2.2
Switching buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.2.3
Timed sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.2.4
Transmit operation (FIFO in transmit data direction) . . . . . . . . . . . . . 101
3.2.5
Receive operation (FIFO in receive data direction) . . . . . . . . . . . . . . 101
3.2.6
Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Assigners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.3.1
HFC-channel assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.3.2
PCM slot assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.3.3
E1 slot assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.3.4
Assigner summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Data flow modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.4.1
3.4.2
4 of 306
97
Simple Mode (SM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.4.1.1
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.4.1.2
Subchannel processing . . . . . . . . . . . . . . . . . . . . . . . 107
3.4.1.3
Example for SM . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Channel Select Mode (CSM) . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.4.2.1
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.4.2.2
HFC-channel assigner . . . . . . . . . . . . . . . . . . . . . . . . 112
Data Sheet
October 2003
Cologne
Chip
HFC-E1
3.4.3
3.5
3.4.2.3
Subchannel Processing . . . . . . . . . . . . . . . . . . . . . . . 112
3.4.2.4
Example for CSM . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FIFO Sequence Mode (FSM) . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.4.3.1
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.4.3.2
FIFO sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.4.3.3
FSM programming . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.4.3.4
Example for FSM . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Subchannel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.5.1.1
3.5.2
3.5.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Details of the FIFO oriented part of the subchannel processor (part A) . . . . 126
3.5.2.1
FIFO transmit operation in transparent mode . . . . . . . . . . . . 126
3.5.2.2
FIFO transmit operation in HDLC mode . . . . . . . . . . . . . . 126
3.5.2.3
FIFO receive operation in transparent mode . . . . . . . . . . . . 126
3.5.2.4
FIFO receive operation in HDLC mode . . . . . . . . . . . . . . . 127
Details of the HFC-channel oriented part of the subchannel processor (part B) 128
3.5.3.1
FIFO transmit operation in SM . . . . . . . . . . . . . . . . . . . 128
3.5.3.2
FIFO transmit operation in CSM and FSM . . . . . . . . . . . . . 128
3.5.3.3
FIFO receive operation in SM . . . . . . . . . . . . . . . . . . . . 128
3.5.3.4
FIFO receive operation in CSM and FSM . . . . . . . . . . . . . . 129
3.5.4
Subchannel example for SM . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.5.5
Subchannel example for CSM . . . . . . . . . . . . . . . . . . . . . . . . . 133
4 FIFO handling and HDLC controller
141
4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.2
FIFO counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.3
FIFO size setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.4
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.5
4.4.1
HDLC transmit FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.4.2
FIFO full condition in HDLC transmit HFC-channels . . . . . . . . . . . . . 146
4.4.3
HDLC receive FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
4.4.4
FIFO full condition in HDLC receive HFC-channels . . . . . . . . . . . . . 147
4.4.5
Transparent mode of the HFC-E1 . . . . . . . . . . . . . . . . . . . . . . . 148
4.4.6
Reading F- and Z-counters . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.5.1
Write only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.5.2
Read only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
October 2003
Data Sheet
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Chip
HFC-E1
4.5.3
Read / write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5 E1 interface
169
5.1
Interface functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.2
Clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.3
External circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.4.1
Write only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.4.2
Read only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6 PCM interface
203
6.1
PCM interface function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.2
PCM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.3
PCM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.4
6.5
6.3.1
Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.3.2
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
External CODECs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.4.1
CODEC select via enable lines
. . . . . . . . . . . . . . . . . . . . . . . . 209
6.4.2
CODEC select via time slot number . . . . . . . . . . . . . . . . . . . . . . 211
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.5.1
Write only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.5.2
Read only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7 Pulse width modulation (PWM) outputs
225
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.2
Standard PWM usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.3
Alternative PWM usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.4.1
Write only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8 Multiparty audio conferences
229
8.1
Conference unit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.2
Overflow handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.3
Conference including the E1 interface . . . . . . . . . . . . . . . . . . . . . . . . . 231
8.4
Conference setup example for CSM . . . . . . . . . . . . . . . . . . . . . . . . . . 231
8.5
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6 of 306
8.5.1
Write only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.5.2
Read only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Data Sheet
October 2003
Cologne
Chip
HFC-E1
9 DTMF controller
239
9.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9.2
DTMF calculation principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9.3
DTMF controller implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
9.4
Access to DTMF coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
9.5
DTMF tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
9.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
10 Bit Error Rate Test (BERT)
249
10.1 BERT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
10.2 BERT transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
10.3 BERT receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
10.4.1 Write only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
10.4.2 Read only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
11 Auxiliary interface
257
12 Clock, reset, interrupt, timer and watchdog
259
12.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.3.1 Common features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.3.2 E1 interface interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.3.3 FIFO interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.3.4 DTMF interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.3.5 External interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.3.6 Timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.3.7 125 µs interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.4 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
12.5.1 Write only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
12.5.2 Read only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
13 General purpose I/O pins (GPIO) and input pins (GPI)
281
13.1 GPIO and GPI functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
13.2 GPIO output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
13.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
13.3.1 Write only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
October 2003
Data Sheet
7 of 306
Cologne
Chip
HFC-E1
13.3.2 Read only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14 Electrical characteristics
.1
297
Frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
.1.1
Allocation of bits 1 to 8 of the frame (Time slot 0) . . . . . . . . . . . . . . 299
.1.2
CRC-4 multiframe structure . . . . . . . . . . . . . . . . . . . . . . . . . . 300
A HFC-E1 package dimensions
301
List of register and bitmap abbreviations
303
G
General Remarks to Notations
1. Numerical values have different notations for various number systems; e.g.
the hexadecimal value 0xC9 is ’11001001’ in binary and 201 in decimal
notation.
2. The first letter of register names indicates the type: ‘R_ . . . ’ is a register,
while ‘A_ . . . ’ is an array-register.
3. The first letter of a register’s bit or bitmap name indicates the type: ‘V_ . . . ’
is a bit or bitmap value and ‘M_ . . . ’ is its mask, i.e. all bits of the bitmap
are set to ’1’.
8 of 306
Data Sheet
October 2003
List of Figures
1.1
HFC-E1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
1.2
HFC-E1 pinout in PCI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.3
HFC-E1 pinout in ISA PnP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
1.4
HFC-E1 pinout in PCMCIA mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
1.5
HFC-E1 pinout in processor mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
1.6
HFC-E1 pinout in SPI mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.1
EEPROM connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
2.2
EE_SCL/EN and EE_SDA connection without EEPROM . . . . . . . . . . . . . . .
50
2.3
PCI configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
2.4
PCI access in PCI I/O mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . .
54
2.5
PCI access in PCI memory mapped mode . . . . . . . . . . . . . . . . . . . . . . .
54
2.6
PCI connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
2.7
ISA PnP circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
2.8
PCMCIA circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
2.9
Read access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel) . . . . .
71
2.10 Write access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel) . . . . .
73
2.11 Byte / word read access from 16 bit proc. in mode 2 (Motorola) & mode 3 (Intel) . .
74
2.12 Byte / word write access from 16 bit proc. in mode 2 (Motorola) & mode 3 (Intel) . .
76
2.13 Byte read access from 8 bit processors in mode 4 (Intel, multiplexed) . . . . . . . . .
78
2.14 Byte write access from 8 bit processors in mode 4 (Intel, multiplexed) . . . . . . . .
79
2.15 Word read access from 16 bit processors in mode 4 (Intel, multiplexed) . . . . . . . .
80
2.16 Word write access from 16 bit processors in mode 4 (Intel, multiplexed) . . . . . . .
81
2.17 Double word read access from 32 bit processors in mode 4 (Intel, multiplexed) . . . .
82
2.18 Double word write access from 32 bit processors in mode 4 (Intel, multiplexed) . . .
84
2.19 8 bit Intel / Motorola processor circuitry example (mode 2) . . . . . . . . . . . . . .
86
2.20 16 bit Intel processor circuitry example (mode 4, multiplexed) . . . . . . . . . . . .
87
2.21 SPI read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
2.22 SPI write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
2.23 Interrupted SPI read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
2.24 SPI connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
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3.1
Data flow block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97
3.2
Areas of FIFO oriented, HFC-channel oriented and PCM time slot oriented numbering 99
3.3
The flow controller in transmit operation
3.4
The flow controller in receive FIFO operation . . . . . . . . . . . . . . . . . . . . . 102
3.5
Overview of the assigner programming . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.6
SM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.7
HFC-channel assigner in CSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.8
CSM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.9
HFC-channel assigner in FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
. . . . . . . . . . . . . . . . . . . . . . . 101
3.10 FSM list processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.11 FSM list programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.12 FSM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.13 General structure of the subchannel processor . . . . . . . . . . . . . . . . . . . . . 125
3.14 Part A of the subchannel processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.15 Part B of the subchannel processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.16 SM example with subchannel processor . . . . . . . . . . . . . . . . . . . . . . . . 129
3.17 CSM example with subchannel processor . . . . . . . . . . . . . . . . . . . . . . . 134
4.1
FIFO organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.2
FIFO data organization in HDLC mode . . . . . . . . . . . . . . . . . . . . . . . . 146
5.1
E1 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.2
Detail of the E1 interface synchronization selection shown in Figure 5.1 . . . . . . . 173
5.3
External E1 transmit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.4
External E1 receive circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.5
VDD_E1 voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.6
Connector circuitry in LT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.7
Connector circuitry in TE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.1
PCM interface function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.2
PCM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.3
Example for two CODEC enable signal shapes with SHAPE0 and SHAPE1. . . . . . 210
6.4
Example for two CODEC enable signal shapes . . . . . . . . . . . . . . . . . . . . 212
8.1
Conference example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
9.1
DTMF controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
10.1 BERT transmitter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
10.2 BERT receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
12.1 Standard HFC-E1 quartz circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
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12.2 External interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.1 GPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
13.2 GPIO block diagram (GPIO0 and GPIO1 exemplarily . . . . . . . . . . . . . . . . . 284
A.1 HFC-E1 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
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List of Tables
2.1
Overview of the HFC-E1 bus interface registers . . . . . . . . . . . . . . . . . . . .
47
2.2
Access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
2.3
Overview of common bus interface pins . . . . . . . . . . . . . . . . . . . . . . . .
49
2.4
SRAM start address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
2.5
Overview of the PCI interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
2.6
PCI command types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
2.7
PCI configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
2.8
Overview of the ISA PnP interface pins . . . . . . . . . . . . . . . . . . . . . . . .
59
2.9
ISA address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
2.10 ISA Plug and Play registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
2.11 Overview of the PCMCIA interface pins . . . . . . . . . . . . . . . . . . . . . . . .
65
2.12 PCMCIA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
2.13 Overview of the parallel processor interface pins in mode 2 and 3 . . . . . . . . . . .
68
2.14 Overview of the processor interface pins in mode 4 . . . . . . . . . . . . . . . . . .
68
2.15 Pins and signal names of the HFC-E1 processor interface modes . . . . . . . . . . .
69
2.16 Overview of read and write accesses in processor interface mode . . . . . . . . . . .
70
2.17 Timing diagrams of the parallel processor interface . . . . . . . . . . . . . . . . . .
70
2.18 Data access width in mode 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
2.19 Symbols of read accesses in Figures 2.9 and 2.11 . . . . . . . . . . . . . . . . . . .
75
2.20 Symbols of write accesses in Figures 2.10 and 2.12 . . . . . . . . . . . . . . . . . .
77
2.21 Data access width in mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
2.22 Symbols of read accesses in Figures 2.13, 2.15 and 2.17 . . . . . . . . . . . . . . . .
83
2.23 Symbols of write accesses in Figures 2.14, 2.16 and 2.18 . . . . . . . . . . . . . . .
85
2.24 Overview of the SPI interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
3.1
Flow controller connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.2
V_DATA_FLOW programming values for bidirectional connections . . . . . . . . . . 103
3.3
Index registers of the FIFO array registers (sorted by address) . . . . . . . . . . . . . 106
3.4
List specification of the example in Figure 3.12 . . . . . . . . . . . . . . . . . . . . 120
3.5
Subchannel processing according to Figure 3.16 (SM – TX, transparent mode) . . . 131
3.6
Subchannel processing according to Figure 3.16 (SM – RX, transparent mode) . . . 131
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3.7
Subchannel processing according to Figure 3.16 (SM — TX, HDLC mode) . . . . . 133
3.8
Subchannel processing according to Figure 3.16 (SM — RX, HDLC mode) . . . . . 134
3.9
Subchannel processing according to Figure 3.17 (CSM – TX, transparent mode) . . 136
3.10 Subchannel processing according to Figure 3.17 (CSM – RX, transparent mode) . . 137
3.11 Subchannel processing according to Figure 3.17 (CSM — TX, HDLC mode) . . . . . 140
3.12 Subchannel processing according to Figure 3.17 (CSM — RX, HDLC mode) . . . . 140
4.1
Overview of the HFC-E1 FIFO registers . . . . . . . . . . . . . . . . . . . . . . . . 141
4.2
F-counter range with different RAM sizes . . . . . . . . . . . . . . . . . . . . . . . 142
4.3
FIFO size setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.1
Overview of the HFC-E1 E1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.2
Overview of the HFC-E1 E1 interface registers . . . . . . . . . . . . . . . . . . . . . 170
6.1
Overview of the HFC-E1 PCM interface registers . . . . . . . . . . . . . . . . . . . 203
6.2
Overview of the HFC-E1 PCM pins ( ∗ : Second pin function) . . . . . . . . . . . . . . 204
6.3
PCM interface configuration with bitmaps of the register A_SL_CFG . . . . . . . . . 206
6.4
Master mode timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.5
Slave mode timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1
Overview of the HFC-E1 PWM pins . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.2
Overview of the HFC-E1 PWM registers . . . . . . . . . . . . . . . . . . . . . . . . 225
8.1
Overview of the HFC-E1 conference registers . . . . . . . . . . . . . . . . . . . . . 229
8.2
Conference example specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
9.1
Overview of the HFC-E1 DTMF registers . . . . . . . . . . . . . . . . . . . . . . . 239
9.2
DTMF tones on a 16-key keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9.3
9.4
16-bit K factors for the DTMF calculation . . . . . . . . . . . . . . . . . . . . . . . 241
Memory address calculation for DTMF coefficients related to equation (9.3) . . . . . 244
10.1 Overview of the HFC-E1 BERT registers . . . . . . . . . . . . . . . . . . . . . . . . 249
12.1 Overview of the HFC-E1 clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . 259
12.2 Overview of the HFC-E1 reset, timer and watchdog registers . . . . . . . . . . . . . 259
12.3 Quartz selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.4 HFC-E1 reset groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.1 Overview of the HFC-E1 general purpose I/O registers . . . . . . . . . . . . . . . . 281
13.2 GPIO pins of HFC-E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
13.3 GPI pins of HFC-E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
1
Allocation of bits 1 to 8 of the frame (Time slot 0) . . . . . . . . . . . . . . . . . . . 299
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2
CRC-4 multiframe structure in time slot 0 . . . . . . . . . . . . . . . . . . . . . . . 300
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List of Registers
G
Please note !
Register addresses are assigned independently for write and read access; i.e. in
many cases there are different registers for write and read access with the same
address. Only registers with the same meaning and bitmap structure in both write
and read directions are declared to be read / write.
It is important to distinguish between registers, array registers and multiregisters.
Array registers have multiple instances and are indexed by a number. This index is either the FIFO number (R_FIFO with 13 indexed registers) or the
PCM time slot number (R_SLOT with 2 indexed registers). Array registers
have equal name, bitmap structure and meaning for every instance.
Multi-registers have multiple instances, too, but they are selected by a bitmap
value. With this value, different registers can be selected with the
same address. Multi-register addresses are 0x15 (14 instances selected
by R_PCM_MD0) and 0x0F (2 instances selected by R_FIFO_MD) for
HFC-E1. Multi-registers have different names, bitmap structure and
meaning for each instance.
The first letter of array register names is ‘A_ . . . ’ whereas all other registers begin
with ‘R_ . . . ’. The index of array registers and multi-registers has to be specified
in the appropriate register.
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Registers sorted by name
G
Please note !
See explanation of register types on page 17.
Write only registers:
Address
Name
Reset
group
Page
Reset
group
Address
Name
Page
0x0A
R_RAM_ADDR2
0
93
0x0C
R_RAM_MISC
H
94
0xF4
A_CH_MSK
0, 1
154
0x25
R_RX_FR0
0, 1, 3
179
0xFC
A_CHANNEL
0, 1
158
0x26
R_RX_FR1
0, 1, 3
181
0xFA
A_CON_HDLC
0, 1
155
0x30
R_RX_OFF
0, 1, 3
187
0xD1
A_CONF
–
236
0x24
R_RX0
0, 1, 3
178
0xFD
A_FIFO_SEQ
0, 1
159
0x15
R_SH0H
0, 2
222
0x0E
A_INC_RES_FIFO
–
152
0x15
R_SH0L
0, 2
222
0xFF
A_IRQ_MSK
0, 1
268
0x15
R_SH1H
0, 2
223
0xD0
A_SL_CFG
0, 3
223
0x15
R_SH1L
0, 2
222
0xFB
A_SUBCH_CFG
0, 1
157
0x15
R_SL_SEL0
0, 2
215
0x1B
R_BERT_WD_MD
0, 1
253
0x15
R_SL_SEL1
0, 2
216
0x02
R_BRG_PCM_CFG
H
264
0x15
R_SL_SEL2
0, 2
216
0x00
R_CIRM
H
91
0x15
R_SL_SEL3
0, 2
217
0x18
R_CONF_EN
0, 2
236
0x15
R_SL_SEL4
0, 2
217
0x01
R_CTRL
H
92
0x15
R_SL_SEL5
0, 2
218
0x1D
R_DTMF_N
0
247
0x15
R_SL_SEL6
0, 2
218
0x1C
R_DTMF
0
246
0x15
R_SL_SEL7
0, 2
219
0x20
R_E1_WR_STA
0, 1, 3
176
0x10
R_SLOT
0, 2
213
0x0D
R_FIFO_MD
H
151
0x35
R_SYNC_CTRL
0, 1, 3
190
0x0F
R_FIFO
0, 1
153
0x31
R_SYNC_OUT
0, 1, 3
188
0x0B
R_FIRST_FIFO
0, 1
151
0x1A
R_TI_WD
0, 1
267
0x0F
R_FSM_IDX
0, 1
154
0x2C
R_TX_FR0
0, 1, 3
184
0x42
R_GPIO_EN0
0
287
0x2D
R_TX_FR1
0, 1, 3
185
0x43
R_GPIO_EN1
0
288
0x2E
R_TX_FR2
0, 1, 3
186
0x40
R_GPIO_OUT0
0
285
0x34
R_TX_OFF
0, 1, 4
189
0x41
R_GPIO_OUT1
0
286
0x28
R_TX0
0, 1, 3
182
0x44
R_GPIO_SEL
0
289
0x29
R_TX1
0, 1, 3
183
0x13
R_IRQ_CTRL
0
266
0x11
R_IRQMSK_MISC
H
266
0x22
R_LOS0
0, 1, 3
176
0x23
R_LOS1
0, 1, 3
177
0x14
R_PCM_MD0
0, 2
214
0x15
R_PCM_MD1
0, 2
220
0x15
R_PCM_MD2
0, 2
221
Reset
group
Page
0x46
R_PWM_MD
0
228
0x38
R_PWM0
0, 1, 3
227
0x39
R_PWM1
0x08
R_RAM_ADDR0
0x09
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R_RAM_ADDR1
0, 1, 3
227
0
93
0
93
Read only registers:
Address
Name
0x0C
A_F1
0, 1
162
0x0C
A_F12
0, 1
163
0x0D
A_F2
0, 1
162
0x04
A_Z1
0, 1
160
Data Sheet
October 2003
Cologne
Chip
HFC-E1
Address
Name
Reset
group
Page
0x04
A_Z12
0, 1
0x05
A_Z1H
0, 1
0x04
A_Z1L
0, 1
0x06
A_Z2
0, 1
161
0x07
A_Z2H
0, 1
161
Reset
group
Page
–
271
0, 3
198
Address
Name
162
0x1C
R_STATUS
160
0x33
R_VIO_ECH
160
0x32
R_VIO_ECL
0, 3
198
Reset
group
Page
0x06
A_Z2L
0, 1
161
0x1B
R_BERT_ECH
0, 1
255
0x1A
R_BERT_ECL
0, 1
254
0x17
R_BERT_STA
0, 1
254
0x16
R_CHIP_ID
H
95
Address
Name
0x1F
R_CHIP_RV
–
96
0x14
R_CONF_OFLOW
0x84
A_FIFO_DATA0_NOINC
–
166
0, 1
237
0x35
R_CRC_ECH
0x80
A_FIFO_DATA0
–
165
0, 3
199
0x34
R_CRC_ECL
0x84
A_FIFO_DATA1_NOINC
–
167
0, 3
198
0x37
R_E_ECH
0x80
A_FIFO_DATA1
–
165
0, 3
199
0x36
R_E_ECL
0x84
A_FIFO_DATA2_NOINC
–
167
0, 3
199
0x20
R_E1_RD_STA
0x80
A_FIFO_DATA2
–
165
0, 3
191
0x19
R_F0_CNTH
0xC0
R_RAM_DATA
–
95
0, 1
224
0x18
R_F0_CNTL
0, 1
224
0x31
R_FAS_ECH
0, 3
197
0x30
R_FAS_ECL
0, 3
197
0x44
R_GPI_IN0
–
292
0x45
R_GPI_IN1
–
293
0x46
R_GPI_IN2
–
294
0x47
R_GPI_IN3
–
295
0x40
R_GPIO_IN0
–
290
0x41
R_GPIO_IN1
–
291
0x88
R_INT_DATA
–
163
0xC8
R_IRQ_FIFO_BL0
0, 1
272
0xC9
R_IRQ_FIFO_BL1
0, 1
273
0xCA
R_IRQ_FIFO_BL2
0, 1
274
0xCB
R_IRQ_FIFO_BL3
0, 1
275
0xCC
R_IRQ_FIFO_BL4
0, 1
276
0xCD
R_IRQ_FIFO_BL5
0, 1
277
0xCE
R_IRQ_FIFO_BL6
0, 1
278
0xCF
R_IRQ_FIFO_BL7
0, 1
279
0x11
R_IRQ_MISC
0, 1
270
0x10
R_IRQ_OVIEW
0, 1
269
0x15
R_RAM_USE
0, 1
95
0x24
R_RX_STA0
0, 3
192
0x25
R_RX_STA1
0, 3
193
0x26
R_RX_STA2
0, 3
194
0x27
R_RX_STA3
0, 3
195
0x39
R_SA6_SA13_ECH
0, 3
200
0x38
R_SA6_SA13_ECL
0, 3
200
0x3B
R_SA6_SA23_ECH
0, 3
201
0x3A
R_SA6_SA23_ECL
0, 3
200
0x2C
R_SLIP
0, 3
196
October 2003
Read / Write registers:
Note: See Table 12.4 on page 261 for ‘Reset group’
explanation.
Data Sheet
19 of 306
Cologne
Chip
HFC-E1
Registers sorted by address
G
Please note !
See explanation of register types on page 17.
Write only registers:
Address
Name
Reset
group
Page
Reset
group
Address
Name
Page
0x24
R_RX0
0, 1, 3
178
0x25
R_RX_FR0
0, 1, 3
179
0x00
R_CIRM
H
91
0x26
R_RX_FR1
0, 1, 3
181
0x01
R_CTRL
H
92
0x28
R_TX0
0, 1, 3
182
0x02
R_BRG_PCM_CFG
H
264
0x29
R_TX1
0, 1, 3
183
0x08
R_RAM_ADDR0
0
93
0x2C
R_TX_FR0
0, 1, 3
184
0x09
R_RAM_ADDR1
0
93
0x2D
R_TX_FR1
0, 1, 3
185
0x0A
R_RAM_ADDR2
0
93
0x2E
R_TX_FR2
0, 1, 3
186
0x0B
R_FIRST_FIFO
0, 1
151
0x30
R_RX_OFF
0, 1, 3
187
0x0C
R_RAM_MISC
H
94
0x31
R_SYNC_OUT
0, 1, 3
188
0x0D
R_FIFO_MD
H
151
0x34
R_TX_OFF
0, 1, 4
189
0x0E
A_INC_RES_FIFO
–
152
0x35
R_SYNC_CTRL
0, 1, 3
190
0x0F
R_FSM_IDX
0, 1
154
0x38
R_PWM0
0, 1, 3
227
0x0F
R_FIFO
0, 1
153
0x39
R_PWM1
0, 1, 3
227
0x10
R_SLOT
0, 2
213
0x40
R_GPIO_OUT0
0
285
0x11
R_IRQMSK_MISC
H
266
0x41
R_GPIO_OUT1
0
286
0x13
R_IRQ_CTRL
0
266
0x42
R_GPIO_EN0
0
287
0x14
R_PCM_MD0
0, 2
214
0x43
R_GPIO_EN1
0
288
0x15
R_PCM_MD1
0, 2
220
0x44
R_GPIO_SEL
0
289
0x15
R_PCM_MD2
0, 2
221
0x46
R_PWM_MD
0
228
0x15
R_SH0H
0, 2
222
0xD0
A_SL_CFG
0x15
R_SH1H
0, 2
223
0xD1
A_CONF
0x15
R_SH0L
0, 2
222
0xF4
A_CH_MSK
0, 1
154
0x15
R_SH1L
0, 2
222
0xFA
A_CON_HDLC
0, 1
155
0x15
R_SL_SEL0
0, 2
215
0xFB
A_SUBCH_CFG
0, 1
157
0x15
R_SL_SEL1
0, 2
216
0xFC
A_CHANNEL
0, 1
158
0x15
R_SL_SEL2
0, 2
216
0xFD
A_FIFO_SEQ
0, 1
159
0x15
R_SL_SEL3
0, 2
217
0xFF
A_IRQ_MSK
0, 1
268
0x15
R_SL_SEL4
0, 2
217
0x15
R_SL_SEL5
0, 2
218
0x15
R_SL_SEL6
0, 2
218
0x15
R_SL_SEL7
0, 2
219
0x18
R_CONF_EN
0, 2
236
0x1A
R_TI_WD
0, 1
267
0x1B
R_BERT_WD_MD
0, 1
253
0x1C
R_DTMF
0
246
0x1D
R_DTMF_N
0
247
0x20
R_E1_WR_STA
0, 1, 3
176
0x22
R_LOS0
0, 1, 3
176
0x23
20 of 306
R_LOS1
0, 1, 3
177
0, 3
223
–
236
Read only registers:
Address
Name
Reset
group
Page
0x04
A_Z12
0, 1
162
0x04
A_Z1L
0, 1
160
0x04
A_Z1
0, 1
160
0x05
A_Z1H
0, 1
160
Data Sheet
October 2003
Cologne
Chip
HFC-E1
Name
Reset
group
Page
0x06
A_Z2L
0, 1
0x06
A_Z2
0, 1
0x07
A_Z2H
0, 1
0x0C
A_F1
0, 1
162
0x0C
A_F12
0, 1
163
Address
Reset
group
Page
R_IRQ_FIFO_BL5
0, 1
277
R_IRQ_FIFO_BL6
0, 1
278
R_IRQ_FIFO_BL7
0, 1
279
Reset
group
Page
Address
Name
161
0xCD
161
0xCE
161
0xCF
0x0D
A_F2
0, 1
162
0x10
R_IRQ_OVIEW
0, 1
269
0x11
R_IRQ_MISC
0, 1
270
0x14
R_CONF_OFLOW
0, 1
237
0x15
R_RAM_USE
0, 1
95
Address
Name
0x16
R_CHIP_ID
H
95
0x17
R_BERT_STA
0x80
A_FIFO_DATA2
–
165
0, 1
254
0x18
R_F0_CNTL
0x80
A_FIFO_DATA0
–
165
0, 1
224
0x19
R_F0_CNTH
0x80
A_FIFO_DATA1
–
165
0, 1
224
0x1A
R_BERT_ECL
0x84
A_FIFO_DATA2_NOINC
–
167
0, 1
254
0x1B
R_BERT_ECH
0x84
A_FIFO_DATA0_NOINC
–
166
0, 1
255
0x1C
R_STATUS
0x84
A_FIFO_DATA1_NOINC
–
167
–
271
0x1F
R_CHIP_RV
0xC0
R_RAM_DATA
–
95
–
96
0x20
R_E1_RD_STA
0, 3
191
0x24
R_RX_STA0
0, 3
192
0x25
R_RX_STA1
0, 3
193
0x26
R_RX_STA2
0, 3
194
0x27
R_RX_STA3
0, 3
195
0x2C
R_SLIP
0, 3
196
0x30
R_FAS_ECL
0, 3
197
0x31
R_FAS_ECH
0, 3
197
0x32
R_VIO_ECL
0, 3
198
0x33
R_VIO_ECH
0, 3
198
0x34
R_CRC_ECL
0, 3
198
0x35
R_CRC_ECH
0, 3
199
0x36
R_E_ECL
0, 3
199
0x37
R_E_ECH
0, 3
199
0x38
R_SA6_SA13_ECL
0, 3
200
0x39
R_SA6_SA13_ECH
0, 3
200
0x3A
R_SA6_SA23_ECL
0, 3
200
0x3B
R_SA6_SA23_ECH
0, 3
201
0x40
R_GPIO_IN0
–
290
0x41
R_GPIO_IN1
–
291
0x44
R_GPI_IN0
–
292
0x45
R_GPI_IN1
–
293
0x46
R_GPI_IN2
–
294
0x47
R_GPI_IN3
–
295
0x88
R_INT_DATA
–
163
0xC8
R_IRQ_FIFO_BL0
0, 1
272
0xC9
R_IRQ_FIFO_BL1
0, 1
273
0xCA
R_IRQ_FIFO_BL2
0, 1
274
0xCB
R_IRQ_FIFO_BL3
0, 1
275
0xCC
R_IRQ_FIFO_BL4
0, 1
276
October 2003
Read / Write registers:
Note: See Table 12.4 on page 261 for ‘Reset group’
explanation.
Data Sheet
21 of 306
Cologne
Chip
HFC-E1
22 of 306
Data Sheet
October 2003
Chapter 1
General description
HFC - E1
RAM
32K x 8
TM
32 for Receive: B, D, PCM
32 for Transmit: B, D, PCM
E1
Interface
Conference
SRAM
FIFO
128K x 8
512K x 8
FIFO
Controller
for
64 FIFOs
SubChannel
Processing
64
HDLC
Controllers
Transmit/Receive
Channel
for FIFO
Bit Count /
Start Bit /
Mask Bits
CODEC
Select
Connect
DTMF
Detect
Channel
HDLC / Transparent
Mode Select
for Channel
E1
(S2M)
Conference /
DTMF and
Connect
Options
Channel
Timeslot
Assigner
Slot
PCM128 /
PCM64 /
PCM30
Interface
PCM128
PCM64
PCM30
MST
(IOM2)
(GCI)
Select PCM
Timeslot
Configuration Registers
EEPROM
(required for
PCMCIA and
ISA-PnP,
optional for PCI)
Universal External Bus Interface
Bridge
8 Bit
PCI / ISA-PnP / PCMCIA /
Microprocessor Interface / SPI
Figure 1.1: HFC-E1 block diagram
October 2003
Data Sheet
23 of 306
HFC-E1
1.1
General description
Cologne
Chip
System overview
The HFC-E1 is an ISDN E1 HDLC primary rate controller for all kinds of PRI equipment, such as
• high performance ISDN PC cards
• ISDN PRI terminal adapters
• ISDN PABX for PRI
• VoIP gateways
• Integrated Access Devices (IAD)
• ISDN LAN routers for PRI
• ISDN least cost routers for PRI
• ISDN test equipment for PRI
The integrated universal bus interface of the HFC-E1 can be configured to PCI, ISA Plug and Play,
PCMCIA, microprocessor interface or SPI. A PCM128 / PCM64 / PCM30 interface for CODEC or
inter chip connection is also integrated. The very deep FIFOs of the HFC-E1 are realized with an
internal or external SRAM.
24 of 306
Data Sheet
October 2003
HFC-E1
General description
Cologne
Chip
1.2 Features
• integrated E1 interface
• single chip ISDN-E1 controller with HDLC support for all B- and D-channels
• full I.431 ITU E1 ISDN support in TE , NT and LT mode
• 32 independent read and write HDLC channels for e.g. 30 ISDN B-channels, 1 ISDN Dchannel
• B-channel transparent mode independently selectable
• up to 32 FIFOs for transmit and receive data each, FIFO sizes are configurable
• each FIFO can be assigned to an arbitrary HFC-channel, moreover each HFC-channel can be
assigned to a time slot of the E1 interface or to a time slot of the PCM interface
• max. 31 HDLC frames (with 128 kByte or 512 kByte external RAM) or 15 HDLC frames (with
32 kByte build-in RAM) per FIFO
• 1 . . 8 bit processing for subchannels selectable
• B-channels for higher data rate can be combined up to 256 bit
• PCM128 / PCM64 / PCM30 interface configurable to interface MSTTM (MVIPTM ) 1 or Siemens
IOM2TM and Motorola GCITM (no monitor or C/I-channel support) for inter chip connection or
external CODECs 2
• Switch matrix for PCM included
• H.100 data rate supported
• integrated ISA Plug and Play interface with buffers for ISA-databus
• integrated PCMCIA interface
• integrated PCI bus interface (Spec. 2.2) for 3.3 V and 5 V signal environment
• microprocessor interface compatible to Motorola bus and Siemens / Intel bus
• Serial processor interface (SPI)
• multiparty audio conferences switchable
• DTMF detection on all 32 channels
• Timer and watchdog with interrupt capability
• CMOS technology 3.3 V (5 V tolerant on nearly all inputs 3 )
• PQFP 208 package
1 Mitel
Serial Telecom bus
marked names are registered trademarks of the appropriate organizations.
3 Never connect the power supply of the HFC-E1 to 5 V!
2 All TM
October 2003
Data Sheet
25 of 306
HFC-E1
Cologne
Chip
General description
Pin description
1.3.1
Pinout diagram
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GPI17
GPI18
GPI19
NC
GND
GPIO8
GPIO9
GPIO10
GPIO11
VDD_E1
NC
GPI20
GPI21
GPI22
GPI23
VDD
GND
GPI24
GPI25
GPI26
GPI27
NC
GND
GPIO12
GPIO13
GPIO14
GPIO15
VDD_E1
NC
GPI28
GPI29
GPI30
GPI31
VDD
GND
STIO2
STIO1
F0IO
C4IO
C2O
GND
VDD
F1_0 / SHAPE0
F1_1 / SHAPE1
F1_2 / F_Q0
F1_3 / F_Q1
F1_4 / F_Q2
F1_5 / F_Q3
F1_6 / F_Q4
F1_7 / F_Q5
NC / F_Q6
GND
1.3
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
HFC - E1
ISDN Controller
Cologne Chip
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD
EE_SDA
EE_SLC/EN
GND
MODE1
MODE0
SYNC_O
SYNC_I
PWM0
PWM1
VDD
GND
CLK_MODE
OSC_OUT
OSC_IN
VDD
GND
/SR_OE / /BRG_RD
/SR_CS
/SR_WR / /BRG_WR
SRD7 / BRG_D7
SRD6 / BRG_D6
SRD5 / BRG_D5
SRD4 / BRG_D4
SRD3 / BRG_D3
SRD2 / BRG_D2
SRD1 / BRG_D1
SRD0 / BRG_D0
VDD
GND
NC / /BRG_CS7
SRA18 / /BRG_CS6
SRA17 / /BRG_CS5
SRA16 / /BRG_CS4
SRA15 / /BRG_CS3
SRA14 / /BRG_CS2
SRA13 / /BRG_CS1
SRA12 / /BRG_CS0
SRA11 / BRG_A11
SRA10 / BRG_A10
SRA9 / BRG_A9
SRA8 / BRG_A8
GND
SRA7 / BRG_A7
SRA6 / BRG_A6
SRA5 / BRG_A5
SRA4 / BRG_A4
SRA3 / BRG_A3
SRA2 / BRG_A2
SRA1 / BRG_A1
SRA0 / BRG_A0
GND
AD27
AD26
AD25
AD24
GND
C/BE3#
IDSEL
AD23
AD22
AD21
AD20
VDD
GND
AD19
AD18
AD17
AD16
C/BE2#
GND
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
VDD
GND
C/BE1#
AD15
AD14
AD13
AD12
GND
AD11
AD10
AD9
AD8
C/BE0#
VDD
GND
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GPI16
VDD
GPI15
GPI14
GPI13
GPI12
NC
VDD_E1
GPIO7
GPIO6
GPIO5
GPIO4
GND
NC
GPI11
GPI10
GPI9
GPI8
VDD
GPI7
GPI6
GPI5
GPI4
NC
VDD_E1
GPIO3
GPIO2
T_B / GPIO1
T_A / GPIO0
GND
ADJ_LEV
R_B / GPI3
LEV_B / GPI2
LEV_A / GPI1
R_A / GPI0
GND
VDD
VDD
/PME_IN
PME
INTA#
RST#
GND
CLKPCI
GND
VDD
AD31
AD30
AD29
AD28
GND
VDD
only normal function
normal and secondary function
interface mode dependend function
NC pins must not be connected
Figure 1.2: HFC-E1 pinout in PCI mode
26 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GPI17
GPI18
GPI19
NC
GND
GPIO8
GPIO9
GPIO10
GPIO11
VDD_E1
NC
GPI20
GPI21
GPI22
GPI23
VDD
GND
GPI24
GPI25
GPI26
GPI27
NC
GND
GPIO12
GPIO13
GPIO14
GPIO15
VDD_E1
NC
GPI28
GPI29
GPI30
GPI31
VDD
GND
STIO2
STIO1
F0IO
C4IO
C2O
GND
VDD
F1_0 / SHAPE0
F1_1 / SHAPE1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
GND
General description
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
HFC - E1
ISDN Controller
Cologne Chip
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD
EE_SDA
EE_SLC/EN
GND
MODE1
MODE0
SYNC_O
SYNC_I
PWM0
PWM1
VDD
GND
CLK_MODE
OSC_OUT
OSC_IN
VDD
GND
/SR_OE / /BRG_RD
/SR_CS
/SR_WR / /BRG_WR
SRD7 / BRG_D7
SRD6 / BRG_D6
SRD5 / BRG_D5
SRD4 / BRG_D4
SRD3 / BRG_D3
SRD2 / BRG_D2
SRD1 / BRG_D1
SRD0 / BRG_D0
VDD
GND
NC / /BRG_CS7
SRA18 / /BRG_CS6
SRA17 / /BRG_CS5
SRA16 / /BRG_CS4
SRA15 / /BRG_CS3
SRA14 / /BRG_CS2
SRA13 / /BRG_CS1
SRA12 / /BRG_CS0
SRA11 / BRG_A11
SRA10 / BRG_A10
SRA9 / BRG_A9
SRA8 / BRG_A8
GND
SRA7 / BRG_A7
SRA6 / BRG_A6
SRA5 / BRG_A5
SRA4 / BRG_A4
SRA3 / BRG_A3
SRA2 / BRG_A2
SRA1 / BRG_A1
SRA0 / BRG_A0
GND
SA11
SA10
SA9
SA8
GND
FL_0
GND
SA7
SA6
SA5
SA4
VDD
GND
SA3
SA2
SA1
SA0
/IOIS16
GND
/AEN
/IOR
/IOW
FL_0
FL_0
/BUSDIR
NC
FL_0
VDD
GND
/SBHE
SD15
SD14
SD13
SD12
GND
SD11
SD10
SD9
SD8
FL_0
VDD
GND
SD7
SD6
SD5
SD4
GND
SD3
SD2
SD1
SD0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GPI16
VDD
GPI15
GPI14
GPI13
GPI12
NC
VDD_E1
GPIO7
GPIO6
GPIO5
GPIO4
GND
NC
GPI11
GPI10
GPI9
GPI8
VDD
GPI7
GPI6
GPI5
GPI4
NC
VDD_E1
GPIO3
GPIO2
T_B / GPIO1
T_A / GPIO0
GND
ADJ_LEV
R_B / GPI3
LEV_B / GPI2
LEV_A / GPI1
R_A / GPI0
GND
VDD
VDD
GND
NC
NC
RESET
GND
GND
GND
VDD
SA15
SA14
SA13
SA12
GND
VDD
only normal function
normal and secondary function
interface mode dependend function
NC pins must not be connected
Figure 1.3: HFC-E1 pinout in ISA PnP mode
October 2003
Data Sheet
27 of 306
HFC-E1
Cologne
Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GPI17
GPI18
GPI19
NC
GND
GPIO8
GPIO9
GPIO10
GPIO11
VDD_E1
NC
GPI20
GPI21
GPI22
GPI23
VDD
GND
GPI24
GPI25
GPI26
GPI27
NC
GND
GPIO12
GPIO13
GPIO14
GPIO15
VDD_E1
NC
GPI28
GPI29
GPI30
GPI31
VDD
GND
STIO2
STIO1
F0IO
C4IO
C2O
GND
VDD
F1_0 / SHAPE0
F1_1 / SHAPE1
F1_2 / F_Q0
F1_3 / F_Q1
F1_4 / F_Q2
F1_5 / F_Q3
F1_6 / F_Q4
F1_7 / F_Q5
NC / F_Q6
GND
General description
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
HFC - E1
ISDN Controller
Cologne Chip
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD
EE_SDA
EE_SLC/EN
GND
MODE1
MODE0
SYNC_O
SYNC_I
PWM0
PWM1
VDD
GND
CLK_MODE
OSC_OUT
OSC_IN
VDD
GND
/SR_OE / /BRG_RD
/SR_CS
/SR_WR / /BRG_WR
SRD7 / BRG_D7
SRD6 / BRG_D6
SRD5 / BRG_D5
SRD4 / BRG_D4
SRD3 / BRG_D3
SRD2 / BRG_D2
SRD1 / BRG_D1
SRD0 / BRG_D0
VDD
GND
NC / /BRG_CS7
SRA18 / /BRG_CS6
SRA17 / /BRG_CS5
SRA16 / /BRG_CS4
SRA15 / /BRG_CS3
SRA14 / /BRG_CS2
SRA13 / /BRG_CS1
SRA12 / /BRG_CS0
SRA11 / BRG_A11
SRA10 / BRG_A10
SRA9 / BRG_A9
SRA8 / BRG_A8
GND
SRA7 / BRG_A7
SRA6 / BRG_A6
SRA5 / BRG_A5
SRA4 / BRG_A4
SRA3 / BRG_A3
SRA2 / BRG_A2
SRA1 / BRG_A1
SRA0 / BRG_A0
GND
A11
A10
A9
A8
GND
FL_0
REG#
A7
A6
A5
A4
VDD
GND
A3
A2
A1
A0
IOIS16#
GND
FL_0
IORD#
IOWR#
OE#
WE#
INPACK#
NC
FL_0
VDD
GND
CE2#
D15
D14
D13
D12
GND
D11
D10
D9
D8
CE1#
VDD
GND
D7
D6
D5
D4
GND
D3
D2
D1
D0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GPI16
VDD
GPI15
GPI14
GPI13
GPI12
NC
VDD_E1
GPIO7
GPIO6
GPIO5
GPIO4
GND
NC
GPI11
GPI10
GPI9
GPI8
VDD
GPI7
GPI6
GPI5
GPI4
NC
VDD_E1
GPIO3
GPIO2
T_B / GPIO1
T_A / GPIO0
GND
ADJ_LEV
R_B / GPI3
LEV_B / GPI2
LEV_A / GPI1
R_A / GPI0
GND
VDD
VDD
GND
NC
IREQ#
RESET
GND
GND
GND
VDD
A15
A14
A13
A12
GND
VDD
only normal function
normal and secondary function
interface mode dependend function
NC pins must not be connected
Figure 1.4: HFC-E1 pinout in PCMCIA mode
28 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GPI17
GPI18
GPI19
NC
GND
GPIO8
GPIO9
GPIO10
GPIO11
VDD_E1
NC
GPI20
GPI21
GPI22
GPI23
VDD
GND
GPI24
GPI25
GPI26
GPI27
NC
GND
GPIO12
GPIO13
GPIO14
GPIO15
VDD_E1
NC
GPI28
GPI29
GPI30
GPI31
VDD
GND
STIO2
STIO1
F0IO
C4IO
C2O
GND
VDD
F1_0 / SHAPE0
F1_1 / SHAPE1
F1_2 / F_Q0
F1_3 / F_Q1
F1_4 / F_Q2
F1_5 / F_Q3
F1_6 / F_Q4
F1_7 / F_Q5
NC / F_Q6
GND
General description
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
HFC - E1
ISDN Controller
Cologne Chip
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD
EE_SDA
EE_SLC/EN
GND
MODE1
MODE0
SYNC_O
SYNC_I
PWM0
PWM1
VDD
GND
CLK_MODE
OSC_OUT
OSC_IN
VDD
GND
/SR_OE / /BRG_RD
/SR_CS
/SR_WR / /BRG_WR
SRD7 / BRG_D7
SRD6 / BRG_D6
SRD5 / BRG_D5
SRD4 / BRG_D4
SRD3 / BRG_D3
SRD2 / BRG_D2
SRD1 / BRG_D1
SRD0 / BRG_D0
VDD
GND
NC / /BRG_CS7
SRA18 / /BRG_CS6
SRA17 / /BRG_CS5
SRA16 / /BRG_CS4
SRA15 / /BRG_CS3
SRA14 / /BRG_CS2
SRA13 / /BRG_CS1
SRA12 / /BRG_CS0
SRA11 / BRG_A11
SRA10 / BRG_A10
SRA9 / BRG_A9
SRA8 / BRG_A8
GND
SRA7 / BRG_A7
SRA6 / BRG_A6
SRA5 / BRG_A5
SRA4 / BRG_A4
SRA3 / BRG_A3
SRA2 / BRG_A2
SRA1 / BRG_A1
SRA0 / BRG_A0
GND
NC
FL_0
VDD
GND
/BE1
D15
D14
D13
D12
GND
D11
D10
D9
D8
/BE0
VDD
GND
D7
D6
D5
D4
GND
D3
D2
D1
D0
VDD
/BUSDIR
FL_0
FL_0
FL_0
FL_0
GND
/BE3
GND
A7
A6
A5
A4
VDD
GND
A3
A2
A1
A0
/BE2
GND
/CS
/IOR
/IOW
/WD
ALE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GPI16
VDD
GPI15
GPI14
GPI13
GPI12
NC
VDD_E1
GPIO7
GPIO6
GPIO5
GPIO4
GND
NC
GPI11
GPI10
GPI9
GPI8
VDD
GPI7
GPI6
GPI5
GPI4
NC
VDD_E1
GPIO3
GPIO2
T_B / GPIO1
T_A / GPIO0
GND
ADJ_LEV
R_B / GPI3
LEV_B / GPI2
LEV_A / GPI1
R_A / GPI0
GND
VDD
VDD
GND
NC
/INT
RESET
GND
GND
GND
VDD
FL_0
FL_0
FL_0
FL_0
GND
VDD
only normal function
normal and secondary function
interface mode dependend function
NC pins must not be connected
Figure 1.5: HFC-E1 pinout in processor mode
October 2003
Data Sheet
29 of 306
HFC-E1
Cologne
Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GPI17
GPI18
GPI19
NC
GND
GPIO8
GPIO9
GPIO10
GPIO11
VDD_E1
NC
GPI20
GPI21
GPI22
GPI23
VDD
GND
GPI24
GPI25
GPI26
GPI27
NC
GND
GPIO12
GPIO13
GPIO14
GPIO15
VDD_E1
NC
GPI28
GPI29
GPI30
GPI31
VDD
GND
STIO2
STIO1
F0IO
C4IO
C2O
GND
VDD
F1_0 / SHAPE0
F1_1 / SHAPE1
F1_2 / F_Q0
F1_3 / F_Q1
F1_4 / F_Q2
F1_5 / F_Q3
F1_6 / F_Q4
F1_7 / F_Q5
NC / F_Q6
GND
General description
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
HFC - E1
ISDN Controller
Cologne Chip
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD
EE_SDA
EE_SLC/EN
GND
MODE1
MODE0
SYNC_O
SYNC_I
PWM0
PWM1
VDD
GND
CLK_MODE
OSC_OUT
OSC_IN
VDD
GND
/SR_OE / /BRG_RD
/SR_CS
/SR_WR / /BRG_WR
SRD7 / BRG_D7
SRD6 / BRG_D6
SRD5 / BRG_D5
SRD4 / BRG_D4
SRD3 / BRG_D3
SRD2 / BRG_D2
SRD1 / BRG_D1
SRD0 / BRG_D0
VDD
GND
NC / /BRG_CS7
SRA18 / /BRG_CS6
SRA17 / /BRG_CS5
SRA16 / /BRG_CS4
SRA15 / /BRG_CS3
SRA14 / /BRG_CS2
SRA13 / /BRG_CS1
SRA12 / /BRG_CS0
SRA11 / BRG_A11
SRA10 / BRG_A10
SRA9 / BRG_A9
SRA8 / BRG_A8
GND
SRA7 / BRG_A7
SRA6 / BRG_A6
SRA5 / BRG_A5
SRA4 / BRG_A4
SRA3 / BRG_A3
SRA2 / BRG_A2
SRA1 / BRG_A1
SRA0 / BRG_A0
GND
FL_0
FL_0
FL_0
FL_0
GND
FL_0
GND
FL_0
FL_0
FL_0
FL_0
VDD
GND
FL_0
FL_0
FL_0
FL_0
FL_0
GND
FL_0
FL_1
FL_1
FL_0
FL_0
NC
NC
FL_0
VDD
GND
FL_0
FL_0
FL_0
FL_0
FL_0
GND
FL_0
FL_0
FL_0
FL_0
FL_0
VDD
GND
FL_0
FL_0
FL_0
FL_0
GND
FL_0
FL_0
FL_0
FL_0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GPI16
VDD
GPI15
GPI14
GPI13
GPI12
NC
VDD_E1
GPIO7
GPIO6
GPIO5
GPIO4
GND
NC
GPI11
GPI10
GPI9
GPI8
VDD
GPI7
GPI6
GPI5
GPI4
NC
VDD_E1
GPIO3
GPIO2
T_B / GPIO1
T_A / GPIO0
GND
ADJ_LEV
R_B / GPI3
LEV_B / GPI2
LEV_A / GPI1
R_A / GPI0
GND
VDD
/SPISEL
SPI_RX
SPI_TX
/INT
RESET
GND
SPICLK
GND
VDD
FL_0
FL_0
FL_0
FL_0
GND
VDD
only normal function
normal and secondary function
interface mode dependend function
NC pins must not be connected
Figure 1.6: HFC-E1 pinout in SPI mode
30 of 306
Data Sheet
October 2003
HFC-E1
1.3.2
Pin
Cologne
Chip
General description
Pin list
Interface
Name
I/O
Description
Uin / V
Iout / mA
Universal bus interface
1
2
3
4
PCI
ISA PnP
PCMCIA
Processor
AD27
SA11
A11
FL0
SPI
FL0
PCI
ISA PnP
PCMCIA
Processor
AD26
SA10
A10
FL0
SPI
FL0
PCI
ISA PnP
PCMCIA
Processor
AD25
SA9
A9
FL0
SPI
FL0
PCI
ISA PnP
PCMCIA
Processor
AD24
SA8
A8
FL0
SPI
FL0
7
I
IO
I
I
I
I
IO
I
I
I
I
IO
I
I
I
I
GND
5
6
IO
I
I
I
Address / Data bit 27
Address bit 11
Address bit 11
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Address / Data bit 26
Address bit 10
Address bit 10
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Address / Data bit 25
Address bit 9
Address bit 9
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Address / Data bit 24
Address bit 8
Address bit 8
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
LVCMOS
8
LVCMOS
8
LVCMOS
8
LVCMOS
Ground
PCI
ISA PnP
PCMCIA
Processor
SPI
C/BE3#
VDD
VDD
/BE3
VDD
PCI
ISA PnP
PCMCIA
IDSEL
GND
REG#
I
I
I
Processor
SPI
GND
GND
I
I
I
I
Bus command and Byte Enable 3
+3.3 V power supply
+3.3 V power supply
Byte Enable 3
+3.3 V power supply
Initialisation Device Select
Ground
PCMCIA Register and Attr. Mem.
Select
Ground
Ground
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
(continued on next page)
October 2003
Data Sheet
31 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
8
PCI
ISA PnP
PCMCIA
Processor
SPI
AD23
SA7
A7
A7
FL0
IO
I
I
I
I
Address / Data bit 23
Address bit 7
Address bit 7
Address bit 7
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
9
PCI
ISA PnP
PCMCIA
Processor
SPI
AD22
SA6
A6
A6
FL0
IO
I
I
I
I
Address / Data bit 22
Address bit 6
Address bit 6
Address bit 6
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
10
PCI
ISA PnP
PCMCIA
Processor
SPI
AD21
SA5
A5
A5
FL0
IO
I
I
I
I
Address / Data bit 21
Address bit 5
Address bit 5
Address bit 5
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
11
PCI
ISA PnP
PCMCIA
Processor
SPI
AD20
SA4
A4
A4
FL0
IO
I
I
I
I
Address / Data bit 20
Address bit 4
Address bit 4
Address bit 4
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
12
VDD
+3.3 V power supply
13
GND
Ground
Iout / mA
14
PCI
ISA PnP
PCMCIA
Processor
SPI
AD19
SA3
A3
A3
FL0
IO
I
I
I
I
Address / Data bit 19
Address bit 3
Address bit 3
Address bit 3
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
15
PCI
ISA PnP
PCMCIA
Processor
SPI
AD18
SA2
A2
A2
FL0
IO
I
I
I
I
Address / Data bit 18
Address bit 2
Address bit 2
Address bit 2
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
16
PCI
ISA PnP
PCMCIA
Processor
SPI
AD17
SA1
A1
A1
FL0
IO
I
I
I
I
Address / Data bit 17
Address bit 1
Address bit 1
Address bit 1
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
(continued on next page)
32 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
17
PCI
ISA PnP
PCMCIA
Processor
SPI
AD16
SA0
A0
A0
FL0
IO
I
I
I
I
Address / Data bit 16
Address bit 0
Address bit 0
Address bit 0
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
18
PCI
ISA PnP
PCMCIA
Processor
SPI
C/BE2#
/IOIS16
IOIS16#
/BE2
FL1
I
Ood
O
I
I
Bus command and Byte Enable 2
16 bit access enable
16 bit access enable
Byte Enable 2
Fixed level (high), connect to power
supply via ext. pull-up
LVCMOS
GND
19
PCI
ISA PnP
PCMCIA
Processor
SPI
FRAME#
/AEN
GND
/CS
VDD
21
PCI
ISA PnP
PCMCIA
Processor
SPI
IRDY#
/IOR
IORD#
/IOR
VDD
22
PCI
ISA PnP
PCMCIA
Processor
SPI
20
23
24
Iout / mA
8
8
8
LVCMOS
LVCMOS
Ground
I
I
Cycle Frame
Address Enable
Ground
Chip Select
+3.3 V power supply
LVCMOS
LVCMOS
I
I
I
I
Initiator Ready
Read Enable
Read Enable
Read Enable
+3.3 V power supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
TRDY#
/IOW
IOWR#
/IOW
FL1
O
I
I
I
I
Target Ready
Write Enable
Write Enable
Write Enable
Fixed level (high), connect to power
supply via ext. pull-up
PCI
ISA PnP
DEVSEL#
FL0
O
I
PCMCIA
OE#
I
Processor
SPI
/WD
FL0
Ood
I
Device Select
Fixed level (low), connect to ground
via ext. pull-down
PCMCIA Output Enable for Attr.
Mem. Read
Watch Dog Output
Fixed level (low), connect to ground
via ext. pull-down
PCI
ISA PnP
STOP#
FL0
O
I
PCMCIA
WE#
I
Processor
SPI
ALE
FL0
I
I
I
Stop
Fixed level (low), connect to ground
via ext. pull-down
PCMCIA Write Enable for Conf.
Reg. Write
Address Latch Enable
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
8
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
LVCMOS
LVCMOS
8
LVCMOS
8
LVCMOS
LVCMOS
LVCMOS
LVCMOS
(continued on next page)
October 2003
Data Sheet
33 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
25
PCI
ISA PnP
PCMCIA
Processor
SPI
PERR#
/BUSDIR
INPACK#
/BUSDIR
NC
IO
O
O
O
Parity Error
Bus Direction
Read access
Bus Direction
LVCMOS
26
PCI
ISA PnP
PCMCIA
Processor
SPI
SERR#
NC
NC
NC
NC
Ood
System Error
27
PCI
ISA PnP
PAR
FL0
IO
I
PCMCIA
FL0
I
Processor
FL0
I
SPI
FL0
I
Parity Bit
Fixed level (low), connect
via ext. pull-down
Fixed level (low), connect
via ext. pull-down
Fixed level (low), connect
via ext. pull-down
Fixed level (low), connect
via ext. pull-down
28
VDD
+3.3 V power supply
29
GND
Ground
30
PCI
ISA PnP
PCMCIA
Processor
SPI
C/BE1#
/SBHE
CE2#
/BE1
VDD
31
PCI
ISA PnP
PCMCIA
Processor
SPI
AD15
SD15
D15
D15
FL0
32
PCI
ISA PnP
PCMCIA
Processor
SPI
33
PCI
ISA PnP
PCMCIA
Processor
SPI
I
I
I
I
Iout / mA
8
8
8
8
8
to ground
LVCMOS
LVCMOS
to ground
LVCMOS
to ground
LVCMOS
to ground
LVCMOS
8
Bus command and Byte Enable 1
High byte enable
High byte enable
Byte Enable 1
+3.3 V power supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
IO
IO
IO
I
Address / Data bit 15
ISA Data Bus Bit 15
PCMCIA Data Bus Bit 15
Data bit 15
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
AD14
SD14
D14
D14
FL0
IO
IO
IO
IO
I
Address / Data bit 14
ISA Data Bus Bit 14
PCMCIA Data Bus Bit 14
Data bit 14
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
AD13
SD13
D13
D13
FL0
IO
IO
IO
IO
I
Address / Data bit 13
ISA Data Bus Bit 13
PCMCIA Data Bus Bit 13
Data bit 13
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
(continued on next page)
34 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
34
PCI
ISA PnP
PCMCIA
Processor
SPI
AD12
SD12
D12
D12
FL0
IO
IO
IO
IO
I
Address / Data bit 12
ISA Data Bus Bit 12
PCMCIA Data Bus Bit 12
Data bit 12
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
GND
35
Iout / mA
Ground
36
PCI
ISA PnP
PCMCIA
Processor
SPI
AD11
SD11
D11
D11
FL0
IO
IO
IO
IO
I
Address / Data bit 11
ISA Data Bus Bit 11
PCMCIA Data Bus Bit 11
Data bit 11
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
37
PCI
ISA PnP
PCMCIA
Processor
SPI
AD10
SD10
D10
D10
FL0
IO
IO
IO
IO
I
Address / Data bit 10
ISA Data Bus Bit 10
PCMCIA Data Bus Bit 10
Data bit 10
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
38
PCI
ISA PnP
PCMCIA
Processor
SPI
AD9
SD9
D9
D9
FL0
IO
IO
IO
IO
I
Address / Data bit 9
ISA Data Bus Bit 9
PCMCIA Data Bus Bit 9
Data bit 9
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
39
PCI
ISA PnP
PCMCIA
Processor
SPI
AD8
SD8
D8
D8
FL0
IO
IO
IO
IO
I
Address / Data bit 8
ISA Data Bus Bit 8
PCMCIA Data Bus Bit 8
Data bit 8
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
40
PCI
ISA PnP
PCMCIA
Processor
SPI
C/BE0#
GND
CE1#
/BE0
GND
Bus command and Byte Enable 0
Ground
Low byte enable
Byte Enable 0
Ground
LVCMOS
I
I
I
41
VDD
+3.3 V power supply
42
GND
Ground
43
PCI
ISA PnP
PCMCIA
Processor
SPI
AD7
SD7
D7
D7
FL0
IO
IO
IO
IO
I
Address / Data bit 7
ISA Data Bus Bit 7
PCMCIA Data Bus Bit 7
Data bit 7
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
(continued on next page)
October 2003
Data Sheet
35 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
44
PCI
ISA PnP
PCMCIA
Processor
SPI
AD6
SD6
D6
D6
FL0
IO
IO
IO
IO
I
Address / Data bit 6
ISA Data Bus Bit 6
PCMCIA Data Bus Bit 6
Data bit 6
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
45
PCI
ISA PnP
PCMCIA
Processor
SPI
AD5
SD5
D5
D5
FL0
IO
IO
IO
IO
I
Address / Data bit 5
ISA Data Bus Bit 5
PCMCIA Data Bus Bit 5
Data bit 5
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
46
PCI
ISA PnP
PCMCIA
Processor
SPI
AD4
SD4
D4
D4
FL0
IO
IO
IO
IO
I
Address / Data bit 4
ISA Data Bus Bit 4
PCMCIA Data Bus Bit 4
Data bit 4
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
GND
47
Iout / mA
Ground
48
PCI
ISA PnP
PCMCIA
Processor
SPI
AD3
SD3
D3
D3
FL0
IO
IO
IO
IO
I
Address / Data bit 3
ISA Data Bus Bit 3
PCMCIA Data Bus Bit 3
Data bit 3
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
49
PCI
ISA PnP
PCMCIA
Processor
SPI
AD2
SD2
D2
D2
FL0
IO
IO
IO
IO
I
Address / Data bit 2
ISA Data Bus Bit 2
PCMCIA Data Bus Bit 2
Data bit 2
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
50
PCI
ISA PnP
PCMCIA
Processor
SPI
AD1
SD1
D1
D1
FL0
IO
IO
IO
IO
I
Address / Data bit 1
ISA Data Bus Bit 1
PCMCIA Data Bus Bit 1
Data bit 1
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
51
PCI
ISA PnP
PCMCIA
Processor
SPI
AD0
SD0
D0
D0
FL0
IO
IO
IO
IO
I
Address / Data bit 0
ISA Data Bus Bit 0
PCMCIA Data Bus Bit 0
Data bit 0
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
8
8
8
52
VDD
+3.3 V power supply
53
GND
Ground
(continued on next page)
36 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
Iout / mA
SRAM / Auxiliary interface
54
1st function
2nd function
SRA0
BRG_A0
O
O
Address bit 0 for external SRAM
Bridge Address bit 0
2
2
55
1st function
2nd function
SRA1
BRG_A1
O
O
Address bit 1 for external SRAM
Bridge Address bit 1
2
2
56
1st function
2nd function
SRA2
BRG_A2
O
O
Address bit 2 for external SRAM
Bridge Address bit 2
2
2
57
1st function
2nd function
SRA3
BRG_A3
O
O
Address bit 3 for external SRAM
Bridge Address bit 3
2
2
58
1st function
2nd function
SRA4
BRG_A4
O
O
Address bit 4 for external SRAM
Bridge Address bit 4
2
2
59
1st function
2nd function
SRA5
BRG_A5
O
O
Address bit 5 for external SRAM
Bridge Address bit 5
2
2
60
1st function
2nd function
SRA6
BRG_A6
O
O
Address bit 6 for external SRAM
Bridge Address bit 6
2
2
61
1st function
2nd function
SRA7
BRG_A7
O
O
Address bit 7 for external SRAM
Bridge Address bit 7
2
2
GND
62
Ground
63
1st function
2nd function
SRA8
BRG_A8
O
O
Address bit 8 for external SRAM
Bridge Address bit 8
2
2
64
1st function
2nd function
SRA9
BRG_A9
O
O
Address bit 9 for external SRAM
Bridge Address bit 9
2
2
65
1st function
2nd function
SRA10
BRG_A10
O
O
Address bit 10 for external SRAM
Bridge Address bit 10
2
2
66
1st function
2nd function
SRA11
BRG_A11
O
O
Address bit 11 for external SRAM
Bridge Address bit 11
2
2
67
1st function
2nd function
SRA12
/BRG_CS0
O
O
Address bit 12 for external SRAM
Bridge Chip Select 0
2
2
68
1st function
2nd function
SRA13
/BRG_CS1
O
O
Address bit 13 for external SRAM
Bridge Chip Select 1
2
2
69
1st function
2nd function
SRA14
/BRG_CS2
O
O
Address bit 14 for external SRAM
Bridge Chip Select 2
2
2
70
1st function
2nd function
SRA15
/BRG_CS3
O
O
Address bit 15 for external SRAM
Bridge Chip Select 3
2
2
71
1st function
2nd function
SRA16
/BRG_CS4
O
O
Address bit 16 for external SRAM
Bridge Chip Select 4
2
2
72
1st function
2nd function
SRA17
/BRG_CS5
O
O
Address bit 17 for external SRAM
Bridge Chip Select 5
2
2
(continued on next page)
October 2003
Data Sheet
37 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
I/O
Description
Uin / V
Iout / mA
Interface
Name
73
1st function
2nd function
SRA18
/BRG_CS6
O
O
Address bit 18 for external SRAM
Bridge Chip Select 6
2
2
74
1st function
2nd function
NC
/BRG_CS7
O
Bridge Chip Select 7
2
75
GND
Ground
76
VDD
+3.3 V power supply
77
1st function
2nd function
SRD0
BRG_D0
IO
IO
Data bit 0 for external SRAM
Bridge Data bit 0
LVCMOS
LVCMOS
8
8
78
1st function
2nd function
SRD1
BRG_D1
IO
IO
Data bit 1 for external SRAM
Bridge Data bit 1
LVCMOS
LVCMOS
8
8
79
1st function
2nd function
SRD2
BRG_D2
IO
IO
Data bit 2 for external SRAM
Bridge Data bit 2
LVCMOS
LVCMOS
8
8
80
1st function
2nd function
SRD3
BRG_D3
IO
IO
Data bit 3 for external SRAM
Bridge Data bit 3
LVCMOS
LVCMOS
8
8
81
1st function
2nd function
SRD4
BRG_D4
IO
IO
Data bit 4 for external SRAM
Bridge Data bit 4
LVCMOS
LVCMOS
8
8
82
1st function
2nd function
SRD5
BRG_D5
IO
IO
Data bit 5 for external SRAM
Bridge Data bit 5
LVCMOS
LVCMOS
8
8
83
1st function
2nd function
SRD6
BRG_D6
IO
IO
Data bit 6 for external SRAM
Bridge Data bit 6
LVCMOS
LVCMOS
8
8
84
1st function
2nd function
SRD7
BRG_D7
IO
IO
Data bit 7 for external SRAM
Bridge Data bit 7
LVCMOS
LVCMOS
8
8
85
1st function
2nd function
/SR_WR
/BRG_WR
O
O
Write enable for external SRAM
Bridge Write enable / RD/WR
4
4
/SR_CS
O
Chip Select for external SRAM
4
/SR_OE
/BRG_RD
O
O
Output enable for external SRAM
Bridge Read enable / /DS
4
4
86
87
1st function
2nd function
88
GND
Ground
89
VDD
+3.3 V power supply
Clock
90
OSC_IN
I
Oscillator Input Signal
91
OSC_OUT
O
Oscillator Output Signal
92
CLK_MODE
I
Clock Mode
93
GND
Ground
94
VDD
+3.3 V power supply
LVCMOS
(continued on next page)
38 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
Iout / mA
Miscellaneous
95
PWM1
O
Pulse Width Modulator Output 1
8
96
PWM0
O
Pulse Width Modulator Output 0
8
97
SYNC_I
I
Synchronization Input
98
SYNC_O
O
Synchronization Output
99
MODE0
I
Interface Mode pin 0
LVCMOS
100
MODE1
I
Interface Mode pin 1
LVCMOS
101
GND
LVCMOS
4
Ground
EEPROM
102
EE_SCL/EN
IO
EEPROM clock / EEPROM enable
LVCMOS
1
103
EE_SDA
IO
EEPROM data I/O
LVCMOS
1
104
VDD
+3.3 V power supply
105
GND
Ground
PCM
1st function
2nd function
ISA PnP
NC
F_Q6
IRQ6
O
O
PCM time slot count 6
ISA Interrupt Request 6
6
6
107
1st function
2nd function
ISA PnP
F1_7
F_Q5
IRQ5
O
O
O
PCM CODEC enable 7
PCM time slot count 5
ISA Interrupt Request 5
6
6
6
108
1st function
2nd function
ISA PnP
F1_6
F_Q4
IRQ4
O
O
O
PCM CODEC enable 6
PCM time slot count 4
ISA Interrupt Request 4
6
6
6
109
1st function
2nd function
ISA PnP
F1_5
F_Q3
IRQ3
O
O
O
PCM CODEC enable 5
PCM time slot count 3
ISA Interrupt Request 3
6
6
6
110
1st function
2nd function
ISA PnP
F1_4
F_Q2
IRQ2
O
O
O
PCM CODEC enable 4
PCM time slot count 2
ISA Interrupt Request 2
6
6
6
111
1st function
2nd function
ISA PnP
F1_3
F_Q1
IRQ1
O
O
O
PCM CODEC enable 3
PCM time slot count 1
ISA Interrupt Request 1
6
6
6
112
1st function
2nd function
ISA PnP
F1_2
F_Q0
IRQ0
O
O
O
PCM CODEC enable 2
PCM time slot count 0
ISA Interrupt Request 0
6
6
6
106
(continued on next page)
October 2003
Data Sheet
39 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
I/O
Description
Uin / V
Iout / mA
Pin
Interface
Name
113
1st function
2nd function
F1_1
SHAPE1
O
O
PCM CODEC enable 1
PCM CODEC enable shape signal 1
6
6
114
1st function
2nd function
F1_0
SHAPE0
O
O
PCM CODEC enable 0
PCM CODEC enable shape signal 0
6
6
115
VDD
+3.3 V power supply
116
GND
Ground
117
C2O
O
118
C4IO
IOpu
PCM double bit clock I/O
LVCMOS
8
119
F0IO
IOpu
PCM frame clock I/O (8 kHz)
LVCMOS
8
120
STIO1
IOpu
PCM data bus 1, I or O per time slot
LVCMOS
8
121
STIO2
IOpu
PCM data bus 2, I or O per time slot
LVCMOS
8
122
GND
Ground
123
VDD
+3.3 V power supply
PCM bit clock output
8
GPIO
124
GPI31
I
General Purpose Input pin 31
LVCMOS
125
GPI30
I
General Purpose Input pin 30
LVCMOS
126
GPI29
I
General Purpose Input pin 29
LVCMOS
127
GPI28
I
General Purpose Input pin 28
LVCMOS
128
NC
129
VDD_E1
130
GPIO15
IO
General Purpose I/O pin 15
LVCMOS
16
131
GPIO14
IO
General Purpose I/O pin 14
LVCMOS
16
132
GPIO13
IO
General Purpose I/O pin 13
LVCMOS
16
133
GPIO12
IO
General Purpose I/O pin 12
LVCMOS
16
134
GND
135
NC
136
GPI27
I
General Purpose Input pin 27
LVCMOS
137
GPI26
I
General Purpose Input pin 26
LVCMOS
138
GPI25
I
General Purpose Input pin 25
LVCMOS
139
GPI24
I
General Purpose Input pin 24
LVCMOS
140
GND
app. +2.8 V power supply (depends
on the E1 transmit amplitude)
Ground
Ground
(continued on next page)
40 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
Iout / mA
141
VDD
142
GPI23
I
General Purpose Input pin 23
LVCMOS
143
GPI22
I
General Purpose Input pin 22
LVCMOS
144
GPI21
I
General Purpose Input pin 21
LVCMOS
145
GPI20
I
General Purpose Input pin 20
LVCMOS
146
NC
147
VDD_E1
148
GPIO11
IO
General Purpose I/O pin 11
LVCMOS
16
149
GPIO10
IO
General Purpose I/O pin 10
LVCMOS
16
150
GPIO9
IO
General Purpose I/O pin 9
LVCMOS
16
151
GPIO8
IO
General Purpose I/O pin 8
LVCMOS
16
152
GND
153
NC
154
GPI19
I
General Purpose Input pin 19
LVCMOS
155
GPI18
I
General Purpose Input pin 18
LVCMOS
156
GPI17
I
General Purpose Input pin 17
LVCMOS
157
GPI16
I
General Purpose Input pin 16
LVCMOS
158
VDD
159
GPI15
I
General Purpose Input pin 15
LVCMOS
160
GPI14
I
General Purpose Input pin 14
LVCMOS
161
GPI13
I
General Purpose Input pin 13
LVCMOS
162
GPI12
I
General Purpose Input pin 12
LVCMOS
163
NC
164
VDD_E1
165
GPIO7
IO
General Purpose I/O pin 7
LVCMOS
16
166
GPIO6
IO
General Purpose I/O pin 6
LVCMOS
16
167
GPIO5
IO
General Purpose I/O pin 5
LVCMOS
16
168
GPIO4
IO
General Purpose I/O pin 4
LVCMOS
16
169
GND
170
NC
+3.3 V power supply
app. +2.8 V power supply (depends
on the E1 transmit amplitude)
Ground
+3.3 V power supply
app. +2.8 V power supply (depends
on the E1 transmit amplitude)
Ground
(continued on next page)
October 2003
Data Sheet
41 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Description
Uin / V
I
General Purpose Input pin 11
LVCMOS
GPI10
I
General Purpose Input pin 10
LVCMOS
173
GPI9
I
General Purpose Input pin 9
LVCMOS
174
GPI8
I
General Purpose Input pin 8
LVCMOS
175
VDD
176
GPI7
I
General Purpose Input pin 7
LVCMOS
177
GPI6
I
General Purpose Input pin 6
LVCMOS
178
GPI5
I
General Purpose Input pin 5
LVCMOS
179
GPI4
I
General Purpose Input pin 4
LVCMOS
180
NC
181
VDD_E1
182
GPIO3
IO
General Purpose I/O pin 3
LVCMOS
16
183
GPIO2
IO
General Purpose I/O pin 2
LVCMOS
16
Pin
Interface
Name
I/O
171
GPI11
172
Iout / mA
+3.3 V power supply
app. +2.8 V power supply (depends
on the E1 transmit amplitude)
E1 interface
184
185
1st function
2nd function
T_ B
GPIO1
O
IO
E1 interface transmit data B
General Purpose I/O pin 1
LVCMOS
16
16
1st function
2nd function
T_ A
GPIO0
O
IO
E1 interface transmit data A
General Purpose I/O pin 0
LVCMOS
16
16
186
GND
187
ADJ_LEV
Ground
Ood
E1 interface level generator
188
1st function
2nd function
R_B
GPI3
I
I
E1 interface receive input B
General Purpose Input pin 3
E1
LVCMOS
189
1st function
2nd function
LEV_B
GPI2
I
I
E1 interface level detect B
General Purpose Input pin 2
E1
LVCMOS
190
1st function
2nd function
LEV_A
GPI1
I
I
E1 interface level detect A
General Purpose Input pin 1
E1
LVCMOS
191
1st function
2nd function
R_A
GPI0
I
I
E1 interface receive input A
General Purpose Input pin 0
E1
LVCMOS
192
GND
Ground
193
VDD
+3.3 V power supply
Universal bus interface (continued)
(continued on next page)
42 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Description
Uin / V
I
I
I
I
I
+3.3 V power supply
+3.3 V power supply
+3.3 V power supply
+3.3 V power supply
SPI device select low active
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
I
LVCMOS
I
Power Management Event Input
Ground
Ground
Ground
SPI receive data input
PME
NC
NC
NC
SPI_TX
O
Power Management Event output
4
O
SPI transmit data output
4
PCI
ISA PnP
PCMCIA
Processor
SPI
INTA#
NC
IREQ#
/INT
/INT
Ood
Interrupt request
4
Ood
Ood
Ood
Interrupt request
Interrupt request
Interrupt request
4
4
4
PCI
ISA PnP
PCMCIA
Processor
SPI
RST#
RESET
RESET
RESET
RESET
I
I
I
I
I
Reset low active
Reset high active
Reset high active
Reset high active
Reset high active
Pin
Interface
Name
194
PCI
ISA PnP
PCMCIA
Processor
SPI
VDD
VDD
VDD
VDD
/SPISEL
195
PCI
ISA PnP
PCMCIA
Processor
SPI
PME_IN
GND
GND
GND
SPI_RX
PCI
ISA PnP
PCMCIA
Processor
SPI
196
197
198
GND
199
200
I/O
PCI
ISA PnP
PCMCIA
Processor
SPI
PCICLK
GND
GND
GND
SPICLK
I
I
PCI Clock Input
Ground
Ground
Ground
SPI clock input
GND
Ground
202
VDD
+3.3 V power supply
PCI
ISA PnP
PCMCIA
Processor
AD31
SA15
A15
FL0
SPI
FL0
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
201
203
Iout / mA
IO
I
I
I
I
Address / Data bit 31
Address bit 15
Address bit 15
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
8
(continued on next page)
October 2003
Data Sheet
43 of 306
HFC-E1
Cologne
Chip
General description
(continued from previous page)
Pin
Interface
Name
I/O
Description
Uin / V
204
PCI
ISA PnP
PCMCIA
Processor
AD30
SA14
A14
FL0
IO
I
I
I
LVCMOS
LVCMOS
LVCMOS
8
SPI
FL0
Address / Data bit 30
Address bit 14
Address bit 14
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
PCI
ISA PnP
PCMCIA
Processor
AD29
SA13
A13
FL0
LVCMOS
LVCMOS
LVCMOS
8
SPI
FL0
Address / Data bit 29
Address bit 13
Address bit 13
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
PCI
ISA PnP
PCMCIA
Processor
AD28
SA12
A12
FL0
LVCMOS
LVCMOS
LVCMOS
8
SPI
FL0
Address / Data bit 28
Address bit 12
Address bit 12
Fixed level (low), connect to ground
via ext. pull-down
Fixed level (low), connect to ground
via ext. pull-down
205
206
I
IO
I
I
I
I
IO
I
I
I
I
207
GND
Ground
208
VDD
+3.3 V power supply
Legend:
Iout / mA
I
Input pin
O
Output pin
IO
Bidirectional pin
Ood
Output pin with open drain
IOpu
Bidirectional pin with internal pull-up resistor of app. 100 kΩ to VDD
NC
Not connected
FL0
Fixed level (low), must be connected to ground via external pull-down (e.g.
100 kΩ)
FL1
Fixed level (high), must be connected to power supply via external external pullup (e.g. 100 kΩ)
Unused input pins should be connected to ground. Unused I/O pins should be connected via a 100 kΩ
resistor to ground.
44 of 306
Data Sheet
October 2003
HFC-E1
G
General description
Cologne
Chip
Important !
FL0 and FL1 pins might be driven as chip output during power-on. To prevent a
short circuit these pins must either be connected via a resistor (e.g. 100 kΩ) to
ground or power supply (VDD) respectively, or they can be directly connected to
ground or power supply, if RESET is always active during power-on.
October 2003
Data Sheet
45 of 306
HFC-E1
General description
46 of 306
Data Sheet
Cologne
Chip
October 2003
Chapter 2
Universal external bus interface
(Overview tables of the HFC-E1 bus interface pins can be found at the beginning
of sections 2.2 . . 2.6.)
Table 2.1: Overview of the HFC-E1 bus interface registers
Read only registers:
Write only registers:
Address
October 2003
Name
Page
Address
Name
Page
0x00
R_CIRM
91
0x15
R_RAM_USE
95
0x01
R_CTRL
92
0x16
R_CHIP_ID
95
0x08
R_RAM_ADDR0
93
0x1C
R_STATUS
271
0x09
R_RAM_ADDR1
93
0x1F
R_CHIP_RV
96
0x0A
R_RAM_ADDR2
93
0x0C
R_RAM_MISC
94
Data Sheet
47 of 306
HFC-E1
Cologne
Chip
Universal external bus interface
The HFC-E1 has an integrated universal external bus interface which can be configured as PCI,
ISA PnP, PCMCIA, microprocessor interface and SPI. Table 2.2 shows how to select the bus mode
via the two pins MODE0 and MODE1.
Table 2.2: Access types
Bus mode
PCI
MODE1
MODE0
0
0
PCI memory mapped mode
PCI I/O mapped mode
8 bit
16 bit
32 bit
Page
52
ISA Plug and Play
1
0
59
PCMCIA
1
1
65
Processor Interface
0
1
Mode 2: Motorola
Mode 3: Intel, non-multiplexed
Mode 4: Intel, multiplexed
SPI
∗:
∗
0
1
68
88
SPI mode is selected by using processor interface mode and connecting pin 200 to SPI clock.
The external bus interface supports 8 bit, 16 bit and 32 bit accesses. The access types available depend
on the selected bus mode like shown in Table 2.2.
Sections 2.2 to 2.6 explain how to use the HFC-E1 in the different bus modes.
48 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
2.1 Common features of all interface modes
Table 2.3: Overview of common bus interface pins ∗
Number
∗:
2.1.1
Name
Description
99
MODE0
Interface Mode pin 0
100
MODE1
Interface Mode pin 1
102
EE_SCL/EN
EEPROM clock / EEPROM enable
103
EE_SDA
EEPROM data I/O
See sections 2.2 to 2.6 for overview tables of the interface specific pins.
EEPROM programming
The ISA PnP and PCMCIA interfaces require an external EEPROM. For the PCI and the processor
interface mode, this EEPROM is optional. The EEPROM is highly recommended in PCI mode. The
EEPROM programming specification is only available on special request from Cologne Chip to avoid
destruction of configuration information by unauthorized programs or software viruses.
PCI mode: 128 bytes of the EEPROM are copied into the PCI configuration space after every hardware reset.
ISA PnP mode: EPPROM data is directly accessible by the ISA PnP interface. A maximum of 512
bytes are used to store the configuration.
PCMCIA mode: 512 bytes of the EEPROM are copied into the SRAM after every hardware reset.
It is used as PCMCIA attribute memory. Table 2.4 show the SRAM start addresses for different
RAM sizes.
Processor mode: The EEPROM is not used in the processor mode and the pins EE_SCL/EN and
EE_SDA must be deactivated as shown in Figure 2.2.
SPI mode: The EEPROM is not used in the SPI mode and the pins EE_SCL/EN and EE_SDA must
be deactivated as shown in Figure 2.2.
Table 2.4: SRAM start address
Start address
SRAM size
October 2003
in SRAM
32k x 8
0x1A00
128k x 8
0x2A00
512k x 8
0x2A00
Data Sheet
49 of 306
HFC-E1
2.1.2
Cologne
Chip
Universal external bus interface
EEPROM circuitry
Figure 2.1 shows the connection of an EEPROM (e.g. 24C04 type) to the HFC-E1 pins EE_SCL/EN
and EE_SDA.
+3.3V
k01
EE_SLC/EN
EE_SDA
R2
k01
R1
U1
U2
8
6
5
102
103
VCC
SCL
SDA
TEST
A0
A1
A2
7
1
2
3
EEPROM 24C04
HFC-E1
GND
Figure 2.1: EEPROM connection circuitry
If no EEPROM is used, pin EE_SCL/EN must be connected to ground while EE_SDA must remain
open as shown in Figure 2.2.
U1
EE_SLC/EN
EE_SDA
102
103
nc
GND
HFC-E1
Figure 2.2: EE_SCL/EN and EE_SDA connection without EEPROM
2.1.3
Register access
In PCI I/O mapped mode, ISA PnP, PCMCIA mode and SPI mode all registers are selected by writing
the register address into the Control Internal Pointer (CIP) register. This is done by writing the CIP
on the higher I/O addresses (AD2, SA2, A2, A/D¯ = 1). The CIP register can also be read with AD2,
¯ = 1.
SA2, A2, A/D
All consecutive read or write data accesses (AD2, SA2, A2, A/D¯ = 0) are done with the selected
register until the CIP register is changed.
In processor interface mode all internal registers can be directly accessed. The registers are selected
by A0 . . A7.
In PCI mode internal A0 and A1 are generated from the byte enable lines.
2.1.4
RAM access
The SRAM of the HFC-E1 can be accessed by the host. To do so, the desired RAM address has to
be written in the R_RAM_ADDR0 . . R_RAM_ADDR2 registers first. Then data can be read / written
50 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
by reading / writing the register R_RAM_DATA. An automatic increment function can be set in the
register R_RAM_ADDR2.
October 2003
Data Sheet
51 of 306
HFC-E1
2.2
Universal external bus interface
Cologne
Chip
PCI interface
Table 2.5: Overview of the PCI interface pins
Number
Name
Description
203 . . 206, 1 . . 4
AD31 . . AD24
Address / Data byte 3
8 . . 17
AD23 . . AD16
Address / Data byte 2
31 . . 39
AD15 . . AD8
Address / Data byte 1
43 . . 51
AD7 . . AD0
Address / Data byte 0
C/BE3# . . C/BE0#
Bus command and Byte Enable 3 . . 0
6, 18, 30, 40
IDSEL
Initialisation Device Select
20
FRAME#
Cycle Frame
21
IRDY#
Initiator Ready
22
TRDY#
Target Ready
23
DEVSEL#
Device Select
24
STOP#
Stop
25
PERR#
Parity Error
26
SERR#
System Error
27
7
PAR
Parity Bit
195
PME_IN
Power Management Event Input
196
PME
Power Management Event output
197
INTA#
Interrupt request
198
RST#
Reset low active
200
PCICLK
PCI Clock Input
The PCI mode is selected by MODE0 = 0 and MODE1 = 0. Only PCI target mode accesses are
supported by the HFC-E1.
5 V PCI bus signaling environment is supported with 3.3 V supply voltage of the HFC-E1. Never
connect the power supply of the HFC-E1 to 5 V!
The PCI interface is build according to the PCI Specification 2.2.
2.2.1
PCI command types
Table 2.6 shows the supported PCI commands of the HFC-E1.
Memory Read Line and Memory Read Multiple commands are aliased to Memory Read. Memory
Write and Invalidate is aliased to Memory Write.
52 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Universal external bus interface
Byte
3
2
1
0
Hex Address
Device ID
Vendor ID
00h
Status Register
Command Register
04h
Class Code
Header
Type
BIST
Latency
Timer
Revision
ID
08h
Cache Line
Size
0Ch
I/O Base Address
10h
Memory Base Address
14h
Base Address 2
18h
Base Address 3
1Ch
Base Address 4
20h
Base Address 5
24h
CardBus CIS Pointer
28h
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
30h
Cap_Ptr
Reserved
Reserved
Max_Lat
Min_Gnt
PMC
Data
PMCSR
BSE
2Ch
34h
38h
Interrupt
Pin
Interrupt
Line
3Ch
Next Item
Ptr
Cap_ID
40h
PMCSR
44h
Register is implemented, value can be set by EEPROM
Register is implemented
Register is not implemented and returns all 0's when read
Figure 2.3: PCI configuration registers
October 2003
Data Sheet
53 of 306
HFC-E1
Cologne
Chip
Universal external bus interface
Table 2.6: PCI command types
C/BE3#
C/BE2#
C/BE1#
C/BE0#
nibble value
0
0
1
0
2
I/O Read
0
1
1
0
6
Memory Read
1
1
0
0
0xC
Memory Read Multiple
1
1
1
0
0xE
Memory Read Line
1
0
1
0
0xA
Configuration Read
0
0
1
1
3
I/O Write
0
1
1
1
7
Memory Write
1
1
1
1
0xF
Memory Write and Invalidate
1
0
1
1
0xB
Configuration Write
I/O-Address
Command type
Byte 3
Byte 2
Byte 1
Byte 0
DATA 3
DATA 2
DATA 1
DATA 0
Byte 7
Byte 6
Byte 5
Byte 4
Register
Select
Register
Select
I/O-Address+4
(PCI bridge only)
}
}
Data
CIP
Figure 2.4: PCI access in PCI I/O mapped mode
memory
address
Byte 3
Byte 2
Byte 1
Byte 0
DATA 3
DATA 2
DATA 1
DATA 0
Figure 2.5: PCI access in PCI memory mapped mode
2.2.2
PCI access description
The HFC-E1 uses only PCI target accesses. A PCI master function is not implemented.
Two modes exist for register access:
1. If HFC-E1 is used in PCI memory mapped mode all registers can directly be accessed by adding
their CIP address to the configured Memory Base Address.
2. In PCI I/O mapped mode HFC-E1 only occupies 8 bytes in the I/O address space.
In PCI I/O mapped mode all registers are selected by writing the register address into the Control
Internal Pointer (CIP) register. This is done by writing the HFC-E1 on the higher I/O addresses (AD2
= 1). If the auxiliary interface is used (see Chapter 11) the CIP write access must have a width of
16 bit.
All consecutive read or write data accesses (AD2 = 0) use the selected register until the CIP register
is changed.
54 of 306
Data Sheet
October 2003
HFC-E1
2.2.3
Universal external bus interface
Cologne
Chip
PCI configuration registers
The PCI configuration space is defined by the configuration register set which is illustrated in Figure 2.3. In the configuration address space 0x00 . . 0x47 the PCI configuration register values are
either
• set by the HFC-E1 default settings of the configuration values or
• they can be written to upper configuration register addresses or
• they are read from the external EEPROM.
The external EEPROM is optional. If no EEPROM is available, the pin EE_SCL/EN has to be connected to GND and the pin EE_SDA has to be left open. Without EEPROM the PCI configuration
registers will be loaded with the default values shown in Table 2.7.
All configuration registers which can be set by the EEPROM can also be written by configuration
write accesses to the upper addresses of the configuration register space (from 0xC0 upwards). The
addresses for configuration writes are shown in Table 2.7. Unimplemented registers return all ’0’s
when read.
Table 2.7: PCI configuration registers
Register Name
Address
Width
Default Value
Vendor ID
0x00
Word
0x1397
Value can be set by EEPROM. Base address for
configuration write is 0xC0.
Device ID
0x02
Word
0x30B1
Value can be set by EEPROM. Base address for
configuration write is 0xC0.
Command
0x04
Word
0x0000
Bits
Function
0
1
5..2
6
7
8
15..9
Enables / disables I/O space accesses
Enables / disables memory space accesses
fixed to 0
PERR# enable / disable
fixed to ’0’
SERR# enable / disable
fixed to 0
Register
Status Register
0x06
Word
0x0210
Remarks
Bits 0 . . 7 can be set by EEPROM. Base address for
configuration write is 0xC4.
Bits
3..0
4
5
6
7
8
10..9
13..11
14
15
Function
reserved
’1’ = Capabilities List exists, fixed to ’1’
’0’ = 33 MHz capable (default)
’1’ = 66 MHz capable
reserved
’0’ = fast Back-to-Back not capable (default)
’1’ = fast Back-to-Back capable
fixed to ’0’
fixed to ’01’: timing of DEVSEL# is medium
fixed to ’000’
system error (address parity error)
any detected data or system parity error
(continued on next page)
October 2003
Data Sheet
55 of 306
HFC-E1
Cologne
Chip
Universal external bus interface
Table 2.7: PCI configuration registers
(continued from previous page)
Register Name
Address
Width
Default Value
Remarks
Revision ID
0x08
Byte
0x01
Class Code
0x09
3 Bytes
0x020400
Header Type
0x0E
Byte
0x00
Header type 0
BIST
0x0F
Byte
0x00
No build in self test supported.
I/O Base
0x10
DWord
HFC-E1 Revision 01
Class code for ‘ISDN controller’.Value can be set
by EEPROM. Base address for configuration write
is 0xC8.
Bits 2 . . 0 are fixed to ’001’
Address
Bits 31 . . 3 are r/w by configuration accesses.
8 Byte address space is used.
Memory Base
0x14
Bits 11 . . 0 are all ’0’
DWord
Address
Bits 31 . . 12 are r/w by configuration accesses.
4 kByte address space is used.
0x2C
Word
0x1397
Value can be set by EEPROM. Base address for
configuration write is 0xEC.
Subsystem ID
0x2E
Word
0x30B1
Value can be set by EEPROM. Base address for
configuration write is 0xEC.
Cap_Ptr
0x34
Byte
0x40
Offset to Power Management register block.
Interrupt Line
0x3C
Byte
0xFF
This register must be configured by configuration
write.
Interrupt Pin
0x3D
Byte
0x01
INTA# supported
Cap_ID
0x40
Byte
0x01
Capability ID. 0x01 identifies the linked list item as
PCI Power Management registers.
Next Item Ptr
0x41
Byte
0x00
There are no next items in the linked list.
Subsystem
Vendor ID
(continued on next page)
56 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
Table 2.7: PCI configuration registers
(continued from previous page)
Register Name
PMC
∗1
PMCSR
Address
Width
Default Value
0x42
Word
0x7E22
0x44
Word
0x0000
Remarks
Power Management Capabilities, see also ‘PCI Bus
Power Management Interface Specification Rev.
1.1’.This register’s value can be set by EEPROM.
Base address for configuration write is 0xE0.
Bits
Function
0..2
’010’ = PCI Power Management Spec.
sion 1.1.
3
’0’ = The HFC-E1 does not require PCI-clock to
generate PME.
4
Fixed to ’0’.
5
’1’ = Device specific initialisation is required.
8..6
’000’ = No report of auxiliary count.
9
’1’ = Supports D1 Power Management State ∗2 .
10
’1’ = Supports D2 Power Management State ∗2 .
15..11
PME can be asserted from D0, D1, D2 and
D3_hot. No D3_cold support ∗1 .
Ver-
Power Management Control/Status
Bits
Function
1..0
PowerState: These bits are used both to determine the current power state of a function and to
set the function into a new power state ∗2 .
’00’: D0
’01’: D1
’10’: D2
’11’: D3_hot
7..2
8
fixed to ’0’
PME_En:
’1’ enables the function to assert PME.
’0’ = PME assertion is disabled.
14..9
fixed to 0
15
PME_Status: This bit is set when the function
would normally assert the PME signal independent of the state of the PME_En bit.
Writing a ’1’ to this bit will clear it and cause the
function to stop asserting a PME (if enabled).
Writing a ’0’ has no effect.
∗1 :
D3_cold support is implemented but must be set in the EEPROM configuration data.
∗2 :
Changing the power management does not change the power dissipation. It is only implemented for PCI
specification compatibility.
October 2003
Data Sheet
57 of 306
HFC-E1
2.2.4
Cologne
Chip
Universal external bus interface
PCI connection circuitry
PCI
list of power-pins:
POWER
+5V:
A5, A8, A61, A62
B5, B6, B61, B62
+3.3V: A21, A27, A33, A39,
A45, A53, B25, B31,
B36, B51, B43, B54
Vi/o: A59, A66, A75, A84,
B19, B59, B70,B79,
B88
GND:
A18, A24; a30, A35,
A37, A42, A48, A56,
A63, A69, A72, A78,
A81, A87, A90, A93,
B3, B15, B22, B28,
B34, B38, B46, B57,
B64, B67, B73, B76,
B82, B85, B91, B94
PCI
INTERRUPT
+12V
-12V
+5V
+3.3V
3.3Vaux
VI/O
A14
nc
nc
GND
PME#
+3.3V
If D3_cold is supported
the Chip must be
supplied from 3.3Vaux.
Only needed if
Power-Management Event
(PME) is supported.
INTD#
INTC#
INTB#
INTA#
PAR
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
AWAKE
A19
Q1
B8
A7
B7
A6
B11
B9
A1
A3
B2
A4
B4
A60
A67
B60
A15
B16
A17
B18
B42
B40
B39
A26
B37
A38
B35
A36
A34
B49
A43
GND
U1
R1
10k
BC848C
C/BE3#
C/BE2#
C/BE1#
C/BE0#
following pins are
not connected:
C/BE4# - C/BE7#
AD32 - AD63
nc
nc
nc
GND
PRSNT2#
PCI PRSNT1#
TRST#
CONTROL
TMS
TCK
TDI
TDO
REQ64
PAR64
ACK64
RST#
CLK
GNT#
REQ#
SERR#
PERR#
LOCK#
IDSEL
DEVSEL#
STOP#
IRDY#
TRDY#
FRAME#
M66EN
PCI
ADDRESS
A2
B1
GND
196
195
10k
R2
nc
nc
nc
194
PME_IN
VDD
+3.3V
197
99
100
nc
nc
nc
nc
nc
nc
nc
nc
PME
GND
nc
nc
nc
GND
INTA#
MODE0
MODE1
GND
198
200
26
25
7
23
24
21
22
20
27
B26
B33
B44
A52
6
18
30
40
B20
A20
B21
A22
B23
A23
B24
A25
B27
A28
B29
A29
B30
A31
B32
A32
A44
B45
A46
B47
A47
B48
A49
B52
B53
A54
B55
A55
B56
A57
B58
A58
203
204
205
206
1
2
3
4
8
9
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
RST#
PCICLK
SERR#
PERR#
IDSEL
DEVSEL#
STOP#
IRDY#
TRDY#
FRAME#
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
HFC- E1
PCI slot
Figure 2.6: PCI connection circuitry
58 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
2.3 ISA Plug and Play interface
Table 2.8: Overview of the ISA PnP interface pins
Number
Name
Description
SA15 . . SA8
Address byte 1
SA7 . . SA0
Address byte 0
31 . . 39
SD15 . . SD8
Data byte 1
43 . . 51
SD7 . . SD0
Data byte 0
IRQ6 . . IRQ0
ISA Interrupt Request 6 . . 0
203 . . 206,1 . . 4
8 . . 17
106 . . 112
18
/IOIS16
16 bit access enable
20
/AEN
Address Enable
21
/IOR
Read Enable
22
/IOW
Write Enable
25
/BUSDIR
Bus Direction
30
/SBHE
High byte enable
198
RESET
Reset high active
ISA Plug and Play mode is selected by MODE0 = 0 and MODE1 = 1. The HFC-E1 needs eight
consecutive addresses in the I/O map of a PC for operation. Usually one of several ISA IRQ lines is
also used. Section 2.3.1 describes how to configure the interrupt lines of the HFC-E1.
The port address is selected by the lines SA0 . . SA15. The address with SA2 = ’1’ is used for register selection via the CIP (Control Internal Pointer) and the address with SA2 = ’0’ is used for data
read / write like shown in Table 2.9. The bits SA3 . . SA15 are decoded by the address decoder to
match the PnP configuration address.
Table 2.9: ISA address decoding (X = don’t care)
Operation
SA2
/IOR
/IOW
/AEN
X
X
X
1
no access
X
1
1
X
no access
0
0
1
0
read data
0
1
0
0
write data
1
0
1
0
read CIP
1
1
0
0
write CIP
The HFC-E1 has no memory or DMA access to any component on the ISA PC bus. Because of its
characteristic power drive, no external driver for the ISA PC bus data lines is needed. If necessary
(e.g. due to an old ISA specification which requires 24 mA output current), an external bus driver can
be added. In this case the output signal /BUSDIR determines the driver direction.
October 2003
Data Sheet
59 of 306
HFC-E1
Cologne
Chip
Universal external bus interface
/BUSDIR = 0 means that the HFC-E1 is read and data is driven to the external bus.
/BUSDIR = 1 means that data is driven (written) into the HFC-E1.
2.3.1
IRQ assignment
Seven different interrupt lines IRQ6 . . IRQ0 are supported by the HFC-E1. They are tristated after a
hardware reset.
The IRQ assigned by the PnP BIOS can be read from the bitmap V_PNP_IRQ of the register
R_CHIP_ID. The bitmap V_IRQ_SEL of the register R_CIRM has to be set according to the IRQ
wiring between HFC-E1 and the ISA slot on the PCB. Thus the IRQ number assigned by the PnP
BIOS is connected to the right IRQ line on the ISA bus.
2.3.2
ISA Plug and Play registers
Table 2.10: ISA Plug and Play registers
Card level
control register
address
Read / write
Mode
Accessable
in state
0x00
w
Isolation state,
Config state ∗1
Set read data port address register.
Bits 0 . . 7 become bits 2 . . 9 of the port’s I/O address. Bits
10 and 11 are hardwired to ’00’ and bits 0 and 1 are hardwired to ’11’.
0x01
r
Isolation state
Serial isolation register.
Used to read the serial identifier during the card isolation
process.
0x02
w
Sleep state,
Isolation state,
Config state
Configuration control register.
Bits Function
Description
0
1
2
7..3
Reset Bit. The value ’1’ resets all of the card’s configuration
registers to their default state. The CSN is not affected.
Return to wait for key state. When set to ’1’, all cards
return to wait for key state. Their CSNs and configuration
registers are not affected. This command is issued after all
cards have been configured and activated.
Reset CSN to ’0’. When set to ’1’, all cards reset their CSN
to ’0’. All bits are automatically cleared by the hardware.
Reserved, must be ’00000’
(continued on next page)
60 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
Table 2.10: ISA Plug and Play registers
(continued from previous page)
Card level
control register
address
Read / write
Mode
Accessable
in state
0x03
w
Sleep state,
Isolation state,
Config state
Description
Wake command register.
Writing a CSN to this register has the following effects:
• If the value written is 0x00, all cards in the sleep
state with a CSN = 0x00 go to the isolation state.
All cards in Config state (CSN not 0x00) go to the
sleep state.
• If the value written is not 0x00, all cards in the
sleep state with a matching CSN go to the Config state. All cards in the isolation state go to the
sleep state.
Every write access to a card’s wake command register
with a match on its CSN causes the pointer to the serial
identifier / resource data to be reset to the first byte of the
serial identifier.
0x04
r
Config state
Resource data register.
This register is used to read the device’s recource data.
Each time when a read is performed from this register
a byte of the resource data is returned and the resource
data pointer is incremented. Prior to reading each byte,
the programmer must read from the status register to determine if the next byte is available for reading from the
resource data register.
The card’s serial identifier and checksum must be read
prior to accessing the resource requirement list via this
register.
0x05
r
Config state
Status register.
Prior to reading the next byte of the device’s resource data,
the programmer must read from this register and check bit
0 for a ’1’. This is the resource data byte available bit. Bits
1 . . 7 are reserved.
0x06
r/w
Isolation state
Config state
0x07
r
Config state
∗2
Card select number (CSN) register.
The configuration software uses the CSN register to assign a unique ID to the card. The CSN is then used to
wake up the card’s configuration logic whenever the configuration program must access its configuration registers.
Logical device number register.
The number in this register points to the logical device
the next commands will operate on. The HFC-E1 only
supports one logical device. This register is hardwired to
all ’0’’s.
(continued on next page)
October 2003
Data Sheet
61 of 306
HFC-E1
Cologne
Chip
Universal external bus interface
Table 2.10: ISA Plug and Play registers
(continued from previous page)
Card level
control register
address
Read / write
Mode
Accessable
in state
0x30
r/w
Config state
Activate register.
Setting bit 0 to ’1’ activates the card on the ISA bus. When
cleared, the card cannot respond to any ISA bus transactions (other than accesses to its Plug and Play configuration ports). Reset clears bit 0. Bits 1 . . 7 are reserved
and return 0 when read. The HFC-E1 only supports one
logical device, so it is not necessary to write the logical
device number into the card’s logical device number register prior to writing to this register.
0x31
r/w
Config state
I/O range check register.
Bits Function
Description
0
When set, the logical device returns 0x55 in response to any
read from the logical device’s assigned I/O space. When
cleared, 0xAA is returned.
1
When set to ’1’, enables I/O range checking and disables it
when cleared to ’0’. When enabled, bit 0 is used to select a
pattern for the logical device to return. This bit is only valid
if the logical device is deactivated (see Activate register).
7..2
Reserved, return ’000000’ when read
0x60
r/w
Config state
I/O decoder 0 base address upper byte.
I/O port base address bits 8 . . 15.
0x61
r/w
Config state
I/O decoder 0 base address lower byte.
I/O port base address bits 0 . . 7.
0x70
r/w
Config state
IRQ select configuration register 0.
Bits 0 . . 3 specify the selected IRQ number. Bits 4 . . 7 are
reserved.
0x71
r/w
Config state
IRQ type configuration register 0.
Bits 0 and 1 are ignored. Bits 2 . . 7 are reserved.
0x74
r
Config state
DMA configuration register 0.
Bits Function
2..0
Select which DMA channel (0 . . 7) is used for DMA 0.
DMA channel 4, the cascade channel, indicates no DMA
channel is active.
7..3
Reserved.
Because no DMA is used this register is hardwired to
0x04.
(continued on next page)
62 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Universal external bus interface
Table 2.10: ISA Plug and Play registers
(continued from previous page)
Card level
control register
address
Read / write
Mode
Accessable
in state
0x75
r
Config state
Description
DMA configuration register 1.
Bits Function
2..0
Select which DMA channel (0 . . 7) is used for DMA 1.
DMA channel 4, the cascade channel, indicates no DMA
channel is active.
7..3
Reserved.
Because no DMA is used this register is hardwired to
0x04.
∗1 :
This is an extension to the Plug and Play Specification.
∗2 :
Only when the isolation process is finished. The last card remains in isolation state until a CSN is assigned.
G
Important !
All ISA registers which are not implemented return 0x00 with a read access except the DMA configuration registers at address 0x74 and 0x75. These two registers return 0x04 with a read access. This means no DMA channel has been
selected.
October 2003
Data Sheet
63 of 306
HFC-E1
2.3.3
Cologne
Chip
Universal external bus interface
ISA connection circuitry
+3.3V
U2
POWER
B5
B9
B7
nc
nc
nc
IN
OUT
C1
470n
C2
LM3940
+
100u
C3
C4
+
100n
100u
2
list of power-pins:
+5V: B3, B29, D16
GND: B1, B10, B31,
D18
3
GND
+5V
-5V
+12V
-12V
ISA PnP
1
GND
ISA PnP
CONTROL
following pins are
not connected:
LA17 - LA23
DRQ0 - DRQ3
DRQ5 - DRQ7
-DACK0 - -DACK3
-DACK5 - -DACK7
-MASTER
-Refresh
BALE
T/C
OWS
OSC
CLK
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
RESET DRV
-I/O CH RDY
-I/O CH CK
-SMEMR
-SMEMW
-MEMR
-MEMW
-IOR
-IOW
AEN
U1
GND
D17
B19
B28
B27
B8
B30
B20
+3.3V
196
194
195
GND
nc
B25
B24
B23
B22
B21
B4
D3
D4
D5
D7
D6
+3.3V
R1
10k
198
200
GND
nc
nc
nc
nc
nc
nc
nc
nc
GND
197
99
100
106
107
108
109
110
111
112
GND
B2
A10
A1
B12
B11
C9
C10
B14
B13
A11
nc
R*
100k
100k
R*
26
25
7
23
24
21
22
20
NC
VDD
GND
NC
MODE0
MODE1
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
RESET
GND
NC
/BUSDIR
GND
FL0
FL0
/IOR
/IOW
/AEN
R* can be omitted if reset
is active during power on.
ISA PnP
ADDRESS / DATA
-MEM CS16
-I/O CS16
SBHE
D1
D2
C1
nc
GND
27
100k
R*
+3.3V
6
18
30
40
GND
following pins are
not connected:
SA16 - SA19
SA15
SA14
SA13
SA12
SA11
SA10
SA09
SA08
SA07
SA06
SA05
SA04
SA03
SA02
SA01
SA00
SD15
SD14
SD13
SD12
SD11
SD10
SD09
SD08
SD07
SD06
SD05
SD04
SD03
SD02
SD01
SD00
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
C18
C17
C16
C15
C14
C13
C12
C11
A2
A3
A4
A5
A6
A7
A8
A9
203
204
205
206
1
2
3
4
8
9
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
ISA PnP slot
FL0
VDD
/IOIS16
/SBHE
GND
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
HFC- E1
(ISA PnP interface)
Figure 2.7: ISA PnP circuitry (see Section 2.3.1 on page 60 for IRQ line assignment)
64 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
2.4 PCMCIA interface
Table 2.11: Overview of the PCMCIA interface pins
Number
Name
Description
A15 . . A8
Address byte 1
A7 . . A0
Address byte 0
31 . . 39
D15 . . D8
Data byte 1
43 . . 51
D7 . . D0
Data byte 0
203 . . 206, 1 . . 4
8 . . 17
REG#
PCMCIA Register and Attr. Mem. Select
18
IOIS16#
16 bit access enable
21
IORD#
Read Enable
22
IOWR#
Write Enable
7
23
OE#
PCMCIA Output Enable for Attr. Mem. Read
24
WE#
PCMCIA Write Enable for Conf. Reg. Write
25
INPACK#
Read access
30
CE2#
High byte enable
40
CE1#
Low byte enable
197
IREQ#
Interrupt request
198
RESET
Reset high active
The PCMCIA mode is selected by MODE0 = 1 and MODE1 = 1. The HFC-E1 occupies eight consecutive addresses in the I/O map.
The base I/O address must be 8 byte aligned. The lines A3 . . A15 are don’t care for I/O accesses.
The address with A2 = 1 is used for register selection via CIP. The address with A2 = 0 is used for
data read / write.
2.4.1
Attribute memory
After a hardware reset the card’s information structure (CIS) is copied from the EEPROM to the
SRAM, starting with the address shown in Table 2.4. The CIS is located on even numbered addresses
from 0 to 0x3FE in the attribute memory space. The CIS occupies 512 byte. To avoid accesses in this
copy phase the signal IREQ# of the HFC-E1 is active. This is interpreted as ‘wait’ by the PCMCIA
host controller after card insertion.
October 2003
Data Sheet
65 of 306
HFC-E1
2.4.2
Cologne
Chip
Universal external bus interface
PCMCIA registers
Table 2.12: PCMCIA registers
Register Name
Configuration Option
Register (COR)
Card Configuration and
Status Register (CSR)
Address
0x400
0x402
∗:
66 of 306
∗
Width
Remarks
Byte
Reset
value
Bit
Name
5..0
Configuration 0x00
Index
6
LevIREQ
7
SRESET
Byte
1
Function
Bit 0 must be set to ’1’
to enable accesses to the
HFC-E1.
This bit is not implemented
and returns always ’1’ when
read to indicate usage of
level mode interrupts.
SRESET card. Setting this
bit to ’1’ places the card in
the reset state. This bit must
be cleared to zero for normal operation.
Reset
Bit
Name
value
0
1
Rsvd
Intr
0
0
2
PwrDwn
0
3
Audio
0
4
Rsvd
0
5
IOis8
0
6
SigChg
0
7
Changed
0
Function
Internal state of interrupt request (IREQ#).
Unimplemented, returns ’0’
when read.
Unimplemented, returns ’0’
when read.
Unimplemented, returns ’0’
when read.
Returns ’0’ when read to indicate
an 16 bit data path.
Unimplemented, returns ’0’
when read.
Unimplemented, returns ’0’
when read.
Register address in attribute memory
Data Sheet
October 2003
HFC-E1
2.4.3
Cologne
Chip
Universal external bus interface
PCMCIA connection circuitry
+3.3V
U2
VS1#/REFRESH
VS2#/RSVD
VPP1
VPP2
list of power-pins:
VCC: 17, 51
GND: 1, 34, 35, 68
43
57
18
52
nc
nc
nc
nc
1
IN
OUT
3
GND
POWER
5V
C1
470n
C2
LM3940
100u
C3
+
not nesassary if
PCMCIA interface is
100n a 3.3V only interface
C4
+
100u
2
PCMCIA
VCC
GND
U1
GND
nc
+3.3V
GND
PCMCIA
196
195
194
NC
GND
VDD
CONTROL
IREQ#
16
197
IREQ#
+3.3V
+3.3V
R1
CD1#
CD2#
RESET
36
67
58
R2
99
100
10k
nc
nc
10k
SPKR#
STSCHG#
62
63
recommended by
PCMCIA spec.
R3
10k
GND
REG#
OE#
WE#
IORD#
IOWR#
59
60
GND
nc
ADDRESS / DATA
IOIS16#
CE2#
CE1#
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
following pins are
not connected:
A16 - A25
GND
nc
61
9
15
44
45
26
25
7
23
24
21
22
20
R* can be omitted
if resetis active
during power on.
PCMCIA
198
200
C5
1n
WAIT#
INPACK#
MODE0
MODE1
RESET
GND
NC
INPACK#
REG#
OE#
WE#
IORD#
IOWR#
GND
R*
100k
+3.3V
GND
27
33
42
7
6
18
30
40
20
14
13
21
10
8
11
12
22
23
24
25
26
27
28
29
41
40
39
38
37
66
65
64
6
5
4
3
2
32
31
30
203
204
205
206
1
2
3
4
8
9
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
PCMCIA slot
FL0
VDD
IOIS16#
CE2#
CE1#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HFC- E1
(PCMCIA interface)
Figure 2.8: PCMCIA circuitry
October 2003
Data Sheet
67 of 306
HFC-E1
2.5
Universal external bus interface
Cologne
Chip
Parallel processor interface
Table 2.13: Overview of the parallel processor interface pins in mode 2 and 3
Number
Name
Description
8 . . 17
A7 . . A0
Address byte
43 . . 51
D7 . . D0
Data byte 0
31 . . 39
D15 . . D8
Data byte 1
/BE3 . . /BE0
Byte Enable 3 . . 0
20
/CS
Chip Select
21
/IOR
Read Enable
22
/IOW
Write Enable
23
/WD
Watch Dog Output
24
ALE
Address Latch Enable
25
6, 18, 30, 40
/BUSDIR
Bus Direction
197
/INT
Interrupt request
198
RESET
Reset high active
Table 2.14: Overview of the processor interface pins in mode 4
Number
43 . . 51
Description
AD7 . . AD0
Address / Data byte 0
31 . . 39
AD15 . . AD8
Address / Data byte 1
8 . . 17
AD23 . . AD16
Address / Data byte 2
203 . . 206, 1 . . 4
AD31 . . AD24
Address / Data byte 3
/BE3 . . /BE0
Byte Enable 3 . . 0
20
/CS
Chip Select
21
/IOR
Read Enable
22
/IOW
Write Enable
23
/WD
Watch Dog Output
24
ALE
Address Latch Enable
25
/BUSDIR
Bus Direction
6, 18, 30, 40
68 of 306
Name
197
/INT
Interrupt request
198
RESET
Reset high active
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Universal external bus interface
The processor interface mode is selected by MODE0 = 1 and MODE1 = 0. Then 256 I/O addresses
(A0 . . A7) are used for addressing the internal registers of the HFC-E1 directly by their address.
In processor interface mode some user data can be stored in the EEPROM (see Section 2.1.1 for
details).
2.5.1
Parallel processor interface modes
The HFC-E1 has 3 different parallel processor interface modes. Due to name compatibility with other
chips of the HFC series the processor interface modes are numbered 2 . . 4 like shown in Table 2.15.
Table 2.15: Pins and signal names of the HFC-E1 processor interface modes
HFC-E1 pins
Number
Name
Signal names
Mode 2
Mode 3
Mode 4
(Motorola)
(Intel)
(Intel)
Non-multiplexed
Non-multiplexed
Multiplexed
20
/CS
/CS
/CS
/CS
21
/IOR
/DS
/RD
/RD
22
/IOW
R/W
/WR
/WR
24
ALE
’1’
’0’
ALE
Processor interface modes 2 and 3 use separate lines for address and data. These two modes are
selected by ALE. This pin must have a fixed level and should be directly connected to ground or
power supply. Mode 4 has multiplexed address / data lines. The address is latched from lines D7 . . D0
with the falling edge of ALE.
The processor interface mode is determined during hardware reset time (pin RESET). For modes 2
and 3 the ALE pin must have the appropriate level. Mode 4 is selected after reset with the first rising
edge of ALE. The HFC-E1 then switches permanently from mode 2 or mode 3 into mode 4. The
HFC-E1 cannot switch to mode 4 before end of reset time. Rising and falling edges of ALE are
ignored during reset time.
ALE must be stable after reset except in processor interface mode 4.
2.5.2
Signal and timing characteristics
Table 2.16 shows the interface signals for the different processor interface modes. Timing characteristics are shown in Figures 2.9 to 2.12 for mode 2 and mode 3. Figures 2.13 to 2.18 show mode 4
timing characteristics. Please see Table 2.17 for a quick timing and symbol list finding.
In processor interface mode 4 it is possible to access byte, word or double word on the lines
AD31 . . AD0. Due to the multiplexed lines the PCI pin names are used in this case. In processor
interface mode 2 and mode 3 the pins AD31 . . AD24 are not available.
Unused byte enable pins should be connected to power supply via pull-up resistors. In mode 4 unused
bus lines AD[31..] should be connected to ground via pull-down resistors to avoid floating inputs.
October 2003
Data Sheet
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Universal external bus interface
Table 2.16: Overview of read and write accesses in processor interface mode (X = don’t care)
/CS
Operation
/IOW
(/DS, /RD)
(R/W, /WR)
1
X
X
X
no access
all
X
1
1
X
no access
all
0
0
1
1
read data
mode 2
0
0
0
1
write data
mode 2
0
0
1
0
read data
mode 3
0
1
0
0
write data
mode 3
0
0
1
0
1
ALE
Processor
/IOR
0
∗:
interface mode
0
∗
read data
mode 4
0
∗
write data
mode 4
1-pulse latches register address
Table 2.17: Timing diagrams of the parallel processor interface
Mode
Processor
Access type
Timing
Figure
Timing values
on page
table
on page
2&3
8 bit
8 bit
read
2.9
71
2.19
75
2&3
8 bit
8 bit
write
2.10
73
2.20
77
2&3
16 bit
16 bit & 8 bit
read
2.11
74
2.19
75
2&3
16 bit
16 bit & 8 bit
write
2.12
76
2.20
77
4
8 bit
8 bit
read
2.13
78
2.22
83
4
8 bit
8 bit
write
2.14
79
2.23
85
4
16 bit
16 bit
read
2.15
80
2.22
83
4
16 bit
16 bit
write
2.16
81
2.23
85
4
32 bit
32 bit
read
2.17
82
2.22
83
4
32 bit
32 bit
write
2.18
84
2.23
85
G
Important !
/BE2 and /BE3 must always be ’1’ in mode 2 and mode 3.
70 of 306
Data Sheet
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Universal external bus interface
2.5.2.1 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
byte read access
A[7:0]
byte read access
address
address
/BE[3:1]
permanently high
/BE0
permanently low
permanently tristate
D[15:8]
D[7:0]
data
t DRDZ
data
t DRDH
t DRDZ
t RDmin
t DRDH
t RDmin
t AS
t AH
t AS
t AH
t CYCLE
t RD
in mode2 only
(Motorola:)
t RD
/DS+/CS
t RWS
t RWH
t RWS
t RWH
R/W
in mode 3 only
(Intel):
/RD+/CS
/WR
permanently high
Figure 2.9: Read access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
8 bit processors read data like shown in Figure 2.9. Timing values are listed in Table 2.19.
/BE3 . . /BE1 must always be ’1’. /BE0 can be fixed to ’0’ or must be low during access to switch the
data bus D7 . . D0 from tristate into data driven state.
Data can be read in mode 2 (Motorola) with 1
/BE0 = ’0’
and
(/DS + /CS) = ’0’
and
R/W = ’1’ .
In mode 3 (Intel, non-multiplexed) the states
/BE0 = ’0’
and
(/RD + /CS) = ’0’
and
/WR = ’1’
must be fulfilled to drive data out. The data bus is stable after tRDmin and returns into tristate after
tDRDH .
1 /DS + /CS
means logical OR function of the two signals.
October 2003
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Address and /BE0 (if not fixed to low) require a setup time tAS which starts when all address and byte
enable signals are valid. The hold time of these lines is tAH .
G
Short read method
In some applications it may be difficult to implement a long read access (tRD ≥
5 · tCLKI ) for only some registers (here called target register).
For this reason there is an alternative method with two register read accesses with
tRD ≥ 20 ns each:
1. The read access to the target register initiates a data transmission from the
RAM to the target register. This job is always done correctly with long
and short tRD , but after a short tRD the data is not yet ‘arrived’ at the target
register. Thus the data which is read with a short tRD must be ignored . . .
2. . . . but the data byte is already internally buffered and can be read from the
register R_INT_DATA. This second register read access can also be executed
with a short tRD ≥ 20 ns. For the time from the first access to the second
one tCYCLE must be met, of course.
The short read method is practical for all read registers in the address range
0xC0 . . 0xFF, these target registers are R_IRQ_FIFO_BL0 . . R_IRQ_FIFO_BL7
and R_RAM_DATA.
72 of 306
Data Sheet
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Universal external bus interface
byte write access
byte write access
A[7:0]
address
address
/BE[3:1]
permanently high
/BE0
permanently low
D[15:8]
D[7:0]
data
t DWRS
t AS
data
t DWRH
t AH
t WR
in mode2 only
t DWRS
t AS
t IDLE
t DWRH
t AH
t WR
(Motorola:)
/DS+/CS
t RWS
t RWH
t RWS
t RWH
R/W
in mode 3 only
(Intel):
/WR+/CS
/RD
permanently high
Figure 2.10: Write access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
8 bit processors write data like shown in Figure 2.10. Timing values are listed in Table 2.20.
/BE3 . . /BE1 must always be ’1’. /BE0 controls the data bus D7 . . D0 and can be fixed to ’0’.
Data is written with of (/DS + /CS) in mode 2 (Motorola) or with of (/WR + /CS) in mode 3
(Intel, non-multiplexed) respectively. The HFC-E1 requires a data setup time tDW RS and a data hold
time tDW RH .
Address and /BE0 (if not fixed to low) require a setup time tAS which starts when all address and byte
enable signals are valid. The hold time of these lines is tAH .
October 2003
Data Sheet
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Universal external bus interface
2.5.2.2 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
word read access
A[7:0]
low byte read access
address
high byte read access
address
/BE[3:2]
address
permanently high
/BE1
byte enable
byte enable
byte enable
/BE0
byte enable
byte enable
byte enable
D[15:8]
data
D[7:0]
data
data
t DRDZ
data
t DRDH
t DRDZ
t RDmin
t AS
t DRDH
t RDmin
t AH
t AS
t RD
t DRDH
t RDmin
t AH
t CYCLE
in mode2 only
(Motorola:)
t DRDZ
t AS
t AH
t CYCLE
t RD
t RD
/DS+/CS
t RWS
t RWH
t RWS
t RWH
t RWS
t RWH
R/W
in mode 3 only
(Intel):
/RD+/CS
/WR
permanently high
Figure 2.11: Byte and word read access from 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
16 bit processors can either read data with byte or word access like shown in Figure 2.11. FIFO and
F- / Z-counter read access have 8 bit or 16 bit width alternatively. The 16 bit processor must support
byte access because all other register read accesses must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 switch the data bus D15 . . D0 from tristate into data
driven state (see Table 2.18).
Data can be read in mode 2 (Motorola) with
/BE = ’0’
and
(/DS + /CS) = ’0’
and
R/W = ’1’ .
In mode 3 (Intel, non-multiplexed) the states
/BE = ’0’
74 of 306
and
(/RD + /CS) = ’0’
Data Sheet
and
/WR = ’1’
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Chip
Universal external bus interface
Table 2.18: Data access width in mode 2 and 3
A[0]
/BE1
/BE0
Data access
’X’
’1’
’1’
no access
’0’
’1’
’0’
byte access on D[7:0]
’1’
’0’
’1’
byte access on D[15:8]
’0’
’0’
’0’
word access
must be fulfilled to drive data out. The data bus is stable after tRDmin and returns into tristate after
tDRDH .
Address and /BE require a setup time tAS which starts when all address and byte enable signals are
valid. The hold time of these lines is tAH .
Table 2.19: Symbols of read accesses in Figures 2.9 and 2.11
Symbol
min / ns
tAS
10
tAH
10
tDRDZ
2
tDRDH
2
tRW S
2
tRW H
2
tRD
max / ns
Characteristic
Address and /BE valid to /DS+/CS (/RD+/CS)
setup time
Address and /BE hold time after /DS+/CS (/RD+/CS) /DS+/CS (/RD+/CS)
15
to data buffer turn on time
/DS+/CS (/RD+/CS) to data buffer turn off time
R/W setup time to /DS+/CS
R/W hold time after /DS+/CS Read time:
= ’0’ (address range 0 . . . 0x7F: normal register access)
20
A[7]
20
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
5 · tCLKI
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers) ∗
Cycle time between two consecutive /DS+/CS (/RD+/CS) tCYCLE
1.5 · tCLKI
A[7]
= ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
5.5 · tCLKI
– after byte access
6.5 · tCLKI
– after word access
5.5 · tCLKI
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
∗:
October 2003
See ‘Short read method’ on page 72.
Data Sheet
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word write access
A[7:0]
low byte write access
high byte write access
address
address
address
/BE[3:2]
permanently high
/BE1
byte enable
byte enable
byte enable
/BE0
byte enable
byte enable
byte enable
D[15:8]
data
D[7:0]
data
t DWRS
t AS
data
data
t DWRH
t AH
t WR
in mode2 only
(Motorola:)
t DWRS
t AS
t IDLE
t DWRH
t DWRS
t AH
t WR
t AS
t IDLE
t DWRH
t AH
t WR
/DS+/CS
t RWS
t RWH
t RWS
t RWH
t RWS
t RWH
R/W
in mode 3 only
(Intel):
/WR+/CS
/RD
permanently high
Figure 2.12: Byte and word write access from 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
16 bit processors can either write data with byte or word access like shown in Figure 2.12. FIFO write
access have 8 bit or 16 bit width alternatively. The 16 bit processor must support byte access because
all other register write accesses must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 control the low byte and high byte of the data bus
D15 . . D0 (see Table 2.18).
Data is written with of (/DS + /CS) in mode 2 (Motorola) respectively with of (/WR + /CS) in
mode 3 (Intel, non-multiplexed). The HFC-E1 requires a data setup time tDW RS and a data hold time
tDW RH .
Address and /BE require a setup time tAS which starts when all address and byte enable signals are
valid. The hold time of these lines is tAH .
76 of 306
Data Sheet
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Universal external bus interface
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Chip
Table 2.20: Symbols of write accesses in Figures 2.10 and 2.12
Symbol
min / ns
tAS
10
tAH
10
tDW RS
20
tDW RH
10
tRW S
2
tRW H
2
tW R
20
tIDLE
max / ns
Characteristic
Address and /BE valid to /DS+/CS (/RD+/CS) setup time
Address and /BE hold time after /DS+/CS (/RD+/CS) Write data setup time to /DS+/CS (/WR+/CS) Write data hold time from /DS+/CS (/WR+/CS) R/W setup time to /DS+/CS
R/W hold time after /DS+/CS Write time
/DS+/CS (/RD+/CS) high time between two consecutive accesses
1.5 · tCLKI
A[7]
= ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
3.5 · tCLKI
– after byte access
4.5 · tCLKI
– after word access
3.5 · tCLKI
October 2003
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access)
Data Sheet
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Universal external bus interface
2.5.2.3 8 bit processors in mode 4 (Intel, multiplexed)
address write
AD[7:0]
byte read access
address
byte read access
data
data
AD[31:8]
t AS
t AH
t DRDZ
t DRDH
t DRDZ
t RDmin
/BE[3:1]
permanently high
/BE0
permanently low
t DRDH
t RDmin
ALE
t ALE
t ALEL
t CYCLE
t RD
t RD
/RD+/CS
/WR
permanently high
Figure 2.13: Byte read access from 8 bit processors in mode 4 (Intel, multiplexed)
8 bit processors read data like shown in Figure 2.13. Timing values are listed in Table 2.22.
/BE3 . . /BE1 must always be ’1’. /BE0 can be fixed to ’0’ or must be low during access to switch the
bus AD7 . . AD0 during the data phase from tristate into data driven state.
Data can be read in mode 4 (Intel, multiplexed) with 2
/BE0 = ’0’
and
(/RD + /CS) = ’0’
and
/WR = ’1’ .
The data bus is stable after tRDmin and returns into tristate after tDRDH .
Address and /BE0 (if not fixed to low) require a setup time tAS which starts with the of ALE. The
hold time of these lines is tAH . If two consecutive read accesses are on the same address, multiple
register address write is not required.
2 /RD + /CS
78 of 306
means logical OR function of the two signals.
Data Sheet
October 2003
HFC-E1
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Chip
Universal external bus interface
address write
A[7:0]
byte write access
address
byte write access
data
data
AD[31:8]
t AS
t AH
t DWRS
t DWRH
/BE[3:1]
permanently high
/BE0
permanently low
t DWRS
t DWRH
ALE
t ALE
t ALEL
t IDLE
t WR
t WR
/WR+/CS
/RD
permanently high
Figure 2.14: Byte write access from 8 bit processors in mode 4 (Intel, multiplexed)
8 bit processors write data like shown in Figure 2.14. Timing values are listed in Table 2.23.
/BE3 . . /BE1 must always be ’1’. /BE0 controls the bus AD7 . . AD0 during the data phase and can be
fixed to ’0’.
Data is written with of (/WR + /CS) in mode 4 (Intel, multiplexed). The HFC-E1 requires a data
setup time tDW RS and a data hold time tDW RH .
Address and /BE0 (if not fixed to low) require a setup time tAS which starts with the of ALE. The
hold time of these lines is tAH . If two consecutive write accesses are on the same address, multiple
register address write is not required.
October 2003
Data Sheet
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Universal external bus interface
2.5.2.4 16 bit processors in mode 4 (Intel, multiplexed)
address write
AD[7:0]
word read access
address
AD[15:8]
word read access
data
data
data
data
AD[31:16]
t DRDZ
t DRDH
t DRDZ
t RDmin
/BE[3:2]
/BE[1:0]
t DRDH
t RDmin
permanently high
byte enable
t AS
t AH
ALE
t ALE
t ALEL
t CYCLE
t RD
t RD
/RD+/CS
/WR
permanently high
Figure 2.15: Word read access from 16 bit processors in mode 4 (Intel, multiplexed)
16 bit processors can either read data with byte or word access. Only 8 bits are used for address
decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A word read is shown in Figure 2.15. FIFO and F- / Z-counter read access have 8 bit or 16 bit width
alternatively. The 16 bit processor must support byte access because all other register read accesses
must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 switch the bus AD15 . . AD0 during the data phase
from tristate into data driven state (see Table 2.21 on page 82).
In mode 4 (Intel, multiplexed) the states
/BE = ’0’
and
(/RD + /CS) = ’0’
and
/WR = ’1’
must be fulfilled to drive data out. The data bus is stable after tRDmin and returns into tristate after
tDRDH .
Address and /BE require a setup time tAS which starts with the of ALE. The hold time of these
lines is tAH . If two consecutive read accesses are on the same address, multiple register address write
is not required.
An 8 bit read access of a low byte is performed in the same way as it is done with 8 bit processors.
Thus see Figure 2.13 for the timing specification. 8 bit read access of a high byte requires AD0 =
’1’ because the address is not decoded from /BE. Nevertheless, /BE[1:0] must be ’01’ to control the
AD15 . . AD0 lines during the data phase.
80 of 306
Data Sheet
October 2003
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Chip
Universal external bus interface
address write
A[7:0]
word write access
address
AD[15:8]
word write access
data
data
data
data
AD[31:16]
t DWRS
/BE[3:2]
t DWRH
t DWRS
t DWRH
permanently high
/BE[1:0]
byte enable
t AS
t AH
ALE
t ALE
t ALEL
t IDLE
t WR
t WR
/WR+/CS
/RD
permanently high
Figure 2.16: Word write access from 16 bit processors in mode 4 (Intel, multiplexed)
16 bit processors can either write data with byte or word access. Only 8 bits are used for address
decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A word write is shown in Figure 2.16. FIFO write access have 8 bit or 16 bit width alternatively. The
16 bit processor must support byte access because all other register write accesses must have a width
of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 control the low byte and high byte of the bus
AD15 . . AD0 during the data phase (see Table 2.21 on page 82).
Data is written with of /WR + /CS in mode 4 (Intel, multiplexed). The HFC-E1 requires a data
setup time tDW RS and a data hold time tDW RH .
Address and /BE require a setup time tAS which starts with the of ALE. The hold time of these
lines is tAH . If two consecutive write accesses are on the same address, multiple register address write
is not required.
An 8 bit write access (low byte) is performed in the same way as it is done with 8 bit processors.
Thus see Figure 2.14 for the timing specification. 8 bit write access of a high byte requires AD0 =
’1’ because the address is not decoded from /BE. Nevertheless, /BE[1:0] must be ’01’ to control the
AD15 . . AD0 lines during the data phase.
October 2003
Data Sheet
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HFC-E1
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Universal external bus interface
2.5.2.5 32 bit processors in mode 4 (Intel, multiplexed)
address write
AD[7:0]
double word read access
double word read access
data
data
address
AD[31:8]
data
data
t DRDZ
t DRDH
t DRDZ
t RDmin
/BE[3:0]
t DRDH
t RDmin
byte enable
t AS
t AH
ALE
t ALE
t ALEL
t CYCLE
t RD
t RD
/RD+/CS
/WR
permanently high
Figure 2.17: Double word read access from 32 bit processors in mode 4 (Intel, multiplexed)
32 bit processors can either read data with byte, word or double word access. Only 8 bits are used for
address decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A double word read is shown in Figure 2.17. FIFO and Z-counter read access have 8 bit, 16 bit or
32 bit width alternatively, F-counter read access have 8 bit or 16 bit width alternatively. The 32 bit
processor must support byte access because all other register read accesses must have a width of 8 bit.
Table 2.21: Data access width in mode 4
A[0]
/BE3
/BE2
/BE1
/BE0
Data access
’X’
’1’
’1’
’1’
’1’
no access
’0’
’1’
’1’
’1’
’0’
byte access on AD[7:0]
’1’
’1’
’1’
’0’
’1’
byte access on AD[15:8]
’0’
’1’
’0’
’1’
’1’
byte access on AD[23:16]
’1’
’0’
’1’
’1’
’1’
byte access on AD[31:24]
’0’
’1’
’1’
’0’
’0’
word access on AD[15:0]
’0’
’0’
’0’
’1’
’1’
word access on AD[31:16]
’0’
’0’
’0’
’0’
’0’
double word access
/BE3 . . /BE0 switch the bus lines AD31 . . AD0 from tristate into data driven state during data phase
(see Table 2.21).
82 of 306
Data Sheet
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Universal external bus interface
In mode 4 (Intel, multiplexed) the states
/BE = ’0’
(/RD + /CS) = ’0’
and
and
/WR = ’1’
must be fulfilled to drive data out. The data bus is stable after tRDmin and returns into tristate after
tDRDH .
Address and /BE require a setup time tAS which starts with the of ALE. The hold time of these
lines is tAH . If two consecutive read accesses are on the same address, multiple register address write
is not required.
An 8 bit read access (low byte) is performed in the same way as it is done with 8 bit processors. Thus
see Figure 2.13 for the timing specification. Accordingly a 16 bit read access (low word) is performed
in the same way as it is done with 16 bit processors. This is shown in Figure 2.15. The requirements
of other byte accesses and the high word access is specified in Table 2.21.
Table 2.22: Symbols of read accesses in Figures 2.13, 2.15 and 2.17
Symbol
min / ns
tALE
10
tALEL
0
max / ns
Characteristic
Address latch time
ALE
to /RD+/CS
tAS
10
Address and /BE valid to ALE
tAH
10
Address and /BE hold time after ALE
tDRDZ
2
tDRDH
2
tRD
/RD+/CS
15
setup time
to data buffer turn on time
/RD+/CS to data buffer turn off time
20
Read time:
20
A[7]
20
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
5 · tCLKI
= ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers) ∗
Cycle time between two consecutive /RD+/CS tCYCLE
1.5 · tCLKI
A[7]
= ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
5.5 · tCLKI
– after byte access
6.5 · tCLKI
– after word access
5.5 · tCLKI
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
∗:
October 2003
See ‘Short read method’ on page 72.
Data Sheet
83 of 306
HFC-E1
address write
A[7:0]
double word write access
address
AD[31:8]
double word write access
data
data
data
data
t DWRS
/BE[3:0]
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Universal external bus interface
t DWRH
t DWRS
t DWRH
byte enable
t AS
t AH
ALE
t ALE
t ALEL
t IDLE
t WR
t WR
/WR+/CS
/RD
permanently high
Figure 2.18: Double word write access from 32 bit processors in mode 4 (Intel, multiplexed)
32 bit processors can either write data with byte, word or double word access. Only 8 bits are used
for address decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A double word write is shown in Figure 2.18. FIFO write access have 8 bit, 16 bit or 32 bit width
alternatively. The 32 bit processor must support byte access because all other register write accesses
must have a width of 8 bit.
/BE3 . . /BE0 control the bus lines AD31 . . AD0 during data phase (see Table 2.21).
Data is written with of /WR + /CS in mode 4 (Intel, multiplexed). The HFC-E1 requires a data
setup time tDW RS and a data hold time tDW RH .
Address and /BE require a setup time tAS which starts with the of ALE. The hold time of these
lines is tAH . If two consecutive write accesses are on the same address, multiple register address write
is not required.
An 8 bit write access (low byte) is performed in the same way as it is done with 8 bit processors.
Thus see Figure 2.14 for the timing specification. Accordingly a 16 bit write access (low word) is
performed in the same way as it is done with 16 bit processors. This is shown in Figure 2.16. The
requirements of other byte accesses and the high word access is specified in Table 2.21.
84 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
Table 2.23: Symbols of write accesses in Figures 2.14, 2.16 and 2.18
Symbol
min / ns
tALE
10
tALEL
0
max / ns
Characteristic
Address latch time
ALE
to /WR+/CS
tAS
10
Address and /BE valid to ALE
tAH
10
Address and /BE hold time after ALE
tDW RS
20
tDW RH
10
Write data hold time from /WR+/CS tW R
20
Write time
tIDLE
setup time
Write data setup time to /WR+/CS /WR+/CS high time between two consecutive data write accesses
1.5 · tCLKI
A[7]
= ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
3.5 · tCLKI
– after byte access
4.5 · tCLKI
– after word access
3.5 · tCLKI
October 2003
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access)
Data Sheet
85 of 306
HFC-E1
2.5.3
Cologne
Chip
Universal external bus interface
Examples of processor connection circuitries
U1
nc
+3.3V
+3.3V GND
R1
8 bit Processor
196
195
194
NC
GND
VDD
CONTROL
197
/INT
/INT
+3.3V
99
100
MODE0
MODE1
GND
198
200
RESET
+3.3V
R2 depends on
application
+3.3V
R3
GND
/WD
/DS
R/W
/CS
R* can be omitted if reset
is active during power on.
+3.3V
8 bit Processor
GND
nc
nc
GND
R*
100k
ADDRESS / DATA
R*
R*
R*
R*
R*
R*
R*
R*
GND
100k
100k
100k
100k
100k
100k
100k
100k
A07
A06
A05
A04
A03
A02
A01
A00
R*
R*
R*
R*
R*
R*
R*
R*
GND
D07
D06
D05
D04
D03
D02
D01
D00
8 bit Processor
(Motorola Mode)
7
23
24
21
22
20
27
6
18
30
40
100k
R5
26
25
100k
100k
100k
100k
100k
100k
100k
100k
203
204
205
206
1
2
3
4
8
9
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
RESET
GND
NC
/BUSDIR
GND
/WD
ALE
/IOR
/IOW
/CS
FL0
/BE3
/BE2
/BE1
/BE0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HFC- E1
(Processor interface,
mode 2, Motorola)
Figure 2.19: 8 bit Intel / Motorola processor circuitry example (mode 2)
86 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Universal external bus interface
U1
nc
+3.3V
+3.3V GND
R1
16 bit Processor
196
195
194
NC
GND
VDD
CONTROL
197
/INT
/INT
+3.3V
99
100
MODE0
MODE1
GND
198
200
RESET
+3.3V
R2
GND
nc
nc
depends on
application
26
25
GND
7
23
24
21
22
20
R3
/RES
ALE
/RD
/WR
/CS
R* can be omitted if reset
is active during power on.
+3.3V
GND
16 bit Processor
ADDRESS / DATA
R*
100k
27
100k R4
6
18
30
40
/BE1
/BE0
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R* GND
R*
R*
R*
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
203
204
205
206
1
2
3
4
8
9
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
RESET
GND
NC
/BUSDIR
GND
/WD
ALE
/IOR
/IOW
/CS
FL0
/BE3
/BE2
/BE1
/BE0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HFC- E1
(Processor interface,
mode 4, INTEL multiplexed)
16 bit Processor
(multiplexed mode)
Figure 2.20: 16 bit Intel processor circuitry example (mode 4, multiplexed)
October 2003
Data Sheet
87 of 306
HFC-E1
2.6
Cologne
Chip
Universal external bus interface
Serial processor interface (SPI)
Table 2.24: Overview of the SPI interface pins
Number
Name
Description
194
/SPISEL
SPI device select low active
195
SPI_RX
SPI receive data input
196
SPI_TX
SPI transmit data output
197
/INT
Interrupt request
198
RESET
Reset high active
200
SPICLK
SPI clock input
The SPI interface mode is selected by MODE0 = 1, MODE1 = 0 and connecting pin 200 to SPI clock.
/SPISEL must be high during reset. The first positive edge on SPICLK switches the interface from
processor interface mode into SPI mode. This may be the first positive clock at the start of an SPI
access.
The interface has 4 pins as shown in Table 2.24. For further information please see the SPI specification.
2.6.1
SPI read and write access
In SPI mode each data transfer is 16 bit long. From the first 8 bits only the bits R/W and ADR/DAT
are used. The other 6 bits must be zero. Depending on the R/W bit the second 8 bits are read from
the HFC-E1 or written into the HFC-E1 as shown in the Figures 2.21 and 2.22. So all data accesses in
SPI mode handle 8 data bits.
1st_byte
2nd_byte
/SPISEL
SPICLK
SPI_RX
SPI_TX
R/W
A/D
6 bit low
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2.21: SPI read access
It is allowed to disable the /SPISEL signal between the two bytes. In this case the transmission pauses
and will be continued after /SPISEL returns to low level. An example for an interrupted read access
is shown in Figure 2.23.
88 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Universal external bus interface
1st_byte
2nd_byte
/SPISEL
SPICLK
SPI_RX
R/W
A/D
6 bit low
D7
D6
D5
D4
D3
D2
D1
D0
SPI_TX
Figure 2.22: SPI write access
1st_byte
2nd_byte
/SPISEL
SPICLK
SPI_RX
R/W A/D
6 bit low
SPI_TX
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2.23: Interrupted SPI read access
October 2003
Data Sheet
89 of 306
HFC-E1
Cologne
Chip
SPI connection circuitry
+3.3V
+3.3V
+3.3V
R1
GND
SPI
Signal
10k
SPI
Power
10k
2.6.2
Universal external bus interface
R2
U1
GND
196
SPI_TX
195
SPI_RX
194
/SPISEL
197
/INT
10k
+3.3V
R3
99
100
SPI_TX
SPI_RX
/SPISEL
/INT
MODE0
MODE1
GND
GND
R4
10k
RESET
CLK
SPI interface
198
200
26
25
+3.3V
R*
R*
R*
R*
100k
100k
R*
100k
100k
27
6
18
30
40
100k
R* can be omitted if reset
is active during power on.
7
23
24
21
22
20
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
100k
203
204
205
206
1
2
3
4
8
9
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
RESET
SPICLK
n.c.
n.c.
GND
FL0
FL0
VDD
FL1
VDD
FL0
VDD
FL1
VDD
GND
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
FL0
HFC- E1
GND
Figure 2.24: SPI connection circuitry
90 of 306
Data Sheet
October 2003
HFC-E1
Universal external bus interface
Cologne
Chip
2.7 Register description
2.7.1
Write only registers
(write only)
R_CIRM
0x00
Interrupt and reset register
Bits
Reset
Name
Description
Value
2..0
0
V_IRQ_SEL
IRQ pin selection in ISA PnP mode
’000’ = interrupt lines disable
’001’ = IRQ0
’010’ = IRQ1
’011’ = IRQ2
’100’ = IRQ3
’101’ = IRQ4
’110’ = IRQ5
’111’ = IRQ6
3
0
V_SRES
Soft reset (reset group 0)
This reset is similar to the hardware reset. The
selected I/O address (CIP) remains unchanged. The
reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
4
0
V_HFC_RES
HFC-reset (reset group 1)
Sets all FIFO and HDLC registers to their initial
values. The reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
5
0
V_PCM_RES
PCM reset (reset group 2)
Sets all PCM registers to their initial values. The
reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
6
0
V_E1_RES
E1-reset (reset group 3)
Sets all E1 interface registers to their initial values.
The reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
7
0
V_RLD_EPR
EEPROM reload
’0’ = normal operation
’1’ = reload EEPROM to SRAM
This bit must be cleared by software. The reload is
started when the bit is cleared.
(For reset group description see Table 12.4 on page 261.)
October 2003
Data Sheet
91 of 306
HFC-E1
Universal external bus interface
R_CTRL
(write only)
Cologne
Chip
0x01
Common control register
Bits
Reset
Name
Description
Must be ’0’.
Value
0
0
(reserved)
1
0
V_FIFO_LPRIO
FIFO access priority for host accesses
’0’ = normal priority
’1’ = low priority
2
0
V_SLOW_RD
One additional wait cycle for PCI read accesses
’0’ = normal operation
’1’ = additional wait (must be set for 66 MHz PCI
operation)
3
0
V_EXT_RAM
Use external RAM
The internal SRAM is switched off when external
SRAM is used.
’0’ = internal SRAM is used in lower 32 kByte
address space
’1’ = external SRAM is used
4
0
(reserved)
Must be ’0’.
5
0
V_CLK_OFF
CLK oscillator
’0’ = normal operation
’1’ = CLK oscillator is switched off
This bit is reset at every write access to the HFC-E1.
7..6
92 of 306
0
(reserved)
Must be ’00’.
Data Sheet
October 2003
HFC-E1
Universal external bus interface
(write only)
R_RAM_ADDR0
Cologne
Chip
0x08
Address pointer, register 0
1st address byte for internal / external SRAM access.
Bits
Reset
Name
Description
V_RAM_ADDR0
Address bits 7 . . 0
Value
7..0
0x00
(write only)
R_RAM_ADDR1
0x09
Address pointer, register 1
2nd address byte for internal / external SRAM access.
Bits
Reset
Name
Description
V_RAM_ADDR1
Address bits 15 . . 8
Value
7..0
0x00
(write only)
R_RAM_ADDR2
0x0A
Address pointer, register 2
High address bits for internal / external SRAM access and access configuration.
Bits
Reset
Name
Description
V_RAM_ADDR2
Address bits 19 . . 16
(reserved)
Must be ’00’.
Value
3..0
0
5..4
6
0
V_ADDR_RES
Address reset
’0’ = normal operation
’1’ = address bits 0 . . 19 are set to zero
This bit is automatically cleared.
7
0
V_ADDR_INC
Address increment
’0’ = no address increment
’1’ = automatically increment of the address after
every write or read on register R_RAM_DATA
October 2003
Data Sheet
93 of 306
HFC-E1
Universal external bus interface
(write only)
R_RAM_MISC
Cologne
Chip
0x0C
RAM size setup and miscellaneous functions register
Bits
Reset
Name
Description
Value
1..0
0
V_RAM_SZ
RAM size
’00’ = 32k x 8
’01’ = 128k x 8
’10’ = 512k x 8
’11’ = reserved
After setting V_RAM_SZ to a value different from
’00’ a soft reset should be initiated.
3..2
(reserved)
Must be ’00’.
4
0
V_PWM0_16KHZ
16 kHz signal on pin PWM0
’0’ = normal PWM0 function
’1’ = 16 kHz output
5
0
V_PWM1_16KHZ
16 kHz signal on pin PWM1
’0’ = normal PWM1 function
’1’ = 16 kHz output
(reserved)
Must be ’0’.
V_FZ_MD
Exchange F- / Z-counter context
(for transmit FIFOs only)
’0’ = A_Z1L, A_Z1H = Z1(F1) and A_Z2L, A_Z2H =
Z2(F1) (normal operation)
’1’ = A_Z1L, A_Z1H = Z1(F1) and A_Z2L, A_Z2H =
Z2(F2) (exchanged operation)
This bit can be used to check the actual RAM usage
of transmit FIFOs.
6
7
94 of 306
0
Data Sheet
October 2003
HFC-E1
2.7.2
Universal external bus interface
Cologne
Chip
Read only registers
(read only)
R_RAM_USE
0x15
SRAM duty factor
Usage of SRAM access bandwidth by the internal data processor.
Bits
Reset
Name
Description
Value
7..0
V_SRAM_USE
Relative duty factor
0x00 = 0% bandwidth used
0x7C = 100% bandwidth used
(read / write)
R_RAM_DATA
0xC0
SRAM data access
Direct access to internal / external SRAM
Bits
Reset
Name
Description
V_RAM_DATA
SRAM data access
The address must be written into the registers
R_RAM_ADDR0 . . R_RAM_ADDR2 in advance.
Value
7..0
0
(read only)
R_CHIP_ID
0x16
Chip identification register
Bits
Reset
Name
Description
IRQ assigned by the PnP BIOS
(only in ISA PnP mode)
V_IRQ_SEL of the R_CIRM register must be set to
the value corresponding to the hardware connected
IRQ lines.
Value
3..0
0
V_PNP_IRQ
7..4
0xE
V_CHIP_ID
Chip identification code
’1110’ means HFC-E1.
October 2003
Data Sheet
95 of 306
HFC-E1
Cologne
Chip
Universal external bus interface
0x1F
(read only)
R_CHIP_RV
HFC-E1 revision
Bits
Reset
Name
Description
Chip revision 1
(Engineering samples were revision 0.)
Value
3..0
1
V_CHIP_RV
7..4
0
(reserved)
96 of 306
Data Sheet
October 2003
Chapter 3
HFC-E1 data flow
HFCchannel
E1 interf.
assigner
HDLC
or
transparent
data
flow
controller
HFC-channel
byte
construction /
decomposition
FIFO
E1 slot
subchannel
processor
E1
interface
PCM slot
assigner
HFCchannel
PCM slot
FIFO
controller
FIFO
host
interface
HFCchannel
HDLC
controller
HFC-channel
assigner
channel
PCM
interface
slot
Figure 3.1: Data flow block diagram
October 2003
Data Sheet
97 of 306
HFC-E1
Data flow
3.1
Data flow concept
3.1.1
Overview
Cologne
Chip
The HFC-E1 has a programmable data flow unit, in which the FIFOs are connected to the PCM and
the E1 interface. Moreover the data flow unit can directly connect PCM and E1 interface or two PCM
time slots 1 .
The fundamental features of the HFC-E1 data flow are as follows:
• programmable interconnection capability between FIFOs, PCM time slots and E1 time slots
• in transmit and receive direction there are
–
–
–
–
up to 32 FIFOs each
32, 64 or 128 PCM time slots each
32 E1 time slots each
32 HFC-channels each to connect the above-mentioned data interfaces
• 3 data flow modes to satisfy different application tasks
• subchannel processing for bitwise data handling
The complete HFC-E1 data flow block diagram is shown in Figure 3.1. Basically, data routing requires
an allocation number at each block. So there are three areas where numbering is based on FIFOs,
HFC-channels and PCM time slots.
FIFO handling and HDLC controller, PCM and E1 interface are described in Chapters 4 to 6. So
this chapter deals with the data flow unit which is located between and including the HFC-channel
assigner, the PCM slot assigner and the E1 slotassigner.
3.1.2
Term definitions
Figure 3.2 clarifies the relationship and the differences between the numbering of FIFOs, HFCchannels and PCM time slots. The inner circle symbolizes the HFC-channel oriented part of the
data flow, while the outer circle shows the connection of three data sources and data drains respectively. The E1 interface have a fixed mapping between HFC-channels and E1 time slots so that there
is no need of a separate E1 time slot numbering.
FIFO: The FIFOs are buffers between the universal bus interface and the PCM and E1 interface.
The HDLC controllers are located on the non host bus side of the FIFOs. The number of
FIFOs depends on the FIFO size configuration (see Section 4.3) and starts with number 0. The
maximum FIFO number is 31. Furthermore data directions transmit and receive are associated
with every FIFO number.
HFC-channel: HFC-channels are used to define data paths between FIFOs on the one side and PCM
and E1 interface on the other side. The HFC-channels are numbered 0 . . 31. Furthermore data
directions transmit and receive are associated with every HFC-channel number.
1 In
this data sheet the shorter expression “slot” instead of “time slot” is also used with the same meaning.
98 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Data flow
host
interface
ISDN applications:
B-channels
D-channel
lot
E1 s
channel
oriented numbering
...
HFCel
n
chan
H
ch FC
an ne
l
FI
FO
FIFO
oriented
numbering
PCM slot
oriented
numbering
PCM
slot
H
chanFCnel
PCM
interface
Figure 3.2: Areas of FIFO oriented, HFC-channel oriented and PCM time slot oriented numbering
It is important not to mix up the HFC-channels of the here discussed data flow (inner circle of
Figure 3.2) with the B-channels and the D-channel of the E1 interface.
PCM time slot: The PCM data stream is organized in time slots. The number of PCM time slots
depends on the data rate, i.e. there are 32 time slots with 2 MBit/s (numbered 0 . . 31), 64 time
slots with 4 MBit/s (numbered 0 . . 63) or 128 time slots with 8 MBit/s (numbered 0 . . 127).
Every PCM time slot exists both in transmit and receive data directions.
E1 time slot: The E1 data stream is organized in time slots. E1 time slots have always the same
number and data direction as the associated HFC-channel.
Each FIFO, HFC-channel and PCM time slot number exist for transmit and receive direction. The
data rate is always 8 kByte/s for every E1 time slot and every PCM time slot. FIFOs, HFC-channels,
E1 time slots and PCM time slots have always a width of 8 bit.
3.2 Flow controller
3.2.1
Overview
The various connections between FIFOs, E1 time slots and PCM time slots are set up by programming
the flow controller, the HFC-channel assigner and the PCM slot assigner.
The flow controller sets up connections between FIFOs and the E1 interface, FIFOs and the PCM
interface and between the E1 interface and the PCM interface. The bitmap V_DATA_FLOW of the
register A_CON_HDLC (which exists for each FIFO) configures these connections. The numbering
of transmit and corresponding receive FIFOs, HFC-channels and PCM time slots is independent from
each other. But in practice the connection table is more clear if the same number is chosen for
corresponding transmit and receive direction.
A direct connection between two PCM time slots can be set up inside the PCM slot assigner and will
be described in Section 3.3.
October 2003
Data Sheet
99 of 306
HFC-E1
Data flow
Cologne
Chip
The flow controller operates on HFC-channel data. Nevertheless it is programmed with a bitmap of
a FIFO-indexed array register. With this concept it is possible to change the FIFO-to-HFC-channel
assignment of a ready-configured FIFO without re-programming its parameters again.
The internal structure of the flow controller contains
• 4 switching buffers, i.e. one for the E1 and PCM interface in transmit and receive direction
each and
• 3 switches to control the data paths.
3.2.2
Switching buffers
The switching buffers decouple the data inside the flow controller from the data that is transmitted / received from / to the E1 and PCM interfaces. With every 125 µs cycle the switching buffers
change their pointers.
If a byte is read from the FIFO and written into a switching buffer, it is transmitted by the connected
interface during the next 125 µs cycle. In the reverse case, a received byte which is stored in a switching buffer is copied to the FIFO during the next 125 µs cycle.
A direct PCM-to-E1 connection delays each data byte two cycles. That means the received byte is
stored in the switching buffer during the first 125 µs cycle, then copied into the transmit buffer during
the second 125 µs cycle and finally transmitted from the interface during the third 125 µs cycle. If
the conference unit is switched on, there is an additional 125 µs delay, because the summation of the
whole frame is processed in the memory (see Section 8).
3.2.3
Timed sequence
The data transmission algorithm of the flow controller is FIFO-oriented and handles all FIFOs, and
of course all connected HFC-channels, every 125 µs in the following sequence 2 :
1. FIFO[0,TX]
2. FIFO[0,RX]
3. FIFO[1,TX]
4. FIFO[1,RX]
..
.
63. FIFO[31,TX]
64. FIFO[31,RX]
If a faulty configuration writes data from several sources into the same switching buffer, the last write
access overwrites the previous ones. Only in this case it is necessary to know the process sequence of
the flow controller.
The HFC-E1 has three data flow modes. One of them (FIFO sequence mode) is used to configure a
programmable FIFO sequence which can be used instead of the ascending FIFO numbering. This is
explained in Section 3.4.
2 Due
to the FIFO size setup (see Section 4.3) the maximum number of FIFOs might be less than 32.
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3.2.4
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Data flow
Transmit operation (FIFO in transmit data direction)
In transmit operation one HDLC or transparent byte is read from a FIFO and can be transmitted to
the E1 and the PCM interface as shown in Figure 3.3. Furthermore, data can be transmitted from
the E1 interface to the PCM interface. From the flow controller point of view, the switches select the source for outgoing data. They are controlled by the bitmap V_DATA_FLOW[2 . . 1] of the
register A_CON_HDLC[n,TX] where n is a FIFO number. Transmit operation is configured with
V_FIFO_DIR = 0 in the multi-register R_FIFO.
V_DATA_FLOW [1]
switching buffer
0
1
transmit S/T
selection
channel data to
transmit E1 slot
switching buffer
channel data from
receive E1 slot
HDLC or
transparent
data
channel data from
HDLC controller
V_DATA_FLOW [2]
channel data to
HDLC controller
no data
transfer
switching buffer
0
channel data to
transmit PCM slot
1
transmit PCM
selection
Flow Controller
in transmit operation
no data
transfer
channel data from
receive PCM slot
Figure 3.3: The flow controller in transmit operation
• FIFO data is only transmitted to the E1 interface if V_DATA_FLOW[1] = 0.
• The PCM interface can transmit a data byte which comes either from the FIFO or from the E1
interface. Bit V_DATA_FLOW[2] selects the source for the PCM transmit slot (see Figure 3.3).
The receiving E1 time slot has always the same number as the transmitting E1 time slot.
• The bit V_DATA_FLOW[0] is ignored in transmit operation.
3.2.5
Receive operation (FIFO in receive data direction)
Figure 3.4 shows the flow controller structure in receive operation. The two switches are controlled
by the bitmap V_DATA_FLOW[1 . . 0] of the register A_CON_HDLC[n,RX] where n is a FIFO number.
Receive operation is configured with V_FIFO_DIR = 1 in the multi-register R_FIFO. FIFO data can
either be received from the E1 or PCM interface. Furthermore, data can be transmitted from the PCM
interface to the E1 interface.
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Data flow
V_DATA_FLOW [0]
V_DATA_FLOW [1]
switching buffer
0
1
transmit S/T
selection
channel data to
transmit E1 slot
switching buffer
channel data from
receive E1 slot
HDLC or
transparent
data
channel data from
HDLC controller
no data
transfer
0
channel data to
HDLC controller
1
receive FIFO
selection
no data
transfer
channel data to
transmit PCM slot
switching buffer
Flow Controller
in receive operation
channel data from
receive PCM slot
Figure 3.4: The flow controller in receive FIFO operation
• Bit V_DATA_FLOW[0] selects the source for the receive FIFO which can either be the PCM or
the E1 interface.
• Furthermore, the received PCM byte can be transferred to the E1 interface. This requires bit
V_DATA_FLOW[1] = 1.
• The bit V_DATA_FLOW[2] is ignored in receive FIFO operation.
3.2.6
Connection summary
Table 3.1 shows the flow controller connections as a whole. Bidirectional connections 3 are pointed
out with a gray box because they are typically used to establish the data transmissions. All rows have
an additional connection to a second destination.
The most important connections are bidirectional data transmissions. For these connections it is
possible to manage the configuration programming of V_DATA_FLOW with only three different values
for transmit and receive FIFO operations. Table 3.2 shows the suitable programming values which
can be used to simplify the programming algorithm.
3.3
Assigners
The data flow block diagram in Figure 3.1 contains three assigners. These functional blocks are used
to connect FIFOs, E1 time slots and PCM time slots to the HFC-channels.
3 In
fact, all connections are unidirectional. However, in typical applications there is always a pair of transmit and
receive data channels which belong together. Instead of “transmit and corresponding receive data connection” the shorter
expression “bidirectional connection” is used in this data sheet.
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Data flow
Table 3.1: Flow controller connectivity
V_DATA_FLOW
Transmit
Receive
(V_FIFO_DIR = 0)
(V_FIFO_DIR = 1)
’000’
FIFO → PCM
FIFO → E1
FIFO ← E1
’001’
FIFO → E1
FIFO → PCM
FIFO ← PCM
’010’
FIFO → PCM
’011’
E1 → PCM
’100’
FIFO → E1
FIFO ← E1
E1 ← PCM
FIFO → PCM
FIFO ← PCM
E1 ← PCM
FIFO → E1
FIFO ← E1
E1 → PCM
FIFO ← PCM
’110’
E1 → PCM
E1 ← PCM
FIFO ← E1
’111’
E1 → PCM
E1 ← PCM
FIFO ← PCM
’101’
Table 3.2: V_DATA_FLOW programming values for bidirectional connections
Connection
3.3.1
Required
Recommended
V_FIFO_DIR
V_DATA_FLOW
V_DATA_FLOW
FIFO
→
E1
’0’ (TX)
’x0x’
FIFO
←
E1
’1’ (RX)
’xx0’
FIFO
→
PCM
’0’ (TX)
’0xx’
FIFO
←
PCM
’1’ (RX)
’xx1’
E1
→
PCM
’0’ (TX)
’1xx’
E1
←
PCM
’1’ (RX)
’x1x’
’000’
’001’
’110’
HFC-channel assigner
The HFC-channel assigner interconnects FIFOs and HFC-channels. Its functionality depends on the
data flow mode described in Section 3.4.
3.3.2
PCM slot assigner
The PCM slot assigner can connect each PCM time slot to an arbitrary HFC-channel. Therefore, for
a selected time slot 4 the connected HFC-channel number and data direction must be written into the
register A_SL_CFG[SLOT] as follows:
4 A time slot is specified by writing its number and data direction into the register R_SLOT. Then all accesses to the slot
array registers belong to this time slot. Please see Chapter 6 for details.
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Register setup:
A_SL_CFG[SLOT] : V_CH_SDIR
= <HFC-channel data direction>
: V_CH_SNUM = <HFC-channel number>
Typically, the data direction of a HFC-channel and its connected PCM time slot is the same.
If two PCM time slots are connected to each other, incoming data on a slot is transferred to the PCM
slot assigner and stored in the PCM receive switching buffer of the connected HFC-channel. From
there it is read (i.e. same HFC-channel) and transmitted to a transmit PCM time slot.
3.3.3
E1 slot assigner
The E1 interface consists of 32 time slots for transmit data and 32 time slots for receive data.
In HFC-E1 applications these time slots are typically used for ISDN data transfer. Then time slot 0 is
reserved for the synchronization process and time slot 16 is normally used to be the D-channel. All
the other time slots are assigned to B-channels for the ISDN data transmission.
Between the HFC-channels 5 and the E1 time slots there is a simple assignment:
HFC-channel[n,TX] ↔ E1 slot[n,TX]
HFC-channel[n,RX] ↔ E1 slot[n,RX]
with n = 0 . . 31. There is no possibility to change this allocation, so there are no registers for programming the E1 slot assigner.
3.3.4
Assigner summary
The three different assigner types of the HFC-E1 are shown in Figure 3.5. Assigner programming is
always handled with array registers. This can be a FIFO array register or a PCM slot array register.
• The E1 interface assigner is not programmable. Every HFC-channel is connected to a E1 time
slot with the same number and data direction.
• The PCM slot assigner is programmed by the register A_SL_CFG[SLOT]. The PCM time slot
must be selected before by writing the desired slot number and direction into the register
R_SLOT.
• The HFC-channel assigner programming depends on the data flow mode which is described
in Section 3.4. This section explains in what cases the assigner is programmable and how this
can be done. Figure 3.5 gives a hint, that the programming procedure is handled with the array
register A_CHANNEL[FIFO]. Please see section 3.4 for details and restrictions.
5 These channels have nothing to do with the mentioned D-channel and B-channels of the E1 interface, please refer to
the inner circle of Figure 3.2.
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Data flow
HFC-channel assigner
programming
Index register for
FIFO array registers
R_FIFO:
V_FIFO_DIR = 0
V_FIFO_NUM
R_FIFO:
V_FIFO_DIR = 1
V_FIFO_NUM
TX
RX
A_CHANNEL[FIFO]:
V_CH_FDIR = 0
V_CH_FNUM
TX
A_CHANNEL[FIFO]:
V_CH_FDIR = 1
V_CH_FNUM
The E1 interface assigner
RX
is not programmable
FIFO
HFCchannel
# TX
# RX
HFCchannel
HFC-channel
# TX
# RX
E1 interf.
# TX
# RX
E1 slot
HFCchannel
# TX
# RX
HFCchannel
PCM slot
FIFOs
FIFO
E1 interface
assigner
# TX
# RX
HFC-channel
assigner
PCM slot
# TX
# RX
PCM slot
assigner
TX
PCM slot assigner
programming
RX
A_SL_CFG[SLOT]:
V_CH_SDIR = 0
V_CH_SNUM
Index register for
PCM array registers
TX
R_SLOT:
V_SL_DIR = 0
A_SL_CFG[SLOT]: V_SL_NUM
V_CH_SDIR = 1
V_CH_SNUM
RX
R_SLOT:
V_SL_DIR = 1
V_SL_NUM
Figure 3.5: Overview of the assigner programming
3.4 Data flow modes
The internal operation of the HFC-channel assigner and the subchannel processor depends on the
selected data flow mode. Three modes are available and will be described in this section:
• Simple Mode (SM),
• Channel Select Mode (CSM) and
• FIFO Sequence Mode (FSM)
Various array registers are available to configure the data flow. Unused FIFOs and PCM time slots
should remain in their reset state.
FIFO array registers are indexed by R_FIFO in most cases. But there are some exceptions depending
on the data flow mode and the target array register. Table 3.3 shows all FIFO array registers and their
index registers at the different data flow modes.
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Table 3.3: Index registers of the FIFO array registers (sorted by address)
Array register
Context
name
address
FIFO data counters
0x04
Index register in
Index meaning in
SM
CSM
FSM
SM
CSM
FSM
A_Z1L[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
0x07
A_Z2H[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
0x0C
A_F1[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
0x0D
A_F2[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
FIFO configuration
0x0E
A_INC_RES_FIFO[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
FIFO data access
0x80
A_FIFO_DATA0[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
0x84
A_FIFO_DATA0_NOINC[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
Subchannel processor
0xF4
A_CH_MSK[FIFO]
R_FIFO
R_FIFO
R_FIFO
HFC-channel
HFC-channel
HFC-channel
FIFO configuration
0xFA
A_CON_HDLC[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
Subchannel Processor
0xFB
A_SUBCH_CFG[FIFO]
R_FIFO
R_FIFO
R_FSM_IDX
FIFO
FIFO
list index
FIFO configuration
0xFC
A_CHANNEL[FIFO]
R_FIFO
R_FIFO
R_FSM_IDX
FIFO
FIFO
list index
FIFO configuration
0xFD
A_FIFO_SEQ[FIFO]
R_FIFO
R_FIFO
R_FSM_IDX
FIFO
FIFO
list index
FIFO configuration
0xFF
A_IRQ_MSK[FIFO]
R_FIFO
R_FIFO
R_FIFO
FIFO
FIFO
FIFO
..
.
FIFO frame counters
..
.
Please note !
The index of FIFO array registers is always denoted ‘[FIFO]’ even if the meaning
is different from this in particular cases (grey marked fields in Table 3.3).
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Data flow
Data Sheet
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HFC-E1
3.4.1
Data flow
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Simple Mode (SM)
3.4.1.1 Mode description
In Simple Mode (SM) only one-to-one connections are possible. That means one FIFO, one E1 time
slot or one PCM time slot can be connected to each other. The number of connections is limited by
the number of FIFOs. It is possible to establish as many connections as there are FIFOs 6 . The actual
number of FIFOs depends on the FIFO setup (see Section 4.3).
Simple Mode is selected with V_DF_MD = ’00’ in the register R_FIFO_MD. All FIFO array registers
are indexed by the multi-register R_FIFO (address 0x0F) in this data flow mode.
The FIFO number is always the same as the HFC-channel number. Thus, the HFC-channel assigner
cannot be programmed in Simple Mode. In contrast to this, the PCM time slot number can be chosen
independently from the HFC-channel number.
Due to the fixed correspondence between FIFO number and HFC-channel, a pair of transmit and
receive FIFOs is allocated even if a bidirectional data connection between the PCM interface and
the E1 interface is established without using the FIFO. Nevertheless, in this case the FIFO must be
enabled to enable the data transmission.
A direct coupling of two PCM time slots uses a PCM switching buffer and no FIFO has to be enabled.
This connection requires a HFC-channel number (resp. the same FIFO number). An arbitrary HFCchannel number can be chosen. If there are less than 32 transmit and receive FIFOs each, it is usefull
to chose a HFC-channel number that is greater than the maximum FIFO number. This saves FIFO
resources where no data is stored in a FIFO.
3.4.1.2 Subchannel processing
In most applications the subchannel processor is not used in Simple Mode. However, if the data
stream of a FIFO does not require full 8 kByte/s data rate, the subchannel processor might be used.
Unused bits can be masked out and replaced by bits of an arbitrary mask byte which can be specified
in A_CH_MSK.
In transparent mode only the non-masked bits of a byte are processed. Masked bits are taken from
the register A_CH_MSK. So the effective FIFO data rate always remains 8 kByte/s whereas the usable
data rate depends on the number of non-masked bits.
In HDLC mode the data rate of the FIFO is reduced according to how many bits are not masked out.
Please see Section 3.5 on page 125 for details concerning the subchannel processor.
3.4.1.3 Example for SM
Figure 3.6 shows an example with three bidirectional connections (– FIFO-to-E1, — FIFO-to-PCM
and ˜ PCM-to-E1). The FIFO box on the left side contains the number and direction information of
the used FIFOs. The E1 and PCM boxes on the right side contain the E1 time slots and PCM time
slot numbers and directions which are used in this example. Black lines illustrate data paths, whereas
dotted lines symbolize blocked resources. These are not used for the data transmission, but they are
necessary to enable the settings.
6 Except PCM-to-PCM connections which do not need a FIFO resource if the involved HFC-channel number is higher
than the maximum FIFO number.
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Data flow
Please note !
E1 slot
E1 slot
#9 TX
#9 RX
HFCchannel
#9 TX
#9 RX
HFC-channel
HFCchannel
FIFOs
FIFO
All settings in Figure 3.6 are configured in bidirectional data paths due to typical applications of the HFC-E1. However, transmit and receive directions are
independent from each other and could occur one at a time as well.
TX RX
FIFO
RX TX
FIFO
2
HFCchannel
#17 TX
#17 RX
#12 TX
#12 RX
HFCchannel
#12 TX
#12 RX
#17 TX
#17 RX
HFCchannel
PCM slot
E1 slot
#12 TX
#12 RX
HFCchannel
PCM slot
3
HFCchannel
E1 slot
HFCchannel
1
#9 TX
#9 RX
#17 TX
#17 RX
#12 TX
#12 RX
PCM slot
#22 TX
#22 RX
#23 TX
#23 RX
Figure 3.6: SM example
The following settings demonstrate the required register values to establish the connections. All
involved FIFOs have to be enabled with either V_HDLC_TRP = 1 (transparent mode and implicit
FIFO enable) or V_TRP_IRQ = 0 (explicit FIFO enable) in the register A_CON_HDLC[FIFO].
The subchannel processor and the conference unit are not used in this example. For this reason, the
registers A_SUBCH_CFG, A_CH_MSK and A_CONF remain in their reset state.
– FIFO-to-E1
As HFC-channel and FIFO numbers are the same in SM, a selected E1 time slot specifies the
corresponding FIFO (and same in inverse, of course). There is no need of programming the
HFC-channel assigner.
To set up a FIFO-to-E1 connection, the desired E1 channel has to be chosen and the linked
FIFO has to be programmed. Due to the user’s requirements, V_REV can be programmed
either to normal or inverted bit order of the FIFO data.
HDLC or transparent mode (V_HDLC_TRP) can freely be chosen as well. In addition to the
settings shown here, a periodic interrupt (in transparent mode) or a end of frame interrupt (in
HDLC mode) can be enabled.
If HDLC mode is chosen, the FIFO must be enabled with V_TRP_IRQ = 0.
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Data flow
(SM – TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 9
(FIFO #9)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[9,TX] : V_IFF
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’000’
(FIFO → E1, FIFO → PCM)
(SM – RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 9
(FIFO #9)
: V_REV
A_CON_HDLC[9,RX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
(HDLC mode)
(enable FIFO)
(FIFO ← E1)
— FIFO-to-PCM
The FIFO-to-PCM connection can use different numbers for the involved HFC-channels and
PCM time slots. The desired numbers are linked together in the PCM slot assigner.
As the E1 interface assigner links the HFC-channels to the E1-channels, every used HFCchannel blocks the connected E1-channel.
Again, V_REV and V_HDLC_TRP can freely be chosen according to the user’s requirements.
As in the previous setting, a periodic interrupt in transperant mode or a end of frame interrupt
in HDLC mode can be enabled.
(SM — TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 17
(FIFO #17)
: V_REV
A_CON_HDLC[17,TX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’001’
R_SLOT
A_SL_CFG[23,TX]
October 2003
(HDLC mode)
(enable FIFO)
(FIFO → E1, FIFO → PCM)
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 23
(slot #23)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 17
(HFC-channel #17)
: V_ROUT
= ’10’
(data to pin STIO1)
Data Sheet
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Data flow
(SM — RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 17
(FIFO #17)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[17,RX] : V_IFF
(receive FIFO)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
= 1
(FIFO ← PCM)
R_SLOT
: V_SL_DIR
: V_SL_NUM
= 23
(slot #23)
A_SL_CFG[23,RX]
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 17
(HFC-channel #17)
: V_ROUT
= ’10’
(data from pin STIO2)
(receive slot)
˜ PCM-to-E1
A direct PCM-to-E1 coupling is shown in the last connection set. The array registers of
FIFO[12,TX] and FIFO[12,RX] contain the data flow settings, so they must be configured
and the FIFOs must be enabled to switch on the data transmission. This is done with either
V_HDLC_TRP = 1 (transparent mode and implicit FIFO enable) or V_TRP_IRQ = 0 (explicit
FIFO enable) in the register A_CON_HDLC[FIFO].
In receive direction, data is stored in the connected FIFO. But it is not used and needs not to
be read. A FIFO overflow has no effect and can be ignored. Consequently, the V_HDLC_TRP
setting has no effect to the transferred data between the PCM and the E1 interface neither
in receive nor in transmit direction. A PCM-to-E1 connection operates always in transparent
mode.
For a PCM-to-E1 connection, the data direction changes between the two interfaces. In detail,
data is received on a RX line and then transmitted on a TX line to the other interface. Therefore,
a TX-RX-exchanger is necessary for this connection. The blocked FIFOs are on the PCM side
of the TX-RX-exchanger, typically 7 . Like shown in the register setting below, data direction
of FIFO, E1 and PCM lines are never mixed up when programming the assigners.
7 It is not forbidden to connect the blocked FIFOs at the E1 side of the TX-RX-exchanger. ‘Advanced users’ might find
configurations where this is useful. But all typical configuration settings do not require this exceptional option.
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Data flow
(SM ˜ TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
: V_FIFO_NUM
= 12
(FIFO #12)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[12,TX] : V_IFF
: V_HDLC_TRP = 1
(transparent mode)
= 0
(interrupt disabled)
: V_TRP_IRQ
: V_DATA_FLOW = ’110’
R_SLOT
A_SL_CFG[22,TX]
(transmit FIFO)
: V_SL_DIR
= 0
(E1 → PCM)
(transmit slot)
: V_SL_NUM
= 22
(slot #22)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 12
(HFC-channel #12)
: V_ROUT
= ’10’
(data to pin STIO1)
(SM ˜ RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 12
(FIFO #12)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[12,RX] : V_IFF
(receive FIFO)
: V_HDLC_TRP = 1
(transparent mode)
= 0
(interrupt disabled)
: V_TRP_IRQ
: V_DATA_FLOW = ’110’
= 1
(FIFO ← E1, E1 ← PCM)
R_SLOT
: V_SL_DIR
: V_SL_NUM
= 22
(slot #22)
A_SL_CFG[22,RX]
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 12
(HFC-channel #12)
: V_ROUT
= ’10’
(data from pin STIO2)
G
(receive slot)
Rule
In Simple Mode for every used FIFO[n] the HFC-channel[n] is also used. This is
valid in reverse case, too.
3.4.2
Channel Select Mode (CSM)
3.4.2.1 Mode description
The Channel Select Mode (CSM) allows an arbitrary assignment between a FIFO and the connected
HFC-channel as shown in Figure 3.7 (left side). Beyond this, it is possible to connect several FIFOs
to one HFC-channel (Fig. 3.7, right side). This works in transmit and receive direction and can be
used to connect one 8 kByte/s E1 time slot or PCM time slot to multiple FIFO data streams, with
lower data rate each. In this case the subchannel processor must be used.
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Data flow
channel
Assigner
Channel
FIFOs
HFCchannel
FIFO
...
HFCchannel
FIFO
FIFO
channel
assigner
Channel
Figure 3.7: HFC-channel assigner in CSM
Channel Select Mode is selected with V_DF_MD = ’01’ in the register R_FIFO_MD. All FIFO array
registers are indexed by the multi-register R_FIFO (address 0x0F) in this data flow mode.
3.4.2.2 HFC-channel assigner
The connection between a FIFO and a HFC-channel can be established by the A_CHANNEL register
which exists for every FIFO. For a selected FIFO, the HFC-channel to be connected must be written
to V_CH_FNUM of the register A_CHANNEL. Typically, the data direction in V_CH_FDIR is the same
as the FIFO data direction V_FIFO_DIR in the multi-register R_FIFO. With the following register
settings the HFC-channel assigner connects the selected FIFO to HFC-channel n.
Register setup:
A_CHANNEL[FIFO] : V_CH_FDIR
= V_FIFO_DIR
: V_CH_FNUM = n
A direct connection between a PCM time slot and an E1 time slot allocates one FIFO although this
FIFO does not store any data. In Channel Select Mode – in contrast to Simple Mode – an arbitrary
FIFO can be chosen. This FIFO must be enabled to switch on the data transmission. If there are less
than 32 FIFOs in transmit and receive direction, it is necessary to select an existing FIFO number (see
Table 4.3 on page 144).
3.4.2.3 Subchannel Processing
If more than one FIFO is connected to one HFC-channel, this HFC-channel number must be written
into the V_CH_FNUM bitmap of all these FIFOs. In this case every FIFO contributes one or more bits
to construct one HFC-channel byte. Unused bits of a HFC-channel byte can be set with an arbitrary
mask byte in the register A_SUBCH_CFG.
In transparent mode the FIFO data rate always remains 8 kByte/s. In HDLC mode the FIFO data rate
is determined by the number of bits transmitted to the HFC-channel.
Please see Section 3.5 on page 125 for details concerning the subchannel processor.
3.4.2.4 Example for CSM
The example for a Channel Select Mode configuration in Figure 3.8 shows three bidirectional connections (– FIFO-to-E1, — FIFO-to-PCM and ˜ PCM-to-E1). The black lines illustrate data paths,
whereas the dotted lines symbolize blocked resources. These are not used for data transmission, but
they are necessary to enable the settings.
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Data Sheet
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HFC-E1
HFC-channel
E1 slot
E1 slot
#1 TX
#1 RX
HFCchannel
#4 TX
#4 RX
HFCchannel
FIFO
FIFOs
Cologne
Chip
Data flow
FIFO
RX TX
FIFO
2
HFCchannel
#13 TX
#13 RX
#8 TX
#8 RX
HFCchannel
#5 TX
#5 RX
#21 TX
#21 RX
E1 slot
TX RX
HFCchannel
PCM slot
#8 TX
#8 RX
HFCchannel
PCM slot
3
HFCchannel
E1 slot
HFCchannel
1
#1 TX
#1 RX
#21 TX
#21 RX
#8 TX
#8 RX
PCM slot
#7 TX
#7 RX
#17 TX
#17 RX
Figure 3.8: CSM example
The following settings demonstrate the required register values to establish the connections. All
involved FIFOs have to be enabled with either V_HDLC_TRP = 1 (transparent mode and implicit
FIFO enable) or V_TRP_IRQ = 0 (explicit FIFO enable) in the register A_CON_HDLC[FIFO].
The subchannel processor and the conference unit are not used in this example. For this reason, the
registers A_SUBCH_CFG, A_CH_MSK and A_CONF remain in their reset state.
– FIFO-to-E1
HFC-channel and FIFO numbers can be chosen independently from each other. This is shown
in the FIFO-to-E1 connection.
Due to the user’s requirements, V_REV can be programmed either to normal or inverted bit
order of the FIFO data.
HDLC or transparent mode (V_HDLC_TRP) can freely be chosen as well. In addition to the
settings shown here, a periodic interrupt (in transparent mode) or a end of frame interrupt (in
HDLC mode) can be enabled.
If HDLC mode is chosen, the FIFO must be enabled with V_TRP_IRQ = 0.
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Data Sheet
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Data flow
(CSM – TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 4
(FIFO #4)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[4,TX] : V_IFF
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’000’
A_CHANNEL[4,TX]
(FIFO → E1, FIFO → PCM)
: V_CH_FDIR
= 0
(transmit HFC-channel)
: V_CH_FNUM
= 1
(HFC-channel #1)
(CSM – RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 4
(FIFO #4)
: V_REV
A_CON_HDLC[4,RX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
A_CHANNEL[4,RX]
(HDLC mode)
(enable FIFO)
(FIFO ← E1)
: V_CH_FDIR
= 1
(receive HFC-channel)
: V_CH_FNUM
= 1
(HFC-channel #1)
— FIFO-to-PCM
The FIFO-to-PCM connection blocks one transmit and one receive E1 time slot.
Again, V_REV and V_HDLC_TRP can freely be chosen according to the user’s requirements. As in the previous setting, HDLC mode is selected and the FIFOs are enabled with
V_TRP_IRQ = 1.
(CSM — TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 13
(FIFO #13)
: V_REV
A_CON_HDLC[13,TX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’001’
A_CHANNEL[13,TX]
R_SLOT
A_SL_CFG[17,TX]
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(HDLC mode)
(enable FIFO)
(FIFO → E1, FIFO → PCM)
: V_CH_FDIR
= 0
(transmit HFC-channel)
: V_CH_FNUM
= 21
(HFC-channel #21)
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 17
(slot #17)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 21
(HFC-channel #21)
: V_ROUT
= ’10’
(data to pin STIO1)
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Data flow
(CSM — RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 13
(FIFO #13)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[13,RX] : V_IFF
(receive FIFO)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
A_CHANNEL[13,RX]
R_SLOT
A_SL_CFG[17,RX]
(FIFO ← PCM)
: V_CH_FDIR
= 1
(receive HFC-channel)
: V_CH_FNUM
= 21
(HFC-channel #21)
: V_SL_DIR
= 1
(receive slot)
: V_SL_NUM
= 17
(slot #17)
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 21
(HFC-channel #21)
: V_ROUT
= ’10’
(data from pin STIO2)
˜ PCM-to-E1
The PCM-to-E1 connection blocks one transmit and one receive FIFO. Although there is no
data stored in these FIFOs, they must be enabled to switch on the data transmission between
the PCM and the E1 interface.
In receive direction, data is stored in the connected FIFO. But it is not used and needs not to
be read. A FIFO overflow has no effect and can be ignored. Consequently, the V_HDLC_TRP
setting has no effect to the transferred data between the PCM and the E1 interface neither
in receive nor in transmit direction. A PCM-to-E1 connection operates always in transparent
mode.
(CSM ˜ TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 5
(FIFO #5)
: V_REV
A_CON_HDLC[5,TX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 1
: V_TRP_IRQ
= 0
: V_DATA_FLOW = ’110’
A_CHANNEL[5,TX]
R_SLOT
A_SL_CFG[7,TX]
October 2003
(transparent mode)
(interrupt disabled)
(E1 → PCM)
: V_CH_FDIR
= 0
(transmit HFC-channel)
: V_CH_FNUM
= 8
(HFC-channel #8)
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 7
(slot #7)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 8
(HFC-channel #8)
: V_ROUT
= ’10’
(data to pin STIO1)
Data Sheet
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Data flow
(CSM ˜ RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 5
(FIFO #5)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[5,RX] : V_IFF
: V_HDLC_TRP = 1
(transparent mode)
= 0
(interrupt disabled)
: V_TRP_IRQ
: V_DATA_FLOW = ’110’
A_CHANNEL[5,RX]
R_SLOT
A_SL_CFG[7,RX]
G
(FIFO ← E1, E1 ← PCM)
: V_CH_FDIR
= 1
(receive HFC-channel)
: V_CH_FNUM
= 8
(HFC-channel #8)
: V_SL_DIR
= 1
(receive slot)
: V_SL_NUM
= 7
(slot #7)
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 8
(HFC-channel #8)
: V_ROUT
= ’10’
(data from pin STIO2)
Rule
In Channel Select Mode
• every used HFC-channel requires at least one enabled FIFO (except for the
PCM-to-PCM connection) with the same data direction and
• every used PCM time slot requires one HFC-channel (except for the PCMto-PCM connection where a full duplex connection with four time slots
allocates only two HFC-channels).
3.4.3
FIFO Sequence Mode (FSM)
3.4.3.1 Mode description
In contrast to the PCM and E1 time slots, the FIFO data rate is not fixed to 8 kByte/s in FIFO Sequence
Mode. In the previous section the CSM allows the functional capability of a FIFO data rate with less
than 8 kByte/s. This section shows how to use FIFOs with a data rate which is higher than 8 kByte/s.
In transmit direction one FIFO can cyclically distribute its data to several HFC-channels. In opposite
direction, received data from several HFC-channels can be collected cyclically in one FIFO (see
Fig. 3.9, right side). A one-to-one connection between FIFO and HFC-channel is also possible in
FSM, of course (Fig. 3.9, left side).
FIFO Sequence Mode is selected with V_DF_MD = ’11’ in the register R_FIFO_MD. This data flow
mode selects the multi-register R_FSM_IDX at the address 0x0F for some FIFO array registers (see
Table 3.3 on page 106).
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Data Sheet
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HFC-E1
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Data flow
channel
assigner
FIFO
Channel
FIFO
...
HFCchannel
HFCchannel
FIFO
FIFO
channel
assigner
Channels
Figure 3.9: HFC-channel assigner in FSM
3.4.3.2 FIFO sequence
To achieve a FIFO data rate higher than 8 kByte/s, a FIFO must be connected to more than one HFCchannel. As there is only one register A_CHANNEL[FIFO] for each FIFO, the FSM programming
path must differ from the previous modes. Some array registers which are indexed by R_FIFO must
be indexed by R_FSM_IDX in FIFO Sequence Mode (see Table 3.3).
In FSM all FIFOs are organized in a list with up to 64 entries. Every list entry is assigned to a
FIFO. The FIFO configuration can be set up as usual, i.e. HFC-channel allocation, flow controller
programming and subchannel processing can be configured as described in the previous sections.
Additionally, each list entry specifies the next FIFO of the sequence. The list is terminated by an ‘end
of list’ entry. This procedure is shown in Figure 3.10 with j + 1 list entries. The first FIFO of the
sequence must be specified in the register R_FIRST_FIFO.
List
Index
R_FIRST_FIFO
0
channel
configuration
next FIFO
specification
FIFO
configuration
1
channel
configuration
next FIFO
specification
FIFO
configuration
2
channel
configuration
next FIFO
specification
FIFO
configuration
...
...
i
channel
configuration
next FIFO
specification
...
...
j
FIFO
configuration
channel
configuration
end of list
FIFO
configuration
...
63
Figure 3.10: FSM list processing
A quite simple FSM configuration with every FIFO and every HFC-channel specified only one time
in the list, would have the same data transmission result as the CSM with an equivalent FIFO ←→
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Data Sheet
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Data flow
HFC-channel setup. But if a specific FIFO is selected n times in the list and connected to n different
HFC-channels, the FIFO data rate is n · 8 kByte/s.
The complete list is processed every 125 µs with ascending list index beginning with 0. Suppose the
transmit FIFO m occurs several times in the list. Then the first FIFO byte is transferred to the first
connected HFC-channel, the second byte of FIFO m to the second connected HFC-channel and so
on. This is similar in receive data direction. The first byte written into FIFO m comes from the first
connected HFC-channel, the second byte from the second connected HFC-channel and so on.
3.4.3.3 FSM programming
The register R_FSM_IDX specifies the list index with the bitmap V_IDX in the range of 0 . . 63.
R_FSM_IDX is a multi-register and has the same address as R_FIFO because in FSM it replaces
R_FIFO for the list programming of the HFC-channel based registers. The array registers A_CHANNEL,
A_FIFO_SEQ and A_SUBCH_CFG are indexed with the list index V_IDX instead of the FIFO number
(see Table 3.3 on page 106). All other FIFO array registers remain indexed by R_FIFO.
List
Index
...
i-1
channel
configuration
next FIFO
is x
FIFO
configuration
i
channel
configuration
next FIFO
specification
FIFO
configuration
R_FSM_IDX
select
channel p
R_FIFO
(channel p)
(FIFO x)
...
select
FIFO x
A_CHANNEL [i]
A_CON_HDLC [x]
A_SUBCH_CFG [i]
A_IRQ_MSK [x]
A_FIFO_SEQ [i]
A_CH_MSK [p]
Figure 3.11: FSM list programming
The first processed FIFO has to be specified in the register R_FIRST_FIFO with the direction bit
V_FIRST_FIFO_DIR and the FIFO number V_FIRST_FIFO_NUM. The next FIFO has to be specified
in the register A_FIFO_SEQ[V_IDX = 0].
A FIFO handles more than one HFC-channel if a FIFO is specified several times in the ‘next FIFO’
entries.
The FIFO sequence list terminates with V_SEQ_END = 1 in the register A_FIFO_SEQ. The other list
entries must specify V_SEQ_END = 0 to continue the sequence processing with the next entry.
Programming of the HFC-channel and FIFO registers is shown in Figure 3.11. The connected HFCchannel array registers are indexed by the list index which is written into the R_FSM_IDX register.
On the other hand, FIFO array registers are indexed by the register R_FIFO as usual.
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Data Sheet
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HFC-E1
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Data flow
• After writing the list index i into the register R_FSM_IDX, the registers A_CHANNEL[i] and
A_SUBCH_CFG[i] can be programmed to assign and configure an HFC-channel.
• The next FIFO in the sequence must be specified in the register A_FIFO_SEQ[i].
• Supposed, that the previous list entry i − 1 has specified A_FIFO_SEQ[i − 1] = FIFO x, then the
corresponding FIFO array registers have to be programmed by first setting R_FIFO = x. Afterwards, the registers A_CON_HDLC[x], A_IRQ_MSK[x] and A_CH_MSK can be programmed in
the usual way. Please note, that the register A_CH_MSK requires the addressed HFC-channel
to be specified in the register R_FIFO (see remark on page 126).
3.4.3.4 Example for FSM
#4 TX
#4 RX
E1 slot
HFCchannel
1
FIFO
E1 slot
E1 slot
#12 TX
#12 RX
HFCchannel
HFC-channel
HFCchannel
#12 TX
#12 RX
#14 TX
#14 RX
HFCchannel
3
HFCchannel
#13 TX
#13 RX
2
#15 TX
#15 RX
HFCchannel
PCM slot
FIFO
E1 slot
HFCchannel
E1 slot
#5 TX
#5 RX
HFCchannel
FIFOs
FIFO
Figure 3.12 shows an example with three bidirectional connections (– 8 kByte/s-FIFO-to-E1,
— 8 kByte/s-FIFO-to-PCM and ˜ 16 kByte/s-FIFO-to-E1). The black lines illustrate data paths,
whereas the dotted lines symbolize blocked HFC-channels. These are not used for data transmission,
but they are necessary to enable the settings.
#12 TX
#12 RX
#4 TX
#4 RX
#5 TX
#5 RX
#15 TX
#15 RX
PCM slot
#21 TX
#21 RX
Figure 3.12: FSM example
The following settings demonstrate the required register values to establish the connections. All
involved FIFOs have to be enabled with either V_HDLC_TRP = 1 (transparent mode and implicit
FIFO enable) or V_TRP_IRQ = 0 (explicit FIFO enable) in the register A_CON_HDLC[FIFO].
The subchannel processor and the conference unit are not used in this example. For this reason, the
registers A_SUBCH_CFG, A_CH_MSK and A_CONF remain in their reset state.
All FIFOs can be arranged in arbitrary order. In the example the list specification of Table 3.4 is
chosen. To select FIFO[12,TX] beeing the first FIFO, R_FIRST_FIFO is set as follows:
October 2003
Data Sheet
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Data flow
Register setup:
R_FIRST_FIFO : V_FIRST_FIFO_DIR
= 0
(transmit FIFO)
: V_FIRST_FIFO_NUM = 12
(FIFO #12)
Table 3.4: List specification of the example in Figure 3.12
Example
number
List index
Connection
–
–
—
—
˜
˜
˜
˜
0
FIFO[12,TX]
→
E1 slot[12,TX]
1
FIFO[12,RX]
←
E1 slot[12,TX]
2
FIFO[13,RX]
←
PCM time slot[21,RX]
3
FIFO[13,TX]
→
PCM time slot[21,TX]
4
FIFO[14,TX]
→
E1 slot[4,TX]
5
FIFO[14,RX]
←
E1 slot[4,RX]
6
FIFO[14,TX]
→
E1 slot[5,TX]
7
FIFO[14,RX]
←
E1 slot[5,RX]
– FIFO-to-E1
The bidirectional FIFO-to-E1 connection use the list indices 0 and 1. The registers A_CHANNEL
and A_FIFO_SEQ are indexed by the list index.
(FSM – list indices 0 and 1)
Register setup:
R_FSM_IDX
: V_IDX
A_CHANNEL[#0] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#0] : V_NEXT_FIFO_DIR
= 0
(List index #0, used for FIFO[12,TX])
= 0
(transmit HFC-channel)
= 12
(HFC-channel #12)
= 1
(next: receive FIFO)
: V_NEXT_FIFO_NUM = 12
: V_SEQ_END
R_FSM_IDX
: V_IDX
A_CHANNEL[#1] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#1] : V_NEXT_FIFO_DIR
= 0
(continue)
= 1
(List index #1, used for FIFO[12,RX])
= 1
(receive HFC-channel)
= 12
(HFC-channel #12)
= 1
(next: receive FIFO)
: V_NEXT_FIFO_NUM = 13
: V_SEQ_END
(next: FIFO #12)
= 0
(next: FIFO #13)
(continue)
The FIFO programming sequence is indexed by the FIFO number and direction. V_REV,
V_HDLC_TRP and V_TRP_IRQ can be programmed due to the user’s requirements. FIFO[12,TX]
and FIFO[12,RX] must both be enabled.
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Data Sheet
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HFC-E1
(FSM – FIFO programming for list indices 0 and 1)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
: V_FIFO_NUM
= 12
(FIFO #12)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[12,TX] : V_IFF
(transmit FIFO)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’000’
R_FIFO
Cologne
Chip
Data flow
(FIFO → E1, FIFO → PCM)
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 12
(FIFO #12)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[12,RX] : V_IFF
(receive FIFO)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’000’
(FIFO ← E1)
— FIFO-to-PCM
The following two list entries (indices 2 and 3) define the bidirectional FIFO-to-PCM connection. Two E1 time slots are blocked. But E1 time slot resources are saved because the
HFC-channels are assigned to an E-channel which is normally not used and an unused transmit
channel.
(FSM — list indices 2 and 3)
Register setup:
R_FSM_IDX
: V_IDX
A_CHANNEL[#2] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#2] : V_NEXT_FIFO_DIR
= 2
(List index #2, used for FIFO[13,RX])
= 1
(receive HFC-channel)
= 15
(HFC-channel #15)
= 0
(next: transmit FIFO)
: V_NEXT_FIFO_NUM = 13
: V_SEQ_END
R_FSM_IDX
: V_IDX
A_CHANNEL[#3] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#3] : V_NEXT_FIFO_DIR
= 0
= 3
(List index #3, used for FIFO[13,TX])
= 0
(transmit HFC-channel)
= 15
(HFC-channel #15)
= 0
(next: transmit FIFO)
: V_NEXT_FIFO_NUM = 14
: V_SEQ_END
October 2003
(next: FIFO #13)
(continue)
= 0
(next: FIFO #14)
(continue)
Data Sheet
121 of 306
HFC-E1
(FSM — RX FIFO programming for list indices 2 and 3)
Register setup:
R_FIFO
Cologne
Chip
Data flow
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 13
(FIFO #13)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[13,RX] : V_IFF
(receive FIFO)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
= 1
(FIFO ← PCM)
R_SLOT
: V_SL_DIR
: V_SL_NUM
= 21
(slot #21)
A_SL_CFG[21,RX]
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 15
(HFC-channel #15)
: V_ROUT
= ’10’
(data from pin STIO2)
(FSM — TX FIFO programming for list indices 2 and 3)
Register setup:
R_FIFO
(receive slot)
: V_FIFO_DIR
= 0
: V_FIFO_NUM
= 13
(FIFO #13)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[13,TX] : V_IFF
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
R_SLOT
A_SL_CFG[21,TX]
(transmit FIFO)
: V_SL_DIR
= 0
(FIFO → E1, FIFO → PCM)
(transmit slot)
: V_SL_NUM
= 21
(slot #21)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 15
(HFC-channel #15)
: V_ROUT
= ’10’
(data to pin STIO1)
˜ FIFO to multiple E1 time slots
The last setting shows a channel bundling configuration of one FIFO to two B-channels of the
E1 interface for both transmit and receive directions. The FIFOs have a data rate of 16 kByte/s
each.
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Chip
Data flow
(FSM ˜ list indices 4 and 5)
Register setup:
R_FSM_IDX
: V_IDX
A_CHANNEL[#4] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#4] : V_NEXT_FIFO_DIR
= 4
(List index #4, used for FIFO[14,TX])
= 0
(transmit HFC-channel)
= 4
(HFC-channel #4)
= 1
(next: receive FIFO)
: V_NEXT_FIFO_NUM = 14
: V_SEQ_END
R_FSM_IDX
: V_IDX
A_CHANNEL[#5] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#5] : V_NEXT_FIFO_DIR
= 0
= 5
(List index #5, used for FIFO[14,RX])
= 1
(receive HFC-channel)
= 4
(HFC-channel #4)
= 0
(next: transmit FIFO)
: V_NEXT_FIFO_NUM = 14
: V_SEQ_END
= 0
(next: FIFO #14)
(continue)
(FSM ˜ FIFO programming for list indices 4 and 5)
Register setup:
R_FIFO
(next: FIFO #14)
(continue)
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 14
(FIFO #14)
: V_REV
A_CON_HDLC[14,TX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
R_FIFO
(HDLC mode)
(enable FIFO)
(FIFO → E1, FIFO → PCM)
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 14
(FIFO #14)
: V_REV
A_CON_HDLC[14,RX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
(HDLC mode)
(enable FIFO)
(FIFO ← E1)
When the FIFO[14,TX] and FIFO[14,RX] are used for the second time, they need not to be
programmed again. So just the HFC-channels have to programmed for the list indices #6 and
#7.
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HFC-E1
(FSM ˜ list indices 6 and 7)
Register setup:
R_FSM_IDX
: V_IDX
A_CHANNEL[#6] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#6] : V_NEXT_FIFO_DIR
= 6
(List index #6, used for FIFO[14,TX])
= 0
(transmit HFC-channel)
= 5
(HFC-channel #5)
= 1
(next: receive FIFO)
: V_NEXT_FIFO_NUM = 14
: V_SEQ_END
R_FSM_IDX
Cologne
Chip
Data flow
: V_IDX
A_CHANNEL[#7] : V_CH_FDIR
: V_CH_FNUM
A_FIFO_SEQ[#7] : V_NEXT_FIFO_DIR
= 0
(next: FIFO #14)
(continue)
= 7
(List index #7, used for FIFO[14,RX])
= 1
(receive HFC-channel)
= 5
(HFC-channel #5)
= 0
: V_NEXT_FIFO_NUM = 0
: V_SEQ_END
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= 1
(end of list)
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Data flow
3.5 Subchannel Processing
3.5.1
Overview
Data transmission between a FIFO and the connected HFC-channel can be controlled by the subchannel processor. The behavior of this functional unit depends on the selected data flow mode (SM,
CSM or FSM) and the operation mode of the HDLC controller (transparent or HDLC mode). The
subchannel controller allows to process less than 8 bits of the transferred FIFO data bytes.
The subchannel processor cannot be used for direct PCM-to-E1 or PCM-to-PCM connections, because a FIFO must participate in the data flow.
A general overview of the subchannel processor in transmit direction is shown as an simplified example in Figure 3.13. Three transmit FIFOs are connected to one HFC-channel. Details of subchannel
processing are described in the following sections, partitioned into the different modes of the data
flow and the HDLC controller.
FIFO b
byte b1
byte b2
byte b3
...
FIFO data output
7
0
FIFO c
byte c1
byte c2
byte c3
...
FIFO data output
7
0
7
FIFO
c
data
m
a
bi sk
t
FIFO data output
7
0
m
a
bi sk
t
FIFO a
byte a1
byte a2
byte a3
...
0
FIFO FIFO FIFO FIFO FIFO
a
a
a
b
b
data data data data data
HFC-channel
byte
HFC-channel mask
Figure 3.13: General structure of the subchannel processor shown with an example of three connected FIFOs
The essence of the subchannel processor is a bit extraction / insertion unit for every FIFO and a byte
mask for every HFC-channel. Therefore, the subchannel processor is divided into two parts A and B.
The behaviour of the FIFO oriented part A depends on the HDLC or transparent mode selection.
The HFC-channel oriented part B has a different behaviour due to the selected data flow SM or
CSM / FSM.
3.5.1.1 Registers
The FIFO bit extraction / insertion requires two register settings. V_BIT_CNT defines the number of
bits to be extracted / inserted. These bits are always aligned to position 0 in the FIFO data. This
bit field can freely be placed in the HFC-channel byte. For this, the start bit can be selected with
V_START_BIT in the range of 0 . . 7. Both values are located in the register A_SUBCH_CFG[FIFO].
The HFC-channel mask can be stored in the register A_CH_MSK[FIFO]. This mask is only used for
transmit data. The processed FIFO bits are stored in this register, so it must be re-initialized after
changing the settings in A_SUBCH_CFG[FIFO]. Each HFC-channel has its own mask byte. To write
this byte for HFC-channel [n,TX], the HFC-channel must be written into the multi-register R_FIFO
first. The desired mask byte m can be written with A_CH_MSK = m after this index selection.
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Chip
Data flow
Important !
Typically, the multi-register R_FIFO contains always a FIFO index. There is one
exception where the R_FIFO value has a different meaning: The HFC-channel
mask byte A_CH_MSK is programmed by writing the HFC-channel into the
R_FIFO register.
The default subchannel configuration of the register A_SUBCH_CFG leads to a transparent behavior.
That means, only complete data bytes are transmitted in receive and transmit direction.
3.5.2
Details of the FIFO oriented part of the subchannel processor (part A)
The subchannel processor part A lies between the HDLC controller and the HFC-channel assigner.
Figure 3.14 shows the block diagram for both receive and transmit data directions.
At the HDLC controller side, there are a data path and two control lines. These communicate the
number of bits to be processed and the HDLC / transparent mode selection between the two modules.
In transparent mode always one byte is transferred between the HDLC controller and the subchannel
controller part A every 125 µs cycle. In HDLC mode the number of bits is specified by the subchannel
bitmap V_BIT_CNT in the register A_SUBCH_CFG[FIFO].
On the other side, the data path between subchannel processor part A and the HFC-channel assigner
transfers always one byte in transmit and receive direction during every 125 µs cycle.
3.5.2.1 FIFO transmit operation in transparent mode
In transparent mode every FIFO has a data rate of 8 kByte/s. Every 125 µs one byte of
a FIFO is processed. The number of bits specified in V_BIT_CNT is placed at position
[V_START_BIT+V_BIT_CNT−1 . . V_START_BIT] while the other bits are not used and will be overwritten from the HFC-channel mask in part B of the subchannel processor.
3.5.2.2 FIFO transmit operation in HDLC mode
The HDLC mode allows to reduce the data rate of a FIFO. With every 125 µs cycle the subchannel
processor requests V_BIT_CNT bits from the HDLC controller. The FIFO data rate is
DRFIFO =
V_BIT_CNT kBit/s
: V_BIT_CNT > 0
8 kBit/s
: V_BIT_CNT = 0
or might be a little lower due to the bit stuffing (zero insertion).
3.5.2.3 FIFO receive operation in transparent mode
The subchannel processor part A receives one byte every 125 µs cycle. Typically, only some bits –
depending on the usage mode of this receive channel – contain valid data. V_START_BIT defines the
position of the valid bit field in the received HFC-channel byte. The subchannel processor part A shifts
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Data Sheet
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HFC-E1
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Chip
7
0
a a a
HFCchannel
x x x x x b b b
data to/from HFC-channel
(exemplarily shown
b1[2] b1[1] b1[0] for V_BIT_CNT = 0 in transp. mode
or V_BIT_CNT = 3 in HDLC mode
and for V_START_BIT = 1)
controller
HDLC or transparent mode
(for TX and RX separately)
(exemplarily shown
for V_BIT_CNT = 3
and V_START_BIT = 1)
FIFO
a1[2] a1[1] a1[0]
data
proc
TX data (processed from FIFO a)
RX data (processed to FIFO b)
Subchannel processor
(FIFO oriented part A)
data
proc
HDLC
controller
8 bit in transp. mode,
n bit in HDLC mode
Data flow
for TX and RX:
V_START_BIT
V_START_BIT
V_BIT_CNT
V_BIT_CNT
HDLC or transparent mode
(for TX and RX separately)
7
0
HFCchannel
data
proc
c
x x x x x x x d
V_START_BIT
V_START_BIT
V_BIT_CNT
V_BIT_CNT
data to/from HFC-channel
(exemplarily shown
d1[0] for V_BIT_CNT = 0 in transp. mode
or V_BIT_CNT = 1 in HDLC mode
and for V_START_BIT = 6)
controller
for TX and RX:
number of bits
(for TX and RX separately)
(exemplarily shown
for V_BIT_CNT = 1
and V_START_BIT = 6)
FIFO
c1[0]
data
proc
TX data (processed from FIFO c)
RX data (processed to FIFO d)
8 bit in transp. mode,
n bit in HDLC mode
number of bits
(for TX and RX separately)
a
data bit to be transferred to or from
FIFO a
unused data bit (will be overwritten
by the HFC-channel mask)
x not usable data bit (should be
masked out by software)
Figure 3.14: Part A of the subchannel processor
the valid bit field to position 0 before a whole byte is transferred to the HDLC controller. The invalid
bits must be masked out by software. The FIFO data rate is always 8 kByte/s in this configuration.
If transparent mode is selected, V_BIT_CNT must always be ’000’ in receive direction. The number of
valid bits must be handled by the software.
3.5.2.4 FIFO receive operation in HDLC mode
From every received HFC-channel data byte only V_BIT_CNT bits beginning at position V_START_BIT
contain valid data. Only these bits are transferred to the HDLC controller. So the FIFO data rate is
V_BIT_CNT kBit/s : V_BIT_CNT > 0
DRFIFO =
8 kBit/s : V_BIT_CNT = 0
or might be a little lower due to the bit stuffing (zero deletion).
October 2003
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3.5.3
Cologne
Chip
Data flow
Details of the HFC-channel oriented part of the subchannel processor (part B)
Part B of the subchannel processor is located inside the HFC-channel area. With every 125 µs cycle
it transmits and receives always one data byte to / from the connected interface (either PCM or E1
interface). On the other side, to / from every connected HFC-channel assigner one byte is transferred
in both transmit and receive directions. Figure 3.15 shows the block diagram of this module.
Subchannel processor
(HFC-channel oriented part B)
data
proc
FIFO
a a a
HFCchannel
TX data
(processed from FIFO a)
RX data
(processed to FIFO b)
(exemplarily shown for two connected FIFOs
in CSM with three bits [3..1] from/for FIFO a/b
and one bit [6] from/for FIFO c/d.
7
0
data inside the HFC-channel,
transferred to/from E1 interface
assigner or PCM slot assigner
1 c 1 1 a a a 0
x d x x b b b x
controller
1 0 1 1 0 0 0 0
for TX only:
c
HFCchannel
TX data
(processed from FIFO c)
RX data
(processed to FIFO d)
FIFO
in CSM / FSM only:
a
V_CH_MSK
data bit to be transferred to or
from FIFO a
0 1 mask bit
x
not usable data bit (should be
masked out by software)
Figure 3.15: Part B of the subchannel processor
3.5.3.1 FIFO transmit operation in SM
As the FIFO and HFC-channel numbers are the same in Simple Mode, only one FIFO can be connected to a HFC-channel. Subchannel processing can do nothing more than masking out some bits of
every transmitted data byte.
The specified bit field is put into the HFC-channel mask byte before the data byte is transmitted to
the connected interface.
3.5.3.2 FIFO transmit operation in CSM and FSM
In Channel Select Mode and FIFO Sequence Mode, several FIFOs can contribute data to one HFCchannel data byte. From every connected HFC-channel assigner, one or more bits are extracted and
are joined to a single HFC-channel data byte.
Here, the subchannel processor works in the same way as in Simple Mode, except that multiple bit
insertion is performed. All FIFOs which contribute data bits to the HFC-channel byte should specify
different bit locations to avoid overwriting data.
3.5.3.3 FIFO receive operation in SM
The received data byte is transferred to the HFC-channel assigner without modification. Part B of the
subchannel processor has no effect to the receive data. Typically, only some bits contain valid data
which will be extracted by the part A of the subchannel processor.
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Chip
Data flow
3.5.3.4 FIFO receive operation in CSM and FSM
If there are several FIFOs connected to one receive HFC-channel in Channel Select Mode or FIFO
Sequence Mode, every received data byte is transferred to all connected HFC-channel assigners without modification. Part B of the subchannel processor has no effect to the receive data. Typically, the
HFC-channel data byte contains bit fields for several FIFOs which will be extracted by their part A of
the subchannel processor.
3.5.4
Subchannel example for SM
The subchannel processing example in Figure 3.16 shows two bidirectional configurations (– FIFOto-E1 and — FIFO-to-PCM) in Simple Mode.
G
Please note !
All subchannel examples in this document have always the same number of bits
and the same start bit for corresponding transmit and receive FIFOs. Actually,
transmit and receive configuration settings are independently from each other.
The settings are chosen for clearness and can simply be reproduced with looped
data pathes.
HFC-channel
FIFOs
7
a a a
0
1 0 1 1 a a a 0
x x x x b b b x
#1 TX
#1 RX
0
FIFO
7
Subchannel processor
part B
7
c c c
x x x x x d d d
HFCchannel
#31 TX
#31 RX
HDLC
controller
Subchannel processor
part A
0
1 0 c c c 0 1 1
x x d d d x x x
2
#31 TX
#31 RX
HFCchannel
PCM slot
E1 slot
HFCchannel
x x x x x b b b
1
E1 slot
0
FIFO
7
HFCchannel
HDLC
controller
#1 TX
#1 RX
Subchannel processor
part B
HFCchannel
E1 interf.
Subchannel processor
part A
#1 TX
#1 RX
#31 TX
#31 RX
PCM slot
#7 TX
#7 RX
Figure 3.16: SM example with subchannel processor
– FIFO-to-E1 (TX)
The first setting shows a FIFO-to-E1 data transmission in transparent mode.
The register A_SUBCH_CFG[FIFO] defines three bits [2 . . 0] to be transmitted from each FIFO
byte. These bits have the position [3 . . 1] in the HFC-channel data byte.
All other data bits in the HFC-channel byte are defined by the HFC-channel mask V_CH_MSK
= ’1011 0000’ in the register A_CH_MSK. This array register must be selected by writing the
October 2003
Data Sheet
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Chip
Data flow
HFC-channel number and direction into the register R_FIFO. The mask bits [3 . . 1] are don’t
care because they are overwritten from the FIFO data.
A detailed overview of the transmitted data is shown in Table 3.5. The first data byte
in FIFO[1,TX] is a1 , the second byte is a2 , and so on. In transparent mode only
(a1 [2 . . 0], a2 [2 . . 0], . . . ) are placed in the HFC-channel bytes at the location [3 . . 1] and
(a1 [7 . . 3], a2 [7 . . 3], . . . ) are ignored and replaced by the HCF-channel mask.
(SM – TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 1
(FIFO #1)
: V_REV
A_CON_HDLC[1,TX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 1
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
A_SUBCH_CFG[1,TX] : V_BIT_CNT
: V_START_BIT
= 3
= 1
: V_LOOP_FIFO = 0
R_FIFO
A_CH_MSK[1,TX]
(transparent mode)
(interrupt all 64 bytes)
(FIFO → E1, FIFO → PCM)
(process 3 bits)
(start with bit 1)
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_FIFO_DIR
= 0
(transmit HFC-channel)
: V_FIFO_NUM
= 1
(HFC-channel #1)
: V_REV
= 0
(normal bit order)
: V_CH_MSK
= ’10110000’
(mask byte)
– FIFO-to-E1 (RX)
Only three bits [3 . . 1] from the received HFC-channel byte are assumed to be valid data. Nevertheless, the number of received bits must be set to the value V_BIT_CNT = 0 which means ‘one
byte’. The start position is specified with V_START_BIT = 1 in the register A_SUBCH_CFG.
As the received bit field is aligned to position 0, these bits represent FIFO data b[2 . . 0].
A detailed overview of the received data is shown in Table 3.6. The first data byte in FIFO[1,RX]
is b1 , the second byte is b2 , and so on. Only (b1 [2 . . 0], b2 [2 . . 0], . . . ) contain valid data and
(b1 [7 . . 3], b2 [7 . . 3], . . . ) must be masked out by software.
(SM – RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 1
(FIFO #1)
: V_REV
A_CON_HDLC[1,RX] : V_IFF
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 1
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
A_SUBCH_CFG[1,RX] : V_BIT_CNT
: V_START_BIT
= 0
= 1
: V_LOOP_FIFO = 0
: V_INV_DATA
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Data Sheet
(transparent mode)
(interrupt all 64 bytes)
(FIFO ← E1)
(process 8 bits)
(start with bit 1)
(normal operation)
(normal data transmission)
October 2003
HFC-E1
Cologne
Chip
Data flow
Table 3.5: Subchannel processing according to Figure 3.16 (SM – TX, transparent mode)
7
0
HFC-channel mask:
1
0
1
1
0
0
0
0
HFC-channel transmit byte 1:
1
0
1
1
a1 [2]
a1 [1]
a1 [0]
0
HFC-channel transmit byte 2:
1
0
1
1
a2 [2]
a2 [1]
a2 [0]
0
HFC-channel transmit byte 3:
1
0
1
1
a3 [2]
a3 [1]
a3 [0]
0
...
...
Table 3.6: Subchannel processing according to Figure 3.16 (SM – RX, transparent mode)
7
0
HFC-channel receive byte 1:
x
x
x
x
b1 [2]
b1 [1]
b1 [0]
x
HFC-channel receive byte 2:
x
x
x
x
b2 [2]
b2 [1]
b2 [0]
x
HFC-channel receive byte 3:
x
x
x
x
b3 [2]
b3 [1]
b3 [0]
x
...
...
— FIFO-to-PCM (TX)
The second Simple Mode configuration connects a FIFO in HDLC mode with the PCM interface 8 . The bitmap V_BIT_CNT in the register A_SUBCH_CFG[FIFO] defines three FIFO data
bits to be transmitted during every 125 µs cycle. The bit field location in the HFC-channel data
byte is specified by the bitmap V_START_BIT in the same register.
All other data bits in the HFC-channel are defined by the HFC-channel mask in the register A_CH_MSK. This array register must be selected by writing the HFC-channel number and
direction into the register R_FIFO. The mask bits [5 . . 3] are don’t care because they are overwritten from the FIFO data.
A detailed overview of the transmitted data is shown in Table 3.7. The first data byte in
FIFO[31,TX] is c1 , the second byte is c2 , and so on. In HDLC mode, FIFO bytes are dispersed among several HFC-channel bytes.
8 HDLC
bit stuffing is not shown in this example.
October 2003
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Chip
Data flow
(SM — TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
: V_FIFO_NUM
= 31
(FIFO #31)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[31,TX] : V_IFF
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
A_SUBCH_CFG[31,TX] : V_BIT_CNT
: V_START_BIT
(FIFO → E1, FIFO → PCM)
= 3
(process 3 bits)
= 3
(start with bit 3)
: V_LOOP_FIFO = 0
R_FIFO
(transmit FIFO)
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_FIFO_DIR
= 0
(transmit HFC-channel)
: V_FIFO_NUM
= 31
(HFC-channel #31)
: V_REV
= 0
(normal bit order)
A_CH_MSK[31,TX]
: V_CH_MSK
= ’10110011’
(mask byte)
R_SLOT
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 7
(slot #7)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 31
(HFC-channel #31)
: V_ROUT
= ’10’
(data to pin STIO1)
A_SL_CFG[7,TX]
— FIFO-to-PCM (RX)
Only three bits [5 . . 3] from the received HFC-channel byte are assumed to be valid data. This is
done with the bitmaps V_BIT_CNT = 3 and V_START_BIT = 3 in the register A_SUBCH_CFG.
The bit field is aligned to position 0 and transferred to the HDLC controller. There, FIFO data
bytes are constructed from several received bit fields.
A detailed overview of the received data is shown in Table 3.8. The first data byte in FIFO[31,RX]
is d1 , the second byte is d2 , and so on. In HDLC mode, FIFO bytes are constructed from several
HFC-channel bytes.
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Chip
Data flow
(SM — RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 31
(FIFO #31)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[31,RX] : V_IFF
(receive FIFO)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
A_SUBCH_CFG[31,RX] : V_BIT_CNT
: V_START_BIT
(FIFO ← PCM)
= 3
(process 3 bits)
= 3
(start with bit 3)
: V_LOOP_FIFO = 0
R_SLOT
A_SL_CFG[7,RX]
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_SL_DIR
= 1
(receive slot)
: V_SL_NUM
= 7
(slot #7)
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 31
(HFC-channel #31)
: V_ROUT
= ’10’
(data from pin STIO2)
Table 3.7: Subchannel processing according to Figure 3.16 (SM — TX, HDLC mode)
7
0
HFC-channel mask:
1
0
0
0
0
0
1
1
HFC-channel transmit byte 1:
1
0
c1 [2]
c1 [1]
c1 [0]
0
1
1
HFC-channel transmit byte 2:
1
0
c1 [5]
c1 [4]
c1 [3]
0
1
1
HFC-channel transmit byte 3:
1
0
c2 [0]
c1 [7]
c1 [6]
0
1
1
HFC-channel transmit byte 4:
1
0
c2 [3]
c2 [2]
c2 [1]
0
1
1
...
3.5.5
...
Subchannel example for CSM
In Channel Select Mode up to 8 FIFOs can be assigned to one HFC-channel if only 1 bit is processed
by every FIFO. The example in Figure 3.17 shows two bidirectional configurations (– FIFO-to-E1
and — FIFO-to-PCM) with two FIFOs per direction each.
– FIFO-to-E1 (TX)
In the first setting two transmit FIFOs are connected to one HFC-channel. Transparent mode is
selected in this example.
The registers A_SUBCH_CFG[FIFO] of FIFO[4,TX] and FIFO[5,TX] define both, the number
of bits to be extracted from the FIFO data bytes and their position in the HFC-channel byte.
October 2003
Data Sheet
133 of 306
HFC-E1
Cologne
Chip
Data flow
Table 3.8: Subchannel processing according to Figure 3.16 (SM — RX, HDLC mode)
7
0
HFC-channel receive byte 1:
x
x
d1 [2]
d1 [1]
d1 [0]
x
x
x
HFC-channel receive byte 2:
x
x
d1 [5]
d1 [4]
d1 [3]
x
x
x
HFC-channel receive byte 3:
x
x
d2 [0]
d1 [7]
d1 [6]
x
x
x
HFC-channel receive byte 4:
x
x
d2 [3]
d2 [2]
d2 [1]
x
x
x
Subchannel processor
part A
7
0
#1 TX
#1 RX
HFCchannel
HFCchannel
1
0
E1 slot
HFCchannel
HFCchannel
e e e
x x x x x f f f
7
0
Subchannel processor
part B
7
0
1 0 e e e g 0 0
x x f f f h x x
#31 TX
#31 RX
g
h
#1 TX
#1 RX
#31 TX
#31 RX
2
HFCchannel
PCM slot
7
HFCchannel
HDLC
controller
HDLC
controller
#8 RX
0
c c 0 0 a a a 1
FIFO
d d
Subchannel processor
part A
#8 TX
7
E1 slot
0
Subchannel processor
part A
#12 TX
#12 RX
E1 interf.
c c
FIFO
HDLC
controller
7
Subchannel processor
part B
d d x x b b b x
FIFO
x x x x x b b b
Subchannel processor
part A
#5 TX
#5 RX
HFC-channel
a a a
PCM slot
#7 TX
#7 RX
HFCchannel
#4 TX
#4 RX
HDLC
controller
FIFOs
...
FIFO
...
Figure 3.17: CSM example with subchannel processor
The HFC-channel mask in the register A_CH_MSK defines the bit values that are not used
for FIFO data. The array register must be selected by writing the HFC-channel number and
direction into the register R_FIFO. The mask bits [7 . . 6, 3 . . 1] are don’t care because they are
overwritten from the FIFO data.
A detailed overview of the transmitted data is shown in Table 3.9. The first data byte in
FIFO[4,TX] is a1 , the second byte is a2 , and so on. FIFO[5,TX] is represented by the data
bytes c1 , c2 , and so on.
134 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Data flow
(CSM – TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 4
(FIFO #4)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[4,TX] : V_IFF
: V_HDLC_TRP = 1
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
A_CHANNEL[4,TX]
(transmit HFC-channel)
: V_CH_FNUM
= 1
(HFC-channel #1)
= 3
(process 3 bits)
= 1
: V_LOOP_FIFO = 0
= 0
(normal data transmission)
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 5
(FIFO #5)
: V_REV
= 0
(normal bit order)
= 0
: V_HDLC_TRP = 1
: V_TRP_IRQ
= 1
: V_DATA_FLOW = ’000’
: V_CH_FDIR
: V_CH_FNUM
A_SUBCH_CFG[5,TX] : V_BIT_CNT
: V_START_BIT
= 0
(0x7E as inter frame fill)
(transparent mode)
(interrupt all 64 bytes)
(FIFO → E1, FIFO → PCM)
(transmit HFC-channel)
= 1
(HFC-channel #1)
= 2
(process 2 bits)
= 6
(start with bit 6)
: V_LOOP_FIFO = 0
A_CH_MSK[0,TX]
(start with bit 1)
(normal operation)
: V_INV_DATA
A_CON_HDLC[5,TX] : V_IFF
R_FIFO
(FIFO → E1, FIFO → PCM)
= 0
: V_START_BIT
A_CHANNEL[5,TX]
(interrupt all 64 bytes)
: V_CH_FDIR
A_SUBCH_CFG[4,TX] : V_BIT_CNT
R_FIFO
(transparent mode)
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_FIFO_DIR
= 0
(transmit HFC-channel)
: V_FIFO_NUM
= 1
(HFC-channel #1)
: V_REV
= 0
(normal bit order)
: V_CH_MSK
= ’0000 0001’
(mask byte)
– FIFO-to-E1 (RX)
The received HFC-channel byte is distributed to two FIFOs. The bit fields [7 . . 6] and [3 . . 1]
from the received HFC-channel byte are assumed to be valid data. Nevertheless, the number
of received bits must be set to the value V_BIT_CNT = 0 which means ‘one byte’. The start
position is specified with V_START_BIT in the register A_SUBCH_CFG. As the received bit
fields are aligned to position 0, these bits represent FIFO data b[2 . . 0] and d[1 . . 0].
A detailed overview of the received data is shown in Table 3.10. The first data byte in FIFO[4,RX]
is b1 , the second byte is b2 , and so on. FIFO[5,RX] data bytes are d1 , d2 , and so on.
October 2003
Data Sheet
135 of 306
HFC-E1
Cologne
Chip
Data flow
(CSM – RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 4
(FIFO #4)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[4,RX] : V_IFF
: V_HDLC_TRP = 1
(transparent mode)
= 1
: V_TRP_IRQ
(interrupt all 64 bytes)
: V_DATA_FLOW = ’000’
A_CHANNEL[4,RX]
= 1
(receive HFC-channel)
: V_CH_FNUM
= 1
(HFC-channel #1)
= 0
(process 8 bits)
A_SUBCH_CFG[4,RX] : V_BIT_CNT
= 1
: V_START_BIT
(start with bit 1)
: V_LOOP_FIFO = 0
R_FIFO
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 5
(FIFO #5)
: V_REV
= 0
(normal bit order)
= 0
A_CON_HDLC[5,RX] : V_IFF
(0x7E as inter frame fill)
: V_HDLC_TRP = 1
(transparent mode)
= 1
: V_TRP_IRQ
(interrupt all 64 bytes)
: V_DATA_FLOW = ’000’
A_CHANNEL[5,RX]
(FIFO ← E1)
: V_CH_FDIR
= 1
: V_CH_FDIR
: V_CH_FNUM
A_SUBCH_CFG[5,RX] : V_BIT_CNT
: V_START_BIT
(receive HFC-channel)
= 1
(HFC-channel #1)
= 0
(process 8 bits)
= 6
(start with bit 6)
: V_LOOP_FIFO = 0
(normal operation)
= 0
: V_INV_DATA
(FIFO ← E1)
(normal data transmission)
Table 3.9: Subchannel processing according to Figure 3.17 (CSM – TX, transparent mode)
7
HFC-channel mask:
0
0
0
0
0
0
0
0
1
HFC-channel transmit byte 1:
c1 [1]
c1 [0]
0
0
a1 [2]
a1 [1]
a1 [0]
1
HFC-channel transmit byte 2:
c2 [1]
c2 [0]
0
0
a2 [2]
a2 [1]
a2 [0]
1
HFC-channel transmit byte 3:
c3 [1]
c3 [0]
0
0
a3 [2]
a3 [1]
a3 [0]
1
...
...
— FIFO-to-PCM (TX)
A FIFO-to-PCM configuration in HDLC mode with two FIFOs in transmit and receive direction
136 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Data flow
Table 3.10: Subchannel processing according to Figure 3.17 (CSM – RX, transparent mode)
7
0
HFC-channel transmit byte 1:
d1 [1]
d1 [0]
x
x
b1 [2]
b1 [1]
b1 [0]
x
HFC-channel transmit byte 2:
d2 [1]
d2 [0]
x
x
b2 [2]
b2 [1]
b2 [0]
x
HFC-channel transmit byte 3:
d3 [1]
d3 [0]
x
x
b3 [2]
b3 [1]
b3 [0]
x
...
...
each is shown in the second example setting 9 .
The registers A_SUBCH_CFG[FIFO] of FIFO[12,TX] and FIFO[8,TX] define both, the numbers of FIFO data bits to be transmitted during every 125 µs cycle and their position in the
HFC-channel byte.
All other data bits in the HFC-channel are defined by the HFC-channel mask in the register A_CH_MSK. This array register must be selected by writing the HFC-channel number and
direction into the register R_FIFO. The mask bits [5 . . 2] are don’t care because they are overwritten from the FIFO data.
A detailed overview of the transmitted data is shown in Table 3.11. The first data byte in
FIFO[12,TX] is e1 , the second byte is e2 , and so on. FIFO[8,TX] transmits bytes g1 , g2 , and so
on. In HDLC mode, FIFO bytes are dispersed among several HFC-channel bytes.
9 HDLC
bit stuffing is not shown in this example.
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
Data flow
(CSM — TX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
: V_FIFO_NUM
= 12
(FIFO #12)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[12,TX] : V_IFF
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
A_CHANNEL[12,TX]
= 0
(transmit HFC-channel)
: V_CH_FNUM
= 31
(HFC-channel #31)
= 3
(process 3 bits)
: V_START_BIT
= 3
: V_LOOP_FIFO = 0
A_CON_HDLC[8,TX]
= 0
(normal data transmission)
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 8
(FIFO #8)
: V_REV
= 0
(normal bit order)
: V_IFF
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_DATA_FLOW = ’001’
: V_CH_FDIR
: V_CH_FNUM
A_SUBCH_CFG[8,TX] : V_BIT_CNT
: V_START_BIT
= 0
(FIFO → E1, FIFO → PCM)
(transmit HFC-channel)
= 31
(HFC-channel #31)
= 1
(process 1 bit)
= 2
(start with bit 2)
: V_LOOP_FIFO = 0
R_FIFO
(start with bit 3)
(normal operation)
: V_INV_DATA
: V_TRP_IRQ
A_CHANNEL[8,TX]
(FIFO → E1, FIFO → PCM)
: V_CH_FDIR
A_SUBCH_CFG[12,TX] : V_BIT_CNT
R_FIFO
(transmit FIFO)
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_FIFO_DIR
= 0
(transmit HFC-channel)
: V_FIFO_NUM
= 31
(HFC-channel #31)
: V_REV
= 0
(normal bit order)
A_CH_MSK[31,TX]
: V_CH_MSK
= ’1000 1100’
(mask byte)
R_SLOT
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 7
(slot #7)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 31
(HFC-channel #31)
: V_ROUT
= ’10’
(data to pin STIO1)
A_SL_CFG[7,TX]
— FIFO-to-PCM (RX)
HFC-channel[31,RX] receives data bits that are to be distributed to FIFO[12,RX] and FIFO[8,RX].
The registers A_SUBCH_CFG[FIFO] of FIFO[12,RX] and FIFO[8,RX] define the numbers
of valid data bits and their positions in the HFC-channel byte. These bits are dispersed to
FIFO[12,RX] and FIFO[8,RX] where they are aligned to bit 0.
A detailed overview of the received data is shown in Table 3.12. The first data byte in FIFO[12,RX]
is f1 , the second byte is f2 , and so on. FIFO[8,RX] receives bytes h1 , h2 , and so on. In HDLC
mode, FIFO bytes are collected from several HFC-channel bytes.
138 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Data flow
(CSM — RX)
Register setup:
R_FIFO
: V_FIFO_DIR
= 1
: V_FIFO_NUM
= 12
(FIFO #12)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
A_CON_HDLC[12,RX] : V_IFF
: V_HDLC_TRP = 0
(HDLC mode)
= 1
(enable FIFO)
: V_TRP_IRQ
: V_DATA_FLOW = ’001’
A_CHANNEL[12,RX]
= 1
(receive HFC-channel)
: V_CH_FNUM
= 31
(HFC-channel #31)
= 3
(process 3 bits)
: V_START_BIT
= 3
: V_LOOP_FIFO = 0
A_CON_HDLC[8,RX]
= 0
(normal data transmission)
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 8
(FIFO #8)
: V_REV
= 0
(normal bit order)
: V_IFF
= 0
(HDLC mode)
= 1
(enable FIFO)
: V_CH_FDIR
: V_CH_FNUM
A_SUBCH_CFG[8,TX] : V_BIT_CNT
: V_START_BIT
= 1
October 2003
(FIFO ← PCM)
(receive HFC-channel)
= 31
(HFC-channel #31)
= 1
(process 1 bit)
= 2
(start with bit 2)
: V_LOOP_FIFO = 0
A_SL_CFG[7,RX]
(0x7E as inter frame fill)
: V_HDLC_TRP = 0
: V_DATA_FLOW = ’001’
R_SLOT
(start with bit 3)
(normal operation)
: V_INV_DATA
: V_TRP_IRQ
A_CHANNEL[8,RX]
(FIFO ← PCM)
: V_CH_FDIR
A_SUBCH_CFG[12,TX] : V_BIT_CNT
R_FIFO
(receive FIFO)
(normal operation)
: V_INV_DATA
= 0
(normal data transmission)
: V_SL_DIR
= 1
(receive slot)
: V_SL_NUM
= 7
(slot #7)
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 31
(HFC-channel #31)
: V_ROUT
= ’10’
(data from pin STIO2)
Data Sheet
139 of 306
HFC-E1
Cologne
Chip
Data flow
Table 3.11: Subchannel processing according to Figure 3.17 (CSM — TX, HDLC mode)
7
0
HFC-channel mask:
1
0
0
0
1
1
0
0
HFC-channel transmit byte 1:
1
0
e1 [2]
e1 [1]
e1 [0]
g1 [0]
0
0
HFC-channel transmit byte 2:
1
0
e1 [5]
e1 [4]
e1 [3]
g1 [1]
0
0
HFC-channel transmit byte 3:
1
0
e2 [0]
e1 [7]
e1 [6]
g1 [2]
0
0
HFC-channel transmit byte 4:
1
0
e2 [3]
e2 [2]
e2 [1]
g1 [3]
0
0
...
...
Table 3.12: Subchannel processing according to Figure 3.17 (CSM — RX, HDLC mode)
7
0
HFC-channel transmit byte 1:
x
x
f1 [2]
f1 [1]
f1 [0]
h1 [0]
x
x
HFC-channel transmit byte 2:
x
x
f1 [5]
f1 [4]
f1 [3]
h1 [1]
x
x
HFC-channel transmit byte 3:
x
x
f2 [0]
f1 [7]
f1 [6]
h1 [2]
x
x
HFC-channel transmit byte 4:
x
x
f2 [3]
f2 [2]
f2 [1]
h1 [3]
x
x
...
140 of 306
...
Data Sheet
October 2003
Chapter 4
FIFO handling and HDLC controller
Table 4.1: Overview of the HFC-E1 FIFO registers
Write only registers:
Address
Name
Read only register:
Page
Address
Name
Page
0x0B
R_FIRST_FIFO
151
0x04
A_Z1L
160
0x0D
R_FIFO_MD
151
0x05
A_Z1H
160
0x0E
A_INC_RES_FIFO
152
0x06
A_Z2L
161
0x0F
R_FIFO
153
0x07
A_Z2H
161
0x0F
R_FSM_IDX
154
0x0C
A_F1
162
0xF4
A_CH_MSK
154
0x0D
A_F2
162
0xFA
A_CON_HDLC
155
0x88
R_INT_DATA
163
0xFB
A_SUBCH_CFG
157
0xFC
A_CHANNEL
158
0xFD
A_FIFO_SEQ
159
October 2003
Read / write registers:
Address
Name
Page
0x80
A_FIFO_DATA0
165
0x84
A_FIFO_DATA0_NOINC
166
Data Sheet
141 of 306
HFC-E1
4.1
FIFO handling and HDLC controller
Cologne
Chip
Overview
There are up to 32 receive FIFOs and up to 32 transmit FIFOs with 64 HDLC controllers in whole.
The HDLC circuits are located on the E1 interface side of the FIFOs. Thus plain data is always stored
in the FIFOs. Automatic zero insertion is done in HDLC mode when HDLC data goes from the
FIFOs to the E1 interface or to the PCM bus (transmit FIFO operation). Automatic zero deletion is
done in HDLC mode when the HDLC data comes from the E1 interface or PCM bus (receive FIFO
operation).
There is a transmit and a receive FIFO for each E1 time slot (even for time slot 0).
The FIFO control registers are used to select and control the FIFOs of the HFC-E1. The FIFO register
set exists for every FIFO number and receive / transmit direction. The FIFO is selected by the FIFO
select register R_FIFO.
All FIFOs are disabled after reset (hardware reset, soft reset or HFC reset). With the register
A_CON_HDLC the selected FIFO is enabled by setting at least one of V_HDLC_TRP or V_TRP_IRQ
to a value different from zero.
4.2
FIFO counters
The FIFOs are realized as ring buffers in the internal or external SRAM. They are controlled by
counters. The counter sizes depend on the setting of the FIFO sizes. Z1 is the FIFO input counter and
Z2 is the FIFO output counter.
Each counter points to a byte position in the SRAM. On a FIFO input operation Z1 is incremented.
On an output operation Z2 is incremented. If Z1 = Z2 the FIFO is empty.
After every pulse on the F0IO signal HDLC bytes are written into the E1 interface (from a transmit
FIFO) and HDLC bytes are read from the E1 interface (to a receive FIFO). A connection to the PCM
interface is also possible.
Additionally there are two counters F1 and F2 for every FIFO for counting the HDLC frames. Their
width is 4 bit for 32 kByte SRAM and 5 bit for larger SRAMs. They form a ring buffer as Z1 and Z2
do, too.
Table 4.2: F-counter range with different RAM sizes
RAM size
FMIN
FMAX
32k x 8
0x00
0x0F
128k x 8
0x00
0x1F
512k x 8
0x00
0x1F
F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented when a complete frame has been read from the FIFO. If F1 = F2 there is no complete frame
in the FIFO.
142 of 306
Data Sheet
October 2003
HFC-E1
FIFO handling and HDLC controller
Cologne
Chip
The reset state of the Z- and F-counters are
• Z1 = Z2 = ZMAX 1 and
• F1 = F2 = FMAX 2 .
This initialization can be carried out with a soft reset or a HDLC reset. For this, the bit V_SRES
or the bit V_HFC_RES in the register R_CIRM has to be set. Individual FIFOs can be reset with bit
V_RES_F of the register A_INC_RES_FIFO.
In addition, a hardware reset initializes the counters.
G
Important !
Busy status after FIFO change, FIFO reset and F1 / F2 incrementation
Changing a FIFO, reseting a FIFO or incrementing the F-counters causes a short
BUSY period of the HFC-E1. This means an access to FIFO control registers
is not allowed until BUSY status is cleared (bit V_BUSY of R_STATUS register). The maximum duration takes 25 clock cycles (∼1 µs). Status, interrupt and
control registers can be read and written at any time.
G
Please note !
The counter state ZMIN (resp. FMIN ) of the Z-counters (resp. F-counters) follows
counter state ZMAX (resp. FMAX ) in the FIFOs.
Please note that ZMIN and ZMAX depend on the FIFO number and FIFO size (s.
Section 4.3 and Table 4.3).
4.3 FIFO size setup
The HFC-E1 can operate with 32k x 8 internal or alternatively with 128k x 8 or 512k x 8 external
SRAM. The bitmap V_RAM_SZ of the register R_RAM_MISC must be set accordingly to the RAM
size. Table 4.3 shows how the FIFO size can be varied with the different RAM sizes. Additionally,
the initial Zmax and Zmin values are given in Table 4.3.
After changing the FIFO size or RAM size a soft reset should be initiated.
1 See
2 See
Zmax value in Table 4.3.
Fmax value in Table 4.2.
October 2003
Data Sheet
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HFC-E1
144 of 306
Table 4.3: FIFO size setup
32k x 8 RAM (internal)
128k x 8 RAM (external)
512k x 8 RAM (external)
V_RAM_SZ = 0x00
V_RAM_SZ = 0x01
V_RAM_SZ = 0x02
FMIN = 0x00, FMAX = 0x0F
FMIN = 0x00, FMAX = 0x1F
FMIN = 0x00, FMAX = 0x1F
V_FIFO_SZ
FIFO
number
ZMIN
ZMAX
FIFO size
(byte)
FIFO
number
ZMIN
ZMAX
FIFO size
(byte)
FIFO
number
ZMIN
ZMAX
FIFO size
(byte)
’00’
’00’
0 . . 31
0x80
0x1FF
384
0 . . 31
0xC0
0x07FF
1856
0 . . 31
0xC0
0x1FFF
8000
’10’
’00’
0 . . 15
0x80
0x0FF
128
0 . . 15
0xC0
0x03FF
832
0 . . 15
0xC0
0x0FFF
3904
16 . . 31
0x00
0x1FF
512
16 . . 31
0x00
0x07FF
2048
16 . . 31
0x00
0x1FFF
8192
0 . . 23
0x80
0x0FF
128
0 . . 23
0xC0
0x03FF
832
0 . . 23
0xC0
0x0FFF
3904
24 . . 31
0x00
0x3FF
1024
24 . . 31
0x00
0x0FFF
4096
24 . . 31
0x00
0x3FFF
16384
’10’
Data Sheet
’10’
’10’
’11’
’11’
’11’
’10’
’11’
’00’
’01’
’10’
’11’
0 . . 27
0x80
0x0FF
128
0 . . 27
0xC0
0x03FF
832
0 . . 27
0xC0
0x0FFF
3904
28 . . 31
0x00
0x7FF
2048
28 . . 31
0x00
0x1FFF
8192
28 . . 31
0x00
0x7FFF
32768
0 . . 29
0x80
0x0FF
128
0 . . 29
0xC0
0x03FF
832
0 . . 29
0xC0
0x0FFF
3904
30 . . 31
0x00
0xFFF
4096
30 . . 31
0x00
0x3FFF
16384
30 . . 31
0x00
0xFFFF
65536
0 . . 15
0x00
0x0FF
256
0 . . 15
0x00
0x03FF
1024
0 . . 15
0x00
0x0FFF
4096
16 . . 31
0x00
0x1FF
512
16 . . 31
0x00
0x07FF
2048
16 . . 31
0x00
0x1FFF
8192
0 .. 7
0x00
0x1FF
512
0 .. 7
0x00
0x07FF
2048
0 .. 7
0x00
0x1FFF
8192
8 . . 15
0x00
0x3FF
1024
8 . . 15
0x00
0x0FFF
4096
8 . . 15
0x00
0x3FFF
16384
0 .. 3
0x00
0x3FF
1024
0 .. 3
0x00
0x0FFF
4096
0 .. 3
0x00
0x3FFF
16384
4 .. 7
0x00
0x7FF
2048
4 .. 7
0x00
0x1FFF
8192
4 .. 7
0x00
0x7FFF
32768
0 .. 1
0x00
0x7FF
2048
0 .. 1
0x00
0x1FFF
8192
0 .. 1
0x00
0x7FFF
32768
2 .. 3
0x00
0xFFF
4096
2 .. 3
0x00
0x3FFF
16384
2 .. 3
0x00
0xFFFF
65536
Cologne
Chip
October 2003
’11’
’01’
FIFO handling and HDLC controller
V_FIFO_MD
HFC-E1
Cologne
Chip
FIFO handling and HDLC controller
4.4 FIFO operation
G
Important !
Without F0IO and C4IO clocks the HDLC controller does not work!
4.4.1
HDLC transmit FIFOs
Data can be transmitted from the host bus interface to the FIFO with write access to the registers
A_FIFO_DATA0 and A_FIFO_DATA0_NOINC. The HFC-E1 converts the data into HDLC code and
tranfers it from the FIFO to the E1 or the PCM bus interface.
Z100
F2
00h
Z100
Z200
02h
Z102
Z202
SRAM
frame 02
end of frame
Z106
F1
07h
end of frame
Z107
OUTPUT
frame 03
frame 06
INPUT
frame 07
1Fh
Figure 4.1: FIFO organization
The HFC-E1 checks Z1 and Z2. If Z1 = Z2 (FIFO empty) the HFC-E1 generates a HDLC flag
(’01111110’) or continuous ’1’s (depending on the bit V_IFF of the register A_CON_HDLC) and transmits it to the E1 interface. In this case Z2 is not incremented. If also F1 = F2 only HDLC flags or
continuous ’1’s are sent to the E1 interface and all counters remain unchanged. If the frame counters
are unequal F2 is incremented and the HFC-E1 tries to transmit the next frame. At the end of a frame
(Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds an ending flag. If there
is another frame in the FIFO (F1 = F2) the F2 counter is incremented again.
With every byte being written from the host bus side to the FIFO, Z1 is incremented automatically. If
a complete frame has been sent into the FIFO F1 must be incremented to transmit the next frame. If
the frame counter F1 is incremented the Z-counters may also change because Z1 and Z2 are functions
of F1 and F2. Thus there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Fig. 4.1).
Z1(F1) is used for the frame which is just written from the host bus side. Z2(F2) is used for the
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FIFO handling and HDLC controller
frame which is just being transmitted to the PCM or E1 interface side of the HFC-E1. Z1(F2) is the
end of frame pointer of the current output frame.
In the transmit HFC-channels F1 is only incremented from the host interface side if the software
driver wants to say “end of transmit frame”. This is done by setting the bit V_INC_F in register
A_INC_RES_FIFO. Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start
address of the next frame. Z2(F2) can not be accessed while Z2(F1) can be accessed for transmit
FIFOs: If V_FZ_MD in the register R_RAM_MISC is set, then Z2(F2) replaces Z2(F1). With this
setting the actual filling of the entire RAM space for a FIFO can be calculated.
G
Please note !
The HFC-E1 begins to transmit the bytes from a FIFO at the moment the FIFO
is changed (writing R_FIFO) or the F1 counter is incremented. Switching to the
FIFO that is already selected also starts the transmission. Thus by selecting the
same FIFO again transmission can be started.
HDLC-frame
HDLC flag
CRC2
HDLC flag
zero - inserted data
01111110
CRC1
CRC2
01111110
frame
Data in
transmit FIFO
data
data
Z1 (F1)
STAT = 00h if CRC o.k.
Data in
receive FIFO
data
data
CRC1
CRC2
STAT
Figure 4.2: FIFO data organization in HDLC mode
4.4.2
FIFO full condition in HDLC transmit HFC-channels
Due to the limited number of registers in the HFC-E1 the driver software must maintain a list of frame
start and end addresses to calculate the actual FIFO size and to check the FIFO full condition. Because
there is a maximum of 32 (resp. 16 with 32k RAM) frame counter values and the start address of a
frame is the incremented value of the end address of the last frame the memory table needs to have
only 32 (resp. 16) values of 16 bit instead of 64 (resp. 32) values.
Remember that an increment of Z-value ZMAX is ZMIN in all FIFOs!
There are two different FIFO full conditions. The first one is met when the FIFO contents comes up
to 31 frames (128k or 512k RAM) or 15 frames (32k RAM). There is no possibility for HFC-E1 to
manage more frames even if the frames are very small. The second limitation is the overall size of
the FIFO. If V_FZ_MD in the register R_RAM_MISC is set, the actual FIFO size can be calculated as
Z1(F1) − Z2(F2) + 1.
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HFC-E1
4.4.3
FIFO handling and HDLC controller
Cologne
Chip
HDLC receive FIFOs
The receive HFC-channels receive data from the E1 or PCM bus interface read registers. The data is
converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus
interface.
The HFC-E1 checks the HDLC data coming in. If it finds a flag or more than 5 consecutive ’1’s it does
not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received
is converted by the HFC-E1 into plain data. After the ending flag of a frame the HFC-E1 checks the
HDLC CRC checksum. If it is correct one byte with all ’0’s is inserted behind the CRC data in the
FIFO named STAT (see Fig. 4.2). This last byte of a frame in the FIFO is different from all ’0’s if
there is no correct CRC field at the end of the frame.
If the STAT value is 0xFF, the HDLC frame ended with at least 8 bits ’1’s. This is similar to an abort
HDLC frame condition.
The ending flag of a HDLC frame can also be the starting flag of the next frame.
After a frame is received completely F1 is incremented by the HFC-E1 automatically and the next
frame can be received.
After reading a frame via the host bus interface F2 has to be incremented. If the frame counter F2 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. Thus
there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Fig. 4.1).
Z1(F1) is used for the frame which is just received from the E1 interface side of the HFC-E1. Z2(F2)
is used for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of
frame pointer of the current output frame.
To calculate the length of the current receive frame the software has to evaluate Z1 − Z2 + 1. When
Z2 reaches Z1 the complete frame has been read.
In the receive HFC-channels F2 must be incremented from the host interface side after the software
detects an end of receive frame (Z1 = Z2) and F1 = F2. Then the current value of Z2 is stored,
F2 is incremented and Z2 is copied as start address of the next frame. This is done by setting the
bit V_INC_F in the register A_INC_RES_FIFO. If Z1 = Z2 and F1 = F2 the FIFO is totally empty.
Z1(F1) can not be accessed.
G
Important !
Before reading a new frame, a change FIFO operation (write access to the register
R_FIFO) has to be done even if the desired FIFO is already selected. The change
FIFO operation is required to update the internal buffer of the HFC-E1. Otherwise
the first 4 bytes of the FIFO will be taken from the internal buffer and may be
invalid.
4.4.4
FIFO full condition in HDLC receive HFC-channels
Because of the E1 time slots not having a hardware based flow control there is no possibility to stop
input data if a receive FIFO is full.
Thus there is no FIFO full condition implemented in the HFC-E1. The HFC-E1 assumes that the
FIFOs are deep enough that the host processor’s hardware and software is able to avoid any overflow
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FIFO handling and HDLC controller
Cologne
Chip
of the receive FIFOs. Overflow conditions are again more than 31 input frames (resp. 15 frames with
32k RAM) or a memory overflow of the FIFO because of excessive data.
Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent
without software intervention. Due to the great size of the HFC-E1 FIFOs it is easy to poll the
HFC-E1 even in large time intervalls without having to fear a FIFO overflow condition.
To avoid any undetected FIFO overflows the software driver should check F1 − F2, i.e. the number
of frames in the FIFO. If F1 − F2 is less than the number in the last reading, an overflow took place
if there was no reading of a frame in between.
After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset bit
V_RES_F in the register A_INC_RES_FIFO.
4.4.5
Transparent mode of the HFC-E1
It is possible to switch off the HDLC operation for each FIFO independently by the bit V_HDLC_TRP
in register A_CON_HDLC. If this bit is set, data from the FIFO is sent directly to the E1 or PCM bus
interface and data from the E1 or PCM bus interface is sent directly to the FIFO.
Be sure to switch into transparent mode only if F1 = F2. Being in transparent mode the F-counters
remain unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1 = F2, the
Z-counters are always accessable and have valid data for FIFO input and output.
If a transmit FIFO changes to FIFO empty condition no CRC is generated and the last data byte
written into the FIFO is repeated until there is new data.
Normally the last byte is undefined because of the Z-counter pointing to a previously unwritten address. To define the last byte, the last write access to the FIFO must be done without Z increment (see
register A_FIFO_DATA0_NOINC).
In receive HFC-channels there is no check on flags or correct CRCs and no status byte added.
Unlike in HDLC mode, where byte synchronization is achieved with HDLC flags, the byte boundaries
are not arbitrary. The data is just the same as it comes from or is sent to the E1 or PCM bus interface.
Transmit and receive transparent data can be done in two ways. The usual way is transporting FIFO
data to the E1 interface with the LSB first as usual in HDLC mode. The second way is transmitting
the bytes in reverse bit order as usual for PCM data. So the first bit is the MSB. The bit order can be
reversed by setting bit V_REV of the register R_FIFO when the FIFO is selected.
G
Important !
For normal data transmission the register A_SUBCH_CFG must be set to 0x00.
To use 56 kbit/s restricted mode for U.S. ISDN lines the register A_SUBCH_CFG
must be set to 0x07 for B-channels.
4.4.6
Reading F- and Z-counters
For all asynchronous host accesses to the HFC-E1 there is a small chance that a register is changed
just in the moment when it is read. Because of slightly different delays of individual bits, it is even
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HFC-E1
FIFO handling and HDLC controller
Cologne
Chip
possible that the read value is fully invalid. Therefore we advise to read a F- or Z-counter register
until two consecutive readings find the same value.
This is not necessary for a time period of at least 125 µs after writing R_FIFO. It is also not necessary
for Z-counters of receive FIFOs if F1 = F2. Then a whole frame has been received and the counters
Z1(F2) and Z2(F2) are stable and valid.
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October 2003
HFC-E1
FIFO handling and HDLC controller
Cologne
Chip
4.5 Register description
4.5.1
Write only registers
(write only)
R_FIRST_FIFO
0x0B
First FIFO of the FIFO sequence
This register is only used in FIFO Sequence Mode, see register R_FIFO_MD for data
flow mode selection.
Bits
Reset
Name
Description
Value
0
0
V_FIRST_FIFO_DIR
Data direction
This bit defines the data direction of the first FIFO
in FIFO sequence.
’0’ = transmit FIFO data
’1’ = receive FIFO data
5..1
0x00
V_FIRST_FIFO_NUM
FIFO number
This bitmap defines the number of the first FIFO in
the FIFO sequence.
(reserved)
Must be ’00’.
7..6
(write only)
R_FIFO_MD
0x0D
FIFO mode configuration
This register defines the FIFO arrangement and the working mode of the FIFOs and
HDLC controllers.
Bits
Reset
Name
Description
FIFO mode
This bitmap and V_FIFO_SZ are used to organize
the FIFOs in the internal or external SRAM.
Value
1..0
0
V_FIFO_MD
3..2
0
V_DF_MD
Data flow mode selection
’00’ = Simple Mode (SM)
’01’ = Channel Select Mode (CSM)
’10’ = not used
’11’ = FIFO Sequence Mode (FSM)
5..4
0
7..6
V_FIFO_SZ
FIFO size
This bitmap and V_FIFO_MD are used to organize
the FIFOs in the internal or external SRAM. The
actual FIFO sizes also depend on the used SRAM
size (see R_RAM_MISC).
(reserved)
Must be ’00’.
(See Table 4.3 on page 144 for suitable V_FIFO_MD and V_FIFO_SZ values.)
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HFC-E1
FIFO handling and HDLC controller
A_INC_RES_FIFO[FIFO]
(write only)
Cologne
Chip
0x0E
Increment and reset FIFO register
This register is automatically cleared.
Before writing this array register the FIFO must be selected by register R_FIFO.
Bits
Reset
Name
Description
Value
0
V_INC_F
Increment the F-counters of the selected FIFO
’0’ = no increment
’1’ = increment
1
V_RES_F
FIFO reset
’0’ = no reset
’1’ = reset selected FIFO (F- and Z-counters and
channel mask A_CH_MSK are reset)
2
V_RES_LOST
LOST error bit reset
’0’ = no reset
’1’ = reset LOST
7..3
152 of 306
(reserved)
Must be ’00000’.
Data Sheet
October 2003
HFC-E1
FIFO handling and HDLC controller
R_FIFO
(write only)
Cologne
Chip
0x0F
FIFO selection register
This register is used to select a FIFO. Before a FIFO array register can be accessed, this
index register must specify the desired FIFO number and data direction.
Note: This register is a multi-register. It is selected with bitmap V_DF_MD less than 0x11 of the
register R_FIFO_MD (SM and CSM). In FSM (V_DF_MD = 0x11) some FIFO array registers
are indexed by the multi-register R_FSM_IDX instead, but most FIFO array registers remain
indexed by this register.
Bits
Reset
Name
Description
Value
0
0
V_FIFO_DIR
FIFO data direction
’0’ = transmit FIFO data
’1’ = receive FIFO data
5..1
0x00
6
7
0
V_FIFO_NUM
FIFO number
(reserved)
Must be ’0’.
V_REV
Bit order
’0’ = normal bit order
’1’ = reversed bit order
Normal bit order means LSB first in HDLC mode
and MSB first in transparent mode. The bit order is
being reversed for the data stored into the FIFO or
when the data is read from the FIFO.
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FIFO handling and HDLC controller
Cologne
Chip
0x0F
(write only)
R_FSM_IDX
Index register of the FIFO sequence
This register is used to select a list number in FIFO Sequence Mode. Some FIFO array
registers are indexed by this list number. Before these registers can be accessed, this index
register must specify the desired list number.
Note: This register is a multi-register. It is selected with bitmap V_DF_MD = 0x11 of the
register R_FIFO_MD. In FSM only few FIFO array registers are indexed by this multi-register,
but most FIFO array registers remain indexed by R_FIFO.
Bits
Reset
Name
Description
V_IDX
List index
The list index must be in the range 0 . . 63.
(reserved)
Must be ’00’.
Value
5..0
0
7..6
A_CH_MSK[FIFO]
0xF4
(write only)
HFC-channel data mask for the selected transmit HFC-channel
For receive FIFOs this register is ignored.
Before writing this array register the HFC-channel must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_CH_MSK
Mask byte
This bitmap defines bit values for not processed
bits of a HFC-channel. All not processed bits of a
HFC-channel are set to the value defined in this
register.
This register has only a meaning when V_BIT_CNT
= 0 in the register A_SUBCH_CFG.
Value
7..0
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0xFF
Data Sheet
October 2003
HFC-E1
Cologne
Chip
FIFO handling and HDLC controller
A_CON_HDLC[FIFO]
0xFA
(write only)
HDLC and connection settings of the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
Bits
Reset
Name
Description
Value
0
0
V_IFF
Inter frame fill
’0’ = write HDLC flags 0x7E as inter frame fill
’1’ = write all ’1’s as inter frame fill
Note: For D-channel this bit must be ’1’.
1
0
V_HDLC_TRP
HDLC mode / transparent mode selection
’0’ = HDLC mode
’1’ = transparent mode
Note: For D-channel this bit must be ’0’.
4..2
0
V_TRP_IRQ
Transparent mode interrupt selection
In transparent mode:
The FIFO is enabled and an interrupt is generated
all 2n bytes when the bits [n-1:0] of the Z1- or
Z2-counter become ’1’. So n = V_TRP_IRQ + 5.
0 = interrupt disabled, but FIFO is enabled anyway
1 = all 26 = 64 bytes an interrupt is generated
2 = all 27 = 128 bytes an interrupt is generated
3 = all 28 = 256 bytes an interrupt is generated
4 = all 29 = 512 bytes an interrupt is generated
5 = all 210 = 1024 bytes an interrupt is generated
6 = all 211 = 2048 bytes an interrupt is generated
7 = all 212 = 4096 bytes an interrupt is generated
Notes: (1) No interrupt occurs, if the Z-counters do
never reach the selected values. This depends on
the ZMAX setting.
(2) The first interrupt after Z = Zmin comes after
2n − Zmin bytes if 2n − 1 > Zmin . Only the following
interrupts come after 2n bytes until Z reaches Zmin
again.
In HDLC mode:
No interrupt capability is given in HDLC mode.
’0’ = FIFO disabled
’1’ . . ’7’ = FIFO enabled
(continued on next page)
October 2003
Data Sheet
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HFC-E1
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Chip
FIFO handling and HDLC controller
(continued from previous page)
Bits
Reset
Name
Description
V_DATA_FLOW
Data flow configuration
In transmit operation (V_FIFO_DIR = 0 in the
register R_FIFO):
Value
7..5
0
’000’, ’001’ = FIFO → E1, FIFO → PCM
’010’, ’011’ = FIFO → PCM
’100’, ’101’ = FIFO → E1, E1 → PCM
’110’, ’111’ = E1 → PCM
In receive operation (V_FIFO_DIR = 1 in the
register R_FIFO):
’000’, ’100’ = FIFO ← E1
’001’, ’101’ = FIFO ← PCM
’010’, ’110’ = FIFO ← E1,
E1 ← PCM
’011’, ’111’ = FIFO ← PCM, E1 ← PCM
(For details on bitmap V_DATA_FLOW see Fig. 3.3 and 3.4 on page 101.)
G
Important !
A FIFO is disabled if V_HDLC_TRP + V_TRP_IRQ = 0 in the register
A_CON_HDLC[FIFO]. This setting is useful to reduce RAM accesses if a FIFO
is not used at all.
If HFC-channel data is routed through the switches of the flow controller (Fig. 3.3
and 3.4) the FIFO must be enabled. That applies to all connections except the
PCM-to-PCM data transmission.
156 of 306
Data Sheet
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HFC-E1
FIFO handling and HDLC controller
A_SUBCH_CFG[FIFO]
Cologne
Chip
(write only)
0xFB
Subchannel parameters for bit processing of the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
Bits
Reset
Name
Description
Value
2..0
0
V_BIT_CNT
Number of bits to be processed in the
HFC-channel byte
In HDLC mode, only this number of bits is read
from or written into the FIFO. In transparent mode
always a whole FIFO byte is read or written, but
only V_BIT_CNT bits contain valid data.
’000’ = process 8 bits (64 kbit/s)
’001’ = process 1 bit (8 kbit/s)
’010’ = process 2 bits (16 kbit/s)
’011’ = process 3 bits (24 kbit/s)
’100’ = process 4 bits (32 kbit/s)
’101’ = process 5 bits (40 kbit/s)
’110’ = process 6 bits (48 kbit/s)
’111’ = process 7 bits (56 kbit/s)
5..3
0
V_START_BIT
Start bit in the HFC-channel byte
This bitmap specifies the position of the bit field in
the HFC-channel byte. The bit field is located at
position V_START_BIT in the HFC-channel byte.
V_BIT_CNT + V_START_BIT must not be greater
than 8 to get the bit field completely inside the
HFC-channel byte. Any value greater than 8
produce undefined behavior of the subchannel
processor.
6
0
V_LOOP_FIFO
FIFO loop
’0’ = normal operation
’1’ = repeat current frame (useful only in
transparent mode)
7
0
V_INV_DATA
Inverted data
’0’ = normal data transmission
’1’ = inverted data transmission
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Data Sheet
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HFC-E1
FIFO handling and HDLC controller
A_CHANNEL[FIFO]
(write only)
Cologne
Chip
0xFC
HFC-channel assignment for the selected FIFO
This register is only used in Channel Select Mode and FIFO Sequence Mode.
Before writing this array register the FIFO must be selected by register R_FIFO.
Bits
Reset
Name
Description
Value
0
V_CH_FDIR
HFC-channel data direction
’0’ = HFC-channel for transmit data
’1’ = HFC-channel for receive data
Reset value: This bitmap is reset to the same value
as the current FIFO, i.e. V_CH_FDIR of
A_CHANNEL[number, direction] = direction.
5..1
7..6
158 of 306
0
V_CH_FNUM
HFC-channel number
(0 . . 31)
Reset value: This bitmap is reset to the same value
as the current FIFO, i.e. V_CH_FNUM of
A_CHANNEL[number, direction] = number.
(reserved)
Must be ’00’.
Data Sheet
October 2003
HFC-E1
FIFO handling and HDLC controller
A_FIFO_SEQ[FIFO]
(write only)
Cologne
Chip
0xFD
FIFO sequence list
This register is only used in FIFO Sequence Mode.
Before writing this array register the FIFO must be selected by register R_FIFO.
Bits
Reset
Name
Description
0
V_NEXT_FIFO_DIR
FIFO data direction
This bit defines the data direction of the next FIFO
in FIFO sequence.
’0’ = transmit FIFO data
’1’ = receive FIFO data
Reset value: This bitmap is reset to the same value
as the current FIFO, i.e. V_NEXT_FIFO_DIR of
A_FIFO_SEQ[number, direction] = direction.
5..1
V_NEXT_FIFO_NUM
FIFO number
This bitmap defines the FIFO number of the next
FIFO in the FIFO sequence.
Reset value: This bitmap is reset to the same value
as the current FIFO, i.e. V_NEXT_FIFO_NUM of
A_FIFO_SEQ[number, direction] = number.
Value
6
0
V_SEQ_END
End of FIFO list
’0’ = FIFO list goes on
’1’ = FIFO list is terminated after this FIFO
(V_NEXT_FIFO_DIR and V_NEXT_FIFO_NUM are
ignored)
7
0
October 2003
(reserved)
Must be ’0’.
Data Sheet
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HFC-E1
4.5.2
FIFO handling and HDLC controller
Cologne
Chip
Read only registers
A_Z1L[FIFO]
(read only)
0x04
FIFO input counter Z1, low byte access
This address can also be accessed with word and double word width to read the complete Z1-counter or Z1- and Z2-counters together (see registers A_Z1 and A_Z12).
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z1L
Bits [7..0] counter value of Z1
Value
7..0
(See Table 4.3 for reset value.)
A_Z1H[FIFO]
(read only)
0x05
FIFO input counter Z1, high byte access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z1H
Bits [15..8] counter value of Z1
Value
7..0
(See Table 4.3 for reset value.)
A_Z1[FIFO]
(read only)
0x04
FIFO input counter Z1, word access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z1
Bits [15..0] counter value of Z1
Value
15..0
(See Table 4.3 for reset value.)
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Data Sheet
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HFC-E1
FIFO handling and HDLC controller
A_Z2L[FIFO]
(read only)
Cologne
Chip
0x06
FIFO output counter Z2, low byte access
This address can also be accessed with word width to read the complete Z2-counter (see
register A_Z2).
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z2L
Bits [7..0] counter value of Z2
Value
7..0
(See Table 4.3 for reset value.)
A_Z2H[FIFO]
(read only)
0x07
FIFO output counter Z2, high byte access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z2H
Bits [15..8] counter value of Z2
Value
7..0
(See Table 4.3 for reset value.)
A_Z2[FIFO]
(read only)
0x06
FIFO output counter Z2, word access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z2
Bits [15..0] counter value of Z2
Value
15..0
(See Table 4.3 for reset value.)
October 2003
Data Sheet
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HFC-E1
FIFO handling and HDLC controller
A_Z12[FIFO]
Cologne
Chip
0x04
(read only)
FIFO input counters Z1 and Z2, double word access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_Z12
Bits [15..0] are counter value of Z1 and bits
[31..16] are counter value of Z2
Value
31..0
(See Table 4.3 for reset value.)
A_F1[FIFO]
(read only)
0x0C
FIFO input HDLC frame counter F1, byte access
This address can also be accessed with word width to read the F1- and F2-counters together (see register A_F12).
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_F1
Counter value
Up to 31 HDLC frames (resp. 15 with 32k RAM)
can be stored in each FIFO.
Value
7..0
(See Table 4.3 for reset value.)
A_F2[FIFO]
(read only)
0x0D
FIFO output HDLC frame counter F2, byte access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_F2
Counter value
Up to 31 HDLC frames (resp. 15 with 32k RAM)
can be stored in each FIFO.
Value
7..0
(See Table 4.3 for reset value.)
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Data Sheet
October 2003
HFC-E1
FIFO handling and HDLC controller
A_F12[FIFO]
(read only)
Cologne
Chip
0x0C
FIFO input HDLC frame counters F1 and F2, word access
Before reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_F12
Bits [7..0] are counter value of F1 and bits
[15..8] are counter value of F2
Up to 31 HDLC frames (resp. 15 with 32k RAM)
can be stored in each FIFO.
Value
15..0
(See Table 4.3 for reset value.)
(read only)
R_INT_DATA
0x88
Internal data register
This register can be read to access data with short read signal.
Bits
Reset
Name
Description
V_INT_DATA
Internal data buffer
Value
7..0
See ‘Short read method’ on page 72.
October 2003
Data Sheet
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HFC-E1
FIFO handling and HDLC controller
164 of 306
Data Sheet
Cologne
Chip
October 2003
HFC-E1
4.5.3
FIFO handling and HDLC controller
Cologne
Chip
Read / write registers
A_FIFO_DATA0[FIFO]
(read / write)
0x80
FIFO data register
This address can also be accessed with word and double word width to access two or
four data bytes (see registers A_FIFO_DATA1 and A_FIFO_DATA2).
Before writing or reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_FIFO_DATA0
Data byte
Read / write one byte from / to the FIFO selected in
the R_FIFO register and increment Z-counter by 1.
Value
7..0
A_FIFO_DATA1[FIFO]
(read / write)
0x80
FIFO data register
Before writing or reading this array register the FIFO must be selected by the register
R_FIFO.
Bits
Reset
Name
Description
V_FIFO_DATA1
Data word
Read / write one word from / to the FIFO selected in
the R_FIFO register and increment Z-counter by 2.
Value
15..0
A_FIFO_DATA2[FIFO]
(read / write)
0x80
FIFO data register
Before writing or reading this array register the FIFO must be selected by the register
R_FIFO.
Bits
Reset
Name
Description
V_FIFO_DATA2
Data double word
Read / write two words from / to the FIFO selected
in the R_FIFO register and increment Z-counter by
4.
Value
31..0
October 2003
Data Sheet
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HFC-E1
FIFO handling and HDLC controller
A_FIFO_DATA0_NOINC[FIFO]
(read / write)
Cologne
Chip
0x84
FIFO data register
This address can also be accessed with word and double word width to access two or
four data bytes (see registers A_FIFO_DATA1_NOINC and A_FIFO_DATA2_NOINC).
Before writing or reading this array register the FIFO must be selected by the register R_FIFO.
Bits
Reset
Name
Description
V_FIFO_DATA0_NOINC
Data byte
Read access: Read one byte from the FIFO selected
in the R_FIFO register and increment Z-counter by
1.
Value
7..0
Write access: Write one byte to the FIFO selected
in the R_FIFO register without incrementing
Z-counter.
(This register can be used to store the last FIFO byte in transparent transmit mode. Then this byte is
repeately transmitted automatically.)
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Data Sheet
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HFC-E1
FIFO handling and HDLC controller
A_FIFO_DATA1_NOINC[FIFO]
Cologne
Chip
0x84
(read / write)
FIFO data register
Before writing or reading this array register the FIFO must be selected by the register
R_FIFO.
Bits
Reset
Name
Description
V_FIFO_DATA1_NOINC
Data word
Read access: Read one word from the FIFO
selected in the R_FIFO register and increment
Z-counter by 2.
Value
15..0
Write access: Write one word to the FIFO selected
in the R_FIFO register without incrementing
Z-counter.
A_FIFO_DATA2_NOINC[FIFO]
0x84
(read / write)
FIFO data register
Before writing or reading this array register the FIFO must be selected by the register
R_FIFO.
Bits
Reset
Name
Description
V_FIFO_DATA2_NOINC
Data double word
Read access: Read two words from the FIFO
selected in the R_FIFO register and increment
Z-counter by 4.
Value
31..0
Write access: Write two words to the FIFO selected
in the R_FIFO register without incrementing
Z-counter.
October 2003
Data Sheet
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FIFO handling and HDLC controller
168 of 306
Data Sheet
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Chip
October 2003
Chapter 5
E1 interface
Table 5.1: Overview of the HFC-E1 E1 pins
Number
October 2003
Name
Description
184
T_B
E1 interface transmit data B
185
T_A
E1 interface transmit data A
187
ADJ_LEV
E1 interface level generator
188
R_B
E1 interface receive input B
189
LEV_B
E1 interface level detect B
190
LEV_A
E1 interface level detect A
191
R_A
E1 interface receive input A
Data Sheet
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HFC-E1
Cologne
Chip
E1 interface
Table 5.2: Overview of the HFC-E1 E1 interface registers
Write only registers:
Address
170 of 306
Name
Read only registers:
Page
Address
Name
Page
0x20
R_E1_WR_STA
176
0x20
R_E1_RD_STA
191
0x22
R_LOS0
176
0x24
R_RX_STA0
192
0x23
R_LOS1
177
0x25
R_RX_STA1
193
0x24
R_RX0
178
0x26
R_RX_STA2
194
0x25
R_RX_FR0
179
0x27
R_RX_STA3
195
0x26
R_RX_FR1
181
0x2C
R_SLIP
196
0x28
R_TX0
182
0x30
R_FAS_ECL
197
0x29
R_TX1
183
0x31
R_FAS_ECH
197
0x2D
R_TX_FR1
185
0x32
R_VIO_ECL
198
0x2E
R_TX_FR2
186
0x33
R_VIO_ECH
198
0x30
R_RX_OFF
187
0x34
R_CRC_ECL
198
0x31
R_SYNC_OUT
188
0x35
R_CRC_ECH
199
0x34
R_TX_OFF
189
0x36
R_E_ECL
199
0x35
R_SYNC_CTRL
190
0x37
R_E_ECH
199
0x38
R_PWM0
227
0x38
R_SA6_SA13_ECL
200
0x39
R_PWM1
227
0x39
R_SA6_SA13_ECH
200
0x46
R_PWM_MD
228
0x3A
R_SA6_SA23_ECL
200
0x3B
R_SA6_SA23_ECH
201
Data Sheet
October 2003
HFC-E1
E1 interface
Cologne
Chip
5.1 Interface functionality
The HFC-E1 is aquipped with a fully ETSI compliant (TBR4) E1 interface which handles 32 time
slots of 8 bits each. The time slots are numbered 0 . . 31. Slot 0 is used for synchronization purposes
and for the CRC4 prodcedure which checks for data integrity. All other slots can be used for data
transmission. In ISDN environments slot 16 is normally used as D-channel.
The HFC-E1 provides the F/G state of the E1 interface in the register R_E1_WR_STA. It is also
implemented to force a specific state by overwriting the automatic E1 state machine.
Fundamental interface mode selections can be done by writing registers R_RX0 for receive direction
and R_TX0 for transmit direction. Fiber optical interface can be selcted by setting V_RX_CODE and
V_TX_CODE to NRZ. In this case R_A is data input and R_B is clock input in receive direction;
accordingly T_A is data output and T_B is clock output then.
For normal E1 operation with the interface circuit of Figure 5.3 and 5.4 the register R_RX0 should be
set to 0x01.
In R_RX_FR1 and R_TX_FR2 double frame or multiframe format is selectable. Double frame format uses a simple synchronization algorithm (see Figure ??) and Multiframe format uses the CRC4
procedure (see Figure ??).
There are several bits to configure different behavior of the time slot 0 synchronization data. Time
slot 0 data can be generated automatically according to the selected mode or can be generated by
FIFO data or from a special area in the RAM of the HFC-E1. If the RAM buffer is used the area
is organized as an alternating buffer. So one half can be read or written by the host processor when
the other half sends or receives via the E1 interface. V_RX_SL0_RAM in register R_RX_FR1 and
V_TX_SL0_RAM in register R_TX_FR2 switch between the RAM area and the HFC-channel[0] as
data destination / source.
The registers R_RX_FR0 and R_RX_FR1 are for the selection of different synchonisation options and
how slot 0 of the E1 interface is interpreted. R_TX_FR0, R_TX_FR1 and R_TX_FR2 are used for the
selection of different slot 0 data generation.
The HFC-E1 includes an elastic buffer in receive and transmit direction which can be 0 . . 3 times
125 µs. Bigger buffers lead to more delay between receive or transmit data in the FIFOs or the PCM
interface and real data on the E1 interface.
The registers R_RX_OFF and R_TX_OFF are used for buffer size selection and buffer initialisation.
After initialisation the buffers are FIFOs. In the register R_SLIP a bit is set when there is a buffer
underrun or overrun. This is reported only when the full 4 frame FIFO is not enough to handle the
data without a slip. Two other bits are slip detection bits which remain set after a slip until the R_SLIP
register is read.
The loss of receive signal (LOS) condition can be set in the registers R_LOS0 and R_LOS1. A LOS
condition is reported in the bit V_SIG_LOS of the register R_RX_STA0 and by changing the state of
the state machine accordingly.
The Receiving Alarm Indication Signal (AIS) is reported in the bit V_AIS of the register R_RX_STA0.
Sending of AIS can be switched on with V_AIS_OUT in register R_TX1.
Some receive status bits in the rigisters R_RX_STA1 . . R_RX_STA3 are readable but only for some
diagnostic purpose. These bits are only valid for 125 µs or those related to a multiframe are valid for
2 ms.
There are 6 error counters of 16 bit size in the HFC-E1 interface. They can operate in 2 modes. If
October 2003
Data Sheet
171 of 306
HFC-E1
Cologne
Chip
E1 interface
V_AUTO_ERR_RES is 0 then they function as normal counters. If V_AUTO_ERR_RES is 1 then
every second the counter value is latched and the counter starts again with 0.
5.2
Clock synchronization
E1 interface
receive
DPLL
32.768 MHz
32.768 MHz
2.048 kHz
1
8 kHz
frame
sync
RX
MUX
0
E1 data
controller
TX
sync
select
PCM interface
2.046 kHz
JATT
sync
select
SYNC_I
divider
÷ 256
MUX
8 kHz
MUX
input
sync
select
divider
÷2
output
sync
select
divider
÷2
SYNC_O
C2O
16384 MHz
8 kHz
PCM data
controller
divider
select
C4IO
PCM Master
PCM
DPLL
16384 kHz
or 8192 kHz
or 4096 kHz
8 kHz
divider
÷ 2048
÷ 1024
÷ 512
F0IO
8 kHz
Figure 5.1: E1 clock synchronization
5.3
External circuitries
172 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
E1 interface
E1 RX
frame clock
SYNC_I
MUX
MUX
FOI
E1 TX
frame clock
to JATT
MUX
MUX
V_PCM_SYNC
V_NEG_CLK
divider
÷2
V_EXT_CLK_SYNC
V_HCLK
Synchronization Selection
Figure 5.2: Detail of the E1 interface synchronization selection shown in Figure 5.1
+3.3V
+3.3V
R1
1k
Q1
BC848C
C1
100n
D1
R2
10
BAV99
R3
*
* for impedance
adjustment
C2
100n
Q2
BC858C
R5
k1
U1
GND
T_B
T_A
D2
GND
D3
TR1
+3.3V
1
184
16
TX
185
nc
2
15
3
14
+3.3V
+3.3V
HFC-E1
optional
1:2,4
C5
GND
D4
R10
D5
UMEC 23014
k1
GND
Q3
BC848C
C3
100n
D6
R11
10
BAV99
C4
*
R12
* for impedance
adjustment
Q4
R14
BC858C
k1
100n
GND
GND
Figure 5.3: External E1 transmit circuitry
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
E1 interface
+3.3V
M1
R1
R2
10k
C1
47n
GND
R3
R4
470
R5
150
R6
150
150
C2
R7
k01
22p
GND
D1
187
191
190
95
189
188
R9
6
BAV99
R10
5k6
100k
C3
R11
47n
11
RX
BAV99
1:1
optional
7
10
8
9
C5
GND
6k5
ADJ_LEV
R_A
LEV_A
PWM1
LEV_B
R_B
HFC-E1
TR1
+3.3V
R8
6k5
U1
D2
UMEC 23014
GND
GND
k01
R12
R13
R14
470
R15
150
R16
150
150
C4
22p
C2 and C4 should be located as
near as possible to the R_A and
R_B inputs of the chip.
GND
Figure 5.4: External E1 receive circuitry
+3.3V
U2
1
3
1µ
GND
LP2980-ADJ
ADJ
+ C3
C2
R1
On/Off
1n
C4
129
147
164
181
VDD_E1
VDD_E1
VDD_E1
VDD_E1
100n
2µ2
4
R2
R3
GND
k1
GND
5
k51
GND
2
Vout
k01
+ C1
Vin
U1
+2.5V ... +3.2V
GND
R4
10k
96
PWM0
C5
100n
GND
HFC-E1
GND
Figure 5.5: VDD_E1 voltage generation
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Data Sheet
October 2003
HFC-E1
Cologne
Chip
E1 interface
For high voltage protection use 5R6 / 5W
cement resistors and P3203AB.
For low voltage protection use 5R6
SMT resistor and omit P3203AB.
R1
1
5R6
U4
TR1
2
1
16
TX
GNDA
1:2,4
2
15
ISDN jack
3
P3203AB
3
5R6
14
6
3
6
R2
+
-
11
RX
4
5
1:1
7
10
8
9
+
-
11
GNDA
RJ45
GNDA
UMEC 23014
Figure 5.6: Connector circuitry in LT mode
For high voltage protection use 5R6 / 5W
cement resistors and P3203AB.
For low voltage protection use 5R6
SMT resistor and omit P3203AB.
R1
1
5R6
U4
TR1
2
1
16
TX
GNDA
1:2,4
2
15
ISDN jack
3
P3203AB
3
5R6
14
6
3
6
R2
+
-
11
RX
7
4
5
1:1
10
11
8
+
GNDA
RJ45
9
GNDA
UMEC 23014
Figure 5.7: Connector circuitry in TE mode
October 2003
Data Sheet
175 of 306
HFC-E1
E1 interface
5.4
Register description
5.4.1
Write only register
Cologne
Chip
0x20
(write only)
R_E1_WR_STA
E1 state machine register
This register is used to set a new state. The current state can be read from the R_E1_RD_STA
register.
Bits
Reset
Name
Description
V_E1_SET_STA
Binary value of new state
(LT: Gx, TE: Fx)
V_E1_LD_STA must also be set to load the state.
(reserved)
Must be ’0’.
Value
2..0
0
3
1
4
V_E1_LD_STA
Load the new state
’0’ = enable the state machine
’1’ = load the prepared state (V_E1_SET_STA) and
stops the state machine
Note: After writing an invalid state the state
machine goes to deactivated state.
7..5
(reserved)
Must be ’000’.
(write only)
R_LOS0
0x22
Alarm set value for loss of input signal
Bits
Reset
Name
Description
V_LOS0
LOS alarm
LOS alarm will be active if the incoming data
stream has no transitions in (V_LOS0 + 1) ·16
consecutive data bit times. Maximum time is
256 · 16 · 488 ns = 2 ms.
Value
7..0
176 of 306
0
Data Sheet
October 2003
HFC-E1
E1 interface
R_LOS1
(write only)
Cologne
Chip
0x23
Alarm clear value for loss of input signal
Bits
Reset
Name
Description
V_LOS1
LOS alarm
LOS alarm will be cleared if the incoming data
stream has V_LOS1 +1 transitions in LOS0 time
interval. After LOS alarm is cleared a new LOS0
time interval will be started.
Value
7..0
0
October 2003
Data Sheet
177 of 306
HFC-E1
E1 interface
R_RX0
(write only)
Cologne
Chip
0x24
E1 receiver configuration register 0
Bits
Reset
Name
Description
Value
1..0
0
V_RX_CODE
Receive code
’00’ = NRZ (pin R_A is data input and pin R_B is
clock input in NRZ mode)
’01’ = HDB3 code
’10’ = AMI code
’11’ = reserved
2
0
V_RX_FBAUD
Full / half bauded
’0’ = receive pulse is half bit long
’1’ = receive pulse is full bit long
3
0
V_RX_CMI
Code mark inversion (CMI)
’0’ = CMI off
’1’ = CMI on
In CMI mode pin R_B is not used.
4
0
V_RX_INV_CMI
Inverted CMI code
This bit is only valid if CMI is on.
’0’ = CMI code
’1’ = inverted CMI code
5
0
V_RX_INV_CLK
Polarity of clock
This bit is only valid if data clock input is used
(NRZ mode).
’0’ = clock is not inverted
’1’ = clock is inverted
6
0
V_RX_INV_DATA
Polarity of input data
’0’ = non-inverted data
’1’ = inverted data
7
0
V_AIS_ITU
AIS alarm specification
’0’ = according to ETS 300233
’1’ = according to ITU-T G.775
178 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
Cologne
Chip
0x25
(write only)
R_RX_FR0
E1 receive frame configuration, register 0
Bits
Reset
Name
Description
Value
0
0
V_NO_INSYNC
Transparent mode
’0’ = normal operation
’1’ = no synchronization to input data
1
0
V_AUTO_RESYNC
Automatic resynchronization
’0’ = normal operation
’1’ = after loss of synchronization the search for
multiframe synchronization pattern is initiated
again
This bit is only valid in CRC multiframe format.
2
0
V_AUTO_RECO
Automatic error recovery
’0’ = normal operation
’1’ = if there are more than 914 CRC errors in one
second the receiver will search for new basic- and
multiframing
This bit is only valid in multiframing synchronous
state.
3
0
V_SWORD_COND
Service word condition
’0’ = loss of synchronization if there are 3 or 4
(depending on V_SYNC_LOSS) consecutive
incorrect service words
’1’ = incorrect service words have no influence in
synchronous state
4
0
V_SYNC_LOSS
Loss of synchronization signal
’0’ = loss of synchronization if there are 3
consecutive incorrect FAS or service words
’1’ = loss of synchronization if there are 4
consecutive incorrect FAS or service words
5
0
V_XCRC_SYNC
Extended CRC4 to non-CRC4
’0’ = according to ITU-T G.706
’1’ = according to ITU-T G.706 except that the
synchronizer will still search for multiframing even
if the 400 ms is expired
6
0
V_MF_RESYNC
7
0
V_RESYNC
Multiframe resynchronization
When this bit is set, the resynchronization of CRC
multiframe alignment is initiated without
influencing doubleframe synchronous state. If
V_AUTO_RESYNC is enabled and multiframe
alignment can not be regained, a new search of
doubleframe is initiated.
Note: This bit is only valid in CRC multiframe
format.
Resynchronization
’1’ = initiate resynchronization of receive frame
October 2003
Data Sheet
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HFC-E1
E1 interface
Cologne
Chip
180 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
Cologne
Chip
0x26
(write only)
R_RX_FR1
E1 receive frame configuration, register 1
Bits
Reset
Name
Description
Value
0
0
V_RX_MF
Multiframe mode
’0’ = normal doubleframe mode
’1’ = multiframe mode (CRC4)
1
0
V_RX_MF_SYNC
Multiframe alignment error
’0’ = normal operation
’1’ = MFA error leads to loss of synchronization
2
0
V_RX_SL0_RAM
Time slot 0 data destination
’0’ = time slot 0 data is written into HFC-channel 0
’1’ = time slot 0 data is written into alternating
RAM buffer
4..3
(reserved)
Must be ’00’.
Error simulation
This bit is for diagnostic purpose only.
’0’ = no action
’1’ = increment all error counters
5
0
V_ERR_SIM
6
0
V_RES_NMF
Reset ‘no multiframe found’ (NMF) status
’0’ = no action
’1’ = reset no MFA found status which is set after
400 ms of MFA searching
This bit is automatically cleared.
7
October 2003
(reserved)
Must be ’0’.
Data Sheet
181 of 306
HFC-E1
E1 interface
R_TX0
(write only)
Cologne
Chip
0x28
E1 transmitter configuration, register 0
Bits
Reset
Name
Description
Value
0
1..0
V_TX_CODE
Transmit code
’00’ = NRZ (pin R_A is data output and pin R_B is
clock output in NRZ mode)
’10’ = AMI code
’01’ = HDB3 code
’11’ = reserved
0
2
V_TX_FBAUD
Full / half bauded
’0’ = transmit pulse is half bit long
’1’ = transmit pulse is full bit long
0
3
V_TX_CMI_CODE
Code mark inversion (CMI)
’0’ = CMI off
’1’ = CMI on (only T_A is used as data output)
4
0
V_TX_INV_CMI_CODE
Inverted CMI code
This bit is only valid if CMI is on.
’0’ = CMI code
’1’ = inverted CMI code
5
0
V_TX_INV_CLK
Polarity of clock
This bit is only valid if data clock output is enabled.
’0’ = non-inverted clock
’1’ = inverted clock
6
0
V_TX_INV_DATA
Polarity of output data
’0’ = non-inverted data
’1’ = inverted data
0
7
V_OUT_EN
Buffer enable
’0’ = output buffers disabled (tristate)
’1’ = output buffers enabled
G
Important !
Transmit data is only generated if V_OUT_EN bit of the register R_TX0 is set to
’1’.
182 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
R_TX1
(write only)
Cologne
Chip
0x29
E1 transmitter configuration, register 1
Bits
Reset
Name
Description
Value
0
0
Polarity of mark
V_INV_CLK
’0’ = normal operation
’1’ = inverted clock
This bit is only valid with CMI code.
1
0
TxD-exchange
V_EXCHG_DATA_LI
’0’ = normal operation
’1’ = exchange data output lines T_A and T_B
2
0
4..3
5
0
V_AIS_OUT
Generate AIS output signal
Continuous ’1’s are generated.
(reserved)
Must be ’00’.
Transmitter mode
V_ATX
’0’ = standard transmitter
’1’ = analog transmitter tandem mode
6
0
No tristate
V_NTRI
’0’ = tristate for gap between pulses enabled
’1’ = tristate for gap between pulses disabled
7
0
Error counter mode
V_AUTO_ERR_RES
’0’ = normal counter operation after reaching
maximum count, counter starts at 0 again
’1’ = every second the error counters will be reset
automatically after they are latched
Note: The latched state should be read within the
next second. During updating reading should be
avoided.
G
Please note !
The default settings are:
October 2003
V_INV_CLK:
’0’
V_EXCHG_DATA_LI:
’0’
V_ATX:
’1’
V_NTRI:
’1’
Data Sheet
183 of 306
HFC-E1
E1 interface
(write only)
R_TX_FR0
Cologne
Chip
0x2C
E1 time slot 0 configuration, register 0
Bits
Reset
Name
Description
Value
0
0
V_TRP_FAS
Transparent Si (FAS) bit
’0’ = Si bit will be taken from V_TX_FAS
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
1
0
V_TRP_NFAS
Transparent Si (NFAS) bit
’0’ = Si bit will be taken from V_TX_NFAS
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
2
0
V_TRP_RAL
Transparent remote alarm
’0’ = remote alarm bit will be generated internally
from the state machine
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
7..3
0
V_TRP_SA
Transparent Sa4 . . Sa8 bits
’0’ = Sa bits will be taken from V_TX_SA
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
184 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
Cologne
Chip
0x2D
(write only)
R_TX_FR1
E1 time slot 0 configuration, register 1
This register is only used if V_TRP_SL0 of the register R_TX_FR2 is not set.
Bits
Reset
Name
Description
Value
0
0
V_TX_FAS
Si (FAS) bit
This bit is only used in doubleframe format.
1
0
V_TX_NFAS
Si (NFAS) bit
2
0
V_TX_RAL
Remote alarm bit
’0’ = normal operation
’1’ = remote alarm bit generated from the state
machine is fixed to ’1’
7..3
0
October 2003
V_TX_SA
Sa4 . . Sa8 bits
Data Sheet
185 of 306
HFC-E1
E1 interface
(write only)
R_TX_FR2
Cologne
Chip
0x2E
E1 time slot 0 configuration, register 2
Bits
Reset
Name
Description
Value
0
0
V_TX_MF
Framing selection
’0’ = doubleframe format
’1’ = multiframe mode (CRC4)
1
0
V_TRP_SL0
Time slot 0 transparent mode
’0’ = normal operation
’1’ = the HFC-channel 0 data or RAM data will be
used and the registers R_TX_FR0 and R_TX_FR1
are ignored
2
0
V_TX_SL0_RAM
Time slot 0 data source
’0’ = time slot 0 data comes from HFC-channel 0
’1’ = time slot 0 data comes from alternating RAM
buffer
3
4
(reserved)
0
V_TX_E
Must be ’0’.
Automatic transmission of submultiframe status
’0’ = XS13 and XS15 bits from V_XS13_ON and
V_XS15_ON of this register are transmitted
’1’ = E-bits are transmitted (CRC calculation result)
5
0
V_NEG_E
Polarity of E-bits
’0’ = positive E-bits
’1’ = negative E-bits
6
0
V_XS13_ON
Transmit spare bit XS13
(Frame 13 of multiframe)
’0’ = XS13 is ’0’
’1’ = XS13 is ’1’
Note: This bit is only valid in CRC multiframe.
7
0
V_XS15_ON
Transmit spare bit XS15
(Frame 15 of multiframe)
’0’ = XS15 is ’0’
’1’ = XS15 is ’1’
Note: This bit is only valid in CRC multiframe.
186 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
Cologne
Chip
0x30
(write only)
R_RX_OFF
E1 receive buffer configuration register
Bits
Reset
Name
Description
Value
1..0
0
V_RX_SZ
Buffer size
Elastic buffer size in number of frames (0 . . 3)
2
0
V_RX_INIT
Buffer initialization
Some data may be lost when this bit is set.
This bit is automatically cleared.
(reserved)
Must be ’00000’.
7..3
October 2003
Data Sheet
187 of 306
HFC-E1
E1 interface
Cologne
Chip
0x31
(write only)
R_SYNC_OUT
E1 synchronization source selection for PCM master
Bits
Reset
Name
Description
Value
0
0
V_SYNC_E1_RX
PCM master synchronization
’0’ = PCM master synchronizes on the E1 TX end
of frame (EOF) signal
’1’ = PCM master synchronizes on the E1 RX end
of frame (EOF) signal
4..1
5
(reserved)
0
V_IPATS0
Must be ’00000’.
RAI pulse configuration for IPATS test
’0’ = normal opeartion
’1’ = delete short RAI low pulses, increase RAI to a
minimum of more than 1 ms
Note: This bit is only used for passing IPATS test
equipment.
6
0
V_IPATS1
CRC configuration for IPTAS test
’0’ = normal operation
’1’ = delete CRC reporting over E-bits up to 8 ms
after MFA synchronization
Note: This bit is only used for passing IPATS test
equipment.
7
0
V_IPATS2
JATT configuration for IPATS test
’0’ = normal operation
’1’ = stop jitter attenuator (JATT) adaptation when
in F3 or G3 state
Note: This bit is only used for passing IPATS test
equipment.
188 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
Cologne
Chip
0x34
(write only)
R_TX_OFF
E1 transmit buffer configuration register
Bits
Reset
Name
Description
Value
1..0
0
V_TX_SZ
Buffer size
Elastic buffer size in number of frames (0 . . 3)
2
0
V_TX_INIT
Buffer initialization
Some data may be lost when this bit is set.
This bit is automatically cleared.
(reserved)
Must be ’00000’.
7..3
October 2003
Data Sheet
189 of 306
HFC-E1
Cologne
Chip
E1 interface
0x35
(write only)
R_SYNC_CTRL
E1 transmit clock sychronization register
Bits
Reset
Name
Description
Value
0
0
V_EXT_CLK_SYNC
E1 synchronization source selection
’0’ = clock synchronization derived from receive
data
’1’ = synchronization is determined from
V_PCM_SYNC, V_NEG_CLK and V_HCLK
1
0
V_SYNC_OFFS
E1 synchronization type selection
’0’ = TX and RX frame synchronization phase
offset 0
’1’ = TX and RX frame synchronization phase
offset arbitrary
Note: If this bit is set the synchronization process
is faster because the phase offset can be arbitrary.
2
0
V_PCM_SYNC
E1 synchronization source selection
’0’ = pin SYNC_I
’1’ = synchronization from PCM pin F0IO
3
0
V_NEG_CLK
External synchronization clock polarity
’0’ = positive edge
’1’ = negative edge
4
0
V_HCLK
Half clock frequency
’0’ = normal operation
’1’ = external synchronization clock will be divided
by 2
5
0
V_JATT_AUTO_DEL
Restricted frequency search
’0’ = automatic frequency search is initiated after 3
frequency mismatches every 0.5 s
’1’ = automatic frequency search is initiated after 10
frequency mismatches every 0.5 s
6
0
V_JATT_AUTO
Automatic JATT adjustment
’0’ = automatic JATT adjust enabled
’1’ = automatic JATT adjust disabled
7
0
V_JATT_EN
JATT enable
’0’ = JATT enabled
’1’ = JATT disabled (transmit clock is generated
from crystal clock)
190 of 306
Data Sheet
October 2003
HFC-E1
5.4.2
E1 interface
Cologne
Chip
Read only register
0x20
(read only)
R_E1_RD_STA
E1 state machine register
Bits
Reset
Name
Description
V_E1_STA
E1 state
Binary value of actual state (LT: Gx, TE: Fx).
Value
2..0
0
5..3
(reserved)
6
0
V_ALT_FR_RX
Alternating RAM bank
Shows which bank of time slot 0 data in RAM is
currently used for receive data. Receive data is
written to the RAM.
This bit is toggled with every multiframe.
7
0
V_ALT_FR_TX
Alternating RAM bank
Shows which bank of time slot 0 data in RAM is
currently used for transmit data. Transmit data is
read from the RAM.
This bit is toggled with every multiframe.
October 2003
Data Sheet
191 of 306
HFC-E1
E1 interface
Cologne
Chip
0x24
(read only)
R_RX_STA0
E1 receive status, register 0
Bits
Reset
Name
Description
Value
1..0
0
V_RX_STA
Receive status
’00’ = not synchronized
’01’ = FAS found
’10’ = NFAS found after FAS
’11’ = synchronized (FAS - NFAS - FAS found)
2
0
V_FR_SYNC
Frame synchronization status
Frame synchronization status according to the state
machine.
3
0
V_SIG_LOS
LOS status
Loss of receive signal detected.
5..4
0
V_MFA_STA
Status of multi frame alignment (MFA)
’01’ = MFA pattern found
’10’ = MFA reached (2 consecutive MFA patterns
found)
6
0
V_AIS
7
0
V_NO_MF_SYNC
Receiving Alarm Indication Signal (AIS)
No multiframe (NMF) synchronization
’1’ = no multiframe synchronization found for
400 ms
This bit is reset by asserting V_RES_NMF of the
register R_RX_FR1.
192 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
(read only)
R_RX_STA1
Cologne
Chip
0x25
E1 receive status, register 1
Bits
Reset
Name
Description
Value
0
0
V_SI_FAS
Si (FAS) in time slot 0
1
0
V_SI_NFAS
Si (NFAS) in time slot 0
2
0
V_A
A-bit of time slot 0
3
0
V_CRC_OK
CRC result
’1’ = CRC4 ok
4
0
V_TX_E1
Transmit CRC4 E1-bit
5
0
V_TX_E2
Transmit CRC4 E2-bit
6
0
V_RX_E1
Receive CRC4 E1-bit
7
0
V_RX_E2
Receive CRC4 E2-bit
October 2003
Data Sheet
193 of 306
HFC-E1
E1 interface
Cologne
Chip
0x26
(read only)
R_RX_STA2
E1 receive status, register 2
Bits
Reset
Name
Description
V_SA6
SA6 [4..1] bits of time slot 0
Value
3..0
0
5..4
(reserved)
6
0
V_SA6_OK
SA6 OK
The same value was received in 3 consecutive
SMFs.
7
0
V_SA6_CHG
SA6 pattern has changed
This bit is automatically reset after register read.
194 of 306
Data Sheet
October 2003
HFC-E1
E1 interface
(read only)
R_RX_STA3
Cologne
Chip
0x27
E1 receive status, register 3
Bits
Reset
Name
Description
V_SA84
Sa [8..4] bits
Value
4..0
0
7..5
October 2003
(reserved)
Data Sheet
195 of 306
HFC-E1
E1 interface
R_SLIP
(read only)
Cologne
Chip
0x2C
Frequency slip warning register
Bits
Reset
Name
Description
Frequency slip in receive transmission
This bit is set when an overflow of the elastic
receive buffer has occured as a result of a frequency
slip. This bit is automatically cleared with new
buffer write access.
Value
0
0
V_SLIP_RX
2..1
0
(reserved)
3
0
V_FOSLIP_RX
Force slip warning
This bit is set when bit V_SLIP_RX had been set at
least one time after the last read access to this
register. This bit is automatically cleared with an
read access to this register.
4
0
V_SLIP_TX
Frequency slip in transmit transmission
This bit is set when an overflow of the elastic
transmit buffer has occured as a result of a
frequency slip. This bit is automatically cleared
with new buffer read access.
6..5
0
(reserved)
7
0
V_FOSLIP_TX
196 of 306
Force slip warning
This bit is set when bit V_SLIP_TX had been set at
least one time after the last read access to this
register. This bit is automatically cleared with an
read access to this register.
Data Sheet
October 2003
HFC-E1
E1 interface
(read only)
R_FAS_ECL
Cologne
Chip
0x30
Error counter for missing or wrong FAS, low byte
Bits
Reset
Name
Description
V_FAS_ECL
Bits [7..0] of FAS error count
Value
7..0
0
(read only)
R_FAS_ECH
0x31
Error counter for missing or wrong FAS, high byte
Bits
Reset
Name
Description
V_FAS_ECH
Bits [15..8] of FAS error count
Value
7..0
0
October 2003
Data Sheet
197 of 306
HFC-E1
E1 interface
Cologne
Chip
0x32
(read only)
R_VIO_ECL
Error counter for code violation of HDB3 code, low byte
Bits
Reset
Name
Description
V_VIO_ECL
Bits [7..0] of code violation error count
Value
7..0
0
0x33
(read only)
R_VIO_ECH
Error counter for code violation of HDB3 code, high byte
Bits
Reset
Name
Description
V_VIO_ECH
Bits [15..8] of code violation error count
Value
7..0
0
(read only)
R_CRC_ECL
0x34
Receive CRC4 error count, low byte
Bits
Reset
Name
Description
V_CRC_ECL
Bits [7..0] of CRC4 error count
Value
7..0
198 of 306
0
Data Sheet
October 2003
HFC-E1
E1 interface
(read only)
R_CRC_ECH
Cologne
Chip
0x35
Receive CRC4 error count, high byte
Bits
Reset
Name
Description
V_CRC_ECH
Bits [15..8] of CRC4 error count
Value
7..0
0
(read only)
R_E_ECL
0x36
Error counter for CRC4 error reporting by received E-bits, low byte
Bits
Reset
Name
Description
V_E_ECL
Bits [7..0] of CRC4 error count
Value
7..0
0
(read only)
R_E_ECH
0x37
Error counter for CRC4 error reporting by received E-bits, high byte
Bits
Reset
Name
Description
V_E_ECH
Bits [15..8] of CRC4 error count
Value
7..0
0
October 2003
Data Sheet
199 of 306
HFC-E1
E1 interface
R_SA6_SA13_ECL
(read only)
Cologne
Chip
0x38
Error count of [SA64, SA63, SA62, SA61] = ’0001’ or ’0011’, low byte
Bits
Reset
Name
Description
V_SA6_SA13_ECL
Bits [7..0] of error count
Value
7..0
0
R_SA6_SA13_ECH
(read only)
0x39
Error count of [SA64, SA63, SA62, SA61] = ’0001’ or ’0011’, high byte
Bits
Reset
Name
Description
V_SA6_SA13_ECH
Bits [15..8] of error count
Value
7..0
0
R_SA6_SA23_ECL
(read only)
0x3A
Error count of [SA64, SA63, SA62, SA61] = ’0010’ or ’0011’, low byte
Bits
Reset
Name
Description
V_SA6_SA23_ECL
Bits [7..0] of error count
Value
7..0
200 of 306
0
Data Sheet
October 2003
HFC-E1
E1 interface
R_SA6_SA23_ECH
(read only)
Cologne
Chip
0x3B
Error count of [SA64, SA63, SA62, SA61] = ’0010’ or ’0011’, high byte
Bits
Reset
Name
Description
V_SA6_SA23_ECH
Bits [15..8] of error count
Value
7..0
0
October 2003
Data Sheet
201 of 306
HFC-E1
E1 interface
Cologne
Chip
202 of 306
Data Sheet
October 2003
Chapter 6
PCM interface
Table 6.1: Overview of the HFC-E1 PCM interface registers
Write only registers:
Address
October 2003
Name
Read only registers:
Page
Address
Name
Page
0x10
R_SLOT
213
0x18
R_F0_CNTL
224
0x14
R_PCM_MD0
214
0x19
R_F0_CNTH
224
0x15
R_SL_SEL0
215
0x15
R_SL_SEL1
216
0x15
R_SL_SEL2
216
0x15
R_SL_SEL3
217
0x15
R_SL_SEL4
217
0x15
R_SL_SEL5
218
0x15
R_SL_SEL6
218
0x15
R_SL_SEL7
219
0x15
R_PCM_MD1
220
0x15
R_PCM_MD2
221
0x15
R_SH0L
222
0x15
R_SH0H
222
0x15
R_SH1L
222
0x15
R_SH1H
223
0xD0
A_SL_CFG
223
Data Sheet
203 of 306
HFC-E1
PCM interface
Cologne
Chip
Table 6.2: Overview of the HFC-E1 PCM pins ( ∗ : Second pin function)
PCM pins:
Number
Name
Description
97
SYNC_I
Synchronization Input
98
SYNC_O
Synchronization Output
117
C2O
PCM bit clock output
118
C4IO
PCM double bit clock I/O
119
F0IO
PCM frame clock I/O (8 kHz)
120
STIO1
PCM data bus 1, I or O per time slot
121
STIO2
PCM data bus 2, I or O per time slot
CODEC select via enable lines:
Number
Name
Description
107
F1_7
PCM CODEC enable 7
108
F1_6
PCM CODEC enable 6
109
F1_5
PCM CODEC enable 5
110
F1_4
PCM CODEC enable 4
111
F1_3
PCM CODEC enable 3
112
F1_2
PCM CODEC enable 2
113
F1_1
PCM CODEC enable 1
114
F1_0
PCM CODEC enable 0
CODEC select via time slot number:
Number
204 of 306
Name
Description
106
∗
NC
107
∗
F1_7
PCM CODEC enable 7
108
∗
F1_6
PCM CODEC enable 6
109
∗
F1_5
PCM CODEC enable 5
110
∗
F1_4
PCM CODEC enable 4
111
∗
F1_3
PCM CODEC enable 3
112
∗
F1_2
PCM CODEC enable 2
113
∗
F1_1
PCM CODEC enable 1
114
∗
F1_0
PCM CODEC enable 0
Data Sheet
October 2003
HFC-E1
Cologne
Chip
PCM interface
6.1 PCM interface function
The PCM interface has up to 32, 64 or 128 time slots for receive and transmit data depending on the
PCM clock frequency and the selected mode. The functional block diagram is shown in Figure 6.1.
The HFC-E1 has two PCM data pins STIO1 and STIO2 which can both be input or output. PCM
output data is transmitted to two output buffers. These can be enabled independently from each other.
PCM input data can either come from one of the two PCM data pins or from the PCM output channel.
This way PCM data can be looped internally without influencing the PCM bus.
Enable Memory
Read for
Transmit Slot
[1]
STIO1 Output
Buffer Enable for
Transmit Slot
[3]
Data Channel
Select for
Transmit Slot
[2]
CHANNEL
PCM data out
CHANNEL
STIO1
Flow Controller
SLOT
CHANNEL
CHANNEL
PCM
data out
A
STIO2
B
C
SLOT
[7]
Enable Memory
Write for
Receive Slot
[6]
Data Channel
Select for
Receive Slot
[5]
Input Buffer
Select for
Receive Slot
[4]
STIO2 Output
Buffer Enable for
Transmit Slot
Figure 6.1: PCM interface function block diagram
6.2 PCM initialization
After hard or soft reset the PCM interface starts an initialization sequence to set all A_SL_CFG registers of the PCM time slots to the reset value 0. This can be done only if valid C4IO and F0IO signals
exist. The initialization process stops after 2 F0IO periods. To check if the initialization sequence is
finished after a reset, the register R_F0_CNTL value must be equal or greater than 2.
October 2003
Data Sheet
205 of 306
HFC-E1
Cologne
Chip
PCM interface
Table 6.3: PCM interface configuration with bitmaps of the register A_SL_CFG (The reference numbers relate
to the numbers given in Figure 6.1)
Reference
Function
Bitmap
Value
[1]
Enable memory read for transmit slot
V_ROUT
= ’00’
[2]
HFC-channel select for transmit slot
V_CH_SNUM
0 . . 31
[3]
STIO1 output buffer enable for transmit slot
V_ROUT
’10’
[4]
STIO2 output buffer enable for transmit slot
V_ROUT
’11’
[5]
Input buffer select for receive slot
(MUX A)
V_ROUT
’01’ (Loop PCM internally)
(MUX B)
V_ROUT
’10’ (Data In from STIO1)
(MUX C)
V_ROUT
’11’ (Data In from STIO2)
[6]
HFC-channel select for receive slot
V_CH_SNUM
0 . . 31
[7]
Enable memory write for receive slot
V_ROUT
= ’00’
G
Important !
The PCM data rate must be set immediately (about 40 µs) after PCM reset to
ensure the complete array register reset procedure. Only the number of PCM
time slots which are available, are initialized during reset. Thus it is not possible
to change the PCM data rate later without manually array register reset.
This is important in slave mode to avoid uncontrolled data transmission caused
by F0IO pulses from an external device.
6.3
∗
PCM timing
F0IO starts one C4IO clock earlier if bit V_F0_LEN in R_PCM_MD0 register is set. If this bit is
set, F0IO is also awaiting one C4IO clock cycle earlier in slave mode.
206 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
PCM interface
tCF0
tCF1
tf
tC4P
tC4H
tC4L
C4IO
tF0iCYCLE
F0IO
*)
tF0iCYCLE
tF0iH
tF0iS
tF0iW
tSToD4
tSToD2
STIO1/2
(output)
tSTiS
tSTiH
STIO1/2
(input)
tD
tC2P - 1 bit cell
tC2H
tC2L
C2O
Figure 6.2: PCM timing
October 2003
Data Sheet
207 of 306
HFC-E1
6.3.1
Cologne
Chip
PCM interface
Master mode
To configure the HFC-E1 as PCM bus master, the bit V_PCM_MD of the R_PCM_MD0 register must
be set. In this case C4IO and F0IO are outputs.
The PCM bit rate is configured by the bitmap V_PCM_DR of the R_PCM_MD1 register.
Table 6.4: Master mode timing specification
Symbol
Characteristics
Min.
tC
for 2 Mb/s
122.07 ns
for 4 Mb/s
61.035 ns
for 8 Mb/s
30.518 ns
Clock C4IO period ∗
Typ.
Max.
2tC − 26 ns
2tC
2tC + 26 ns
Clock C4IO High
Width ∗
tC − 26 ns
tC
tC + 26 ns
tC4L
Clock C4IO Low
Width ∗
tC − 26 ns
tC
tC + 26 ns
tC2P
Clock C2O Period
4tC − 52 ns
4tC
4tC + 52 ns
tC2H
Clock C2O High Width
2tC − 26 ns
2tC
2tC + 26 ns
tC2L
Clock C2O Low Width
2tC − 26 ns
2tC
2tC + 26 ns
tF0iW
F0IO Width
Short F0IO
2tC − 6 ns
2tC
2tC + 6 ns
Long F0IO
4tC − 6 ns
4tC
4tC + 6 ns
tC4P
tC4H
tSToD2
STIO1/2 Delay fom C2O 15 ns
30 ns
tSToD4
STIO1/2 Delay fom C4IO
10 ns
25 ns
tCF1
C4IO to F0IO tCF0
C4IO to F0IO
tF0iCYCLE
F0IO Cycle Time
∗:
0.5 ns
3 ns
0.5 ns
3 ns
1 half clock adjust
124.975 µs
125.000 µs
125.025 µs
2 half clocks adjust
124.950 µs
125.000 µs
125.050 µs
3 half clocks adjust
124.925 µs
125.000 µs
125.075 µs
4 half clocks adjust
124.900 µs
125.000 µs
125.100 µs
Time depends on accuracy of OSC_IN frequency. Because of clock adjustment in the 31st time slot these
are the worst case timings when C4IO is adjusted.
208 of 306
Data Sheet
October 2003
HFC-E1
6.3.2
Cologne
Chip
PCM interface
Slave mode
To configure the HFC-E1 as PCM bus slave the bit V_PCM_MD f the R_PCM_MD0 register must be
cleared. In this case C4IO and F0IO are inputs.
Table 6.5: Slave mode timing specification
Symbol
Characteristics
tC
for 2 Mb/s
122.07 ns
for 4 Mb/s
61.035 ns
for 8 Mb/s
30.518 ns
Typ.
Max.
tC4P
Clock C4IO period ∗
tC4H
Clock C4IO High Width
20 ns
tC4L
Clock C4IO Low Width
20 ns
tC2P
Clock C2O Period ∗
4tC
tC2H
Clock C2O High Width
2tC
tC2L
Clock C2O Low Width
2tC
tF0iS
F0IO Setup Time to C4IO
20 ns
tF0iH
F0IO Hold Time after C4IO
20 ns
tF0iW
F0IO Width
170 ns
tSTiS
STIO1 / STIO2 Setup Time
20 ns
tSTiH
STIO1 / STIO2 Hold Time
20 ns
tCF1
C4IO to F0IO 0.5 ns
3 ns
0.5 ns
3 ns
tCF0
∗:
Min.
C4IO to F0IO
2tC
If the E1 interface is synchronized from C4IO (LT mode) the requency must be stable to ±10−4 .
6.4 External CODECs
External CODECs can be connected to the HFC-E1 PCM interface. There are two ways of programming the PCM–CODEC–interconnection. First, a set of eight CODEC enable lines allow to connect
up to eight external CODECs to the HFC-E1. The second way uses the current time slot number
that must be decoded to a CODEC’s select signal. Then up to 128 external CODECs can be connected to the HFC-E1. The choice of these connectivities is done with V_CODEC_MD of the register
R_PCM_MD1.
6.4.1
CODEC select via enable lines
The HFC-E1 has eight CODEC enable signals F1_7 . . F1_0. Every external CODEC has to
be assigned to a PCM time slot via the bitmaps V_SL_SEL7 . . V_SL_SEL0 of the registers
R_SL_SEL7 . . R_SL_SEL0.
October 2003
Data Sheet
209 of 306
HFC-E1
Cologne
Chip
PCM interface
Two shape signals can be programmed. The last bit determines the inactive level by which
non-inverted and inverted shape signals can be programmed. Every external CODEC can
choose one of the two shape signals with the bits V_SH_SEL7 . . V_SH_SEL0 of the registers
R_SL_SEL7 . . R_SL_SEL0.
F0IO
C4IO
low byte
F1_0
high byte
low byte
high byte
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
MSB
LSB
F1_1
1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1
LSB
MSB
C2O
bit
1
0
7
6
5
4
slot
3
2
1
0
0
7
6
1
16 C4IO pulses per slot
8 C2O pulses per slot
Figure 6.3: Example for two CODEC enable signal shapes with SHAPE0 and SHAPE1.
Figure 6.3 shows an example with two external CODECs with F1_0 and F1_1 enable signals. Time
slot 0 starts with the F0IO pulse. In this example – assuming that PCM30 is configured – F1_0 enables
the first CODEC on time slot 0 and shape bytes on R_SH0L and R_SH0H with the following register
settings.
Register setup:
R_PCM_MD0 : V_PCM_IDX = 0
R_SL_SEL0
(R_SL_SEL0 register accessible)
: V_SL_SEL0 = 0x1F
(time slot #0)
: V_SH_SEL0 = 0
(shape bytes R_SH0L and R_SH0H)
The second CODEC on time slot 1 and shape bytes on R_SH1L and R_SH1H must be configured as
shown below.
Register setup:
R_PCM_MD0 : V_PCM_IDX = 1
R_SL_SEL1
(R_SL_SEL1 register accessible)
: V_SL_SEL1 = 0
(time slot #1)
: V_SH_SEL1 = 1
(shape bytes R_SH1L and R_SH1H)
The shown shape signals have to be programmed in reverse bit order by the following register settings.
210 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
PCM interface
Register setup:
R_PCM_MD0 : V_PCM_IDX = 0xC
R_SH0L
: V_SH0L
= 0xF8
R_PCM_MD0 : V_PCM_IDX = 0xD
R_SH0L
: V_SH0L
= 0x03
R_PCM_MD0 : V_PCM_IDX = 0xE
R_SH0L
: V_SH0L
= 0x1F
R_PCM_MD0 : V_PCM_IDX = 0xF
R_SH0L
6.4.2
: V_SH0L
= 0xF0
(R_SH0L register accessible)
(0xF8 = ’11111000’
reverse
−→
’00011111’)
(R_SH0H register accessible)
(0x03 = ’00000011’
reverse
−→
’11000000’)
(R_SH1L register accessible)
(0x1F = ’00011111’
reverse
−→
’11111000’)
(R_SH1H register accessible)
(0xF0 = ’11110000’
reverse
−→
’00001111’)
CODEC select via time slot number
Alternatively, external CODECs can be enabled by decoding the time slot number. In this case, two
programmable shape signals SHAPE0 and SHAPE1 are put out with every time slot. The current time
slot number is issued on the pins F_Q6 . . F_Q0.
The shape signals can be programmed. The example in Figure 6.4 shows shape signals that are
programmed in the same way as shown above (see Section 6.4.1).
F_Q6 . . F_Q0 must be decoded externally to generate CODEC select signals in dependence on the
PCM time slot.
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
PCM interface
F0IO
C4IO
low byte
SHAPE0
high byte
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
LSB
SHAPE1
low byte
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
MSB
LSB
1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1
LSB
MSB
1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1
LSB
MSB
F_Q[6..0]
high byte
MSB
0
1
C2O
bit
slot
1
0
7
6
5
4
3
2
1
0
0
7
6
1
16 C4IO pulses per slot
8 C2O pulses per slot
Figure 6.4: Example for two CODEC enable signal shapes
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Data Sheet
October 2003
HFC-E1
PCM interface
Cologne
Chip
6.5 Register description
6.5.1
Write only register
(write only)
R_SLOT
0x10
PCM time slot selection
This register is used to select a PCM time slot. Before a PCM slot array register can be
accessed, this index register must specify the desired slot number and data direction. Depending
on the V_PCM_DR value in the R_PCM_MD1 register 32, 64 or 128 time slots are available for
each data direction.
Bits
Reset
Name
Description
Value
0
0
V_SL_DIR
PCM time slot data direction
’0’ = transmit PCM data
’1’ = receive PCM data
7..1
0x00
October 2003
V_SL_NUM
PCM time slot number
Data Sheet
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HFC-E1
PCM interface
Cologne
Chip
0x14
(write only)
R_PCM_MD0
PCM mode, register 0
Bits
Reset
Name
Description
Value
0
0
V_PCM_MD
PCM bus mode
’0’ = slave (pins C4IO and F0IO are inputs)
’1’ = master (pins C4IO and F0IO are outputs)
If no external C4IO and F0IO signal is provided this
bit must be set for operation.
1
0
V_C4_POL
Polarity of C4IO clock
’0’ = pin F0IO is sampled on negative clock
transition of C4IO
’1’ = pin F0IO is sampled on positive clock
transition of C4IO
2
0
V_F0_NEG
Polarity of F0IO signal
’0’ = positive pulse
’1’ = negative pulse
3
0
V_F0_LEN
Duration of F0IO signal in slave mode
’0’ = active for one C4IO clock (244 ns at 4 MHz)
’1’ = active for two C4IO clocks (488 ns at 4 MHz)
7..4
0
V_PCM_IDX
Index value to select the register at address 15
At address 15 a so-called multi-register is
accessible.
0 = R_SL_SEL0 register accessible
1 = R_SL_SEL1 register accessible
2 = R_SL_SEL2 register accessible
3 = R_SL_SEL3 register accessible
4 = R_SL_SEL4 register accessible
5 = R_SL_SEL5 register accessible
6 = R_SL_SEL6 register accessible
7 = R_SL_SEL7 register accessible
9 = R_PCM_MD1 register accessible
0xA = R_PCM_MD2 register accessible
0xC = R_SH0L register accessible
0xD = R_SH0H register accessible
0xE = R_SH1L register accessible
0xF = R_SH1H register accessible
214 of 306
Data Sheet
October 2003
HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_SL_SEL0
Slot selection register for pin F1_0
This multi-register is selected with bitmap V_PCM_IDX = 0 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_0 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_0. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL0
7
1
V_SH_SEL0
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
G
Important !
For selecting slot 0 the value that has to be written to the bitmap
V_SL_SEL0 . . V_SL_SEL7 of the register R_SL_SEL0 . . R_SL_SEL7 depends on
the PCM data rate:
PCM data rate Value
PCM30
0x1F
PCM64
0x3F
PCM128
0x7F
Please note that time slot 0 for PCM128 can only be used
with V_SH_SEL0 . . V_SH_SEL7 = 0 (SHAPE 0) in the registers
R_SL_SEL0 . . R_SL_SEL7.
October 2003
Data Sheet
215 of 306
HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_SL_SEL1
Slot selection register for pin F1_1
This multi-register is selected with bitmap V_PCM_IDX = 1 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_1 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_1. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL1
7
1
V_SH_SEL1
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
0x15
(write only)
R_SL_SEL2
Slot selection register for pin F1_2
This multi-register is selected with bitmap V_PCM_IDX = 2 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_2 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_2. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL2
7
1
V_SH_SEL2
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
216 of 306
Data Sheet
October 2003
HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_SL_SEL3
Slot selection register for pin F1_3
This multi-register is selected with bitmap V_PCM_IDX = 3 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_3 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_3. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL3
7
1
V_SH_SEL3
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
0x15
(write only)
R_SL_SEL4
Slot selection register for pin F1_4
This multi-register is selected with bitmap V_PCM_IDX = 4 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_4 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_4. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL4
7
1
V_SH_SEL4
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
October 2003
Data Sheet
217 of 306
HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_SL_SEL5
Slot selection register for pin F1_5
This multi-register is selected with bitmap V_PCM_IDX = 5 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_5 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_5. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL5
7
1
V_SH_SEL5
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
0x15
(write only)
R_SL_SEL6
Slot selection register for pin F1_6
This multi-register is selected with bitmap V_PCM_IDX = 6 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_6 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_6. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL6
7
1
V_SH_SEL6
Shape selection
’0’ = use shape 1 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
218 of 306
Data Sheet
October 2003
HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_SL_SEL7
Slot selection register for pin F1_7
This multi-register is selected with bitmap V_PCM_IDX = 7 of the register R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_7 is disabled.
Bits
Reset
Name
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 +1 for
F1_7. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Value
6..0
0x7F
V_SL_SEL7
7
1
V_SH_SEL7
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
October 2003
Data Sheet
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HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_PCM_MD1
PCM mode, register 1
This multi-register is selected with bitmap V_PCM_IDX = 9 of the register R_PCM_MD0.
Bits
Reset
Name
Description
Value
0
0
V_CODEC_MD
CODEC enable signal selection
’0’ = CODEC enable signals on F1_0 . . F1_7
’1’ = SHAPE 0 pulse on pin SHAPE0, SHAPE 1
pulse on pin SHAPE1 and CODEC count on
F_Q0 . . F_Q6 for up to 128 external CODECs.
1
0
(reserved)
3..2
0
V_PLL_ADJ
Must be ’0’.
DPLL adjust speed
’00’ = C4IO clock is adjusted in the last time slot of
PCM frame 4 times by one half clock cycle of
internal PCM clock
’01’ = C4IO clock is adjusted in the last time slot of
PCM frame 3 times by one half clock cycle of
internal PCM clock
’10’ = C4IO clock is adjusted in the last time slot of
PCM frame twice by one half clock cycle of
internal PCM clock
’11’ = C4IO clock is adjusted in the last time slot of
PCM frame once by one half clock cycle of internal
PCM clock
Note: Internal PCM clock is 16.384 MHz nominell
5..4
0
V_PCM_DR
PCM data rate
’00’ = 2 MBit/s (C4IO is 4.096 MHz, 32 time slots)
’01’ = 4 MBit/s (C4IO is 8.192 MHz, 64 time slots)
’10’ = 8 MBit/s (C4IO is 16.384 MHz, 128 time
slots)
’11’ = unused
Every time slot exists in transmit and receive data
direction.
6
7
220 of 306
0
V_PCM_LOOP
PCM test loop
When this bit is set, the PCM output data is looped
to the PCM input data internally for all PCM time
slots.
(reserved)
Must be ’0’.
Data Sheet
October 2003
HFC-E1
PCM interface
Cologne
Chip
0x15
(write only)
R_PCM_MD2
PCM mode, register 2
This multi-register is selected with bitmap V_PCM_IDX = 0xA of the register R_PCM_MD0.
Bits
Reset
Name
Description
(reserved)
Must be ’0’.
V_SYNC_PLL
SYNC_O with internal PLL output
’0’ = V_SYNC_OUT is used for synchronization
Value
0
1
0
selection
’1’ = SYNC_O has a frequency of the internal PLL
output signal C4O divided by 8 (512 kHz, 1024 kHz
or 2048 kHz depending on the PCM data rate)
2
0
V_SYNC_SRC
PCM PLL synchronization source selection
’0’ = E1 interface (see R_SYNC_CTRL for further
sync configuration)
’1’ = SYNC_I input (8 kHz)
3
0
5..4
V_SYNC_OUT
SYNC_O output selection
’0’ = E1 interface
’1’ = SYNC_I is connected to SYNC_O
(reserved)
Must be ’00’.
Increase PCM frame time
This bit is only valid if V_EN_PLL is set.
’0’ = PCM frame time is reduced as selected by the
bitmap V_PLL_ADJ of the R_PCM_MD1 register
’1’ = PCM frame time is increased as selected by the
bitmap V_PLL_ADJ of the R_PCM_MD1 register
6
0
V_ICR_FR_TIME
7
0
V_EN_PLL
PLL enable
’0’ = normal operation
’1’ = enable PCM PLL adjustment
If enabled, the PCM clock is adjusted according to
V_ICR_FR_TIME. This can be used to make
synchronization by software if no synchronization
source is available.
October 2003
Data Sheet
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HFC-E1
PCM interface
R_SH0L
(write only)
Cologne
Chip
0x15
CODEC enable signal SHAPE0, low byte
This multi-register is selected with bitmap V_PCM_IDX = 0xC of the register R_PCM_MD0.
Bits
Reset
Name
Description
V_SH0L
Shape bits 7 . . 0
Every bit is used for 1/2 C4IO clock cycle.
Value
7..0
0
0x15
(write only)
R_SH0H
CODEC enable signal SHAPE0, high byte
This multi-register is selected with bitmap V_PCM_IDX = 0xD of the register R_PCM_MD0.
Bits
Reset
Name
Description
V_SH0H
Shape bits 15 . . 8
Every bit is used for 1/2 C4IO clock cycle.
Bit 7 of V_SH0H defines the value for the rest of
the period.
Value
7..0
0
0x15
(write only)
R_SH1L
CODEC enable signal SHAPE1, low byte
This multi-register is selected with bitmap V_PCM_IDX = 0xE of the register R_PCM_MD0.
Bits
Reset
Name
Description
V_SH1L
Shape bits 7 . . 0
Every bit is used for 1/2 C4IO clock cycle.
Value
7..0
222 of 306
0
Data Sheet
October 2003
HFC-E1
PCM interface
R_SH1H
(write only)
Cologne
Chip
0x15
CODEC enable signal SHAPE1, high byte
This multi-register is selected with bitmap V_PCM_IDX = 0xF of the register R_PCM_MD0.
Bits
Reset
Name
Description
V_SH1H
Shape bits 15 . . 8
Every bit is used for 1/2 C4IO clock cycle.
Bit 7 of V_SH1H defines the value for the rest of
the period.
Value
7..0
0
A_SL_CFG[SLOT]
(write only)
0xD0
HFC-channel assignment for the selected PCM time slot and PCM output buffer configuration
With this register a HFC-channel can be assigned to the selected PCM time slot. Additionally, the PCM buffers can be configured.
Before writing this array register the PCM time slot must be selected by the register R_SLOT.
Bits
Reset
Name
Description
Value
0
0
V_CH_SDIR
HFC-channel data direction
’0’ = HFC-channel for transmit data
’1’ = HFC-channel for receive data
5..1
0
V_CH_SNUM
HFC-channel number
(0 . . 31)
7..6
0
V_ROUT
PCM output buffer configuration
For transmit time slots:
’00’ = disable output buffers, no data transmision
’01’ = transmit data internally, output buffers
disabled
’10’ = output buffer enabled for STIO1
’11’ = output buffer enabled for STIO2
For receive time slots:
’00’ = input data is ignored
’01’ = loop PCM data internally
’10’ = data in from STIO2
’11’ = data in from STIO1
(See Figure 6.1 on page 205 for detailed information).
October 2003
Data Sheet
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HFC-E1
6.5.2
PCM interface
Cologne
Chip
Read only register
(read only)
R_F0_CNTL
0x18
F0IO pulse counter, low byte
Bits
Reset
Name
Description
V_F0_CNTL
Low byte (bits 7 . . 0) of the 125 µs time counter
This register should be read first to ‘lock’ the value
of the R_F0_CNTH register until R_F0_CNTH has
also been read.
Value
7..0
0x00
(read only)
R_F0_CNTH
0x19
F0IO pulse counter, high byte
Bits
Reset
Name
Description
V_F0_CNTH
High byte (bits 15 . . 8) of the 125 µs time counter
The low byte must be read first (see register
R_F0_CNTL)
Value
7..0
224 of 306
0
Data Sheet
October 2003
Chapter 7
Pulse width modulation (PWM) outputs
Table 7.1: Overview of the HFC-E1 PWM pins
Number
Name
Description
95
PWM1
Pulse Width Modulator Output 1
96
PWM0
Pulse Width Modulator Output 0
Table 7.2: Overview of the HFC-E1 PWM registers
Address
October 2003
Name
Page
0x38
R_PWM0
227
0x39
R_PWM1
227
0x46
R_PWM_MD
228
Data Sheet
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HFC-E1
7.1
PWM
Cologne
Chip
Overview
The HFC-E1 has two PWM output lines PWM0 and PWM1 with programmable output characteristic.
The output lines can be configured as open drain, open source and push / pull by setting V_PWM0_MD
respectively V_PWM1_MD in the register R_PWM_MD.
7.2
Standard PWM usage
The duty cycle of the output signals can be set in the registers R_PWM0 and R_PWM1. The register
value 0 generates an output signal which is permanently low. The register value defines the number
of clock periods where the output signal is high during the cycle time
T = 256 ·
1
= 256 · 40.69 ns = 10.42 µs
24.576 MHz
for the normal system clock 24.576 MHz.
The ouput signal of the PWM unit can be used for analog settings by using an external RC filter which
generates a voltage that can be adapted by changing the PWM register value.
7.3
Alternative PWM usage
The PWM output lines can be programmed to generate a 16 kHz signal. This signal can be used as
analog metering pulse for POTS interfaces. Each PWM output line can be switched to 16 kHz signal
by setting V_PWM0_16KHZ or V_PWM1_16KHZ in the register R_RAM_MISC. In this case the output
characteristic is also determined by the R_PWM_MD register settings.
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HFC-E1
PWM
Cologne
Chip
7.4 Register description
7.4.1
Write only register
(write only)
R_PWM0
0x38
Modulator register for pin PWM0
Bits
Reset
Name
Description
V_PWM0
PWM duty cycle
The value specifies the number of clock periods
where the output signal of PWM0 is high during a
256 clock periods cycle, e.g.
0x00 = no pulse, always low
0x80 = 1/1 duty cycle
0xFF = 1 clock period low after 255 clock periods
high
Value
7..0
0
(write only)
R_PWM1
0x39
Modulator register for pin PWM1
Bits
Reset
Name
Description
V_PWM1
PWM duty cycle
The value specifies the number of clock periods
where the output signal of PWM1 is high during a
256 clock periods cycle, e.g.
0x00 = no pulse, always low
0x80 = 1/1 duty cycle
0xFF = 1 clock period low after 255 clock periods
high
Value
7..0
0
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Data Sheet
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HFC-E1
PWM
Cologne
Chip
0x46
(write only)
R_PWM_MD
PWM output mode register
Bits
Reset
Name
Description
Must be ’000’.
Value
2..0
0
(reserved)
3
0
V_EXT_IRQ_EN
External interrupt enable
’0’ = normal operation
’1’ = external interrupt from GPI24 . . GPI31 enable
Note: The GPI pins must be connected to a pull-up
resistor to VDD. Any low input signal on one of the
lines will generate an external interrupt.
5..4
0
V_PWM0_MD
Output buffer configuration for pin PWM0
’00’ =PWM output tristate (disable)
’01’ = PWM push / pull output
’10’ = PWM push to 0 only
’11’ = PWM pull to 1 only
7..6
0
V_PWM1_MD
Output buffer configuration for pin PWM1
’00’ = PWM output tristate (disable)
’01’ = PWM push / pull output
’10’ = PWM push to 0 only
’11’ = PWM pull to 1 only
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Data Sheet
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Chapter 8
Multiparty audio conferences
Table 8.1: Overview of the HFC-E1 conference registers
Write only registers:
Address
October 2003
Name
Read only registers:
Page
Address
0x14
0x18
R_CONF_EN
236
0xD1
A_CONF
236
Data Sheet
Name
R_CONF_OFLOW
Page
237
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HFC-E1
8.1
Multiparty audio conferences
Cologne
Chip
Conference unit description
The HFC-E1 has a built in conference unit which allows up to 8 conferences with an arbitrary number
of members each. The conference unit is located in the data stream going out to the PCM interface.
So the normal outgoing data is replaced by the conference data. The number of conference members
that can be combined to one conference is limited by the number of receive HFC-channels. Thus the
total number of conference members is 32. Each PCM time slot can only be part of one conference.
All PCM values combined to a conference are added in one 125 µs time intervall. Then for every conference member the added value for this member is substracted so that every member of a conference
hears all the others but not himself. This is done on a alternating buffer scheme for every 125 µs time
intervall.
To enable the conference unit the bit V_CONF_EN in the register R_CONF_EN must be set. If this is
done there are additional accesses to the SRAM of HFC-E1 which reduces performance of the on-chip
processor on the other hand. Thus conference cannot be used with 8 Mbit/s PCM data rate where 128
slots are used, except the chip operates in double clock mode (see Chapter 12.1 on page 260). When
the conference unit is switched on or off during data processing, erroneous data may be transmitted
during the 125 µs cycle in progress.
To add a PCM time slot to a conference the slot number must be written into the register R_SLOT.
If the time slot has not yet been linked to a HFC-channel this can be done by writing the HFCchannel number and the channels source / destination (input / output pins) to the A_SL_CFG register.
Afterwards the conference number must be written into the bitmap V_CONF_NUM of the register
A_CONF. Additionally, the conference must be enabled for this time slot with V_CONF_SL set to
’1’ in the same register. Noise suppression, threshold and input attenuation level can be configured
independently for each time slot.
G
Important !
The register A_CONF must be initialized for every time slot. There is no specific
default value after reset. Time slots which are not member of a conference must
have A_CONF = 0x00.
The conference unit should never be enabled before all registers A_CONF[SLOT]
are initialized.
To remove a time slot from a conference the time slot must be selected by writing its number to the
R_SLOT register. Then 0x00 must be written into the A_CONF register.
8.2
Overflow handling
The data summation of the conference HFC-channels can cause signal overflows. The conference
unit internally works with signed 16 bit words. In case of an overflow the amplitude value is limited
to the maximum amplitude value.
Overflow conditions can be checked with the R_CONF_OFLOW register. Every bit of this register
indicates that an overflow has occured in one of the eight corresponding conferences.
The more conference members are involved in a conference, the higher is the probability of signal
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Cologne
Chip
Multiparty audio conferences
overflows. In this case the signal attenuation can be reduced by the bitmap V_ATT_LEV in the register
A_CONF. This can be done on-the-fly to improve the signal quality of a conference.
8.3 Conference including the E1 interface
As the conference unit is located in the PCM transmit data path, some additional explanations for
conference members on the E1 interface have to be made.
Conference members can also be time slots of the E1 interface. In this case, a pair of transmit / receive
PCM time slots have to be configured to loop back the data.
In detail, the conference signal received by the E1 gets assigned to a transmit HFC-channel, this gets
assigned to a transmit PCM time slot where it passes the summing circuit. The PCM interface loopesback the signal to a receive time slot. This is asigned to a receive HFC-channel which finally passes
the signal to a transmit E1 channel.
The data transmission on both the receive and transmit HFC-channels require one transmit and one
receive FIFO to be enabled, although the FIFOs are not used to store data (see Section 3.4).
8.4 Conference setup example for CSM
The following example shows the register settings for a conference with three members. Two members are located on the PCM interface side while the other one is located on the E1 interface side. The
example uses conference number 2. It is specified in Table 8.2.
Table 8.2: Conference example specification
Conference member
Connection
– 1st PCM member : PCM slot[5,RX]
→
HFC-channel[31,RX]
: PCM slot[5,TX]
←
HFC-channel[31,RX]
PCM member : PCM slot[20,RX]
→
HFC-channel[27,RX]
: PCM slot[20,TX]
←
HFC-channel[27,RX]
: S/T interf. #1, RX B1
→
PCM slot[6,TX]
: S/T interf. #1, TX B1
←
PCM slot[6,RX]
—
2nd
˜ E1 member
Only two FIFOs are used in this example. Channel select mode should be selected to avoid unnecessary FIFO usage 1 . A PCM member allocates a single HFC-channel to establish the data loop via the
switching buffer (see Fig. 3.3 and 3.3).
– 1st PCM conference member
A PCM conference member can be looped over an arbitrary receive HFC-channel. In this
example HFC-channel[31,TX] is used for the first PCM conference member. The conference
is enabled only on the transmit time slot of the PCM interface.
1 Remember that in Simple Mode FIFO numbers are equal to HFC-channel numbers. In the example four HFC-channels
are enabled, so that in Simple Mode all FIFOs with the same number are blocked.
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Chip
3
HFCchannel
Multiparty audio conferences
E1 slot
E1 slot
#4 TX
#4 RX
HFCchannel
TX RX
HFCchannel
E1 slot
RX TX
loop
2
loop
HFCchannel
PCM slot
#27 RX
PCM slot
-
HFCchannel
PCM slot
#31 RX
1
#31 RX
Conference #2
-
HFCchannel
PCM slot
HFCchannel
#11 TX
#11 RX
#27 RX
E1 slot
#4 RX
#4 TX
FIFO
FIFOs
E1 member
#4 TX
#4 RX
-
#6 TX
#6 RX
#5 TX
#5 RX
#20 TX
#20 RX
loop
1st PCM member
2nd PCM member
+
Figure 8.1: Conference example
(CSM – 1st PCM conference member)
Register setup:
R_SLOT
: V_SL_DIR
: V_SL_NUM
A_SL_CFG[5,RX] : V_CH_SDIR
: V_CH_SNUM
A_CONF[5,RX]
= 1
= 5
(slot #5)
= 1
(receive HFC-channel)
= 31
(HFC-channel #31)
: V_ROUT
= ’10’
(data from pin STIO2)
: V_CONF_NUM
= 0
(conference #0)
: V_NOISE_SUPPR = 0
R_SLOT
= 0
(0 dB attenuation level)
: V_CONF_SL
= 0
(slot is not added to the conference)
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 5
(slot #5)
= 1
(receive HFC-channel)
= 31
(HFC-channel #31)
: V_CH_SNUM
: V_ROUT
= ’10’
(data to pin STIO1)
: V_CONF_NUM
= 2
(conference #2)
: V_NOISE_SUPPR = 0
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(no noise suppression)
: V_ATT_LEV
A_SL_CFG[5,TX] : V_CH_SDIR
A_CONF[5,TX]
(receive slot)
(no noise suppression)
: V_ATT_LEV
= 0
(0 dB attenuation level)
: V_CONF_SL
= 1
(slot is added to the conference)
Data Sheet
October 2003
Multiparty audio conferences
HFC-E1
Cologne
Chip
— 2nd PCM conference member
The settings for the second PCM conference member is quite similar.
(CSM — 2nd PCM conference member)
Register setup:
R_SLOT
: V_SL_DIR
= 1
(receive slot)
: V_SL_NUM
= 20
(slot #20)
= 1
(receive HFC-channel)
= 27
(HFC-channel #27)
: V_ROUT
= ’10’
(data from pin STIO2)
: V_CONF_NUM
= 0
A_SL_CFG[20,RX] : V_CH_SDIR
: V_CH_SNUM
A_CONF[20,RX]
: V_NOISE_SUPPR = 0
R_SLOT
: V_ATT_LEV
= 0
(0 dB attenuation level)
: V_CONF_SL
= 0
(slot is not added to the conference)
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 20
(slot #20)
= 1
(receive HFC-channel)
A_SL_CFG[20,TX] : V_CH_SDIR
A_CONF[20,TX]
(conference #0)
(no noise suppression)
: V_CH_SNUM
= 27
(HFC-channel #27)
: V_ROUT
= ’10’
(data to pin STIO1)
: V_CONF_NUM
= 2
: V_NOISE_SUPPR = 0
(conference #2)
(no noise suppression)
: V_ATT_LEV
= 0
(0 dB attenuation level)
: V_CONF_SL
= 1
(slot is added to the conference)
˜ E1 conference member
Finally the E1 conference member must loop back its data via the PCM interface. This is
normally done internally, i.e. the PCM output buffers are both disabled (see Chapter 6 for
details). A pair of FIFOs is used to configure the PCM-to-E1 connection but no data is stored
in these FIFOs.
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Chip
Multiparty audio conferences
(CSM ˜ E1 conference member)
Register setup:
R_FIFO
: V_FIFO_DIR
= 0
(transmit FIFO)
: V_FIFO_NUM
= 11
(FIFO #11)
: V_REV
A_CON_HDLC[11,TX] : V_IFF
: V_HDLC_TRP
A_CHANNEL[11,TX]
R_SLOT
A_SL_CFG[6,TX]
A_CONF[6,TX]
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
= 1
(transparent mode)
: V_TRP_IRQ
= 0
(interrupt disabled)
: V_DATA_FLOW
= ’110’
(E1 → PCM)
: V_CH_FDIR
= 0
(transmit HFC-channel)
: V_CH_FNUM
= 4
(HFC-channel #4)
: V_SL_DIR
= 0
(transmit slot)
: V_SL_NUM
= 6
(slot #6)
: V_CH_SDIR
= 0
(transmit HFC-channel)
: V_CH_SNUM
= 4
(HFC-channel #4)
: V_ROUT
= ’01’
(internal PCM data transmission)
: V_CONF_NUM
= 2
: V_NOISE_SUPPR = 0
R_FIFO
(conference #2)
(no noise suppression)
: V_ATT_LEV
= 0
(0 dB attenuation level)
: V_CONF_SL
= 1
(slot is added to the conference)
: V_FIFO_DIR
= 1
(receive FIFO)
: V_FIFO_NUM
= 11
(FIFO #11)
: V_REV
= 0
(normal bit order)
= 0
(0x7E as inter frame fill)
: V_HDLC_TRP
= 1
(transparent mode)
: V_TRP_IRQ
= 0
(interrupt disabled)
: V_DATA_FLOW
= ’110’
(FIFO ← E1, E1 ← PCM)
= 1
(receive HFC-channel)
: V_CH_FNUM
= 4
(HFC-channel #4)
R_SLOT
: V_SL_DIR
= 1
(receive slot)
: V_SL_NUM
= 6
(slot #6)
A_SL_CFG[6,RX]
: V_CH_SDIR
= 1
(receive HFC-channel)
: V_CH_SNUM
= 4
(HFC-channel #4)
: V_ROUT
= ’01’
(internal PCM data loop)
: V_CONF_NUM
= 0
(conference #0)
A_CON_HDLC[11,RX] : V_IFF
A_CHANNEL[11,RX] : V_CH_FDIR
A_CONF[6,RX]
: V_NOISE_SUPPR = 0
(no noise suppression)
: V_ATT_LEV
= 0
(0 dB attenuation level)
: V_CONF_SL
= 0
(slot is not added to the conference)
• Global conference enable
After the configuration procedure of settings – to ˜, the conference unit can be switched on
and the data coding can be chosen. Both is done by setting the register R_CONF_EN.
Register setup:
R_CONF_EN : V_CONF_EN = 1
: V_ULAW
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= 1
(enable conference unit)
(µ-Law data coding)
Data Sheet
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HFC-E1
October 2003
Multiparty audio conferences
Cologne
Chip
Data Sheet
235 of 306
HFC-E1
8.5
8.5.1
Multiparty audio conferences
Cologne
Chip
Register description
Write only registers
0x18
(write only)
R_CONF_EN
Conference mode register
Bits
Reset
Name
Description
Value
0
0
V_CONF_EN
Global conference enable
’0’ = disable
’1’ = enable
Note: When this bit is changed, erroneous data
may be processed during the 125 µs cycle in
progress.
6..1
(reserved)
0
7
V_ULAW
Must be ’000000’.
Data coding of the conference unit
’0’ = A-Law
’1’ = µ-Law
A_CONF[SLOT]
0xD1
(write only)
Conference parameter register for the selected PCM time slot
Before writing this array register the PCM time slot must be selected by register R_SLOT.
Note: This register has no specific default value after reset.
Bits
Reset
Name
Description
2..0
V_CONF_NUM
Conference number
(0 . . 7)
4..3
V_NOISE_SUPPR
Value
Noise suppression threshold
’00’ = no noise suppression
’01’ = data values less or equal to 5 are set to 0
’10’ = data values less or equal to 9 are set to 0
’11’ = data values less or equal to 16 are set to 0
6..5
V_ATT_LEV
Input attenuation level
’00’ = 0 dB
’01’ = -3 dB
’10’ = -6 dB
’11’ = -9 dB
7
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V_CONF_SL
Conference enable for the selected PCM time
slot
’0’ = slot is not added to the conference
’1’ = slot is added to the conference
Data Sheet
October 2003
HFC-E1
8.5.2
Cologne
Chip
Multiparty audio conferences
Read only registers
0x14
(read only)
R_CONF_OFLOW
Conference overflow indication register
Specifies the conference numbers where an overflow has occured.
clears the bits.
Bits
Reset
Name
Description
Reading this register
Value
0
0
V_CONF_OFLOW0
Overflow occured in conference 0
1
0
V_CONF_OFLOW1
Overflow occured in conference 1
2
0
V_CONF_OFLOW2
Overflow occured in conference 2
3
0
V_CONF_OFLOW3
Overflow occured in conference 3
4
0
V_CONF_OFLOW4
Overflow occured in conference 4
5
0
V_CONF_OFLOW5
Overflow occured in conference 5
6
0
V_CONF_OFLOW6
Overflow occured in conference 6
7
0
V_CONF_OFLOW7
Overflow occured in conference 7
October 2003
Data Sheet
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Multiparty audio conferences
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Data Sheet
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Chip
October 2003
Chapter 9
DTMF controller
Table 9.1: Overview of the HFC-E1 DTMF registers
Write only registers:
Address
October 2003
Name
Page
0x1C
R_DTMF
246
0x1D
R_DTMF_N
247
Data Sheet
239 of 306
HFC-E1
9.1
Cologne
Chip
DTMF controller
Overview
The HFC-E1 has an on-chip DTMF 1 detection machine. This contains the recursive part of the
Goertzel filter while the non-recursive part has to be calculated by firmware.
The Goertzel filter is well known in literature. It describes a special form of the DFT algorithm on
the base of an infinite-duration impulse response filter (IIR filter). The Goertzel algorithm calculates
only a single spectral line. It is very fast and has low memory requirements.
9.2
DTMF calculation principles
The transmission of dialed numbers on analog lines is normaly done by DTMF (Dual Tone MultiFrequency). This means that pairs of two frequencies are used to determine one key of a keypad like
shown in Table 9.2.
Table 9.2: DTMF tones on a 16-key keypad
Keypad
Frequencies
1
2
3
A
697
4
5
6
B
770
low tones
7
8
9
C
852
( f /Hz)
∗
0
#
D
941
1209
1336
1477
1633
high tones ( f /Hz)
Thus there are 4 low tones and 4 high tones and therefore 16 combinations of 2 tones. Because the
ISDN network has several interfaces to the old-fashioned POTS analog network, in-band number
dialing with DTMF can take place. To decode this DTMF information the HFC-E1 has a built in
DTMF detection engine.
The detection is done by the digital processing of the HFC-channel data by the so-called Goerzel
Algorithm
(9.1)
Wn = K ·Wn−1 −Wn−2 + x ,
where Wn is a DTMF coefficient calculated from the 2 previous coefficients Wn−1 and Wn−2 . The
factor
f
K = 2 cos 2π ·
8000 Hz
is a constant for each frequency and x is a new HFC-channel value every 125 µs. The start condition
is W−1 = W−2 = 0.
After processing equation (9.1) for N + 1 times with n = 0 . . N the real power amplitude
2
A2 = WN2 +WN−1
− K ·WN ·WN−1 .
1 DTMF:
(9.2)
Dual tone multi-frequency
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Chip
DTMF controller
has to be calculated by the host processor.
The calculation of equation (9.1) is done for all 8 frequencies and for every new HFC-channel value
(every 125 µs). Optionally also the second harmonic (double frequency) is also investigated. The K
factors are values concerning to the DTMF frequencies. If the DTMF calculation is implemented in
integer arithmetic, it is useful to multiply K with 214 to exploit the whole 16 bit value range. These K
values are listed in Table 9.3.
Table 9.3: 16-bit K factors for the DTMF calculation
1st harmonic
∗:
2nd harmonic
f/Hz
K · 214
f/Hz
K · 214
697
27 980
1406 ∗
14 739
770
26 956
1555 ∗
11 221
852
25 701
1704
7 549
941
24 219
1882
3 032
1209
19 073
2418
-10 565
1336
16 325
2672
-16 503
1477
13 085
2954
-22 318
1633
9 315
3266
-27 472
These frequencies are modified to achieve a better detection compared with the high fundamental tones.
9.3 DTMF controller implementation
The DTMF controller picks up the values of the HFC-channels and stores the temporary or final
results in the internal or external RAM. Figure 9.1 shows how the DTMF controller is embedded
between the HFC-channels of the PCM part and the internal or external RAM. K factors are read
from the chip internal ROM.
After reset, the DTMF controller is disabled. It is to be enabled by setting bit V_DTMF_EN in register
R_DTMF. This bit can be changed at any time.
W coefficients of all 32 transmit or receive channels can be calculated if only the first harmonic (i.e.
8 frequencies) are chosen with V_HARM_SEL = ’0’ in the register R_DTMF. With V_HARM_SEL =
’1’, the second harmonics are calculated, too. Then the DTMF coefficients of only 16 HFC-channels
are calculated, namely #0 . . #15 if V_CHBL_SEL = ’0’ or #16 . . #31 if V_CHBL_SEL = ’1’. In any case
either transmit or receive HFC-channels of the PCM part can be selected with V_DTMF_RX_CH of
the same register.
The W coefficients are stored in the internal or external RAM after calculation. These are always 256
values; either from 8 frequencies of 32 HFC-channels or from 16 frequencies of 16 HFC-channels.
Equation 9.1 is calculated N + 1 times to obtain the power amplitude (see Equation 9.2). Then, after
(N + 1) · 125 µs the result can be read from the RAM. The value of N can be programmed in the
register R_DTMF_N. A good balance between the bandwith of the Goerzel filter and the length of the
investigation is N = 102, e.g.
October 2003
Data Sheet
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Chip
DTMF controller
1
1
0
RX
#17
RX
RX
#16
#31
RX
RX
#15
RX
#1
V_DTMF_RX_CH
lower or upper channels
(if 16 channels only)
1
V_CHBL_SEL
16 or 32 channels
1
0
...
TX or RX
0
none or 16
channels
x(0..15)
...
1
0
0
#0
TX
TX
#17
1
0
...
#31
TX
#16
TX
#1
...
#15
TX
TX
#0
HFC-channel (data to / from PCM slot)
none or 16
channels
x(16..31)
DTMF
controller
V_ULAW_SEL
A/uLaw
V_DTMF_STOP
float
Reset
n=0
x(ch)
Wn(ch,f) = K(f) * Wn-1 - Wn-2 + x(ch)
Stop
controller
n = 0..N
V_DTMF_IRQ
N
Wn
Wn-1
Wn-2
V_RESTART_DTMF
K(f)
V_DTMF_N
K(8..15)
0
K(0..7)
ROM
1
V_HARM_SEL
1st
2nd
harmonics
K
Goertzel
filter coefficients
Wn(ch,f)
(256 values)
internal or
external RAM
RAM read
access
from CPU
Wn-1(ch,f)
(256 values)
Figure 9.1: DTMF controller block diagram
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DTMF controller
Cologne
Chip
When n = N, the V_DTMF_IRQ flag in the register R_IRQ_MISC is set to alert the termination of the
power amplitude calculation. This bit can either be polled by software or it can trigger an interrupt if
the mask bit V_DTMF_IRQMSK in the register R_IRQMSK_MISC is set.
The V_DTMF_STOP bit should be set to ’1’ in the register R_DTMF to stop the DTMF engine after
every calculation of WN and WN−1 . The software has time to read the DTMF coefficients from the
RAM. After this, a new calculation can be started with V_RST_DTMF is set to ’1’ in the register
R_DTMF. Depending on the time required from the software, some x values might not be considered
by the next DTMF detection 2 .
9.4 Access to DTMF coefficients
The host processor should read the two WN and WN−1 16-bit coefficients for 8 or 16 frequencies for
the desired channels. The coefficients are located in the internal or external SRAM. The memory
address is calculated by
address = base address + frequency offset + channel offset + W-byte offset .
(9.3)
The individual address components are shown in Table 9.4.
The DTMF coefficients have a special float format which increases the precision by some bits. They
have 16 bit length and are coded sign – exponent – mantissa with a width of 1 – 3 – 12 bit.
The exponent is always as small as possible. In other words, an exponent value greater than zero
requires the most significant mantissa bit to be ’1’. Thus this bit has not to be coded. The following
pseudocode shows how to convert float values to linear values:
// input: w_float (16 bit, word)
// output: w_linear (32 bit singned integer)
// mantissa and exponent extraction:
mantissa = w_float and 0xFFF; // bits[11..0]
exponent = (w_float shr 12) and 0x7; // bits[14..12]
// sign evaluation:
if w_float and 0x8000 <> 0 then
{
mantissa = mantissa or 0xFFFFF000; // set bits[31..12]
}
// exponent evaluation:
if exponent <> 0 then
{
mantissa = mantissa xor 0x1000; // restore bit[12]
mantissa = mantissa shl (exponent-1);
}
// return result:
w_linear = mantissa;
2 It
is not recommended to set up a continous DTMF detection with V_DTMF_STOP = ’0’. This would require hard time
constraints and a special software algorithm to read the WN and WN−1 coefficients. Please ask the Cologne Chip support
team if this procedure is desired anyway.
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
DTMF controller
Table 9.4: Memory address calculation for DTMF coefficients related to equation (9.3)
base address
frequency offset
(1st harmonic)
(2nd harmonic)
channel offset
W-byte offset
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RAM size
address
RAM size
address
32k
0x1000
128k
0x2000
512k
0x2000
low tones
offset
high tones
offset
697 Hz
0x00
1406 Hz
0x40
770 Hz
0x80
1555 Hz
0xC0
852 Hz
0x100
1704 Hz
0x140
941 Hz
0x180
1882 Hz
0x1C0
1209 Hz
0x200
2418 Hz
0x240
1336 Hz
0x280
2672 Hz
0x2C0
1477 Hz
0x300
2954 Hz
0x340
1633 Hz
0x380
3266 Hz
0x3C0
number
offset
number
offset
0
0x00
16
0x40
1
0x04
17
0x44
2
0x08
18
0x48
3
0x0C
19
0x4C
4
0x10
20
0x50
5
0x14
21
0x54
6
0x18
22
0x58
7
0x1C
23
0x5C
8
0x20
24
0x60
9
0x24
25
0x64
10
0x28
26
0x68
11
0x2C
27
0x6C
12
0x30
28
0x70
13
0x34
29
0x74
14
0x38
30
0x78
15
0x3C
31
0x7C
WN−1
offset
WN
offset
low byte
0
low byte
2
high byte
1
high byte
3
Data Sheet
October 2003
HFC-E1
DTMF controller
Cologne
Chip
9.5 DTMF tone detection
DTMF tones are detected by evaluation of the power amplitude A2 (see Equation 9.2). This procedure
is widely presented in literature.
The discrimination process should consider the maximum power amplitude of a pair of low tone and
high tone frequencies and the timing requirements given by the DTMF specification in ITU-T Q.24.
Additionally, the second highest power amplitude can be investigated to ensure a sufficient distance
to the maximum amplitude. In this way, the software can determine if a DTMF signal has been on
the line or not. If a DTMF signal has been there, the tone pair is detected and so the dialed digit is
decoded.
If potential DTMF tones are superimposed on arbitrary voice signal, it is helpfull to investigate not
only the 8 DTMF tones but also their second harmonics. For DTMF tones the second harmonics
should have no significant amplitude.
October 2003
Data Sheet
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HFC-E1
9.6
DTMF controller
Cologne
Chip
Register description
(write only)
R_DTMF
0x1C
DTMF configuration register
Bits
Reset
Name
Description
Value
0
0
V_DTMF_EN
Global DTMF enable
’0’ = disable DTMF unit
’1’ = enable DTMF unit
1
0
V_HARM_SEL
2
0
V_DTMF_RX_CH
Harmonics selection
Investigation of the 2nd harmonics of the DTMF
frequencies can be enabled to improve the
detection algorithm.
’0’ = 8 frequencies in 32 channels (only 1st
harmonics are processed)
’1’ = 16 frequencies in 16 channels (1st and 2nd
harmonics are processed)
Note: If 2nd harmonics are processed, only 16
HFC-channels can be considered (see
V_CHBL_SEL).
DTMF data source
’0’ = transmit HFC-channels are used for DTMF
detection
’1’ = receive HFC-channels are used for DTMF
detection
3
0
V_DTMF_STOP
Stop DTMF unit
’0’ = continuous DTMF processing
’1’ = DTMF processing stops after n processed
samples
4
0
5
6
0
V_CHBL_SEL
HFC-Channel block selection
HFC-Channel block selection (only if 16 channels
are used, see V_HARM_SEL)
’0’ = lower 16 channels (0 . . 15)
’1’ = upper 16 channels (16 . . 31)
(reserved)
Must be ’0’.
V_RST_DTMF
Restart DTMF prosessing
’0’ = no action
’1’ = enables new DTMF calculation phase after
stop, automatically cleared
7
0
V_ULAW_SEL
Data coding for DTMF detection
’0’ = A-Law code
’1’ = µ-Law code
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HFC-E1
DTMF controller
(write only)
R_DTMF_N
Cologne
Chip
0x1D
Number of samples
This register defines the number of samples which are calculated in the recursive part of
the Goertzel filter.
Bits
Reset
Name
Description
V_DTMF_N
Number of samples
The recursive part of the Goertzel filter is looped
V_DTMF_N +1 times (n = 0 . . V_DTMF_N = 0 . . N)
to calculate one pair of DTMF coefficients WN and
WN−1 (1 PCM value every 125 µs, i.e. 1 pair of
DTMF coefficients every (N + 1) · 125 µs).
Value
7..0
0
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DTMF controller
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October 2003
Chapter 10
Bit Error Rate Test (BERT)
Table 10.1: Overview of the HFC-E1 BERT registers
Write only registers:
Address
October 2003
Name
Read only registers:
Page
Address
Name
Page
0x1B
R_BERT_WD_MD
253
0x17
R_BERT_STA
254
0xFF
A_IRQ_MSK
268
0x1A
R_BERT_ECL
254
0x1B
R_BERT_ECH
255
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HFC-E1
10.1
Cologne
Chip
BERT
BERT functionality
Bit Error Rate Test (BERT) is a very important test for communication lines. The bit error rate should
be as low as possible. Increasing bit error rate is an early indication of a malfunction of components
or the communication wire link itself.
HFC-E1 includes a high performance pseudo random bit generator (PRBG) and a pseudo random
bit receiver with automatic synchronization capability. The error rate can be checked by the also
implemented Bit Error counter (BERT counter).
10.2
BERT transmitter
0
HDLC
controller
# TX
1
autoclear
1
0
controller
...
V_BERT_ERR
TX
FIFO
sequence
V_BERT_EN
FIFO
1
V_BERT_EN
TX
HFCchannel
0
HDLC
controller
# TX
FIFO
1
V_BERT_EN
HFC-channel
TX
HFCchannel
HDLC
controller
0
HFCchannel
FIFOs
# TX
FIFO
The PRBG can be set to a variety of different pseudo random bit patterns. Continous ’0’, continous ’1’
or pseudo random bit patterns with one of 6 selectable sequence length’s from 29 − 1 bit to 223 − 1 bit
can be configured with the bitmap V_PAT_SEQ in the register R_BERT_WD_MD. All bit sequences
are defined in the ITU-T O.150 and O.151 specifications.
bit stream
V_PAT_SEQ
Pseudo Random
Bit Generator
V_BIT_CNT
Figure 10.1: BERT transmitter block diagram
The BERT patterns are passed through the HFC-channel assigner if V_BERT_EN = ’1’ in the register
A_IRQ_MSK[FIFO]. For this reason, either a FIFO-to-E1 or a FIFO-to-PCM configuration must be
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HFC-E1
BERT
Cologne
Chip
selected. Furthermore, the allocated FIFO must be enabled to switch on the data path.
BERT patterns are generated if at least one FIFO has its bit V_BERT_EN set to ’1’. When more than
one transmit FIFO are using BERT patterns, all these patterns are generated from the same pseudo
random generator. They are distrubuted to the FIFOs in the order of the FIFO processing sequence
(see Section 3.2.3 on page 100).
Subchannel processing can be used together with the Bit Error Rate Test. Then the number of bits
taken from the PRBG is V_BIT_CNT.
G
Please note !
To test a connection and the error detection capability of the BERT error counter,
a BERT error can be generated on the receiver side of an E1 link. Setting the
V_BERT_ERR bit in the register R_BERT_WD_MD generates one wrong BERT
bit in the outgoing data stream. V_BERT_ERR is automatically cleared afterwards.
10.3 BERT receiver
The BERT receiver has an automatically synchonization capability. When the incoming bit stream is
synchronized with the PRBG, the bit V_BERT_SYNC in the register R_BERT_STA is set to ’1’.
A 16 bit BERT error counter is available in the registers R_BERT_ECL and R_BERT_ECH. The low
byte R_BERT_ECL should be read first to latch the high byte (‘counter lock’). Then the high byte
can be read from the register R_BERT_ECH. A read access to the low byte R_BERT_ECL clears the
16 bit counter.
The BERT procedure should first wait for the synchronization state. After this, the BERT error
counter should be cleared by reading the register R_BERT_ECL.
Received BERT data is passed through the HFC-channel assigner if V_BERT_EN = ’1’ in the register
A_IRQ_MSK[FIFO]. For this reason, either a FIFO-to-E1 or a FIFO-to-PCM configuration must be
selected. Furthermore, the allocated FIFO must be enabled to switch on the data path. Received
BERT data is stored in the FIFO but it needs not to be read out. Received BERT data is collected
from all FIFOs which have V_BERT_EN = ’1’ in the order of the FIFO processing sequence (see
Section 3.2.3 on page 100).
Subchannel processing can be used together with the Bit Error Rate Test. Then V_BIT_CNT bits taken
passed to the BERT receiver.
Inverted BERT data is automatically detected and can be checked with the V_BERT_INV_DATA in the
register R_BERT_STA.
The automatically synchronization works only if the bit error rate is less than 4 · 10−2 . Synchronization state will not be achieved with a higher error rate. It is lost when many bit errors occur during a
short time period. In this case, the re-synchronization starts automatically and a high bit error counter
value indicates that a re-synchronization might has happened.
October 2003
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HFC-E1
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Chip
FIFO
BERT
1
0
RX
1
0
RX
bit stream
V_BERT_INV_DATA
...
V_BERT_ECL
V_PAT_SEQ
lock
incre ment
V_BERT_ECH
16 bit
error counter
V_BERT_SYNC
error sync
detect
HFCchannel
0
FIFO
sequence
1
V_BERT_EN
RX
controller
# RX
HDLC
controller
FIFO
V_BERT_EN
HFCchannel
# RX
HDLC
controller
FIFO
V_BERT_EN
HFC-channel
HFCchannel
# RX
HDLC
controller
FIFOs
Pseudo Random
Bit Generator
V_BIT_CNT
Figure 10.2: BERT receiver block diagram
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HFC-E1
BERT
Cologne
Chip
10.4 Register description
10.4.1
Write only register
0x1B
(write only)
R_BERT_WD_MD
Bit error rate test (BERT) and watchdog mode
Bits
Reset
Name
Description
Value
2..0
0
V_PAT_SEQ
Continuous ’0’ / ’1’ or pseudo random pattern
sequence for BERT
’000’ = continuous ’0’ pattern
’001’ = continuous ’1’ pattern
’010’ = sequence length 29 − 1 bits
’011’ = sequence length 210 − 1 bits
’100’ = sequence length 215 − 1 bits
’101’ = sequence length 220 − 1 bits
’110’ = sequence length 220 − 1 bits, but maximal
14 bits are zero
’111’ = pseudo random pattern seq. 223 − 1
Note: These sequences are defined in ITU-T O.150
and O.151 specifications.
3
0
V_BERT_ERR
BERT error
Generates 1 error bit in the BERT data stream
’0’ = no error generation
’1’ = generates one error bit
This bit is automatically cleared.
(reserved)
Must be ’0’.
4
5
0
V_AUTO_WD_RES
Automatically watchdog timer reset
’0’ = watchdog is only reset by V_WD_RES
’1’ = watchdog is reset after every access to the chip
6
7
(reserved)
0
V_WD_RES
Must be ’0’.
Watchdog timer reset
’0’ = no action
’1’ = manual watchdog timer reset
This bit is automatically cleared.
October 2003
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HFC-E1
10.4.2
BERT
Cologne
Chip
Read only register
0x17
(read only)
R_BERT_STA
Bit error rate test status
Bits
Reset
Name
Description
Value
3..0
0
(reserved)
4
0
V_BERT_SYNC
BERT synchronization status
’0’ = BERT not synchronized to input data
’1’ = BERT sync to input data
0
5
V_BERT_INV_DATA
BERT data inversion
’0’ = BERT receives normal data
’1’ = BERT receives inverted data
7..6
0
(reserved)
(read only)
R_BERT_ECL
0x1A
BERT error counter, low byte
Bits
Reset
Name
Description
V_BERT_ECL
Bits 7 . . 0 of the BERT error counter
This register should be read first to ‘lock’ the value
of the R_BERT_ECH register until R_BERT_ECH
has also been read.
Note: The BERT counter is cleared after reading
this register.
Value
7..0
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0
Data Sheet
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HFC-E1
BERT
(read only)
R_BERT_ECH
Cologne
Chip
0x1B
BERT error counter, high byte
Bits
Reset
Name
Description
V_BERT_ECH
Bits 15 . . 8 of the BERT error counter
Note: Low byte must be read first (see register
R_BERT_ECL).
Value
7..0
0
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Data Sheet
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BERT
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October 2003
Chapter 11
Auxiliary interface
G
Please note !
Please contact the Cologne Chip support team if you want to use the
auxiliary interface.
October 2003
Data Sheet
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HFC-E1
Auxiliary interface
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Data Sheet
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October 2003
Chapter 12
Clock, reset, interrupt, timer and
watchdog
Table 12.1: Overview of the HFC-E1 clock pins
Number
Name
Description
90
OSC_IN
Oscillator Input Signal
91
OSC_OUT
Oscillator Output Signal
92
CLK_MODE
Clock Mode
Table 12.2: Overview of the HFC-E1 reset, timer and watchdog registers
Write only registers:
Address
October 2003
Name
Read only registers:
Page
Address
Name
Page
0x11
R_IRQMSK_MISC
266
0x10
R_IRQ_OVIEW
269
0x13
R_IRQ_CTRL
266
0x11
R_IRQ_MISC
270
0x1A
R_TI_WD
267
0x1C
R_STATUS
271
0xFF
A_IRQ_MSK
268
0xC8
R_IRQ_FIFO_BL0
272
0xC9
R_IRQ_FIFO_BL1
273
0xCA
R_IRQ_FIFO_BL2
274
0xCB
R_IRQ_FIFO_BL3
275
0xCC
R_IRQ_FIFO_BL4
276
0xCD
R_IRQ_FIFO_BL5
277
0xCE
R_IRQ_FIFO_BL6
278
0xCF
R_IRQ_FIFO_BL7
279
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HFC-E1
12.1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
Clock
The clock oscillator of the HFC-E1 is shown in Figure 12.1. Two different crystal frequencies can be
used. Pin CLK_MODE must be set as shown in Table 12.3 to ensure a system clock of 32,768 MHz.
E1 applications need an exact clock frequency. So it is mandatory to ensure an accuracy of ±100 ppm
in worst case.
Table 12.3: Quartz selection
Crystal frequency
CLK_MODE
System clock fCLKI
32,768 MHz
’1’
32,768 MHz
65,536 MHz
’0’
32,768 MHz
+3.3V
U1
CLK_MODE
OSC_OUT
OSC_IN
91
90
R2
033
R1
M1
HFC-E1
92
Q1
32.768 MHz
C1
C2
47p
47p
GND
GND
Figure 12.1: Standard HFC-E1 quartz circuitry
12.2
Reset
HFC-E1 has a level sensitive RESET input at pin 198. This is low active in PCI mode (pin name
RST#) and high active in all other modes (pin name RESET). The pins MODE0 and MODE1 must be
valid during RESET and /SPISEL must be ’1’ (inactive). After RESET HFC-E1 enters an initialization
sequence.
The HFC-E1 has 4 different software resets. The FIFO registers, PCM registers and E1 registers can
be reset independently with the bits of the register R_CIRM which are listed in Table 12.4. The reset
bits must be set and cleared by software.
Information about the allocation of the registers to the different reset groups can be found in the
register list on pages 18 and 20. Many registers are allocated to more than one reset group, and some
are not resetable by software.
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HFC-E1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
Table 12.4: HFC-E1 reset groups
Reset name
Reset group
Register bit
Description
Soft Reset
0
V_SRES
Reset for FIFO, PCM and E1 registers of the HFC-E1. Soft
reset is the same as reset of all partial reset registers.
HFC Reset
1
V_HFC_RES
Reset for all FIFO registers of the HFC-E1.
PCM Reset
2
V_PCM_RES
Reset for all PCM registers of the HFC-E1.
E1 Reset
3
V_E1_RES
Reset for all E1 registers of the HFC-E1.
Hardware reset
H
–
Hardware reset initiated by RESET input pin.
12.3 Interrupt
12.3.1
Common features
The HFC-E1 is equipped with a maskable interrupt engine. A big variety of interrupt sources can
be enabled and disabled. All interrupts except FIFO interrupts are reported on reading the interrupt
status registers independently of masking the interrupt or not. Only mask enabled interrupts are used
to generate an interrupt on the interrupt pin of the HFC-E1. Reading the interrupt status register resets
the bits. Interrupt bits set during the reading are reported at the next reading of the interrupt status
registers.
Pin 197 is the interrupt output line for all bus interface modes except ISA PnP, which uses pins
106 . . 112 for interrupt purposes. After reset, all interrupts are disabled. The interrupt lines must
be enabled with V_GLOB_IRQ_EN set to ’1’ in the register R_IRQ_CTRL. The polarity of the interrupt signals can be changed from active low to active high with the bitmap V_IRQ_POL in the same
register.
12.3.2
E1 interface interrupt
A state change condition of the state machine can be signaled from an interrupt. When the bit
V_STA_IRQMSK of the register R_IRQMSK_MISC is set to ’1’, the interrupt is enabled. The bit register V_STA_IRQ of the register R_IRQ_MISC contains the state change condition even if the interruptis
disabled.
12.3.3
FIFO interrupt
FIFO interrupts can be enabled or disabled by setting the bit V_IRQ in register A_IRQ_MSK[FIFO].
Because there are 64 interrupts there are 8 interrupt status registers for FIFO interrupts. To determine which interrupt register must be read in an interrupt routine there is an interrupt overview
register which shows in which status register at least one interrupt bit is set (R_IRQ_OVIEW).
Reading this register does not clear any interrupt. The following reading of an interrupt register
(R_IRQ_FIFO_BL0 . . R_IRQ_FIFO_BL7) clears the reported interrupts.
The FIFO interrupts must be enabled with the global bit V_FIFO_IRQ in the register R_IRQ_CTRL.
October 2003
Data Sheet
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HFC-E1
12.3.4
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
DTMF interrupt
When DTMF detection has been finished, V_DTMF_IRQ in the register R_IRQ_MISC and
V_DTMF_IRQSTA in the register V_DTMF_IRQSTA are set to ’1’.
An interrupt occurs, when the bitmap V_DTMF_IRQMSK in the register R_IRQMSK_MISC is set to
’1’. The interrupt is cleared with a read access to the register R_IRQMSK_MISC. On the other hand,
the register V_DTMF_IRQSTA can be read without changing the interrupt state.
12.3.5
External interrupt
The GPI[31 . . 24] pins have interrupt capability. Figure 12.2 shows the block diagram of this external
interrupt capability. External interrupts can only be used if the E1 interface #6 and #7 are not in use.
The external interrupt occurs, when at least one of the eight GPI lines have low input signal. For this
reason all unused GPI lines must be connected to VDD when the external interrupt is enabled. The bit
V_EXT_IRQ_EN must be set to ’1’ in the register R_PWM_MD to enable the external interrupt unit.
The current state of the joined GPI signals can be read from the bit V_EXT_IRQSTA in the register
R_STATUS.
From this signal an interrupt can be generated if the R_IRQMSK_MISC register’s bit V_SA6_IRQMSK
is set to ’1’. In case of an interrupt event, V_SA6_IRQ can be read to determine if the external interrupt occured. When V_SA6_IRQ is set, the interrupt condition was either the external interrupt or
the SA6 pattern has changed. With the last-mentioned condition the bit V_SA6_CHG in the register
R_RX_STA2 will be set as well.
12.3.6
Timer interrupt
The HFC-E1 includes a timer with interrupt capability.
The timer counts F0IO pulses, i.e. it is incremented every 125 µs.
A timer event is indicated with V_TI_IRQ = ’1’ in the register R_IRQ_MISC. This event generates an
interrupt if the mask bit V_TI_IRQMSK is set to ’1’ in the register R_IRQMSK_MISC.
A timer event is generated every 2V_EV_TS · 250 µs where V_EV_TS = 0 . . 15 in the register R_TI_WD.
This leads to a timer event frequency from 250 µs to 8,192 s.
12.3.7
125 µs interrupt
The HFC-E1 changes every 125 µs from non processing into processing state. This event can be
reported with an interrupt. The bit V_PROC_IRQMSK in the register R_IRQMSK_MISC must be set
to ’1’ to enable this interrupt capability. In case of an interrupt, the bit V_IRQ_PROC in the register
R_IRQ_MISC has the value ’1’.
12.4
Watchdog reset
The processor mode of the HFC-E1 includes a watchdog functionality.
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HFC-E1
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Chip
Clock, reset, interrupt, timer and watchdog
124
GPI30
GPI31
...
GPI24
GPI25
GPI31
V_EXT_IRQ_STA
V_EXT_IRQ_EN
SA6 pattern
has changed
V_EXT_IRQ
V_EXT_IRQMSK
interrupt
controller
197
interrupt
output
Figure 12.2: External interrupt block diagram
A watchdog event generates a low signal at pin /WD. The watchdog timer can either be reset manually
or automatically.
• Manual watchdog reset is selected with V_AUTO_WD_RES = ’0’ in the register R_BERT_WD_MD.
Then, writing V_WD_RES = ’1’ into the register R_BERT_WD_MD resets the watchdog timer.
This bit is automatically cleared afterwards.
• V_AUTO_WD_RES = ’1’ must be set to switch on the automatically watchdog reset. In this case
every access to the chip clears the watchdog timer.
The watchdog counter is incremented every 2 ms. An event occurs after 2V_WD_TS · 2 ms where
V_WD_TS = 0 . . 15 in the register R_TI_WD. This leads to a watchdog event frequency from 2 ms
to 65,536 s.
October 2003
Data Sheet
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HFC-E1
Clock, reset, interrupt, timer and watchdog
12.5
Register description
12.5.1
Write only register
R_BRG_PCM_CFG
(write only)
Cologne
Chip
0x02
Auxiliary bridge and PCM configuration register
Bits
Reset
Name
Description
(reserved)
Must be ’00000’.
Value
4..0
5
0
V_PCM_CLK
Clock of the PCM module
’0’ = system clock / 2
’1’ = system clock / 4
PCM clock must be 16.384 MHz, system clock is
normaly 32.768 MHz. This bitmap is used in
double clock mode only.
7..6
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0
(reserved)
Must be ’00’.
Data Sheet
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HFC-E1
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Clock, reset, interrupt, timer and watchdog
Cologne
Chip
Data Sheet
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HFC-E1
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Clock, reset, interrupt, timer and watchdog
0x11
(write only)
R_IRQMSK_MISC
Miscellaneous interrupt status mask register
’0’ means that the interrupt is not used for generating an interrupt on the interrupt pin
197. ’1’ enables the interrupt generation in case of the committed event.
Bits
Reset
Name
Description
Value
0
0
V_STA_IRQMSK
State of state machine changed interrupt mask
bit
1
0
V_TI_IRQMSK
Timer elapsed interrupt mask bit
2
0
V_PROC_IRQMSK
Processing / nonprocessing transition interrupt
mask bit
(every 125 µs)
3
0
V_DTMF_IRQMSK
DTMF detection interrupt mask bit
4
0
V_IRQ1S_MSK
1 second interrupt mask bit
5
0
V_SA6_IRQMSK
SA6 pattern changed or external interrupt mask
bit
6
0
V_RX_EOMF_MSK
Receive end of multiframe mask bit
7
0
V_TX_EOMF_MSK
Transmit end of multiframe mask bit
(write only)
R_IRQ_CTRL
0x13
Interrupt control register
Bits
Reset
Name
Description
Value
0
0
FIFO interrupt
V_FIFO_IRQ
’0’ = FIFO interrupts disabled
’1’ = FIFO interrupts enabled
2..1
(reserved)
Must be ’00’.
Global interrupt signal enable
The interrupt lines are either pins 106 . . 112 in
ISA PnP mode or pin 197 in all other bus interface
modes.
’0’ = disable
’1’ = enable
3
0
V_GLOB_IRQ_EN
4
0
V_IRQ_POL
266 of 306
7..5
Polarity of interrupt signal
Data
(reserved)
’0’ = low active signal
Sheet
’1’ = high active signal
Must be ’000’.
October 2003
HFC-E1
Clock, reset, interrupt, timer and watchdog
(write only)
R_TI_WD
Cologne
Chip
0x1A
Timer and watchdog control register
Bits
Reset
Name
Description
Value
3..0
0
V_EV_TS
Timer event after 2n · 250 µs
0 = 250 µs
1 = 500 µs
2 = 1 ms
3 = 2 ms
4 = 4 ms
5 = 8 ms
6 = 16 ms
7 = 32 ms
8 = 64 ms
9 = 128 ms
0xA = 256 ms
0xB = 512 ms
0xC = 1.024 s
0xD = 2.048 s
0xE = 4.096 s
0xF = 8.192 s
7..4
0
V_WD_TS
Watchdog event after 2n · 2 ms
0 = 2 ms
1 = 4 ms
2 = 8 ms
3 = 16 ms
4 = 32 ms
5 = 64 ms
6 = 128 ms
7 = 256 ms
8 = 512 ms
9 = 1.024 s
0xA = 2.048 s
0xB = 4.096 s
0xC = 8.192 s
0xD = 16.384 s
0xE = 32.768 s
0xF = 65.536 s
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
Clock, reset, interrupt, timer and watchdog
A_IRQ_MSK[FIFO]
0xFF
(write only)
Interrupt register for the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
Bits
Reset
Name
Description
Value
0
0
V_IRQ
Interrupt mask for the selected FIFO
’0’ = disabled
’1’ = enabled
1
0
V_BERT_EN
BERT output enable
’0’ = BERT disabled, normal data is transmitted
’1’ = BERT enabled, output of BERT generator is
transmitted
2
0
V_MIX_IRQ
Mixed interrupt generation
’0’ = disabled (normal operation)
’1’ = frame interrupts and transparent mode
interrupts are both generated in HDLC mode
7..3
268 of 306
(reserved)
Must be ’00000’.
Data Sheet
October 2003
HFC-E1
12.5.2
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
Read only register
(read only)
R_IRQ_OVIEW
0x10
FIFO interrupt overview register
Every bit with value ’1’ indicates that an interrupt has occured in the FIFO block. A
FIFO block consists of 4 transmit and 4 receive FIFOs. The exact FIFO can be determined by
reading the R_IRQ_FIFO_BL0 . . R_IRQ_FIFO_BL7 registers that belong to the specified FIFO
block.
Reading any R_IRQ_FIFO_BL0 . . R_IRQ_FIFO_BL7 registers clear the corresponding bit in this
register. Reading this overview register does not clear any interrupt bit.
Bits
Reset
Name
Description
0
V_IRQ_FIFO_BL0
Interrupt overview of FIFO block 0
(FIFOs 0 . . 3)
1
V_IRQ_FIFO_BL1
Interrupt overview of FIFO block 1
(FIFOs 4 . . 7)
2
V_IRQ_FIFO_BL2
Interrupt overview of FIFO block 2
(FIFOs 8 . . 11)
3
V_IRQ_FIFO_BL3
Interrupt overview of FIFO block 3
(FIFOs 12 . . 15)
4
V_IRQ_FIFO_BL4
Interrupt overview of FIFO block 4
(FIFOs 16 . . 19)
5
V_IRQ_FIFO_BL5
Interrupt overview of FIFO block 5
(FIFOs 20 . . 23)
6
V_IRQ_FIFO_BL6
Interrupt overview of FIFO block 6
(FIFOs 24 . . 27)
7
V_IRQ_FIFO_BL7
Interrupt overview of FIFO block 7
(FIFOs 28 . . 31)
Value
October 2003
Data Sheet
269 of 306
HFC-E1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
0x11
(read only)
R_IRQ_MISC
Miscellaneous interrupt status register
All bits of this register are cleared after a read access.
Bits
Reset
Name
Description
Value
0
0
V_STA_IRQ
State change
’1’ = state of E1 state machine has changed
1
0
V_TI_IRQ
Timer interrupt
’1’ = timer elapsed
2
0
V_IRQ_PROC
3
0
V_DTMF_IRQ
Processing / non processing transition interrupt
status
’1’ = The HFC-E1 has changed from processing to
non processing phase (every 125 µs).
DTMF detection interrupt
’1’ = DTMF detection has been finished. The
results can be read from the RAM.
4
0
V_IRQ1S
1 second interrupt
’1’ = 1 second elapsed
5
0
V_SA6_IRQ
SA6 pattern has changed or external interrupt
6
0
V_RX_EOMF
End of multiframe received
7
0
V_TX_EOMF
End of multiframe transmited
270 of 306
Data Sheet
October 2003
HFC-E1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
0x1C
(read only)
R_STATUS
HFC-E1 status register
Bits
Reset
Name
Description
Value
0
0
V_BUSY
BUSY / NOBUSY status
’1’ = the HFC-E1 is BUSY after initialising Reset
FIFO, increment F-counter or change FIFO
’0’ = the HFC-E1 is not busy, all accesses are
allowed
1
1
V_PROC
Processing / non processing status
’1’ = the HFC-E1 is in processing phase (once every
125 µs cycle)
’0’ = the HFC-E1 has finished the processing phase
during the 125 µs cycle
2
0
V_DTMF_IRQSTA
DTMF interrupt
DTMF interrupt has occured
3
0
V_LOST_STA
LOST error (frames have been lost)
This means the HFC-E1 did not process all data in
125 µs. So data may be corrupted.
Bit V_RES_LOST of the A_INC_RES_FIFO
register must be set to reset this bit.
4
0
V_SYNC_IN
Synchronization input
Value of the SYNC_I input pin
5
0
V_EXT_IRQSTA
External interrupt
The external interrupt signal is currently set.
6
0
V_MISC_IRQSTA
Any miscellaneous interrupt
All enabled miscellaneous interrupts of the register
R_IRQ_MISC are ‘ored’.
7
0
V_FR_IRQSTA
Any FIFO interrupt
All enabled FIFO interrupts in the registers
R_IRQ_FIFO_BL0 . . R_IRQ_FIFO_BL7 are ‘ored’.
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
Clock, reset, interrupt, timer and watchdog
0xC8
(read only)
R_IRQ_FIFO_BL0
FIFO interrupt register for FIFO block 0
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO0_TX
Interrupt occured in transmit FIFO 0
1
0
V_IRQ_FIFO0_RX
Interrupt occured in receive FIFO 0
2
0
V_IRQ_FIFO1_TX
Interrupt occured in transmit FIFO 1
3
0
V_IRQ_FIFO1_RX
Interrupt occured in receive FIFO 1
4
0
V_IRQ_FIFO2_TX
Interrupt occured in transmit FIFO 2
5
0
V_IRQ_FIFO2_RX
Interrupt occured in receive FIFO 2
6
0
V_IRQ_FIFO3_TX
Interrupt occured in transmit FIFO 3
7
0
V_IRQ_FIFO3_RX
Interrupt occured in receive FIFO 3
272 of 306
Data Sheet
October 2003
HFC-E1
Clock, reset, interrupt, timer and watchdog
(read only)
R_IRQ_FIFO_BL1
Cologne
Chip
0xC9
FIFO interrupt register for FIFO block 1
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO4_TX
Interrupt occured in transmit FIFO 4
1
0
V_IRQ_FIFO4_RX
Interrupt occured in receive FIFO 4
2
0
V_IRQ_FIFO5_TX
Interrupt occured in transmit FIFO 5
3
0
V_IRQ_FIFO5_RX
Interrupt occured in receive FIFO 5
4
0
V_IRQ_FIFO6_TX
Interrupt occured in transmit FIFO 6
5
0
V_IRQ_FIFO6_RX
Interrupt occured in receive FIFO 6
6
0
V_IRQ_FIFO7_TX
Interrupt occured in transmit FIFO 7
7
0
V_IRQ_FIFO7_RX
Interrupt occured in receive FIFO 7
October 2003
Data Sheet
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HFC-E1
Cologne
Chip
Clock, reset, interrupt, timer and watchdog
0xCA
(read only)
R_IRQ_FIFO_BL2
FIFO interrupt register for FIFO block 2
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO8_TX
Interrupt occured in transmit FIFO 8
1
0
V_IRQ_FIFO8_RX
Interrupt occured in receive FIFO 8
2
0
V_IRQ_FIFO9_TX
Interrupt occured in transmit FIFO 9
3
0
V_IRQ_FIFO9_RX
Interrupt occured in receive FIFO 9
4
0
V_IRQ_FIFO10_TX
Interrupt occured in transmit FIFO 10
5
0
V_IRQ_FIFO10_RX
Interrupt occured in receive FIFO 10
6
0
V_IRQ_FIFO11_TX
Interrupt occured in transmit FIFO 11
7
0
V_IRQ_FIFO11_RX
Interrupt occured in receive FIFO 11
274 of 306
Data Sheet
October 2003
HFC-E1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
(read only)
R_IRQ_FIFO_BL3
0xCB
FIFO interrupt register for FIFO block 3
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO12_TX
Interrupt occured in transmit FIFO 12
1
0
V_IRQ_FIFO12_RX
Interrupt occured in receive FIFO 12
2
0
V_IRQ_FIFO13_TX
Interrupt occured in transmit FIFO 13
3
0
V_IRQ_FIFO13_RX
Interrupt occured in receive FIFO 13
4
0
V_IRQ_FIFO14_TX
Interrupt occured in transmit FIFO 14
5
0
V_IRQ_FIFO14_RX
Interrupt occured in receive FIFO 14
6
0
V_IRQ_FIFO15_TX
Interrupt occured in transmit FIFO 15
7
0
V_IRQ_FIFO15_RX
Interrupt occured in receive FIFO 15
October 2003
Data Sheet
275 of 306
HFC-E1
Cologne
Chip
Clock, reset, interrupt, timer and watchdog
0xCC
(read only)
R_IRQ_FIFO_BL4
FIFO interrupt register for FIFO block 4
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO16_TX
Interrupt occured in transmit FIFO 16
1
0
V_IRQ_FIFO16_RX
Interrupt occured in receive FIFO 16
2
0
V_IRQ_FIFO17_TX
Interrupt occured in transmit FIFO 17
3
0
V_IRQ_FIFO17_RX
Interrupt occured in receive FIFO 17
4
0
V_IRQ_FIFO18_TX
Interrupt occured in transmit FIFO 18
5
0
V_IRQ_FIFO18_RX
Interrupt occured in receive FIFO 18
6
0
V_IRQ_FIFO19_TX
Interrupt occured in transmit FIFO 19
7
0
V_IRQ_FIFO19_RX
Interrupt occured in receive FIFO 19
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Data Sheet
October 2003
HFC-E1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
(read only)
R_IRQ_FIFO_BL5
0xCD
FIFO interrupt register for FIFO block 5
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO20_TX
Interrupt occured in transmit FIFO 20
1
0
V_IRQ_FIFO20_RX
Interrupt occured in receive FIFO 20
2
0
V_IRQ_FIFO21_TX
Interrupt occured in transmit FIFO 21
3
0
V_IRQ_FIFO21_RX
Interrupt occured in receive FIFO 21
4
0
V_IRQ_FIFO22_TX
Interrupt occured in transmit FIFO 22
5
0
V_IRQ_FIFO22_RX
Interrupt occured in receive FIFO 22
6
0
V_IRQ_FIFO23_TX
Interrupt occured in transmit FIFO 23
7
0
V_IRQ_FIFO23_RX
Interrupt occured in receive FIFO 23
October 2003
Data Sheet
277 of 306
HFC-E1
Cologne
Chip
Clock, reset, interrupt, timer and watchdog
0xCE
(read only)
R_IRQ_FIFO_BL6
FIFO interrupt register for FIFO block 6
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO24_TX
Interrupt occured in transmit FIFO 24
1
0
V_IRQ_FIFO24_RX
Interrupt occured in receive FIFO 24
2
0
V_IRQ_FIFO25_TX
Interrupt occured in transmit FIFO 25
3
0
V_IRQ_FIFO25_RX
Interrupt occured in receive FIFO 25
4
0
V_IRQ_FIFO26_TX
Interrupt occured in transmit FIFO 26
5
0
V_IRQ_FIFO26_RX
Interrupt occured in receive FIFO 26
6
0
V_IRQ_FIFO27_TX
Interrupt occured in transmit FIFO 27
7
0
V_IRQ_FIFO27_RX
Interrupt occured in receive FIFO 27
278 of 306
Data Sheet
October 2003
HFC-E1
Clock, reset, interrupt, timer and watchdog
Cologne
Chip
(read only)
R_IRQ_FIFO_BL7
0xCF
FIFO interrupt register for FIFO block 7
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is ’0’, no
interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
Bits
Reset
Name
Description
Value
0
0
V_IRQ_FIFO28_TX
Interrupt occured in transmit FIFO 28
1
0
V_IRQ_FIFO28_RX
Interrupt occured in receive FIFO 28
2
0
V_IRQ_FIFO29_TX
Interrupt occured in transmit FIFO 29
3
0
V_IRQ_FIFO29_RX
Interrupt occured in receive FIFO 29
4
0
V_IRQ_FIFO30_TX
Interrupt occured in transmit FIFO 30
5
0
V_IRQ_FIFO30_RX
Interrupt occured in receive FIFO 30
6
0
V_IRQ_FIFO31_TX
Interrupt occured in transmit FIFO 31
7
0
V_IRQ_FIFO31_RX
Interrupt occured in receive FIFO 31
October 2003
Data Sheet
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HFC-E1
Clock, reset, interrupt, timer and watchdog
280 of 306
Data Sheet
Cologne
Chip
October 2003
Chapter 13
General purpose I/O pins (GPIO)
and input pins (GPI)
(For an overview of the GPIO and GPI pins see Tables 13.2 and 13.2 on
page 283.)
Table 13.1: Overview of the HFC-E1 general purpose I/O registers
Write only registers:
Address
October 2003
Name
Read only registers:
Page
Address
Name
Page
0x40
R_GPIO_OUT0
285
0x40
R_GPIO_IN0
290
0x41
R_GPIO_OUT1
286
0x41
R_GPIO_IN1
291
0x42
R_GPIO_EN0
287
0x44
R_GPI_IN0
292
0x43
R_GPIO_EN1
288
0x45
R_GPI_IN1
293
0x44
R_GPIO_SEL
289
0x46
R_GPI_IN2
294
0x47
R_GPI_IN3
295
Data Sheet
281 of 306
HFC-E1
13.1
Cologne
Chip
General purpose I/O pins
GPIO and GPI functionality
The HFC-E1 has up to 16 general purpose I/O (GPIO) and up to 32 general purpose input (GPI) pins.
As shown in Tables 13.2 and 13.3, some of them – two GPIO and four GPI pins – are shared with the
E1 interface pins and can only be used if this interface is not in use.
E1 interface pins are always called 1st pin function. GPIO and GPI pins are called 2nd pin function
even if a pin has no functionality at its 1st function.
GPIOs must be switched into GPIO mode in the register R_GPIO_SEL if they should be used as
outputs. The input functionality of all GPIOs and GPIs is allways enabled (see Figure 13.1). The
output values for the GPIOs are set in the registers R_GPIO_OUT0 and R_GPIO_OUT1. The output
function can be enabled in the registers R_GPIO_EN0 and R_GPIO_EN1. If disabled, the output
drivers are tristated. A detailed GPIO block diagram is shown in Figure 13.2.
The input values for the GPIO[0..15] can be read in the registers R_GPIO_IN0 and R_GPIO_IN1.
The input values for GPI[0..31] can be read in the registers R_GPI_IN0, R_GPI_IN1, R_GPI_IN2 and
R_GPI_IN3.
1st pin function (E1 interface)
Power supply
VDD
2nd pin function (GPIO)
V_GPI_IN0
V_GPI_IN1
input data
Pin #191
(R_A or GPI0)
input data
Pin #190
(LEV_A or GPI1)
...
V_GPI_IN31
...
input data
...
Pin #124
(GPI31)
Figure 13.1: GPI block diagram
13.2
GPIO output voltage
The GPIO output high voltage can be influenced for each set of 4 GPIOs by connecting the appropiate
VDD_E1 pin to a voltage different from VDD. The voltage must not exceed 3.6 V. Table 13.2 shows
the allocation of power supply pins to the GPIO output drivers.
282 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
General purpose I/O pins
Table 13.2: GPIO pins of HFC-E1
GPIO pin
Shared with
interface
Output
supply pin
GPIO pin
130
??
–
165
??
–
131
??
–
166
??
–
132
??
–
167
??
–
133
??
–
168
??
–
148
??
–
182
??
–
149
??
–
183
??
–
150
??
–
184
GPIO1
E1
151
??
–
185
GPIO0
E1
Shared with
interface
Output
supply pin
Table 13.3: GPI pins of HFC-E1
GPIO pin
October 2003
Shared with
interface
GPIO pin
Shared with
interface
124
??
–
159
??
–
125
??
–
160
??
–
126
??
–
161
??
–
127
??
–
162
??
–
136
??
–
171
??
–
137
??
–
172
??
–
138
??
–
173
??
–
139
??
–
174
??
–
142
??
–
176
??
–
143
??
–
177
??
–
144
??
–
178
??
–
145
??
–
179
??
–
154
??
–
188
GPI3
E1
155
??
–
189
GPI2
E1
156
??
–
190
GPI1
E1
157
??
–
191
GPI0
E1
Data Sheet
283 of 306
HFC-E1
Cologne
Chip
General purpose I/O pins
1st pin function (E1 interface)
Power supply
VDD_E1
VDD
2nd pin function (GPIO)
V_GPIO_EN0
V_GPIO_SEL0
enable output driver
select 1st or 2nd
pin function
0
V_GPIO_OUT0
1
1
enable
Pin #185
(T_A or GPIO0)
output data
0
V_GPIO_IN0
input data
V_GPIO_EN1
0
V_GPIO_OUT1
1
1
enable
Pin #184
(T_B or GPIO1)
output data
0
V_GPIO_IN1
input data
...
Figure 13.2: GPIO block diagram (GPIO0 and GPIO1 exemplarily
284 of 306
Data Sheet
October 2003
HFC-E1
General purpose I/O pins
Cologne
Chip
13.3 Register description
13.3.1
Write only register
(write only)
R_GPIO_OUT0
0x40
GPIO output data bits 7 . . 0
Bits
Reset
Name
Description
Value
0
0
V_GPIO_OUT0
Output data bit for pin GPIO0
1
0
V_GPIO_OUT1
Output data bit for pin GPIO1
2
0
V_GPIO_OUT2
Output data bit for pin GPIO2
3
0
V_GPIO_OUT3
Output data bit for pin GPIO3
4
0
V_GPIO_OUT4
Output data bit for pin GPIO4
5
0
V_GPIO_OUT5
Output data bit for pin GPIO5
6
0
V_GPIO_OUT6
Output data bit for pin GPIO6
7
0
V_GPIO_OUT7
Output data bit for pin GPIO7
October 2003
Data Sheet
285 of 306
HFC-E1
General purpose I/O pins
(write only)
R_GPIO_OUT1
Cologne
Chip
0x41
GPIO output data bits 15 . . 8
Bits
Reset
Name
Description
Value
0
0
V_GPIO_OUT8
Output data bit for pin GPIO8
1
0
V_GPIO_OUT9
Output data bit for pin GPIO9
2
0
V_GPIO_OUT10
Output data bit for pin GPIO10
3
0
V_GPIO_OUT11
Output data bit for pin GPIO11
4
0
V_GPIO_OUT12
Output data bit for pin GPIO12
5
0
V_GPIO_OUT13
Output data bit for pin GPIO13
6
0
V_GPIO_OUT14
Output data bit for pin GPIO14
7
0
V_GPIO_OUT15
Output data bit for pin GPIO15
286 of 306
Data Sheet
October 2003
HFC-E1
General purpose I/O pins
(write only)
R_GPIO_EN0
Cologne
Chip
0x42
GPIO output enable bits 7 . . 0
Every bit value ’1’ enables the allocated output driver. If an output driver is disabled (bit
value ’0’), the pin is used for data input.
Bits
Reset
Name
Description
Value
0
0
V_GPIO_EN0
Output enable for pin GPIO0
1
0
V_GPIO_EN1
Output enable for pin GPIO1
2
0
V_GPIO_EN2
Output enable for pin GPIO2
3
0
V_GPIO_EN3
Output enable for pin GPIO3
4
0
V_GPIO_EN4
Output enable for pin GPIO4
5
0
V_GPIO_EN5
Output enable for pin GPIO5
6
0
V_GPIO_EN6
Output enable for pin GPIO6
7
0
V_GPIO_EN7
Output enable for pin GPIO7
October 2003
Data Sheet
287 of 306
HFC-E1
General purpose I/O pins
(write only)
R_GPIO_EN1
Cologne
Chip
0x43
GPIO output enable bits 15 . . 8
Every bit value ’1’ enables the allocated output driver. If an output driver is disabled (bit
value ’0’), the pin is used for data input.
Bits
Reset
Name
Description
Value
0
0
V_GPIO_EN8
Output enable for pin GPIO8
1
0
V_GPIO_EN9
Output enable for pin GPIO9
2
0
V_GPIO_EN10
Output enable for pin GPIO10
3
0
V_GPIO_EN11
Output enable for pin GPIO11
4
0
V_GPIO_EN12
Output enable for pin GPIO12
5
0
V_GPIO_EN13
Output enable for pin GPIO13
6
0
V_GPIO_EN14
Output enable for pin GPIO14
7
0
V_GPIO_EN15
Output enable for pin GPIO15
288 of 306
Data Sheet
October 2003
HFC-E1
General purpose I/O pins
(write only)
R_GPIO_SEL
Cologne
Chip
0x44
GPIO selection register
This register allows to select the first or second function of GPIO pins. Always two pins
are controlled by one register bit. Every bit controls only the output driver, whereas the input
functionality needs no programming.
Bits
Reset
Name
Description
Value
0
0
V_GPIO_SEL0
GPIO0 and GPIO1
’0’ = pins T_A and T_B enabled
’1’ = pins GPIO0 and GPIO1 enabled
1
0
V_GPIO_SEL1
GPIO2 and GPIO3
’0’ = pins GPIO2 and GPIO3 disabled
’1’ = pins GPIO2 and GPIO3 enabled
2
0
V_GPIO_SEL2
GPIO4 and GPIO5
’0’ = pins GPIO4 and GPIO5 disabled
’1’ = pins GPIO4 and GPIO5 enabled
3
0
V_GPIO_SEL3
GPIO6 and GPIO7
’0’ = pins GPIO6 and GPIO7 disabled
’1’ = pins GPIO6 and GPIO7 enabled
4
0
V_GPIO_SEL4
GPIO8 and GPIO9
’0’ = pins GPIO8 and GPIO9 disabled
’1’ = pins GPIO8 and GPIO9 enabled
5
0
V_GPIO_SEL5
GPIO10 and GPIO11
’0’ = pins GPIO10 and GPIO11 disabled
’1’ = pins GPIO10 and GPIO11 enabled
6
0
V_GPIO_SEL6
GPIO12 and GPIO13
’0’ = pins GPIO12 and GPIO13 disabled
’1’ = pins GPIO12 and GPIO13 enabled
7
0
V_GPIO_SEL7
GPIO14 and GPIO15
’0’ = pins GPIO14 and GPIO15 disabled
’1’ = pins GPIO14 and GPIO15 enabled
October 2003
Data Sheet
289 of 306
HFC-E1
13.3.2
General purpose I/O pins
Cologne
Chip
Read only register
(read only)
R_GPIO_IN0
0x40
GPIO input data bits 7 . . 0
Bits
Reset
Name
Description
Value
0
0
V_GPIO_IN0
Input data bit from pin GPIO0
1
0
V_GPIO_IN1
Input data bit from pin GPIO1
2
0
V_GPIO_IN2
Input data bit from pin GPIO2
3
0
V_GPIO_IN3
Input data bit from pin GPIO3
4
0
V_GPIO_IN4
Input data bit from pin GPIO4
5
0
V_GPIO_IN5
Input data bit from pin GPIO5
6
0
V_GPIO_IN6
Input data bit from pin GPIO6
7
0
V_GPIO_IN7
Input data bit from pin GPIO7
290 of 306
Data Sheet
October 2003
HFC-E1
General purpose I/O pins
(read only)
R_GPIO_IN1
Cologne
Chip
0x41
GPIO input data bits 15 . . 8
Bits
Reset
Name
Description
Value
0
0
V_GPIO_IN8
Input data bit from pin GPIO8
1
0
V_GPIO_IN9
Input data bit from pin GPIO9
2
0
V_GPIO_IN10
Input data bit from pin GPIO10
3
0
V_GPIO_IN11
Input data bit from pin GPIO11
4
0
V_GPIO_IN12
Input data bit from pin GPIO12
5
0
V_GPIO_IN13
Input data bit from pin GPIO13
6
0
V_GPIO_IN14
Input data bit from pin GPIO14
7
0
V_GPIO_IN15
Input data bit from pin GPIO15
October 2003
Data Sheet
291 of 306
HFC-E1
General purpose I/O pins
(read only)
R_GPI_IN0
Cologne
Chip
0x44
GPI input data bits 7 . . 0
Note: Unused GPI pins should be connected to ground.
Bits
Reset
Name
Description
Value
0
0
V_GPI_IN0
Input data bit from pin GPI0
1
0
V_GPI_IN1
Input data bit from pin GPI1
2
0
V_GPI_IN2
Input data bit from pin GPI2
3
0
V_GPI_IN3
Input data bit from pin GPI3
4
0
V_GPI_IN4
Input data bit from pin GPI4
5
0
V_GPI_IN5
Input data bit from pin GPI5
6
0
V_GPI_IN6
Input data bit from pin GPI6
7
0
V_GPI_IN7
Input data bit from pin GPI7
292 of 306
Data Sheet
October 2003
HFC-E1
General purpose I/O pins
(read only)
R_GPI_IN1
Cologne
Chip
0x45
GPI input data bits 15 . . 8
Note: Unused GPI pins should be connected to ground.
Bits
Reset
Name
Description
Value
0
0
V_GPI_IN8
Input data bit from pin GPI8
1
0
V_GPI_IN9
Input data bit from pin GPI9
2
0
V_GPI_IN10
Input data bit from pin GPI10
3
0
V_GPI_IN11
Input data bit from pin GPI11
4
0
V_GPI_IN12
Input data bit from pin GPI12
5
0
V_GPI_IN13
Input data bit from pin GPI13
6
0
V_GPI_IN14
Input data bit from pin GPI14
7
0
V_GPI_IN15
Input data bit from pin GPI15
October 2003
Data Sheet
293 of 306
HFC-E1
General purpose I/O pins
(read only)
R_GPI_IN2
Cologne
Chip
0x46
GPI input data bits 23 . . 16
Note: Unused GPI pins should be connected to ground.
Bits
Reset
Name
Description
Value
0
0
V_GPI_IN16
Input data bit from pin GPI16
1
0
V_GPI_IN17
Input data bit from pin GPI17
2
0
V_GPI_IN18
Input data bit from pin GPI18
3
0
V_GPI_IN19
Input data bit from pin GPI19
4
0
V_GPI_IN20
Input data bit from pin GPI20
5
0
V_GPI_IN21
Input data bit from pin GPI21
6
0
V_GPI_IN22
Input data bit from pin GPI22
7
0
V_GPI_IN23
Input data bit from pin GPI23
294 of 306
Data Sheet
October 2003
HFC-E1
General purpose I/O pins
(read only)
R_GPI_IN3
Cologne
Chip
0x47
GPI input data bits 31 . . 24
Note: Unused GPI pins should be connected to ground.
Bits
Reset
Name
Description
Value
0
0
V_GPI_IN24
Input data bit from pin GPI24
1
0
V_GPI_IN25
Input data bit from pin GPI25
2
0
V_GPI_IN26
Input data bit from pin GPI26
3
0
V_GPI_IN27
Input data bit from pin GPI27
4
0
V_GPI_IN28
Input data bit from pin GPI28
5
0
V_GPI_IN29
Input data bit from pin GPI29
6
0
V_GPI_IN30
Input data bit from pin GPI30
7
0
V_GPI_IN31
Input data bit from pin GPI31
October 2003
Data Sheet
295 of 306
HFC-E1
General purpose I/O pins
296 of 306
Data Sheet
Cologne
Chip
October 2003
Chapter 14
Electrical characteristics
October 2003
Data Sheet
297 of 306
HFC-E1
Absolute maximum ratings
Parameter
Cologne
Chip
Electrical characteristics
∗1
Symbol
Min.
Max.
Power supply
VDD
−0.3 V
+4.6 V
Input voltage
VI
−0.3 V
6.0 V
Operating temperature
Topr
−30 ◦ C
+70 ◦ C
Junction temperature
T jnc
0 ◦C
+100 ◦ C
Storage temperature
Tstg
−55 ◦ C
+125 ◦ C
∗2
Recommended operating conditions
Parameter
Power supply
Operating temperature
Symbol
Min.
Typ.
Max
VDD
3.0 V
3.3 V
3.6 V
Topr
0 ◦C
Conditions
+70 ◦ C
Electrical characteristics for 3.3 V power supply
Parameter
Symbol
Min.
Typ.
Max
Low input voltage
VIL
−0.3 V
0.2VDD
High input voltage
VIH
0.7VDD
5.5 V
Low output voltage
VOL
0V
High output voltage
VOH
2.4 V
Conditions
∗2
0.4 V
5.5 V
∗2
∗1 : Stresses beyond those listed under ‘Absolute maximum ratings’ may cause permanent damage to the device.
These are stress ratings only, and operation of the device at these or at any other conditions above those given
in this data sheet is not implied. Exposure to limiting values for extended periods may affect device reliability.
∗2 :
Maximum voltage for oscillator pins is VDD .
298 of 306
Data Sheet
October 2003
HFC-E1
Cologne
Chip
Electrical characteristics
.1 Frame structure
.1.1
Allocation of bits 1 to 8 of the frame (Time slot 0)
Table 1: Allocation of bits 1 to 8 of the frame (Time slot 0)
Bit number
1
2
3
4
5
6
7
8
Si
0
0
1
1
0
1
1
Sa7
Sa8
Alternate frames
frame containing the
frame alignment signal
(note 1)
Frame alignment signal
frame not containing the
Si
1
A
frame alignment signal
(note 1)
(note 2)
(note 3)
Sa4
Sa5
Sa6
(note 1)
Note 1: Si bits used for Cyclic Redundancy Check (CRC4) multiframe alignment.
Note 2: This bit is fixed at ’1’ to assist in avoiding simulations of the frame alignment signal.
Note 3: A = remote alarm indication. In undisturbed operation set to ’0’.
In alarm condition set to ’1’.
Note 4: Bits Sa4 to Sa8 shall be set to ’1’ by the TE.
October 2003
Data Sheet
299 of 306
HFC-E1
.1.2
Cologne
Chip
Electrical characteristics
CRC-4 multiframe structure
Table 2: CRC-4 multiframe structure in time slot 0
Frame
SMF
number
1
2
3
4
5
6
7
8
I
0
C1
0
0
1
1
0
1
1
1
0
1
A
Sa4
Sa5
Sa61
Sa7
Sa8
2
C2
0
0
1
1
0
1
1
3
0
1
A
Sa4
Sa5
Sa62
Sa7
Sa8
4
C3
0
0
1
1
0
1
1
II
5
1
1
A
Sa4
Sa5
Sa63
Sa7
Sa8
6
C4
0
0
1
1
0
1
1
7
0
1
A
Sa4
Sa5
Sa64
Sa7
Sa8
0
C1
0
0
1
1
0
1
1
1
1
1
A
Sa4
Sa5
Sa61
Sa7
Sa8
2
C2
0
0
1
1
0
1
1
3
1
1
A
Sa4
Sa5
Sa62
Sa7
Sa8
4
C3
0
0
1
1
0
1
1
5
E1
1
A
Sa4
Sa5
Sa63
Sa7
Sa8
6
C4
0
0
1
1
0
1
1
7
E2
1
A
Sa4
Sa5
Sa64
Sa7
Sa8
Sa4 . . Sa8
=
Spare bits
A
=
Remote alarm indication
C1 . .C4
=
CRC-4 bits
E1 , E2
=
CRC-4 error indication bits
300 of 306
Bits 1 to 8 of the frame
Sub-Multiframe
Data Sheet
October 2003
Appendix A
HFC-E1 package dimensions
October 2003
Data Sheet
301 of 306
Cologne
Chip
HFC-E1 package dimensions
1.400 ± 0.05
1.600 MAX
HFC-E1
0~7
0.050 MIN
28.000 ± 0.100
1.000 ± 0.20
0.600 ± 0.150
30.00 ± 0.150
LQFP 208 package
Unit: mm
0.220 ± 0.05
0.500 ± 0.10
30.000 ± 0.150
Figure A.1: HFC-E1 package dimensions
302 of 306
Data Sheet
October 2003
List of register and bitmap abbreviations
This list shows all abbreviations which are used to define the register and bitmap names. Appended digits are
not shown here except they have a particular meaning.
16KHZ
16 kHz
CODE
CODEC
A
A bit
CON
ADDR
address
COND
ADDR0
address (byte 0)
CONF
ADDR1
address (byte 1)
CRC
ADDR2
address (byte 2)
ADJ
adjust
AIS
alarm indication
signal
DATA
ALT
alternate
DEL
ATT
attenuation
DF
ATX
analog transmitter
DIR
AUTO
automatic
DR
CTRL
DTMF
BERT
bit error rate test
BIT
bit
BL
block
BRG
bridge
E1
BUSY
busy
E1
C4
C4IO clock
CFG
configuration
CH
HFC-channel
CHANNEL
HFC-channel
CHG
changed
EN
CHIP
chip
END
CLK
clock
EOMF
CMI
code mark
inversion
EPR
CNT
counter
EV
CNTH
counter, high byte
EXCHG
CNTL
counter, low byte
EXT
E
E2
October 2003
ECH
ECL
ERR
code
CODEC
connection settings
condition
conference
cyclic redundancy
check
control
data
deletion
data flow
direction
data rate
dual tone multiple
frequency
CRC error
indication bits
E1 bit
E1 interface
E2 bit
error counter, high
byte
error counter, low
byte
enable
end
end of multiframe
EEPROM
error
event
exchange
external
Data Sheet
F
F-counter
F0
frame
synchronization
signal
F1
F1-counter
F12
F1- and
F2-counters
F2
F2-counter
FAS
frame alignment
signal
FBAUD
full bauded
FDIR
direction
(FIFO-related)
FG
F/G state
FIFO
FIFO
FIRST
first
FLOW
flow
FNUM
number
(FIFO-related)
FOSLIP
force frequency slip
warning
FOSTA
force state
FR
frame
FSM
FIFO sequence
mode
FZ
F- and Z-counter
GLOB
global
GPI
general purpose
input
GPIO
general purpose
input/output
HARM
harmonic
303 of 306
HFC-E1
HCLK
half clock
(frequency
HDLC
high-level data link
control
HFC
HDLC FIFO
controller
ICR
increase
ID
identifier
IDX
index
IFF
inter frame fill
IN
input
INC
increment
INIT
INSYNC
Cologne
Chip
HFC-E1 package dimensions
buffer initialization
synchronization to
input data
NEXT
next
SDIR
NFAS
no frame alignment
signal
SEL
NMF
no multiframe
SEQ
NO
no
SET
NOINC
no increment
SH
NOISE
noise
NTRI
no tristate
NUM
number
OFF
off
OFFS
offset
OFLOW
overflow
OK
ok
ON
on
SLIP
SH0H
SH0L
SH1H
SH1L
SI
SIG
SIM
SL
SL0
INT
internal
OUT
output
SLOT
INV
invert
OVIEW
overview
SLOW
IPATS
IPATS test
pattern
SNUM
IRQ
interrupt
PAT
IRQ1S
one-second
interrupt
PCM
PCM
SRAM
PLL
phase locked loop
SRC
IRQMSK
interrupt mask
PNP
plug and play
SRES
IRQSTA
interrupt status
POL
polarity
ST
ITU
ITU-T G.775
PROC
processing
PWM
pulse width
modulation
JATT
jitter attenuator
STA
START
STATUS
STOP
LEN
length
RAL
remote alarm
SUBCH
LEV
level
RAM
RAM
SUPPR
LI
line
RD
read
LOOP
loop
RECO
recovery
LOS
loss of signal
RES
reset
LOSS
loss of
synchronization
signal
RESYNC
resynchronization
REV
reverse
TI
RLD
reload
TIME
ROUT
routing (of PCM
buffer
TRANS
RST
restart
TS
RV
revision
TX
RX
receive
LOST
frame data lost
LPRIO
low priority
MD
mode
MF
multiframe
MFA
multiframe
alignment
MISC
miscellaneous
SA
spare bits
MIX
mixed
SA13
spare bit Sa13
MSK
mask
SA23
spare bit Sa23
SA6
NEG
negative
SA84
304 of 306
SWORD
SYNC
SZ
TRP
direction
(slot-related)
select
sequence
setup
shape
shape 0, high byte
shape 0, low byte
shape 1, high byte
shape 1, low byte
SI bit
signal
simulation
time slot
time slot 0
frequency slip
PCM time slot
slow
number
(slot-related)
SRAM
source
soft reset
S/T interface
state, status
start
status
stop
subchannel
suppression
threshold
service word
synchronize
size
timer
time
transition
transparent
timestep
transmit
use
µ-law
usage
VIO
code violation
spare bit Sa6
WD
spare bits Sa [8..4]
WRDLY
watchdog timer
write delay
ULAW
Data Sheet
October 2003
HFC-E1
XCRC
extended CRC4
XS13
Spare bit of frame
13
XS15
Cologne
Chip
HFC-E1 package dimensions
Spare bit of frame
15
October 2003
Z1
Z1-counter
Z12
Z1- and
Z2-counters
Z1H
Z1-counter, high
byte
Z1L
Z1-counter, low
Data Sheet
byte
Z2
Z2H
Z2L
Z2-counter
Z2-counter, high
byte
Z2-counter, low
byte
305 of 306
Cologne Chip AG
Data Sheet of HFC-E1
Cologne
Chip