HM 65728B MATRA MHS 2K × 8 High Speed CMOS SRAM Description The HM 65728B is a high speed CMOSstatic RAM organized as 2048 × 8 bits. It is manufactured using MHS’s high performance CMOS technology. Access times as fast as 25 ns are available with maximum power consumption of only 600 mW. The HM 65728B features fully static operation requiring no external clocks or timing strobes. The automatic power-down feature reduces the power consumption by 80 % when the circuit is deselected. Easy memory expansion is provided by an active low chip select (CS) and active low output enable (OE) and three state drivers. All inputs and outputs of the HM 65728 are TTL compatible and operate from single 5V supply thus simplifying system design. The HM 65728B is 100 % processed following the test methods of MIL STD 883 and/or ESA/SCC 9000 making it ideally suitable for military/space applications that demand superior levels of performance and reliability. Features Fast Access Time Commercial : 25/35/45/55 ns (max) Military : 25/35/45/55 ns (max) Low Power Consumption Active : 550 mW (max) Standby : 110 mW (max) Wide Temperature Range : –55°C to + 125°C 300 and 600 Mils Width Package TTL Compatible Inputs and Outputs Asynchronous Capable of Withstanding Greater than 2000 V Electrostatic Discharge Single 5 Volt Supply Interface Block Diagram Rev. C (16/08/95) 1 HM 65728B MATRA MHS Pin Configuration Ceramic 300 mils, 24 pins, DIL Plastic 300 & 600 mils, 24 pins, DIL SOIC 300 mils, 24 pins LCC, 32 pins Pinout DIL/SOIC 24 pins (top view) Logic Symbol Pinout LCC 32 pins (top view) Pin Names A0–A10: Address inputs CS : Chip Select I/O0–I/O7 : Input/Output OE : Output Enable Vcc : Power W : Write enable Gnd : Ground Truth Table 2 CS OE W DATA–IN DATA–OUT MODE H X X Z Z Deselect L L H Z Valid Read L H L Valid Z Write L L L Valid Z Write Rev. C (16/08/95) HM 65728B MATRA MHS Electrical Characteristics Supply voltage to GND potential : . . . . . . . . . . . . . . . –0.5 V to +7.0 V DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . –3.0 V to +7.0 V DC output voltage in high Z state : . . . . . . . . . . . . . . –0.5 V to +7.0 V Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA Electro Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . > 2000 V (MIL STD 883 METHOD 3015.2) Operating Range OPERATING VOLTAGE OPERATING TEMPERATURE Military (– 2) 5 V ± 10 % – 55_C to + 125_C Automotive –A 5 V ± 10 % – 40_C to + 125_C Industrial (– 9) 5 V ± 10 % – 40_C to + 85_C Commercial (– 5) 5 V ± 10 % 0_C to + 70_C Recommended DC Operating Conditions PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT Vcc Supply Voltage 4.5 5.0 5.5 V Gnd Ground 0.0 0.0 0.0 V VIL Input low voltage – 0.3 0.0 0.8 V VIH Input high voltage 2.2 – 5.5 V MINIMUM TYPICAL MAXIMUM UNIT Capacitance PARAMETER DESCRIPTION Cin (1) Input capacitance – – 5 pF Cout (1) Output capacitance – – 7 pF MINIMUM TYPICAL MAXIMUM UNIT Input leakage current – 10.0 – 10.0 µA Output leakage current – 10.0 – 10.0 µA Note : 1. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested. DC Parameters PARAMETER IIX IOZ (2) (3) DESCRIPTION IOS (3) Output short circuit current – – – 300.0 mA VOL (4) Output low voltage – – 0.4 V VOH (5) Output high voltage 2.4 – – V Note : 2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled. 3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds. Not more than 1 output should be shorted at one time. 4. Vcc min, IOL = 8.0 mA. 5. Vcc min, IOH = -4.0 mA. Rev. C (16/08/95) 3 HM 65728B MATRA MHS Consumption for Commercial (–5) Specification SYMBOL PARAMETER 65728B H–5 65728B K–5 65728B M–5 65728B N–5 UNIT VALUE ICCSB (6) Standby supply current 20 20 20 30 mA max ICCOP (7) Dynamic operating current 100 100 100 100 mA max Consumption for Military (–2) Automotive (–A), Industrial (–9) Specification SYMBOL PARAMETER 65728B H–2/A/9 65728B K–2/A/9 65728B M–2/A/9 65728B N–2/A/9 UNIT VALUE ICCSB (6) Standby supply current 40 30 30 30 mA max ICCOP (7) Dynamic operating current 120 120 120 120 mA max Note : 6. CS ≥ VIH, a pull-up resistor to Vcc on the CS input is required to keep the device deselected during Vcc power-up otherwise ICCSB will exceed values above. 7. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd. AC Parameters AC Conditions Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output loading IOL/IOH (see figure 1a and 1b) : . . . . . . . . . . . +30 pF AC Test Loads and Waveforms Figure 1 a 4 Figure 1 b Figure 2 Rev. C (16/08/95) HM 65728B MATRA MHS Write Cycle : Commercial (–5) Specification SYMBOL PARAMETER 65728B H–5 65728B K–5 65728B M–5 65728B N–5 UNIT VALUE TAVAV Write cycle time 25 35 45 55 ns min TAVWL Address set–up time 0 0 0 0 ns min TAVWH Address valid to end of write 20 30 40 50 ns min TDVWH Data set–up time 15 15 20 25 ns min TELWH CS low to write end 20 30 40 50 ns min TWLQZ(8) Write low to high Z 10 15 15 20 ns max TWLWH Write pulse width 20 20 20 30 ns min TWHAX Address hold to end of write 2 2 2 2 ns min TWHDX Data hold time 0 0 0 5 ns min Write high to low Z 3 0 0 0 ns min Address hold end CS 3 3 3 3 ns min TWHQX (8, 9) TEHAX Notes : 8. The data input set up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. At any given temperature and voltage condition, TWHQX is less than TWLQZ for all devices. These parameters are sampled and not 100 % tested. Write Cycle : Military (–2) Automotive (–A) Industrial (–9) Specification SYMBOL PARAMETER 65728B H–2 65728B K–2 65728B M–2 65728B N–2 UNIT VALUE TAVAV Write Cycle time 25 35 45 55 ns min TAVWL Address set–up time 0 0 0 0 ns min TAVWH Address valid to end of write 20 30 40 50 ns min TDVWH Data set–up time 15 15 20 25 ns min TELWH CS low to write end 20 30 40 50 ns min TWLQZ(8) Write low to high Z 10 15 15 20 ns max TWLWH Write pulse width 20 20 25 30 ns min TWHAX Address hold to end of write 2 2 2 2 ns min TWHDX Data hold time 5 5 5 5 ns min TEHAX Address hold end CS 3 3 3 3 ns min Rev. C (16/08/95) 5 HM 65728B MATRA MHS Write Cycle 1 (W Controlled) Write Cycle 2 (CS controlled) 6 Rev. C (16/08/95) HM 65728B MATRA MHS Read Cycle : Commercial (–5) Specification SYMBOL PARAMETER 65728B H–5 65728B K–5 65728B M–5 65728B N–5 UNIT VALUE TAVAV Read cycle time 25 35 45 55 ns min TAVQV Address access time 25 35 45 55 ns max TAVQX Address valid to low Z 5 5 5 5 ns min TELQV Chip–select access time 25 35 45 55 ns max TELQX CS low to low Z 5 5 5 5 ns min TEHQZ CS high to high Z 12 15 20 20 ns max TELIC CS low to power up 0 0 0 0 ns min TEHICL CS high to power down 15 20 25 25 ns max TGLQV Output enable access time 15 15 20 25 ns max TGLQX OE low to low Z 2 0 0 0 ns min TGHQZ OE high to high Z 10 15 15 20 ns max Read Cycle : Military (–2) Automotive (–A) Industrial (–9) Specification SYMBOL PARAMETER 65728B H–2 65728B K–2 65728B M–2 65728B N–2 UNIT VALUE TAVAV Read cycle time 25 35 45 55 ns min TAVQV Address access time 25 35 45 55 ns max TAVQX Address valid to low Z 5 5 5 5 ns min TELQV Chip–select access time 25 35 45 55 ns max TELQX CS low to low Z 5 5 5 5 ns min TEHQZ CS high to high Z 12 15 20 20 ns max TELIC CS low to power up 0 0 0 0 ns min TEHICL CS high to power down 20 20 25 25 ns max TGLQV Output enable access time 15 15 20 25 ns max TGLQX OE low to low Z 0 0 0 0 ns min TGHQZ OE high to high Z 12 15 15 20 ns max Rev. C (16/08/95) 7 HM 65728B MATRA MHS Read Cycle nb 1 Read Cycle nb 2 Ordering Information 0 – Chip form 8 k × 8 high speed 1 – Ceramic 24 pins static RAM 3 – Plastic 24 pins 300 mils 3E – Plastic 24 pins 600 mils 4 – LCC 32 pins T – SOIC 24 pins 300 mils H = 25 ns K = 35 ns M = 45 ns N = 55 ns –2 –5 –6 –9 –A /883 DB R RD D : : : : : : : : : : Military Commercial 100% 25°C Probe Industrial Automotive MIL STD 883 Class B or S Dice Military program Tape & Reel option Tape & Reel/Dry pack option Dry pack option The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use. 8 Rev. C (16/08/95)