ETC PCK210

INTEGRATED CIRCUITS
PCK210
Low voltage dual 1:5 differential
ECL/PECL clock driver
Product data
Supersedes data of 2002 Apr 11
Philips
Semiconductors
2002 Nov 13
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
FEATURES
PINNING
• 85 ps part-to-part skew typical
• 20 ps output-to-output skew typical
• Differential design
• VBB output
• Voltage and temperature compensated outputs
• Low voltage VEE range of -2.25 V to -3.8 V
• 75 kΩ input pull-down resistors
• Form, fit, and function compatible with MC100EP210
VCCO
QA0
QA0
QA1
QA1
QA2
QA2
VCCO
32
31
30
29
28
27
26
25
Pin configuration
VCC
1
24 QA3
NC
2
23 QA3
CLKA
3
22 QA4
CLKA
4
21 QA4
PCK210
DESCRIPTION
8
17 QB1
QB4
VCCO
9
The PCK210 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
tPD distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
VCCO 16
18 QB1
QB2 15
7
VEE
QB2 14
CLKB
QB3 13
19 QB0
11
20 QB0
6
QB3 12
5
CLKB
QB4 10
The PCK210 is a low skew 1-to-5 dual differential driver, designed
with clock distribution in mind. The input signals can be either
differential or single-ended if the VBB output is used. The signal is
fanned out to 5 identical differential outputs.
VBB
SW00909
Figure 1. Pin configuration
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50 Ω, even if
only one side is being used. In most applications, all ten differential
pairs will be used, and therefore terminated. In the case where fewer
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10-20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
Pin description
SYMBOL
PIN
DESCRIPTION
VCC
1
Supply voltage
NC
2
Not connected
CLKA, CLKA
3, 4
Differential input pair
The PCK210, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the PCK210
to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Designers can take advantage of the PCK210’s
performance to distribute low skew clocks across the backplane or
the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies.
VBB
5
VBB output
CLKB, CLKB
6, 7
Differential input pair
VEE
8
Ground
VCCO
9, 16, 25, 32
Output drive power supply
voltage
QA0-QA4,
QB0-QB4
31, 29, 27, 24, 22,
20, 18, 15, 13, 11
Differential outputs
The PCK210 may be driven single-endedly utilizing the VBB bias
output with the CLKA or CLKB input. If a single-ended signal is to be
used, the VBB pin should be connected to the CLKA or CLKB input
and bypassed to ground via a 0.01 µF capacitor. The VBB output
can only source/sink 0.3 mA, therefore, it should be used as a
switching reference for the PCK210 only. Part-to-part skew
specifications are not guaranteed when driving the PCK210
single-endedly.
QA0-QA4 ,
QB0-QB4
30, 28, 26, 23, 21,
19, 17, 14, 12, 10
Differential outputs
ORDERING INFORMATION
Type number
PCK210BD
2002 Dec 13
Package
Name
Description
Version
Temperature
range
LQFP32
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
-40 to +70 °C
2
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
LOGIC SYMBOL
QA0
QB0
QA0
QB0
QA1
CLKA
QB1
CLKB
QA1
CLKA
QB1
CLKB
QA2
QB2
QA2
QB2
QA3
QB3
QA3
QB3
QA4
QB4
VBB
QA4
QB4
SW00910
Figure 2. Logic symbol
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
VCC
LIMITS
PARAMETER
MIN
UNIT
MAX
Supply voltage
-0.3
+4.6
V
VI
Input voltage
-0.3
VCC + 0.3
V
IIN
Input current
Tstg
Storage temperature range
-
±20
mA
-40
+125
°C
>1750
V
ESDHBM
Electrostatic discharge (Human Body Model; 1.5 kΩ, 100 pF)
-
ESDMM
Electrostatic discharge (Machine Model; 0 kΩ, 100 pF)
-
>200
V
ESDCDM
Electrostatic discharge (Charge Device Model)
-
>1000
V
NOTE:
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
Supply voltage
VIR
Receiver input voltage
VDIFF
Input differential voltage1
Tamb
Operating ambient temperature range in free air
CONDITIONS
V(CLKinN)- V(CLKin)
MIN
MAX
UNIT
2.25
3.8
V
VEE
VCC
V
—
1.00
V
-40
+85
°C
NOTE:
1. To idle an unused differential clock input, connect one input terminal (e.g. CLK1) to VBB and leave its complimentary input terminal
(e.g. CLK1) open-circuit, in which case CLK1 will default low by its internal pull-down reistor. Inputs should not be shorted to ground or VCC.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fan-out and high drive capability products.
2002 Dec 13
3
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
DC ELECTRICAL CHARACTERISTICS
Vsupply: VCC = VCCO = 0.0 V; VEE = -2.25 V to -3.80 V.
SYMBOL
PARAMETER
-40 °C
CONDITIONS
+25 °C
+85 °C
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
IEE
Internal supply current
Absolute value of current
20
80
20
85
30
90
mA
ICC
Output and internal
supply current
All outputs terminated
50 Ω to VCC - 2.0 V
270
390
270
395
270
405
mA
IIN
Input current
Includes pull-up/pull-down
resistors
-
150
-
150
-
150
µA
VBB
Internally generated bias
voltage
for VEE = -2.25 V to -3.8 V
-1.38
-1.16
-1.38
-1.16
-1.38
-1.16
V
VPP
Input amplitude
Difference of input
≈ VIH - VIL (Note 1)
0.5
1.3
0.5
1.3
0.5
1.3
V
Common mode voltage
Crosspoint of input
≈ average (VIH, VIL)
VEE + 1.0
-0.3
VEE + 1.0
-0.3
VEE + 1.0
-0.3
V
VOH
HIGH-level output voltage
IOH = -30 mA
-1.30
-0.95
-
-
-1.20
-0.85
V
VOL
LOW-level output voltage
IOL = -5 mA
-1.85
-1.40
-
-
-1.90
-1.50
V
VOUTpp
Differential output swing
350
-
-
-
500
-
mV
VCMR
DC ELECTRICAL CHARACTERISTICS
Vsupply: VCC = VCCO = 2.25 V to 3.80 V; VEE = 0.0 V.
SYMBOL
PARAMETER
IEE
Internal supply current
ICC
IIN
CONDITIONS
-40 °C
+25 °C
+85 °C
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Absolute value of
current
20
80
20
85
30
90
mA
Output and internal
supply current
All outputs terminated
50 Ω to VCC - 2.0 V
270
390
270
395
270
405
mA
Input current
Includes pull-up/
pull-down resistors
-
150
-
150
-
150
µA
VBB
Internally generated
bias voltage
VCC = 2.25 V to 3.8 V
VCC - 1.38
VCC - 1.16
VCC - 1.38
VCC - 1.16
VCC - 1.38
VCC - 1.16
V
VPP
Input amplitude
Difference of input
≈ VIH - VIL (Note 1)
0.5
1.3
0.5
1.3
0.5
1.3
V
VCMR
Common mode
voltage
Crosspoint of input
≈ average (VIH, VIL)
1
VCC - 0.3
1
VCC - 0.3
1
VCC - 0.3
V
VOH
HIGH-level output
voltage
IOH = -30 mA
VCC - 1.30
VCC - 0.95
-
-
VCC - 1.20
VCC - 0.85
V
VOL
LOW-level output
voltage
IOL = -5 mA
VCC - 1.85
VCC - 1.40
-
-
VCC - 1.90
VCC - 1.50
V
VOUTpp
Differential output
swing
350
-
-
-
500
-
mV
NOTE:
1. VPP minimum and maximum required to maintain AC specifications. Actual device function will tolerate minimum VPP of 100 mV.
2002 Dec 13
4
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
AC CHARACTERISTICS — PECL input
Vsupply: VCC = VCCO = 2.25 V to 3.80 V; VEE = 0.0 V -ORSYMBOL
PARAMETER
tPD
Differential propagation
delay
CLK,CLK to all
Q0,Q0 through Q4,Q4
CONDITIONS
VCC = VCCO = 0.0 V; VEE = -2.25 V to -3.80 V.
-40 °C
+25 °C
+85 °C
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Nominal (single input
condition)
VPP = 0.650 V,
VCMR = VCC - 0.800 V
Applies to 500 MHz
reference. (Note 1)
270
-
420
300
-
450
380
-
530
ps
Part-to-part skew
Single input condition
(Note 1)
-
-
110
-
-
110
-
-
110
ps
tSK(output)
Output-to-output skew
for given part
Single input condition
(Note 1)
-
15
50
-
15
50
-
15
50
ps
tPD
Differential propagation
delay
CLK,CLK to all
Q0,Q0 through Q4,Q4
All input conditions
(Note 1)
220
-
520
250
-
550
320
-
620
ps
Part-to-part skew
(Note 1)
-
-
160
-
-
160
-
-
160
ps
Output-to-output skew
for given part
(Note 1)
-
15
50
-
15
50
-
15
50
ps
-
-
1
-
-
1
-
-
1
ns
-
-
1500
-
-
1500
-
-
1500
MHz
100
-
320
100
-
320
100
-
320
ps
tSK(part)
tSK(part)
tSK(output)
tjitter
Cyle-to-cycle jitter
fMAX
Maximum frequency
Functional to 1.5 GHz
Timing specifications
apply up to 1.0 GHz
tr, tf
Output rise and fall
times (20%, 80%)
(Note 1)
NOTE:
1. For operation with 2.5 V supply, the output termination is 50 Ω to VEE.
For operation at 3.3 V supply, the output termination is 50 Ω to VCC - 2 V.
2002 Dec 13
5
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
2002 Dec 13
6
SOT358-1
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
REVISION HISTORY
Rev
Date
PCK210
Description
_2
20021213
Product data (9397 750 10866); ECN 853-2336 29225 of 22 November 2002.
Modifications:
• Addition of jitter specification to datasheet.
_1
20020411
Product data (9397 750 09657); ECN 853-2336 27995 of 11 April 2002.
2002 Dec 13
7
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
Data sheet status
Level
Data sheet status[1]
Product
status[2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 12-02
For sales offices addresses send e-mail to:
[email protected].
Document order number:
Philips
Semiconductors
2002 Dec 13
8
9397 750 10866