ICS ICS853210AY

Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853210 is a low skew, high performance dual 1 - t o -5 Differential-to-2.5V/3.3V
HiPerClockS™
LVPECL/ECL Fanout Buffer and a member of
the HiPerClockS™family of High Performance
Clock Solutions from ICS. The ICS853210
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS853210 ideal for those clock
distribution applications demanding well defined performance and repeatability.
• 2 differential 2.5V/3.3V LVPECL / ECL bank outputs
ICS
• 2 differential clock input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLKx input
• Output skew: 13ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: 485ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP210 and MC100LVEP210
nQB1
QB1
nQB0
QB0
24 23 22 21 20 19 18 17
VCCO
15
QB2
QA2
27
14
nQB2
nQA1
28
13
QB3
QA1
29
12
nQB3
nQA0
30
11
QB4
QA0
31
10
nQB4
VCCO
32
9
VCCO
2
3
4
5
6
7
8
nPCLKB
VEE
QB2
nQB2
1
PCLKB
QB1
nQB1
ICS853210
VBB
QB0
nQB0
16
26
nPCLKA
QA4
nQA4
25
PCLKA
QA3
nQA3
VCCO
nQA2
nc
QA2
nQA2
PCLKB
nPCLKB
nQA4
QA1
nQA1
QA4
QA3
QA0
nQA0
VCC
PCLKA
nPCLKA
PIN ASSIGNMENT
nQA3
BLOCK DIAGRAM
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
V BB
QB3
nQB3
QB4
nQB4
853210AY
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1
REV. A NOVEMBER 12, 2003
ICS853210
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VCC
Power
Type
2
nc
Unused
3
PCLKA
Input
4
nPCLKA
Input
5
V BB
Output
6
PCLKB
Input
7
nPCLKB
Input
Description
Core supply pin.
No connect.
Pulldown Non-inver ting differential clock input.
Pullup/
Clock input. VCC/2 default when left floating.
Pulldown
Bias voltage.
Pulldown Non-inver ting differential clock input.
Pullup/
Clock input. VCC/2 default when left floating.
Pulldown
Negative supply pin.
8
V EE
Power
9, 25, 32
VCCO
Power
Output supply pins.
10, 11
nQB4, QB4
Output
Differential output pair. LVPECL interface levels.
12, 13
nQB3, QB3
Output
Differential output pair. LVPECL interface levels.
14, 15
nQB2, QB2
Output
Differential output pair. LVPECL interface levels.
17, 18
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
19, 20
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
21, 22
nQA4, QA4
Output
Differential output pair. LVPECL interface levels.
23, 24
nQA3, QA3
Output
Differential output pair. LVPECL interface levels.
26, 27
nQA2, QA2
Output
Differential output pair. LVPECL interface levels.
28, 29
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
30, 31
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN
Input Pulldown Resistor
75
KΩ
RVCC/2
Pullup/Pulldown Resistors
50
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
PCLKA or
PCLKB
0
nPCLKA or
nPCLKB
1
1
0
Outputs
QA0:QA4,
nQA0:nQA4,
QB0:QB4
nQB0:nQB4
HIGH
LOW
HIGH
LOW
Input to Output Mode
Polarity
Differential to Differential
Non Inver ting
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853210AY
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2
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Negative Supply Voltage, VEE
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5V
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Supply Voltage, VCC
Outputs, IO
Continuous Current
Surge Current
VBB Sink/Source, IBB
to the device. These ratings are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
50mA
100mA
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol
Parameter
VCC
Core Supply Voltage
I EE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
3.3
3.8
V
80
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.37
2.295
2.33
2.365
V
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VIH
Input High Voltage(Single-Ended)
2.075
2.36
2.075
2.36
2.075
2.36
V
VIL
Input Low Voltage(Single-Ended)
1.43
1.765
1.43
1.765
1.43
1.765
V
VBB
Output Voltage Reference; NOTE 2
1.86
1.98
1.86
1.98
1.86
1.98
V
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
150
1200
150
1200
150
1200
mV
3.3
1.2
3.3
1.2
3.3
V
150
µA
Symbol
Parameter
VOH
VOL
VCMR
IIH
IIL
800
1.2
800
150
800
150
Units
-10
-10
-10
µA
-150
-150
-150
µA
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853210AY
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3
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.495
1.53
1.565
VOL
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VIH
Input High Voltage(Single-Ended)
1.275
1.56
1.275
1.56
1.275
-0.83
V
VIL
Input Low Voltage(Single-Ended)
0.63
0.965
0.63
0.965
0.63
0.965
V
VPP
150
1200
150
1200
150
1200
mV
2.5
1.2
2.5
1.2
2.5
V
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
150
µA
IIL
Input
Low Current
VCMR
PCLK0, PCLK1
800
1.2
800
150
-10
800
150
-10
-10
V
µA
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
µA
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Output High Voltage; NOTE 1
-1.125
-1.025
-0.92
-1.075
-1.005
-0.93
-1.005
-0.97
-0.935
V
VOL
Output Low Voltage; NOTE 1
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.765
-1.67
V
VIH
Input High Voltage(Single-Ended)
-1.225
-0.94
-1.225
-0.94
-1.225
-0.94
V
VIL
Input Low Voltage(Single-Ended)
-1.87
-1.535
-1.87
-1.535
-1.87
-1.535
V
VBB
Output Voltage Reference; NOTE 2
-1.44
-1.32
-1.44
-1.32
-1.44
VPP
150
1200
150
1200
150
0
VEE+1.2V
0
VEE+1.2V
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
IIL
Input
Low Current
VCMR
PCLK0, PCLK1
800
VEE+1.2V
150
-10
800
800
150
-10
-10
853210AY
-150
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4
-150
V
1200
mV
0
V
150
µA
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
-150
-1.32
µA
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V
Symbol
VCC = 2.375 TO 3.8V; VEE = 0V
-40°C
Parameter
fMAX
Output Frequency
tP LH
tsk(o)
Propagation Delay, Low-to-High; NOTE 1
Propagation Delay,
@ 2.5V
High-to-Low; NOTE 1
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR/tF
Output Rise/Fall Time
tPHL
OR
Min
Typ
415
400
25°C
Max
Min
Typ
470
520
430
470
540
425
13
Min
Typ
485
545
435
515
585
ps
490
550
445
515
585
ps
25
13
25
13
25
ps
85
160
85
160
85
160
ps
115
188
260
190
250
190
235
ps
>3
130
Max
Units
Max
>3
20% to 80%
85°C
>3
145
GHz
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853210AY
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5
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
VCCO
Qx
VCC
SCOPE
nPCLKA,
nPCLKB
LVPECL
V
V
Cross Points
PP
CMR
PCLKA,
PCLKB
nQx
VEE
V EE
-0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
nQy
nQy
Qx
PART 2
Qy
Qy
t sk(pp)
t sk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLKA,
nPCLKB
80%
PCLKA,
PCLKB
80%
VSW I N G
Clock
Outputs
nQA0:nQA4,
nQB0:nQB4,
20%
20%
tR
tF
QA0:QA4,
QB0:QB4,
tp
OUTPUT RISE/FALL TIME
853210AY
LH
tp
HL
PROPAGATION DELAY
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6
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1A shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level V BB generated from the device is connected to the
negative input. The C1 capacitor should be located as close
as possible to the input pin.
VCC(or VDD)
CLK_IN
PCLK
VBB
nPCLK
FIGURE 1A. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1B shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1B. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
853210AY
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7
REV. A NOVEMBER 12, 2003
ICS853210
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
853210AY
125Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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8
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
TERMINATION
FOR
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853210AY
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9
REV. A NOVEMBER 12, 2003
ICS853210
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm
the driver termination requirements.
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLKx/nPCLKx input
driven by the most common driver types. The input interfaces
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R3
120
R2
50
Zo = 60 Ohm
SSTL
Zo = 50 Ohm
R4
120
PCLK
PCLK
Zo = 60 Ohm
Zo = 50 Ohm
nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R3
1K
R4
1K
PCLK
PCLK
R5
100
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerClockS
Input
R1
1K
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PC L K /n PC LK
R2
1K
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853210AY
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10
REV. A NOVEMBER 12, 2003
Integrated
Circuit
Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853210.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853210 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 304mW + 309.4mW = 613.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.613W * 42.1°C/W = 110.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853210AY
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11
REV. A NOVEMBER 12, 2003
ICS853210
Integrated
Circuit
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
-V
Pd_H = [(V
– (V
CCO_MAX
OH_MAX
CCO_MAX
– 0.935V
) = 0.935V
For logic low, VOUT = V
(V
=V
OL_MAX
=V
CCO_MAX
– 1.67V
) = 1.67V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO _MAX
L
-V
OH_MAX
)=
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A NOVEMBER 12, 2003
Integrated
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ICS853210
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853210 is: 437
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REV. A NOVEMBER 12, 2003
ICS853210
Integrated
Circuit
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PACKAGE OUTLINE - Y SUFFIX
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FOR
32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. A NOVEMBER 12, 2003
ICS853210
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS853210AY
ICS853102AY
32 lead LQFP
250 per tray
-40°C to 85°C
ICS853210AYT
ICS853210AY
32 lead LQFP on Tape and Reel
1000
-40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A NOVEMBER 12, 2003