Constant Frequency Current-Mode Step-Down DC/DC Controller in TSOT ADP1864 FEATURES GENERAL DESCRIPTION Wide input voltage range: 3.15 V to 14 V Wide output voltage range: 0.8 V to input voltage Pin-to-pin compatible with LTC1772, LTC3801 Up to 94% efficiency 0.8 V ±1.25% reference accuracy over temperature Internal soft start 100% duty cycle for low dropout voltage Current-mode operation for good line and load transient response 7 μA shutdown current 235 μA quiescent supply current Short-circuit and overvoltage protection Small 6-lead TSOT package The ADP1864 is a compact, inexpensive, constant-frequency current-mode step-down DC-to-DC controller. The ADP1864 drives a P-channel MOSFET that regulates an output voltage as low as 0.8 V with ±2% accuracy, for up to 5 A load currents, from input voltages as high as 14 V. The ADP1864 provides system flexibility by allowing accurate setting of the current limit with an external resistor, while the output voltage is easily adjustable using two external resistors. The ADP1864 includes an internal soft start to allow quick power-up while preventing input inrush current. Additional safety features include short-circuit protection, output overvoltage protection, and input under voltage protection. Current-mode control provides fast and stable load transient performance, while the 580 kHz operating frequency allows a small inductor to be used in the system. To further the life of a battery source, the controller turns on the external P-channel MOSFET 100% of the duty cycle in dropout. APPLICATIONS Wireless devices 1- to 3-cell Li-Ion battery-powered applications Set-top boxes Processor core power supplies Hard disk drives The ADP1864 operates over the −40°C to +85°C temperature range and is available in a small, low profile, 6-lead TSOT package. MOSFET = FDC638P 100 VOUT = 2.5V 95 ADP1864 90 VIN = 3.3V to 10V COMP IN 5 80.6kΩ 85 0.03Ω 2 GND 3 FB 10μF 3.3V CS 4 80 5μH PGATE 6 174kΩ 2.5V, 2.0A 75 4.2V 47μF 70 65 60 0.01 5.0V 05562-018 1 470pF 05562-001 15kΩ 0.1 1.0 10.0 EFFICIENCY vs. LOAD CURRENT FOR APPLICATION Figure 1. Typical Applications Diagram Figure 2. Efficiency vs. Load Current Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. ADP1864 TABLE OF CONTENTS Features .............................................................................................. 1 Application Information................................................................ 10 Applications....................................................................................... 1 Duty Cycle ................................................................................... 10 General Description ......................................................................... 1 Ripple Current ............................................................................ 10 Specifications..................................................................................... 3 Sense Resistor.............................................................................. 10 Absolute Maximum Ratings............................................................ 4 Inductor Value ............................................................................ 10 ESD Caution.................................................................................. 4 MOSFET...................................................................................... 11 Pin Configuration and Function Descriptions............................. 5 Diode............................................................................................ 11 Typical Performance Characteristics ............................................. 6 Input Capacitor........................................................................... 11 Theory of Operation ........................................................................ 8 Output Capacitor........................................................................ 11 Loop Start-Up ............................................................................... 8 Feedback Resistors ..................................................................... 12 Short-Circuit Protection.............................................................. 9 Layout Considerations................................................................... 13 Undervoltage Lockout (UVLO) ................................................. 9 Example Applications Circuits ..................................................... 14 Overvoltage Lockout Protection (OVP).................................... 9 Outline Dimensions ....................................................................... 15 Soft Start ........................................................................................ 9 Ordering Guide .......................................................................... 15 REVISION HISTORY 10/05—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADP1864 SPECIFICATIONS VIN = 5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY Input Voltage Quiescent Current Shutdown Supply Current Undervoltage Lockout Threshold ERROR AMPLIFIER FB Input Current FB Input Current Amplifier Transconductance COMP Startup Threshold COMP Shutdown Threshold COMP Startup Current Source FB Regulation Voltage Overvoltage Protection Threshold Overvoltage Protection Hysteresis CURRENT SENSE Peak Current Sense Voltage Peak Current Sense Voltage Current Sense Gain OUTPUT REGULATION Line Regulation 1 Load Regulation 2 OSCILLATOR Oscillator Frequency FB Frequency Foldback Threshold GATE DRIVE Gate Rise Time Gate Fall Time Minimum On Time SOFT START POWER-ON TIME Symbol VIN IQ ISD VUVLO Conditions Min Typ Max Unit 14 350 15 3.01 3.10 V μA μA V V 3.15 VIN = 3.15 V to 14 V, GATE = IN VIN = 3.15 V to 14 V, COMP = GND VIN falling, TA = −40°C to +85°C VIN rising, TA = −40°C to +85°C 2.75 2.85 235 7 2.90 3.00 IFB IFB VFB = 0.8 V VFB = 0.8 V, TA = −40°C to +85°C −20 −35 -2 -2 20 35 nA nA VOVP VFB = 0.8 V, ICOMP = ±5 μA VIN = 3.15 V to 14 V , TA = −40°C to +85° VIN = 3.15 V to 14 V , TA = −40°C to +85° COMP = GND VIN = 3.15 V to 14 V , TA = −40°C to +85° Measured at FB 0.55 0.15 0.25 0.790 0.87 0.24 0.67 0.3 0.6 0.8 0.885 50 0.80 0.55 0.85 0.810 0.9 mS V V μA V V mV TA = −40°C to +85°C VIN = 3.15 V to 14 V, TA = −40°C to +85°C VCS to VCOMP 90 80 VIN = 3.15 V to 14 V, VFB/VIN VFB/VCOMP VFB = 0.8 V VFB = 0 V CGATE = 3 nF CGATE = 3 nF PGATE minimum low duration 1 500 125 125 12 mV mV V/V 0.12 −2 mV/V mV/V 580 190 0.35 50 40 190 1.1 650 kHz kHz V ns ns ns ms Line regulation is measured with the application circuit of Figure 1. Line regulation is specified as being the change in the FB voltage resulting from a 1 V change in the IN voltage. 2 Load regulation is measured using the application circuit from Figure 1. Load regulation is specified as the change in the FB voltage resulting from a 1 V change in COMP voltage. The COMP voltage range is typically 0.9 V to 2.3 V for the minimum to maximum load current condition. Rev. 0 | Page 3 of 16 ADP1864 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter IN to GND CS, PGATE to GND FB, COMP to GND θJA 2-Layer (SEMI Standard Board) θJA 4-Layer (JEDEC Standard Board) Operating Ambient Temperature Operating Junction Temperature Storage Temperature Lead Temperature Range Rework Temperature (J-STD-020B) Peak Reflow Temperature (20 sec to 40 sec, J-STD-020B) Rating −0.3 V to +16 V −0.3 V to (VIN + 0.3 V) −0.3 V to +6 V 315°C/W 186°C/W −40°C to +85°C −55°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 260°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 16 ADP1864 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COMP 1 6 PGATE ADP1864 TOP VIEW 5 (Not to Scale) FB 3 4 IN CS 05562-002 2 GND Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic COMP 2 GND 3 FB 4 CS 5 IN 6 PGATE Description Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between COMP and GND to further reduce switching jitter. The value of this is typically one tenth of the main compensation capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET. Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small analog GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to the GND pin. See the Layout Considerations section for more information. Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin. Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal used to terminate the PWM on-time. Place a current sense resistor between IN and CS to set the current limit. The current limit threshold is typically 125 mV. Power Input. IN is the ADP1864 power supply and the positive input of the current sense amplifier. Connect IN to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor, as close as possible to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the IN pin. Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the external MOSFET. Rev. 0 | Page 5 of 16 ADP1864 TYPICAL PERFORMANCE CHARACTERISTICS 0.81 0.8 VIN = 5V 0.805 COMP RISING 0.6 COMP (V) 0.5 0.80 0.4 COMP FALLING 0.3 0.795 0.1 –20 0 20 40 60 80 100 0 –40 120 05562-006 0.79 –40 0.2 05562-003 REFERENCE VOLTAGE (X) 0.7 –20 0 20 TEMPERATURE (°C) 40 60 80 100 120 TEMPERATURE (°C) Figure 4. Reference Voltage vs. Temperature Figure 7. COMP Shutdown Threshold vs. Temperature 2.52 600 VIN = 5V 2.50 2.48 580 VOUT (V) 2.46 570 2.44 560 05562-004 550 –40 2.42 –20 0 20 40 60 80 100 05562-007 FREQUENCY (kHz) 590 2.40 0 120 0.5 1.0 1.5 2.0 2.5 3.5 3.0 LOAD (A) TEMPERATURE (°C) Figure 5. Normalized Oscillator Frequency vs. Temperature Figure 8. Typical Load Regulation (VIN = 5 V; See Figure 1) 2.52 3.1 3.05 2.515 3.0 UVLO RISE VOUT (V) 2.9 UVLO FALL 2.85 2.505 2.8 05562-005 2.75 2.7 –40 2.51 –20 0 20 40 60 80 100 05562-008 VIN (V) 2.95 2.50 3 120 5 7 9 11 13 VIN (V) TEMPERATURE (°C) Figure 9. Typical Line Regulation vs. VIN (ILOAD = 1 A; See Figure 19) Figure 6. UVLO Voltage vs. Temperature (VIN Rising and VIN Falling) Rev. 0 | Page 6 of 16 ADP1864 12 650 TEMPERATURE = 25°C 640 630 11 620 610 FREQUENCY (kHz) 10 VIN = 16V uA 9 8 VIN = 5V 7 600 590 580 570 560 550 540 530 5 –40 –20 0 20 40 60 80 100 510 500 120 3 TEMPERATURE (°C) 7V 270 5V 4V 230 3.1V 210 190 –40 05562-010 QUIESCENT (uA) 12V 250 –20 0 20 40 7 9 11 Figure 12. Oscillator Frequency vs. VIN 16V 290 5 VIN (V) Figure 10. ISD vs. VIN 310 05562-011 VIN = 3.15V VIN = 4V 520 05562-009 6 60 80 100 120 TEMPERATURE (°C) Figure 11. IQ vs. VIN Rev. 0 | Page 7 of 16 13 ADP1864 THEORY OF OPERATION The ADP1864 is a constant frequency (580 kHz), current-mode buck controller. PGATE drives the gate of the external P-channel FET. The duty cycle of the external FET dictates the output voltage and the current supplied to the load. The voltage at the COMP node is the output of the internal error amplifier. The negative input of the error amplifier is the output voltage scaled by an external resistive divider, while the positive input to the error amplifier is driven by a 0.8 V band gap reference. An increase in the load current causes a small drop in the feedback voltage, in turn causing an increase in the COMP voltage and therefore the duty cycle. The resulting increase in the on-time of the FET provides the additional current required by the load. The peak inductor current is measured across the external sense resistor, while the system output voltage is fed back through an external resistor divider to the FB pin. At the start of every oscillator cycle, PGATE turns on the external FET, causing the inductor current, and therefore the current sense amplifier voltage, to increase. The inductor current increases until the current amplifier voltage equals the voltage at the COMP pin. This resets the internal flip-flop, causing PGATE to go high and turning off the external FET. The inductor current decreases until the beginning of the next oscillator period. LOOP START-UP Pulling the COMP pin to GND disables the ADP1864. When the COMP pin is released from GND, an internal 0.6 μA current source charges the external compensation capacitor on the COMP node. Once the COMP voltage has charged to 0.67 V, the internal control blocks are enabled and COMP is pulled up to its minimum normal operating voltage (0.9 V). As the voltage at COMP continues to increase, the on-time of the external FET increases to supply the required inductor current. The loop stabilizes completely once COMP voltage is sufficiently high to support the load current. The regulation voltage at FB is 0.8 V. VIN = 3.15V TO 14V IN 5 4 CS 15mV VREF 0.8V VREF RSI R Q S SLOPE COMP UVLO OSC FREQUENCY FOLDBACK GND 2 VIN ICMP S UVLO, SWITCHING LOGIC AND BLANKING CIRCUIT 6 PGATE D 2.5V 2A OVP 0.35V VREF + 80mV SHORT-CIRCUIT DETECT VIN G EAMP 0.6μA VREF 0.8V VFB 3 VIN 0.3V 0.3V SHDN CMP SHDN COMP 1 0.8V Figure 13. Functional Block Diagram Rev. 0 | Page 8 of 16 05562-013 ADP1864 ADP1864 SHORT-CIRCUIT PROTECTION OVERVOLTAGE LOCKOUT PROTECTION (OVP) If there is a short across the output load, the voltage at the feedback pin (FB) drops rapidly. When the FB voltage drops below 0.35 V, the ADP1864 reduces the oscillator frequency to 190 kHz. The increase in the oscillator period allows the inductor additional time to discharge, preventing the output current from running away. Once the output short is removed and the feedback voltage increases above the 0.35 V threshold, the oscillator frequency returns to 580 kHz. The ADP1864 provides an overvoltage protection feature to protect the system against output short circuits to a higher voltage supply. If the feedback voltage increases to 0.885 V, PGATE is held high, turning the external FET off. The FET continues to be held high until the voltage at FB decreases to 0.84 V, at which time the ADP1864 resumes normal operation. UNDERVOLTAGE LOCKOUT (UVLO) To prevent erratic operation when the input voltage drops below the minimum acceptable voltage, the ADP1864 has an undervoltage lockout (UVLO) feature. If the input voltage drops below 2.90 V, PGATE is pulled high. The ADP1864 will continue to draw its typical quiescent current. Current consumption continues to drop toward the shutdown current as input voltage is reduced. The ADP1864 is re-enabled and begins switching once the IN voltage is increased above the UVLO rising threshold (3.0 V). SOFT START The ADP1864 includes a soft start feature that limits the rate of increase in inductor current once the part is enabled. Soft start is activated when the input voltage is increased above the UVLO threshold or COMP is released from GND. Soft start limits the inrush current at the input and also limits the output voltage overshoot. The soft start control slope is set internally. Rev. 0 | Page 9 of 16 ADP1864 APPLICATION INFORMATION DUTY CYCLE 1.05 VOUT + VD VIN + VD 0.85 0.75 0.65 0.55 where VD is the diode forward drop. A typical Schottky diode has a forward voltage drop of 0.5 V. 0.45 RIPPLE CURRENT 0.35 05562-016 DUTY CYCLE (DC ) = 0.95 SLOPE FACTOR (SF) To determine the worst case inductor ripple current, output voltage ripple, and slope compensation factor, determine the system maximum and minimum duty cycle. The duty cycle is calculated by the equation 0 Choose the peak-to-peak inductor ripple current between 20% and 40% of the maximum load current at the system’s highest input voltage. A good starting point for a design is to pick the peak-to-peak ripple current at 30% of the load current. ΔI(PEAK) = 0.3 × ILOAD(MAX) SENSE RESISTOR Choose the sense resistor value to provide the desired current limit. The internal current comparator measures the peak current (sum of load current and positive inductor ripple current) and compares it against the current limit threshold. The current sense resistor value is calculated by the equation 0.1 where PCSV is the peak current sense voltage, typically 0.125 V. To ensure the design provides the required output load current over all system conditions, consider the variation in PCSV over temperature (see the Specifications section) as well as increases in ripple current due to inductor tolerance. If the system is being operated with >40% duty cycle, incorporate the slope compensation factor into the calculation. where SF is the slope factor correction ratio, taken from Figure 14, at the system maximum duty cycle (minimum input voltage). 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Figure 14. Slope Factor (SF) vs. Duty Ratio INDUCTOR VALUE The inductor value choice is important because it dictates the inductor ripple and, therefore, the voltage ripple at the output. When operating the part at greater than 40% duty cycle, keep the inductor value low enough for the slope compensation to remain effective. The inductor ripple current is inversely related to the inductor value. (VIN − VOUT ) × ⎛⎜ VOUT + VD ⎞⎟ L× f ⎜ V +V ⎟ D ⎠ ⎝ IN Smaller inductor values are typically smaller in size and usually less expensive, but increase the ripple current and the output voltage ripple. Too large an inductor value results in added expense and may impede effective load transient responses at >40% duty cycle because it reduces the effect of slope compensation. Start with the highest input voltage, and assume ripple current is 30% of the maximum load current: L= SF × PCSV RSENSE ( MIN ) = ΔI I LOAD ( MAX ) + ( PEAK ) 2 0.3 DUTY CYCLE ΔI ( PEAK ) = PCSV RSENSE ( MIN ) = ΔI I LOAD ( MAX ) + ( PEAK ) 2 0.2 (VIN − VOUT ) ⎛V + VD × ⎜ OUT ⎜ 0.3 × I LOAD ( MAX ) × f ⎝ VIN + VD ⎞ ⎟ ⎟ ⎠ From this starting point, modify the inductance to obtain the right balance of size, cost, and output voltage ripple while maintaining the inductor ripple current between 20% and 40% of the maximum load current. Rev. 0 | Page 10 of 16 ADP1864 MOSFET INPUT CAPACITOR Choose the external P-channel MOSFET based on the following: Vt (threshold voltage), maximum voltage and current ratings, RDS(ON), and gate charge. The input capacitor provides a low impedance path for the pulsed current drawn by the external P-channel FET. Choose an input capacitor whose impedance at the switching frequency is lower than the impedance of the voltage source (VIN). The preferred input capacitor is a 10μF ceramic capacitor due to its low ESR and low impedance. The minimum operating voltage of the ADP1864 is 3.15 V. Choose a MOSFET with a Vt that is at least 1 V lower than the minimum input supply voltage used in the application. Ensure that the maximum ratings for MOSFET VGS and VDS are a few volts greater than the maximum input voltage used with the ADP1864. Where space is limited, multiple capacitors can be placed in parallel to meet the rms current requirement. Place the input capacitor as close as possible to the IN pin of the ADP1864. Estimate the rms current in the MOSFET under continuous conduction mode by ⎛ (V + VD ) ⎞ ⎟ ×I I MOSFET ( RMS ) = ⎜ OUT ⎜ (V + V ) ⎟ LOAD D ⎠ ⎝ IN OUTPUT CAPACITOR The ESR and capacitance value of the output capacitor determine the amount of output voltage ripple: Derate the MOSFET current by at least 20% to account for inductor ripple and changes in the diode voltage. The MOSFET power dissipation is the sum of the conducted and the switching losses: ( For all types of capacitors, make sure the ripple current rating of the capacitor is greater than half of the maximum output load current. ) PDMOSFET (COND ) = I MOSFET ( RMS ) × (1 +T )× RDS(ON ) ⎛ ⎞ 1 ΔV ≅ ΔI × ⎜ + ESRCOUT ⎟ ⎜8× f ×C ⎟ OUT ⎝ ⎠ where f = oscillator frequency (typically 580 kHz). 2 where T is 0.005/˚C × (MOSFET Junction Temperature − 25˚C). Because the output capacitance is typically >40 μF, the ESR dominates the voltage ripple. Ensure the output capacitor ripple rating is greater than the maximum inductor ripple. Ensure the maximum power dissipation calculated is significantly less than the maximum rating of the MOSFET. I rms ≅ DIODE The diode carries the inductor current during the off time of the external FET. The average current of the diode is, therefore, dependent on the duty cycle of the controller as well as the output load current. ⎛ (V + VD ) × (VIN − VOUT ) ⎞ 1 ⎟ × ⎜⎜ OUT ⎟ L × f × VIN 2× 3 ⎝ ⎠ POSCAP capacitors from Sanyo offer a good size, ESR, ripple, and current capability trade-off. ⎛ (V + VD ) ⎞⎟ × I I DIODE ( AV ) = ⎜1 − OUT ⎜ (VIN + VD ) ⎟⎠ LOAD ⎝ where VD is the diode forward drop. A typical Schottky diode has a 0.5 V forward drop. A Schottky diode is recommended for best efficiency because it has a low forward drop and faster switching speed than junction diodes. If a junction diode is used it must be an ultrafast recovery diode. The low forward drop reduces the power losses during the FET off time, and fast switching speed reduces the switching losses during PFET transitions. Rev. 0 | Page 11 of 16 ADP1864 FEEDBACK RESISTORS The feedback resistor ratio sets the output voltage of the system. 0.8 V = VOUT × ADP1864 R1 = R2 × VOUT R1 FB 05562-015 3 R2 Figure 15. Two Feedback Resistors Used to Set Output Voltage (V R2 R1 + R2 OUT − 0.8 ) 0.8 Choose 80.6 kΩ for R2. Using higher values for R2 results in reduced output voltage accuracy while lower values cause increased voltage divider current, increasing quiescent current consumption. Rev. 0 | Page 12 of 16 ADP1864 LAYOUT CONSIDERATIONS ADP1864 Layout is important with all switching regulators, but is particularly important for high switching frequencies. Ensure all high current paths are as wide as possible to minimize track inductance, which causes spiking and electromagnetic interference (EMI). These paths are shown in bold in Figure 16. Place the current sense resistor and the input capacitor(s) as close to the IN pin as possible. COMP 2 GND 3 FB PGATE 6 VIN IN 5 CIN 05562-019 PGND CS 4 VOUT Keep the PGND connections for the diode, input capacitor(s), and output capacitor(s) as close together as possible on a wide PGND plane. Connect the PGND and GND planes at a single point with a narrow trace close to the ADP1864 GND connection. Ensure the feedback resistors are placed as close as possible to the FB pin to prevent stray pickup. To prevent extra noise pickup on the FB line, do not allow the feedback trace from the output voltage to FB to pass right beside the drain of the external PFET. Add an extra copper plane at the connection of the FET drain and the cathode of the diode to help dissipate the heat generated by losses in those components. 1 Figure 16. Application Circuit Showing High Current Paths (in Bold) VIN RCOMP ADP1864 CCOMP RS CIN RFB2 PGND PGND RFB1 CO D1 MOSFET VOUT 05562-017 L1 Figure 17. Example of Layout for an ADP1864 3A Application Rev. 0 | Page 13 of 16 ADP1864 EXAMPLE APPLICATIONS CIRCUITS ADP1864 COMP IN 5 68pF 80.6kΩ 2 GND 3 FB 10μF 470pF 3.3μH 3.3V, 2.0A 47μF 05562-020 255kΩ RSENSE LRC-LR1206_01_R030-F MOSFET FAIRCHILD SEMI FDC638P INDUCTOR TOKO FDV0630-3R3M DIODE SYNSEMI SK22 CIN LMK325BJ106KN COUT SANYO POSCAP 6TPB47M COMP IN 5 0.03Ω 68pF CS 4 PGATE 6 VIN = 3.15V to 14V 1 0.03Ω 2 GND 3 FB CS 4 5μH 80.6kΩ PGATE 6 Figure 19. Rev. 0 | Page 14 of 16 2.5V, 2.0A 47μF 174kΩ RSENSE LRC-LR1206_01_R030-F MOSFET FAIRCHILD SEMI FDC658P INDUCTOR SUMIDA CDRH6D38-5R0 DIODE VISHAY SSB43L CIN LMK325BJ106KN COUT SANYO POSCAP 6TPB47M Figure 18. 10μF 05562-021 1 470pF ADP1864 25kΩ VIN = 4.5V to 5.5V 25kΩ ADP1864 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 1 2 3 2.80 BSC 1.60 BSC PIN 1 INDICATOR 0.95 BSC 1.90 BSC *0.90 0.87 0.84 *1.00 MAX 0.50 0.30 0.10 MAX 0.20 0.08 SEATING PLANE 8° 4° 0° 0.60 0.45 0.30 *COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 20. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters ORDERING GUIDE Model ADP1864AUJZ-R7 1 ADP1864-EVAL 2 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 6-Lead Thin Small Outline Transistor Package (TSOT) Evaluation Board Z = Pb-free part. VOUT 2.5 V (variable), ILOAD = 0 A to 3 A, VIN = 3.15 V to 14 V. Rev. 0 | Page 15 of 16 Package Option UJ-6 Branding P0N ADP1864 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05562–0–10/05(0) Rev. 0 | Page 16 of 16