AD ADP123

5.5 V Input, 300 mA, Low Quiescent
Current, CMOS Linear Regulator
ADP122/ADP123
FEATURES
APPLICATIONS
TYPICAL APPLICATION CIRCUIT
VIN = 2.3V TO 5.5V
VOUT = 1.8V
1
CIN
1µF
VOUT
VIN
5
COUT
1µF
ON
2
GND
3
EN
NC
08399-001
ADP122
4
OFF
Figure 1. ADP122 with Fixed Output Voltage
VIN = 2.3V TO 5.5V
VOUT = 0.5V(1 + R1/R2)
1
CIN
1µF
VIN
VOUT
5
COUT
1µF
ADP123
ON
2
GND
3
EN
R1
ADJ
4
OFF
R2
08399-002
Input voltage supply range: 2.3 V to 5.5 V
300 mA maximum output current
Fixed and adjustable output voltage versions
Very low dropout voltage: 85 mV at 300 mA load
Low quiescent current: 45 μA at no load
Low shutdown current: <1 μA
Initial accuracy: ±1% accuracy
Up to 31 fixed-output voltage options available from
1.75 V to 3.3 V
Adjustable-output voltage range
0.8 V to 5.0 V (ADP123)
Excellent PSRR performance: 60 dB at 100 kHz
Excellent load/line transient response
Optimized for small 1.0 μF ceramic capacitors
Current limit and thermal overload protection
Logic controlled enable
Compact, 5-lead TSOT package
Figure 2. ADP 123 with Adjustable Output Voltage
Digital camera and audio devices
Portable and battery-powered equipment
Automatic meter reading (AMR) meters
GPS and location management units
Medical instrumentation
Point-of-sale equipment
GENERAL DESCRIPTION
The ADP122/ADP123 are low quiescent current, low dropout
linear regulators. They are designed to operate from an input
voltage between 2.3 V and 5.5 V and to provide up to 300 mA of
output current. The low 85 mV dropout voltage at a 300 mA load
improves efficiency and allows operation over a wide input
voltage range.
The low 170 μA of quiescent current at full load makes the ADP122
ideal for battery-operated portable equipment.
The ADP122 is capable of 31 fixed output voltages from 1.75 V
to 3.3 V. The ADP123 is the adjustable version of the device and
allows the output voltage to be set between 0.8 V and 5.0 V by
an external voltage divider.
The ADP122/ADP123 are specifically designed for stable operation
with tiny 1 μF ceramic input and output capacitors to meet the
requirements of high performance, space constrained applications.
The ADP122/ADP123 have an internal soft start that gives a
constant start-up time of 350 μs. Short-circuit protection and
thermal overload protection circuits prevent damage in adverse
conditions. The ADP122/ADP123 are available in a tiny, 5-lead
TSOT package for the smallest footprint solution to meet a
variety of portable applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADP122/ADP123
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 Typical Application Circuit ............................................................. 1 Applications Information .............................................................. 12 General Description ......................................................................... 1 Capacitor Selection .................................................................... 12 Revision History ............................................................................... 2 Undervoltage Lockout ............................................................... 13 Specifications..................................................................................... 3 Enable Feature ............................................................................ 13 Recommended Specifications ..................................................... 4 Current Limit and Thermal Overload Protection ................. 14 Absolute Maximum Ratings............................................................ 5 Thermal Considerations............................................................ 14 Thermal Data ................................................................................ 5 Junction Temperature Calculations ......................................... 15 Thermal Resistance ...................................................................... 5 Printed Circuit Board Layout Considerations ....................... 16 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 18 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 18 REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP122/ADP123
SPECIFICATIONS
Unless otherwise noted, VIN = (VOUT + 0.3 V) or 2.3 V, whichever is greater; ADJ connected to VOUT; IOUT = 10 mA; CIN = 1.0 μF;
COUT = 1.0 μF; TA = 25°C.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT 1
Symbol
VIN
IGND
SHUTDOWN CURRENT
ISD
OUTPUT VOLTAGE ACCURACY 2
Fixed Output
VOUT
Adjustable Output
LINE REGULATION
LOAD REGULATION 3
∆VOUT/∆VIN
∆VOUT/∆IOUT
ADJ INPUT BIAS CURRENT
DROPOUT VOLTAGE 4
ADJI-BIAS
VDROPOUT
Test Conditions
IOUT = 0 μA
IOUT = 0 μA, TJ = −40°C to +125°C
IOUT = 1 mA
IOUT = 1 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
IOUT = 300 mA
IOUT = 300 mA, TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
IOUT = 10 mA
100 μA < IOUT < 300 mA, VIN = (VOUT + 0.5 V) to 5.5 V,
TJ = −40°C to +125°C
IOUT = 10 mA
100 μA < IOUT < 300 mA, VIN = 2.3 V to 5.5 V,
TJ = −40°C to +125°C
VIN = VIN = 2.3 V to 5.5 V, TJ = −40°C to +125°C
IOUT = 1 mA to 300 mA
IOUT = 1 mA to 300 mA , TJ = −40°C to +125°C
2.3 V ≤ VIN ≤ 5.5 V, ADJ connected to VOUT
TSSD
TSSD-HYS
TJ rising
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
VIH
VIL
VI-LEAKAGE
2.3 V ≤ VIN ≤ 5.5 V
2.3 V ≤ VIN ≤ 5.5 V
EN = VIN or GND
EN = VIN or GND, TJ = −40°C to +125°C
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
UVLO
UVLORISE
UVLOFALL
UVLOHYS
Typ
Max
5.5
1
Unit
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
+1
+1.5
%
%
0.505
0.5075
V
V
+0.05
%/V
%/mA
%/mA
nA
45
105
60
120
130
190
170
240
0.1
−1
−2
0.495
0.490
0.500
0.500
−0.05
0.0005
0.001
15
IOUT = 10 mA, VOUT > 2.3 V
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA, VOUT > 2.3 V
IOUT = 150 mA, TJ = −40°C to +125°C
IOUT = 300 mA, VOUT > 2.3V
IOUT = 300 mA, TJ = −40°C to +125°C
VOUT = 3.0 V
START-UP TIME 5
CURRENT LIMIT THRESHOLD 6
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
tSTART-UP
ILIMIT
Min
2.3
3
5
45
75
85
150
350
350
500
650
°C
°C
150
15
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TA = 25°C
Rev. 0 | Page 3 of 20
1.2
0.4
0.1
1
2.1
1.5
125
mV
mV
mV
mV
mV
mV
μs
mA
V
V
μA
μA
V
V
mV
ADP122/ADP123
Parameter
OUTPUT NOISE
Symbol
OUTNOISE
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 0.5 V)
PSRR
Test Conditions
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.2 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 4.2 V
10 kHz, VOUT = 3.3 V
10 kHz, VOUT = 2.5 V
10 kHz, VOUT = 1.8 V
100 kHz, VOUT = 3.3 V
100 kHz, VOUT = 2.5 V
100 kHz, VOUT = 1.8 V
Min
Typ
25
35
45
55
65
60
60
60
60
60
60
Max
Unit
μV rms
μV rms
μV rms
μV rms
dB
dB
dB
dB
dB
dB
1
The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP123) should be subtracted from the ground current measured.
Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of
the resistors used.
3
Based on an endpoint calculation using 1 mA and 300 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages
greater than 2.3 V.
5
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
6
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3V, or 2.97 V.
2
RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Minimum Input and Output
Capacitance 1
Capacitor ESR
1
Symbol
CAPMIN
Test Conditions
TA = −40°C to +125°C
Min
0.70
RESR
TA = −40°C to +125°C
0.001
Typ
Max
Unit
μF
1
Ω
The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 20
ADP122/ADP123
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
ADJ to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to +4 V
−0.3 V to +6.5 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP122/ADP123 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ will remain within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
application and board layout. In applications in which high maximum power dissipation exists, close attention to thermal board
design is required. The value of θJA may vary, depending on PCB
material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board.
Refer to JESD51-7 for detailed information on the board
construction
ΨJB is the junction-to-board thermal characterization parameter
and is measured in °C/W. The ΨJB of the package is based on
modeling and calculation using a 4-layer board. The Guidelines for
Reporting and Using Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package—factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on the
Rev. 0 | Page 5 of 20
θJA
170
ΨJB
43
Unit
°C/W
ADP122/ADP123
GND 2
ADP122
5
VOUT
VIN 1
TOP VIEW
(Not to Scale)
EN 3
GND 2
4
NC = NO CONNECT
NC
EN 3
08399-004
VIN 1
ADP123
5
VOUT
4
ADJ
TOP VIEW
(Not to Scale)
08399-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADP123 Adjustable Output Pin Configuration
Figure 3. ADP122 Fixed Output Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
ADP122 ADP123
1
1
2
2
3
3
Mnemonic
VIN
GND
EN
N/A
4
ADJ
4
5
N/A
5
NC
VOUT
Description
Regulator Input Supply. Bypass VIN to GND with a capacitor of at least 1 μF.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN.
Output Voltage Adjust Input. Connect the midpoint of an external divider from VOUT to GND to this
pin to set the output voltage.
Not Connected Internally.
Regulated Output Voltage. Bypass VOUT to GND with a capacitor of at least 1 μF.
Rev. 0 | Page 6 of 20
ADP122/ADP123
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, VOUT = 3.3 V, IOUT = 10 mA, CIN = 1.0 μF, COUT = 1.0 μF, TA = 25°C, unless otherwise noted.
250
3.300
3.295
200
GROUND CURRENT (µA)
3.290
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
3.270
IOUT = 200mA
IOUT = 100mA
100
IOUT = 10mA
50
IOUT = 100µA
3.265
–40
–5
25
85
JUNCTION TEMPERATURE (°C)
0
08399-005
3.260
125
–40
Figure 5. Output Voltage vs. Junction Temperature
180
3.2935
160
GROUND CURRENT (µA)
200
3.2940
VOUT (V)
3.2930
3.2925
3.2920
3.2915
3.2910
120
100
80
60
40
3.2900
20
100
0
08399-006
10
1000
IOUT (mA)
0.1
1
10
100
1000
IOUT (mA)
Figure 9. Ground Current vs. Load Current
Figure 6. Output Voltage vs. Load Current
200
3.296
IOUT = 300mA
180
3.294
GROUND CURRENT (µA)
160
3.292
3.290
3.288
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
3.286
3.284
3.6
3.8
4.0
4.2
140
IOUT = 200mA
120
IOUT = 100mA
100
IOUT = 10mA
80
IOUT = 1mA
60
IOUT = 100µA
40
20
4.4
4.6
VIN (V)
4.8
5.0
5.2
5.4
08399-007
VOUT (V)
125
140
3.2905
1
–5
25
85
JUNCTION TEMPERATURE (°C)
Figure 8. Ground Current vs. Junction Temperature
3.2945
3.2895
0.1
IOUT = 1mA
08399-008
3.275
150
08399-009
3.280
IOUT = 300mA
Figure 7. Output Voltage vs. Input Voltage
0
3.6
3.8
4.0
4.2
4.4
4.6
VIN (V)
4.8
5.0
5.2
Figure 10. Ground Current vs. Input Voltage
Rev. 0 | Page 7 of 20
5.4
08399-010
VOUT (V)
3.285
0.50
3.35
0.45
3.30
0.40
0.35
0.30
0.25
IOUT
IOUT
IOUT
IOUT
3.25
VIN = 3.6V
VIN = 3.8V
VIN = 4.2V
VIN = 4.4V
VIN = 5.0V
VIN = 5.2V
VIN = 5.4V
VIN = 5.5V
VOUT (V)
3.20
3.15
3.10
0.20
3.05
0.15
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3.00
3.05
08399-011
0.10
–50
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
3.10
3.15
3.20
3.25
VIN (V)
3.30
3.35
3.40
Figure 14. Output Voltage vs. Input Voltage (in Dropout)
70
–10
–20
60
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
–30
50
–40
PSRR (dB)
DROPOUT (mV)
= 10mA
= 100mA
= 150mA
= 300mA
08399-013
SHUTDOWN CURRENT (µA)
ADP122/ADP123
40
30
–50
–60
–70
20
–80
1
10
100
1000
IOUT (mA)
–100
08399-012
0
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.8 V, VIN = 3.3 V
Figure 12. Dropout Voltage vs. Load Current
–10
400
–20
350
–30
300
–40
PSRR (dB)
450
250
200
150
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
–50
–60
–70
IOUT = 10mA
IOUT = 100mA
IOUT = 150mA
IOUT = 300mA
50
0
3.05
3.10
3.15
3.20
–80
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT 1µF
–90
3.25
VIN (V)
3.30
3.35
3.40
3.45
Figure 13. Ground Current vs. Input Voltage (in Dropout)
08399-016
100
–100
08399-014
IGND (µA)
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT 1µF
–90
08399-015
10
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 16. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V
Rev. 0 | Page 8 of 20
ADP122/ADP123
–10
5
–20
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
PSRR (dB)
–40
–50
VOUT = 4.2V
4
VOUT = 3.3V
NOISE (µv/√Hz)
–30
–60
3
2
–70
–80
1
–100
10
100
1k
10k
100k
1M
VOUT = 2.8V
08399-020
08399-017
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT 1µF
–90
0
10
10M
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
100k
Figure 20. Output Noise Spectrum
Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 4.2 V, VIN = 4.7 V
70
–10
VOUT = 2.8V,
VOUT = 3.3V,
VOUT = 4.2V,
VOUT = 2.8V,
VOUT = 3.3V,
VOUT = 4.2V,
–30
–40
–50
65
IOUT = 1mA
IOUT = 1mA
IOUT = 1mA
IOUT = 300mA
IOUT = 300mA
IOUT = 300mA
VOUT = 4.2V
60
RMS NOISE (µV)
–20
PSRR (dB)
10k
–60
VOUT = 3.3V
55
50
45
VOUT = 2.8V
–70
40
–100
10
100
1k
35
10k
100k
1M
30
0.001
10M
08399-021
–90
08399-018
VIN = VOUT + 0.5V
VRIPPLE = 50mV
CIN = COUT 1µF
–80
0.01
0.1
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency, Various Output
Voltages and Load Currents
1
IOUT (mA)
10
100
1000
Figure 21 Output Noise vs. Load Current and Output Voltage
–10
VIN = 3.1V,
VIN = 3.3V,
VIN = 3.8V,
VIN = 4.8V,
VIN = 3.1V,
VIN = 3.3V,
VIN = 3.8V,
VIN = 4.8V,
–20
–30
PSRR (dB)
–40
IOUT = 1mA
IOUT = 1mA
IOUT = 1mA
IOUT = 1mA
IOUT = 300mA
IOUT = 300mA
IOUT = 300mA
IOUT = 300mA
IOUT
1mA TO 300mA LOAD STEP
1
–50
–60
VOUT
2
VRIPPLE = 50mV
CIN = COUT 1µF
VIN = 3.7V
VOUT = 3.3V
08399-019
–80
–90
–100
10
100
1k
10k
100k
1M
CH1 200mA Ω
10M
FREQUENCY (Hz)
Figure 19. Power Supply Rejection Ratio vs. Headroom Voltage (VIN − VOUT)
Rev. 0 | Page 9 of 20
B
W CH2
50.0mV
B
W
M 40.0µs A CH1
T
10.20%
196mA
Figure 22. Load Transient Response, COUT = 1 μF
08399-022
–70
ADP122/ADP123
IOUT
VIN
1mA TO 300mA LOAD STEP
4V TO 4.5V VOLTAGE STEP
1
2
VOUT
VOUT
2
CH1 200mA Ω
B
W
CH2 20.0mV
B
W
M 40.0µs A CH1
T
10.40%
08399-025
VIN = 3.7V
VOUT = 3.3V
08399-023
1
CH1 1.00V BW CH2 2.00mV
196mA
Figure 23. Load Transient Response, COUT = 4.7 μF
VIN
2
VOUT
08399-024
1
B
W
M 10.0µs A CH3
T
10.00%
M 10.0µs A CH3
T
9.600%
2.04V
Figure 25. Line Transient Response, Load Current = 300 mA
4V TO 4.5V VOLTAGE STEP
CH1 1.00V Ω BW CH2 2.00mV
B
W
2.04V
Figure 24. Line Transient Response, Load Current = 1 mA
Rev. 0 | Page 10 of 20
ADP122/ADP123
THEORY OF OPERATION
The ADP122/ADP123 are low quiescent current, low-dropout
linear regulators that operate from 2.3 V to 5.5 V and can provide
up to 300 mA of output current. Drawing a low 170 μA of quiescent current (typical) at full load makes the ADP122/ADP123
ideal for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.
Note that in shutdown, the output is turned off and the divider
current is 0.
The ADP122/ADP123 use the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is high,
VOUT turns on; when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.
Optimized for use with small 1 μF ceramic capacitors, the
ADP122/ADP123 provide excellent transient performance.
ADP122
VIN
The adjustable ADP123 has an output voltage range of 0.8 V to
5.0 V. The output voltage is set by the ratio of two external resistors,
as shown in Figure 2. The device servos the output to maintain
the voltage at the ADJ pin at 0.5 V referenced to ground. The
current in R1 is then equal to 0.5 V/R2 and the current in R1 is
the current in R2 plus the ADJ pin bias current. The ADJ pin
bias current, 15 nA at 25°C, flows through R1 into the ADJ pin.
GND
EN
SHORT CIRCUIT,
UVLO AND
THERMAL
PROTECT
SHUTDOWN
0.5V REFERENCE
R1
R2
08399-121
Internally, the ADP122/ADP123 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.
VOUT
NOTES
1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON
THE ADP122 ONLY.
Figure 26. ADP122 Internal Block Diagram (Fixed Output)
ADP123
VIN
GND
The output voltage can be calculated using the equation:
VOUT
SHORT CIRCUIT,
UVLO AND
THERMAL
PROTECT
VOUT = 0.5 V(1 + R1/R2) + (ADJI-BIAS)(R1)
Rev. 0 | Page 11 of 20
ADJ
EN
SHUTDOWN
0.5V REFERENCE
08399-122
The value of R1 should be less than 200 kΩ to minimize errors
in the output voltage caused by the ADJ pin bias current. For
example, when R1 and R2 each equal 200 kΩ, the output voltage
is 1.0 V. The output voltage error introduced by the ADJ pin
bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias
current of 15 nA at 25°C.
Figure 27. ADP123 Internal Block Diagram (Adjustable Output)
ADP122/ADP123
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input and Output Capacitor Properties
Output Capacitor
Any good quality ceramic capacitors can be used with the ADP122/
ADP123, as long as the capacitor meets the minimum capacitance
and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have an
adequate dielectric to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. Using an
X5R or X7R dielectric with a voltage rating of 6.3 V or 10 V is
recommended. However, using Y5V and Z5U dielectrics is not
recommended for any LDO, due to their poor temperature and
dc bias characteristics.
The ADP122/ADP123 are designed for operation with small,
space-saving ceramic capacitors, but these devices can function
with most commonly used capacitors as long as care is taken to
ensure an appropriate effective series resistance (ESR) value. The
ESR of the output capacitor affects the stability of the LDO control
loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω or
less is recommended to ensure stability of the ADP122/ADP123.
The transient response to changes in load current is also affected by
the output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP122/ADP123 to
dynamic changes in load current. Figure 28 and Figure 29 show
the transient responses for output capacitance values of 1 μF and
4.7 μF, respectively.
IOUT
1mA TO 300mA LOAD STEP
1
Figure 30 depicts the capacitance vs. capacitor voltage bias characteristics of a 0603, 1 μF, 6.3 V X5R capacitor. The voltage stability of
a capacitor is strongly influenced by the capacitor size and the
voltage rating. In general, a capacitor in a larger package or of a
higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the −40°C to
+85°C temperature range and is not a function of package or
voltage rating.
1.10
1.05
2
VOUT
CH1 200mA
Ω BW
CH2 50.0mV
B
W
M 400ns A CH1
T
14.80%
08399-026
VIN = 3.7V
VOUT = 3.3V
CAPACITANCE (µF)
1.00
196mA
Figure 28. Output Transient Response, COUT = 1 μF
0.95
0.90
0.85
0.80
IOUT
08399-030
0.75
0.70
0
1mA TO 300mA LOAD STEP
1
2
3
4
5
6
7
BIAS VOLTAGE (V)
1
Figure 30. Capacitance vs. Capacitor Voltage Bias Characteristics
Equation 1 can be used to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
2
CEFF = C × (1 − TEMPCO) × (1 − TOL)
VOUT
CH1 200mA Ω
B
W
CH2 20.0mV
M 400ns
A CH1
T
15.00%
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
08399-027
VIN = 3.7V
VOUT = 3.3V
(1)
196mA
Figure 29. Output Transient Response, COUT = 4.7 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the circuit
sensitivity to the printed circuit board (PCB) layout, especially
when a long input trace or high source impedance is encountered.
If greater than 1 μF of output capacitance is required, the input
capacitor should be increased to match it.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C is 0.96 μF at 4.2 V from the graph in Figure 30.
Substituting these values in Equation 1 yields
Rev. 0 | Page 12 of 20
CEFF = 0.96 μF × (1 − 0.15) × (1 − 0.1) = 0.734 μF
ADP122/ADP123
1.1
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.
ENABLE THRESHOLDS (V)
1.0
To guarantee the performance of the ADP122/ADP123, it is
imperative that the effects of dc bias, temperature, and tolerances
on the behavior of the capacitors are evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP122/ADP123 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 2 V. This ensures that the
ADP122/ADP123 inputs and the output behave in a predictable
manner during power-up.
RISING
0.9
0.8
FALLING
0.7
0.5
2.2
2.7
3.2
ENABLE FEATURE
The ADP122/ADP123 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 31, when a rising voltage on EN crosses the active threshold,
VOUT turns on. Conversely, when a falling voltage on EN crosses
the inactive threshold, VOUT turns off.
3.5
3.0
4.7
5.2
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
The ADP122/ADP123 utilize an internal soft start to limit the
in-rush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 350 μs from the time the
EN active threshold is crossed to when the output reaches 90%
of its final value. As shown in Figure 33, the start-up time is
dependent on the output voltage setting and increases slightly
as the output voltage increases.
2.5
VOUT
3.7
4.2
VIN(V)
08399-034
0.6
VIN = 5V
VOUT = 4.2V
2.0
VOUT = 3.3V
1.5
VOUT = 2.8V
1.0
08399-230
0.5
0
0.2
0.4
0.6
0.8
VEN
1.0
1.2
1.4
1
2
1.6
08399-033
0
Figure 31. Typical EN Pin Operation
CH1 1.00V
As shown in Figure 31, the EN pin has built-in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.
The active and inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary as the input
voltage changes. Figure 32 shows typical EN active and inactive
thresholds when the VIN voltage varies from 2.3 V to 5.5 V.
Rev. 0 | Page 13 of 20
CH2 1.00V
M200µs
A CH1
T
600.000µs
Figure 33. Typical Start-Up Time
3.08V
ADP122/ADP123
The junction temperature of the ADP122/ADP123 can be
calculated from the following equation:
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP122/ADP123 are protected from damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP122/ADP123 are designed to limit the current
when the output load reaches 500 mA (typical). When the output
load exceeds 500 mA, the output voltage is reduced to maintain
a constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C typical. Under extreme conditions (that is, high ambient temperature and power dissipation),
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing output current to zero. When the
junction temperature cools to less than 135°C, the output is turned
on again and the output current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP122/ADP123 limit the current so that only 500 mA
is conducted into the short. If self-heating causes the junction
temperature to rise above 150°C, thermal shutdown activates,
turning off the output and reducing the output current to zero.
When the junction temperature cools to less than 135°C, the
output turns on and conducts 500 mA into the short, again
causing the junction temperature to rise above 150°C. This
thermal oscillation between 135°C and 150°C results in a current
oscillation between 500 mA and 0 mA that continues as long as
the short remains at the output.
Current and thermal limit protections are intended to protect the
device from damage due to accidental overload conditions. For
reliable operation, the device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.
TJ = TA + (PD × θJA)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
The power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
can be simplified as follows:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 34
through Figure 40 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the junction temperature rise. The maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power dissipation
(PD) using the formula
To guarantee reliable operation, the junction temperature of the
ADP122/ADP123 must not exceed 125°C. To ensure that the
junction temperature is less than this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The value
of θJA is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 6 shows typical θJA values of the
5-lead TSOT package for various PCB copper sizes.
Table 6. Typical θJA Values for Specified PCB Copper Sizes
1
(3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
THERMAL CONSIDERATIONS
Copper Size (mm2)
01
50
100
300
500
(2)
θJA (°C/W)
170
152
146
134
131
Device soldered to narrow traces.
The typical ΨJB value is 42.8°C/W.
Rev. 0 | Page 14 of 20
TJ = TB + (PD × ΨJB)
(5)
ADP122/ADP123
JUNCTION TEMPERATURE CALCULATIONS
140
140
TJ MAX
TJ MAX
120
JUNCTION TEMPERATURE (°C)
ILOAD = 300mA
100
80
ILOAD = 150mA
60
ILOAD = 100mA
40
ILOAD = 25mA
20
ILOAD = 150mA
100
80
ILOAD = 100mA
ILOAD = 25mA
60
40
2.0
2.5
3.0
0
0.5
1.0
3.0
140
TJ MAX
TJ MAX
120
JUNCTION TEMPERATURE (°C)
120
ILOAD = 300mA
100
ILOAD = 150mA
80
60
ILOAD = 100mA
40
ILOAD = 25mA
20
ILOAD = 300mA
ILOAD = 150mA
100
80
ILOAD = 100mA
ILOAD = 25mA
60
40
ILOAD = 1mA
ILOAD = 10mA
20
ILOAD = 10mA
1.0
1.5
2.0
2.5
3.0
VOUT – VIN (V)
0
0.5
08399-129
ILOAD = 1mA
1.0
1.5
2.0
2.5
3.0
VOUT – VIN (V)
Figure 35. Junction Temperature vs. Power Dissipation,
100 mm2 of PCB Copper, TA = 25°C
08399-132
JUNCTION TEMPERATURE (°C)
2.5
Figure 37. Junction Temperature vs. Power Dissipation,
500 mm2 of PCB Copper, TA = 50°C
140
Figure 38. Junction Temperature vs. Power Dissipation,
100 mm2 of PCB Copper, TA = 50°C
140
140
TJ MAX
TJ MAX
120
JUNCTION TEMPERATURE (°C)
120
ILOAD = 300mA
100
80
ILOAD = 150mA
60
ILOAD = 100mA
40
ILOAD = 25mA
20
ILOAD = 300mA
ILOAD = 150mA
100
ILOAD = 100mA
80
ILOAD = 25mA
60
40
ILOAD = 1mA
ILOAD = 10mA
20
ILOAD = 1mA
1.0
1.5
ILOAD = 10mA
2.0
2.5
VOUT – VIN (V)
3.0
08399-130
JUNCTION TEMPERATURE (°C)
2.0
VOUT – VIN (V)
Figure 34. Junction Temperature vs. Power Dissipation,
500 mm2 of PCB Copper, TA = 25°C
0
0.5
1.5
08399-131
1.5
08399-128
1.0
ILOAD = 10mA
VOUT – VIN (V)
0
0.5
ILOAD = 10mA
ILOAD = 1mA
20
ILOAD = 1mA
0
0.5
ILOAD = 300mA
Figure 36. Junction Temperature vs. Power Dissipation,
0 mm2 of PCB Copper, TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
VOUT – VIN (V)
Figure 39. Junction Temperature vs. Power Dissipation,
0 mm2 of PCB Copper, TA = 50°C
Rev. 0 | Page 15 of 20
3.0
08399-133
JUNCTION TEMPERATURE (°C)
120
ADP122/ADP123
140
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP122/ADP123.
However, as shown in Table 6, a point of diminishing returns
eventually is reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
100
80
60
40
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 150mA
ILOAD = 250mA
ILOAD = 300mA
TJ MAX
20
0
0.4
0.8
1.2
1.6
2.0
2.4
VIN – VOUT (V)
2.8
08399-134
JUNCTION TEMPERATURE (°C)
120
The input capacitor should be placed as close as possible to the
VIN and GND pins, and the output capacitor should be placed
as close as possible to the VOUT and GND pins. Use of 0402 or
0603 size capacitors and resistors achieves the smallest possible
footprint solution on boards where the area is limited.
Figure 40. Junction Temperature vs. Power Dissipation,
Board Temperature = 85°C
Rev. 0 | Page 16 of 20
08399-041
ADP122/ADP123
08399-042
Figure 41. Example ADP122 PCB Layout
Figure 42. Example ADP123 PCB Layout
Rev. 0 | Page 17 of 20
ADP122/ADP123
OUTLINE DIMENSIONS
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
0.95 BSC
1.90
BSC
*1.00 MAX
0.10 MAX
0.50
0.30
0.20
0.08
8°
4°
0°
SEATING
PLANE
0.60
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
100708-A
*0.90 MAX
0.70 MIN
Figure 43. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP122AUJZ-2.5-R7 2
ADP122AUJZ-2.7-R72
ADP122AUJZ-2.8-R72
ADP122AUJZ-2.85-R72
ADP122AUJZ-2.9-R72
ADP122AUJZ-3.0-R72
ADP122AUJZ-3.3-R72
ADP123AUJZ-R72
ADP122-3.3-EVALZ2
ADP123-EVALZ2
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output Voltage (V) 1
2.5
2.7
2.8
2.85
2.9
3.0
3.3
0.8 to 5.0 (Adjustable)
3.3
Adjustable
Package Description
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
Evaluation Board
Evaluation Board
1
Package Option
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
Branding
LE6
LE9
LEA
LEC
LED
LEE
LEF
LEG
Up to 31 fixed-output voltage options from 1.75 V to 3.3 V are available. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution
representative.
2
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
ADP122/ADP123
NOTES
Rev. 0 | Page 19 of 20
ADP122/ADP123
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08399-0-10/09(0)
Rev. 0 | Page 20 of 20