Ultralow Noise VGAs with Preamplifier and Programmable RIN AD8331/AD8332 FUNCTIONAL BLOCK DIAGRAM FEATURES LON1 LOP1 25 24 VIP1 VIN1 VPSV VCM1 VCM2 HILO 22 21 15 20 9 19 VPS1 26 VMID COM1 23 [(–48 to 0) + 21] dB +19dB 3.5dB/15.5dB 17 VOH1 – INH1 27 + LMD1 28 + BIAS (VMID) 16 VOL1 10 GAIN + 13 VOL2 POST AMP2 VGA 2 LNA 2 + – INH2 2 GAIN INT BIAS AND INTERPOLATOR – LMD2 1 POST AMP1 VGA 1 LNA 1 – 12 VOH2 VPS2 3 CLAMP COM2 6 4 5 7 8 14 18 11 LON2 LOP2 VIP2 VIN2 COMM ENB RCLMP 03199-B-001 Ultralow noise preamplifier Voltage noise = 0.74 nV/√Hz Current noise = 2.5 pA/√Hz 3 dB bandwidth: 120 MHz Low power: 125 mW/channel Wide gain range with programmable postamp –4.5 dB to +43.5 dB +7.5 dB to +55.5 dB Low output-referred noise: 48 nV/√Hz typical Active input impedance matching Optimized for 10-/12-bit ADCs Selectable output clamping level Single 5 V supply operation Available in space-saving chip scale package Figure 1. AD8332 Shown 28-Lead TSSOP APPLICATIONS 50 Ultrasound and sonar time-gain control High performance AGC systems I/Q signal processing High speed dual ADC driver Each channel consists of an ultralow noise preamplifier (LNA), an X-AMP® VGA with 48 dB of gain range, and a selectable gain postamplifier with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs capable of accurate, programmable active input impedance matching by selecting an external feedback resistor. Active impedance control optimizes noise performance for applications that benefit from input matching. The 48 dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Differential signal paths lead to superb second and third order distortion performance and low crosstalk. 0.6V 20 0.4V 10 0.2V 0 0V –10 –20 100k 1M 03199-C-002 The AD8331/AD8332 are single- and dual-channel ultralow noise, linear-in-dB, variable gain amplifiers. Although optimized for ultrasound systems, they are usable as low noise variable gain elements at frequencies up to 120 MHz. 0.8V 30 GAIN (dB) GENERAL DESCRIPTION VGAIN = 1V 40 10M 100M 1G FREQUENCY (Hz) Figure 2. Frequency Response vs. Gain The VGA’s low output-referred noise is advantageous in driving high speed differential ADCs. The gain of the postamplifier may be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output may be limited to a user-selected clamping level, preventing input overload to a subsequent ADC. An external resistor adjusts the clamping level. The operating temperature range is –40°C to +85°. The AD8331 is available in a 20-lead QSOP package, and the AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. They require a single 5 V supply, and the quiescent power consumption is 125 mW/ch. A power-down (enable) pin is provided. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD8331/AD8332 LNA – External Components ................................................... 22 TABLE OF CONTENTS Driving ADCs ............................................................................. 24 REVISION HISTORY.................................................................. 2 Overload ...................................................................................... 24 AD8331, AD8332—Specifications.................................................. 3 Optional Input Overload Protection. ...................................... 25 Absolute Maximum Ratings............................................................ 6 Layout, Grounding, And Bypassing ......................................... 25 ESD CAUTION ............................................................................ 6 Multiple Input Matching ........................................................... 25 AD8331, AD8332—Typical Performance Characteristics .......... 7 Disabling the LNA...................................................................... 25 Test Circuits..................................................................................... 15 Measurement Considerations................................................... 26 Theory of Operation ...................................................................... 17 Ultrasound TGC Application ................................................... 26 Overview...................................................................................... 17 Pin Configuration and Function Descriptions........................... 30 Low Noise Amplifier (LNA)...................................................... 17 AD8331........................................................................................ 30 Variable Gain Amplifier............................................................. 19 AD8332........................................................................................ 31 Postamplifier ............................................................................... 21 Outline Dimensions ....................................................................... 32 Applications..................................................................................... 22 Ordering Guide .......................................................................... 32 REVISION HISTORY Revision C 11/03—Data Sheet Changed from REV. B to REV. C Addition of New Part...........................................................Universal Changes to Figures ...............................................................Universal Updated Outline Dimensions..........................................................32 5/03—Data Sheet Changed from REV. A to REV. B Edits to Ordering Guide....................................................................32 Edits to Ultrasound TGC Application section................................25 Added Figure 71, Figure 72, and Figure 73......................................26 Updated Outline Dimensions............................................................31 2/03—Data Sheet Changed from REV. 0 to REV. A Edits to Ordering Guide.....................................................................32 Rev. C | Page 2 of 32 AD8331/AD8332 AD8331, AD8332—SPECIFICATIONS Table 1. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating, –4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. Parameter LNA CHARACTERISTICS Gain Input Voltage Range Input Resistance Input Capacitance Output Impedance –3 dB Small Signal Bandwidth Slew Rate Input Voltage Noise Input Current Noise Noise Figure Active Termination Match Unterminated Harmonic Distortion @ LOP1 or LOP2 HD2 HD3 Output Short-Circuit Current LNA + VGA CHARACTERISTICS –3 dB Small Signal Bandwidth –3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise Noise Figure Active Termination Match Unterminated Output-Referred Noise Output Impedance, Postamplifier Output Signal Range, Postamplifier Differential Output Offset Voltage Differential Common-Mode Output Short-Circuit Current Conditions Min Single-Ended Input to Differential Output Input to Output (Single-Ended) AC-Coupled RFB = 280 Ω RFB = 412 Ω RFB = 562 Ω RFB = 1.13 kΩ RFB = ∞ Single-Ended, Either Output VOUT = 0.2 V p-p RS = 0 Ω, HI or LO Gain, RFB = ∞, f = 5 MHz RFB = ∞, HI or LO Gain, f = 5 MHz f = 10 MHz, LOP Output RS = RIN = 50 Ω RS = 50 Ω, RFB = ∞ VOUT = 0.5 V p-p, Single-Ended, f = 10 MHz Pins LON, LOP VOUT = 0.2 V p-p VOUT = 2 V p-p LO Gain HI Gain RS = 0 Ω, HI or LO Gain, RFB = ∞, f = 5 MHz VGAIN = 1.0 V RS = RIN = 50 Ω, f = 10 MHz, Measured RS = RIN = 200 Ω, f = 5 MHz, Simulated RS = 50 Ω, RFB = ∞, f = 10 MHz, Measured RS = 200 Ω, RFB = ∞, f = 5 MHz, Simulated VGAIN = 0.5 V, LO Gain VGAIN = 0.5 V, HI Gain DC to 1 MHz RL ≥ 500 Ω, Unclamped, Either Pin VGAIN = 0.5 V –50 –125 Rev. C | Page 3 of 32 Typ Max Unit 19 dB 13 ±275 50 75 100 200 6 13 5 130 650 dB mV Ω Ω Ω Ω kΩ pF Ω MHz V/µs 0.74 nV/√Hz 2.5 pA/√Hz 3.7 2.5 dB dB –56 –70 165 dBc dBc mA 120 110 300 1200 MHz MHz V/µs V/µs 0.82 nV/√Hz 4.15 dB 2.0 dB 2.5 dB 1.0 dB 48 178 1 nV/√Hz nV/√Hz Ω VCM ± 1.125 V 4.5 V p-p ±5 –25 45 +50 +100 mV mV mA AD8331/AD8332 Parameter Harmonic Distortion HD2 HD3 HD2 HD3 Input 1 dB Compression Point Two-Tone Intermodulation Distortion (IMD3) Output Third Order Intercept Channel-to-Channel Crosstalk (AD8332) Overload Recovery Group Delay Variation ACCURACY Absolute Gain Error2 Gain Law Conformance3 Channel-to-Channel Gain Matching GAIN CONTROL INTERFACE (Pin GAIN) Gain Scaling Factor Gain Range Input Voltage (VGAIN) Range Input Impedance Response Time COMMON-MODE INTERFACE (Pin VCMn) Input Resistance Output CM Offset Voltage Voltage Range ENABLE INTERFACE (Pins ENB, ENBL, ENBV) Logic Level to Enable Power Logic Level to Disable Power Input Resistance Power-Up Response Time Conditions VGAIN = 0.5 V, VOUT = 1 V p-p 2 3 Typ Max Unit VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz–10 MHz VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz –88 –85 –68 –65 7 –80 –72 38 33 dBc dBc dBc dBc dBm1 dBc dBc dBm dBm VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz –84 dB 5 ns ±2 ns f = 1 MHz f = 10 MHz VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 MHz < f < 50 MHz, Full Gain Range 0.05 V < VGAIN < 0.10 V 0.10 V < VGAIN < 0.95 V 0.95 V < VGAIN < 1.0 V 0.1 V < VGAIN < 0.95 V 0.1 V < VGAIN < 0.95 V –1 –1 –2 0.10 V < VGAIN < 0.95 V LO Gain HI Gain Current Limited to ±1 mA VCM = 2.5 V +0.5 ±0.3 –1 ±0.2 ±0.1 +2 +1 +1 50 –4.5 to +43.5 +7.5 to +55.5 0 to 1.0 10 750 48 dB Gain Change to 90% Full Scale –125 VOUT = 2.0 V p-p 30 –25 2.25 0 Pin ENB Pin ENBL Pin ENBV VINH = 30 mV p-p VINH = 150 mV p-p +100 50 All dBm values are referred to 50 Ω, unless otherwise noted. Conformance to theoretical gain expression (see Equation 1). Conformance to best fit dB linear curve. Rev. C | Page 4 of 32 Ω mV V 5 1.0 V V kΩ kΩ kΩ µs ms 5 1.0 V V kΩ 25 40 70 300 4 2.25 0 dB dB dB dB dB dB/V dB dB V MΩ ns 1.5 to 3.5 HILO GAIN RANGE INTERFACE (Pin HILO) Logic Level to Select HI Gain Range Logic Level to Select LO Gain Range Input Resistance 1 Min AD8331/AD8332 Parameter OUTPUT CLAMP INTERFACE (Pin RCLMP; HI or LO Gain) Accuracy HILO = LO HILO = HI MODE INTERFACE (Pin MODE) Logic Level for Positive Gain Slope Logic Level for Negative Gain Slope Input Resistance POWER SUPPLY (Pins VPS1, VPS2, VPSV, VPSL, VPOS) Supply Voltage Quiescent Current per Channel Power Dissipation per channel Disable Current AD8332 (VGA and LNA) AD8331 (VGA and LNA) AD8332 (ENBL) AD8332 (ENBV) AD8331 (ENBL) AD8331 (ENBV) PSRR Conditions Min RCLMP = 2.74 kΩ, VOUT = 1 V p-p (Clamped) RCLMP = 2.21 kΩ, VOUT = 1 V p-p (Clamped) Typ Max ±50 ±75 0 2.25 mV mV 1.0 5 V V kΩ 5.0 25 125 5.5 V mA mW 300 240 12 13 11 14 –68 600 400 µA µA mA mA mA mA dB 200 4.5 No Signal Each Channel Each Channel VGAIN = 0, f = 100 kHz Rev. C | Page 5 of 32 Unit AD8331/AD8332 ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Parameter Voltage Supply Voltage (VPSn, VPSV, VPSL, VPOS) Input Voltage (INHn) ENB, ENBL, ENBV, HILO Voltage GAIN Voltage Power Dissipation RU-28 Package (AD8332)4 CP-32 Package (AD8332)5 RQ-20 Package (AD8331)4 Temperature Operating Temperature Storage Temperature Lead Temperature (Soldering 60 sec) θJA RU-28 Package (AD8332)4 CP-32 Package (AD8332)5 RQ-20 Package (AD8331)4 θJC RU-28 Package (AD8332)4 CP-32 Package (AD8332)5 RQ-20 Package (AD8331)4 4 5 Rating Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.5 V VS + 200 mV VS + 200 mV 2.5 V 0.96 W 1.97 W 0.78 W –40°C to +85°C –65°C to +150°C 300°C 68°C/W 33°C/W 83°C/W 14°C/W 33°C/W n/a Four-Layer JEDEC Board (2S2P). Exposed pad soldered to board, nine thermal vias in pad — JEDEC 4-Layer Board J-STD-51-9. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 6 of 32 AD8331/AD8332 AD8331, AD8332—TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V, –4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified. 60 50 SAMPLE SIZE = 80 UNITS VGAIN = 0.5V 50 HILO = HI 40 30 % OF UNITS GAIN (dB) 40 MODE = HI (AC PACKAGE ONLY) MODE = LO 20 30 20 10 HILO = LO –10 0 0.2 0.4 0.6 0.8 1.0 03199-C-006 03199-C-003 10 0 0 1.1 –0.5 VGAIN (V) –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 GAIN ERROR (dB) Figure 3. Gain vs. VGAIN and MODE (MODE Available on AC Package) Figure 6. Gain Error Histogram 2.0 25 SAMPLE SIZE = 50 UNITS 20 VGAIN = 0.2V 1.5 15 10 +25°C –40°C 0.5 5 % OF UNITS 0 –0.5 0 25 20 +85°C –1.0 VGAIN = 0.7V 03199-C-004 15 03199-C-007 0.19 0.21 0.17 0.15 0.13 0.09 0.11 0.07 CHANNEL-TO-CHANNEL GAIN MATCH (dB) Figure 4. Absolute Gain Error vs. VGAIN at Three Temperatures Figure 7. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V 2.0 50 1.5 VGAIN = 1V 40 1.0 0.8V 0.5 30 10MHz 0.6V 1MHz GAIN (dB) 0 –0.5 30MHz 70MHz 20 0.4V 10 0.2V –1.0 0 03199-C-005 –1.5 –2.0 0 0.2 0.4 0.6 VGAIN (V) 0.8 1.0 0V –10 1.1 –20 100k 03199-C-008 GAIN ERROR (dB) 0.05 0 1.1 0.03 1.0 –0.01 0.01 0.8 –0.03 0.6 VGAIN (V) –0.05 0.4 –0.07 0 .2 –0.11 –0.09 0 5 –0.13 –2.0 10 –0.15 –1.5 –0.17 GAIN ERROR (dB) 1.0 1M 10M FREQUENCY (Hz) 100M Figure 5. Absolute Gain Error vs. VGAIN at Various Frequencies Figure 8. Frequency Response for Various Values of VGAIN Rev. C | Page 7 of 32 1G AD8331/AD8332 0 60 VGAIN = 1V VOUT = 1 V p-p –10 50 0.8V –20 30 0.4V 20 0.2V 10 –30 –40 –50 VGAIN = 1V –60 0V 0.9V –70 –10 100k 0.7V 03199-C-009 0 1M 10M FREQUENCY (Hz) 100M 0.5V –90 100k 1G Figure 9. Frequency Response for Various Values of VGAIN, HILO = HI 1M 10M FREQUENCY (Hz) 100M Figure 12. Channel-to-Channel Crosstalk vs. Frequency for Various Values of VGAIN 30 50 20 RIN = R S = 50Ω, 75Ω, 100Ω 40 RIN = R S = 1kΩ 10 GROUP DELAY (ns) RIN = R S = 500Ω 0 RIN = R S = 200Ω –10 –20 1M 10M 100M 35 30 25 20 1µF COUPLING 15 10 03199-C-010 –30 –40 100k 0.1µF COUPLING 45 03199-C-013 VGAIN = 0.5 V GAIN (dB) 0.4V –80 03199-C-012 0.6V CROSSTALK (dB) GAIN (dB) 40 5 0 100k 1G 1M FREQUENCY (Hz) 10M FREQUENCY (Hz) 100M Figure 13. Group Delay vs. Frequency Figure 10. Frequency Response for Various Matched Source Impedances 20 30 T = –40°C HI GAIN VGAIN = 0.5V RFB = ∞ T = +25°C T = +85°C T = +25°C 10 20 OFFSET VOLTAGE (mV) 0 0 –10 –20 –10 T = +85°C T = –40°C –20 20 LO GAIN T = +85°C T = –40°C 10 –40 100k T = +25°C 1M 10M FREQUENCY (Hz) 100M Figure 11. Frequency Response, Unterminated, RS = 50 Ω –10 T = –40°C –20 1G 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 03199-C-014 0 –30 03199-C-011 GAIN (dB) 10 1.1 VGAIN (V) Figure 14. Representative Differential Output Offset Voltage vs. VGAIN at Three Temperatures Rev. C | Page 8 of 32 AD8331/AD8332 50j 35 SAMPLE SIZE = 100 0.2V < VGAIN < 0.7V 30 25 % TOTAL 100j 25j f = 100kHz RIN = 50Ω , RFB = 270Ω RIN = 75Ω, RFB = 412Ω 20 RIN = 100Ω, RFB = 549Ω 15 17Ω 0Ω 10 49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3 50.4 RIN = 6kΩ, RFB = ∞ 50.5 GAIN SCALING FACTOR –25j –100j Figure 15. Gain Scaling Factor Histogram 03199-B-018 0 RIN = 200Ω, RFB = 1.1kΩ 03199-B-015 5 –50j Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz for Various Values of RFB 100 SINGLE ENDED, PIN VOH OR VOL RL = ∞ RIN = 50Ω, 75Ω, AND 100Ω 15 RIN = 200Ω 10 10 GAIN (dB) 5 1 RIN = 1kΩ RIN = 500Ω RIN = 200Ω 0 –5 03199-C-016 0.1 100k 1M 10M FREQUENCY (Hz) –10 03199-C-019 OUTPUT IMPEDANCE (Ω) 20 –15 100M –20 100k Figure 16. Output Impedance vs. Frequency 1M 10M FREQUENCY (Hz) 100M 1G Figure 19. LNA Frequency Response, Single-Ended, for Various Values of RIN 10k RFB = ∞, CSH = 0pF 20 RFB = 6.65kΩ, CSH = 0pF 10 1k RFB = ∞ RFB = 3.01kΩ, CSH = 0pF GAIN (dB) 5 RFB = 1.1kΩ, CSH = 1.2pF RFB = 549Ω, CSH = 8.2pF 0 –5 RFB = 412Ω, CSH = 12pF RFB = 270Ω, CSH = 22pF 10 100k 1M –10 10M 03199-C-020 100 03199-C-017 INPUT IMPEDANCE (Ω) 15 –15 100M –20 100k FREQUENCY (Hz) Figure 17. LNA Input Impedance vs. Frequency for Various Values of RFB and CSH 1M 10M FREQUENCY (Hz) 100M 1G Figure 20. LNA Frequency Response, Unterminated, Single-Ended Rev. C | Page 9 of 32 AD8331/AD8332 1.00 500 0.90 INPUT NOISE (nV/ Hz) 400 300 200 HILO = HI 0.85 0.80 0.75 0.70 0.65 HILO = LO 0.2 0 0.6 0.4 0.8 03199-C-024 0.60 100 0 RS = 0, RFB = ∞, VGAIN = 1V, f = 10MHz 0.95 03199-C-021 OUTPUT-REFERRED NOISE (nV/ Hz) f = 10MHz 0.55 0.50 –50 1.0 –30 –10 30 50 70 90 Figure 24. Short-Circuit Input-Referred Noise vs. Temperature Figure 21. Output-Referred Noise vs. VGAIN 1.6 10 TEMPERATURE (°C) VGAIN (V) 10 RS = 0, RFB = ∞, VGAIN = 1V HILO = LO OR HI f = 5MHz, RFB = ∞, VGAIN = 1V 1.2 INPUT NOISE (nV/ Hz) INPUT NOISE (nV/ Hz) 1.4 1.0 0.8 0.6 1.0 0.4 0 100k 1M 10M FREQUENCY (Hz) 0.1 1 100M Figure 22. Short-Circuit Input-Referred Noise vs. Frequency 10 100 SOURCE RESISTANCE (Ω) 1k Figure 25. Input-Referred Noise vs. RS 7 100 RS = 0, RFB = ∞, HILO = LO OR HI, f = 10MHz INCLUDES NOISE OF VGA NOISE FIGURE (dB) 6 10 1 5 RIN = 50Ω 4 75Ω 3 100Ω 200Ω 2 RFB = ∞ 0.2 0.4 0.6 VGAIN (V) 0.8 03199-C-026 0.1 0 1 03199-C-023 INPUT NOISE (nV/ Hz) 03199-C-025 RS = THERMAL NOISE ALONE 03199-C-022 0.2 SIMULATION 0 1.0 50 100 1k SOURCE RESISTANCE (Ω) Figure 26. Noise Figure vs. RS for Various Values of RIN Figure 23. Short-Circuit Input-Referred Noise vs. VGAIN Rev. C | Page 10 of 32 AD8331/AD8332 50 –30 f = 10MHz VOUT = 1V p-p f = 10MHz, RS = 50Ω 45 –40 HARMONIC DISTORTION (dBc) 40 35 HILO = HI, RIN = 50Ω 30 25 HILO = LO, RFB = ∞ 15 HILO = HI, RFB = ∞ 03199-C-027 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VGAIN (V) 0.8 0.9 1.0 HILO = LO, HD2 –60 –70 HILO = HI, HD2 –80 HILO = HI, HD3 –90 03199-C-030 20 HILO = LO, HD3 –50 –100 1.1 0 Figure 27. Noise Figure vs. VGAIN HARMONIC DISTORTION (dBc) 15 10 HILO = LO, RFB = ∞ f = 10MHz, RS = 50Ω 15 20 25 35 30 40 GAIN (dB) 45 50 55 –60 2.0k HILO = HI, HD2 HILO = LO, HD3 HILO = HI, HD3 –80 –100 0 60 HILO = LO, HD2 10 20 30 CLOAD (pF) 40 50 Figure 31. Harmonic Distortion vs. CLOAD 0 –40 f = 10MHz GAIN = 30 dB G = 30dB VOUT = 1VP-P HILO = HI, HD3 –50 HARMONIC DISTORTION (dBc) –20 HILO = LO, HD3 –40 –50 HILO = LO, HD2 HILO = HI, HD2 HILO = HI, HD3 –80 –90 10M FREQUENCY (Hz) HILO = LO, HD3 –60 –70 HILO = LO, HD2 HILO = HI, HD2 –80 –90 03199-C-032 –30 03199-C-029 HARMONIC DISTORTION (dBc) 1.8k –70 Figure 28. Noise Figure vs. Gain –100 1M 1.6k –90 03199-C-028 NOISE FIGURE (dB) HILO = LO, RIN = 50Ω –70 1.4k –50 20 –60 800 1.0k 1.2k RLOAD (Ω) f = 10MHz VOUT = 1V p-p HILO = HI, RIN = 50Ω HILO = HI, RFB = ∞ –10 600 –40 25 0 10 400 Figure 30. Harmonic Distortion vs. RLOAD 30 5 200 03199-C-031 NOISE FIGURE (dB) HILO = LO, RIN = 50Ω –100 100M 0 Figure 29. Harmonic Distortion vs. Frequency 1 2 VOUT (V p-p) 3 4 Figure 32. Harmonic Distortion vs. Differential Output Voltage Rev. C | Page 11 of 32 AD8331/AD8332 0 0 VOUT = 1V p-p VOUT = 1V p-p COMPOSITE (f1 + f2) G = 30dB –10 –20 INPUT RANGE LIMITED WHEN HILO = LO –40 HILO = LO, HD3 –30 IMD3 (dBc) HILO = LO, HD2 –60 HILO = HI, HD2 –50 –60 –80 HILO = HI, HD3 –70 03199-C-033 –100 –120 –40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 03199-C-036 DISTORTION (dBc) –20 –80 –90 1M 1.0 10M FREQUENCY (Hz) VGAIN (V) Figure 36. IMD3 vs. Frequency Figure 33. Harmonic Distortion vs. VGAIN, f = 1 MHz 40 0 35 VOUT = 1V p-p HILO = HI, 1MHz –20 INPUT RANGE LIMITED WHEN HILO = LO HILO = LO, HD3 –60 25 15 VOUT = 1V p-p COMPOSITE (f1 + f2) 10 HILO = HI, HD2 –120 0.2 0.3 0.4 0.5 5 03199-C-034 HILO = HI, HD3 –100 0.1 HILO = LO, 1MHz 20 –80 0 HILO = HI, 10MHz 0.6 0.7 0.8 0.9 03199-C-037 –40 HILO = LO, 10MHz 30 HILO = LO, HD2 OUTPUT IP3 (dBm) DISTORTION (dBc) 100M 0 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) VGAIN (V) Figure 37. Output Third Order Intercept vs. VGAIN Figure 34. Harmonic Distortion vs. VGAIN, f = 10 MHz 10 2mV 5 100 f = 10MHz 90 HILO = HI HILO = LO –5 –10 –15 10 –25 50mV –30 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN (V) 0.7 0.8 0.9 10ns Figure 38. Small Signal Pulse Response, G = 30 dB, Top: Input, Bottom: Output Voltage, HILO = HI or LO 1.0 Figure 35. Input 1 dB Compression vs. VGAIN Rev. C | Page 12 of 32 03199-C-038 0 –20 03199-C-035 INPUT POWER (dBm) 0 AD8331/AD8332 5 20mV 100 4 90 VOUT (V p-p) HILO = HI HILO = LO 3 2 10 0 0 Figure 39. Large Signal Pulse Response, G = 30 dB, HILO = HI or LO, Top: Input, Bottom: Output Voltage 03199-C-042 1 03199-C-039 10ns 500mV 0 10 20 30 RCLMP (kΩ) 40 50 Figure 42. Clamp Level vs. RCLMP 2 G = 30dB 4 CL = 50pF G = 40dB 3 1 INPUT CL = 0pF RCLMP = 16.5kΩ RCLMP = 7.15kΩ RCLMP = 2.67kΩ VOUT (V) 1 0 0 –1 –1 20 30 40 50 60 70 03199-C-043 03199-C-040 INPUT IS NOT TO SCALE –2 –40 –30 –20 –10 0 10 –2 –3 80 –4 –10 TIME (ns) 0 Figure 40. Large Signal Pulse Response for Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF 10 20 30 TIME (ns) 40 50 60 Figure 43. Clamp Level Pulse Response 200mV 500mV 100 90 10 200mV 400ns 100ns Figure 44. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst, VGAIN = 0.27 V, VGA Output Shown Figure 41. Pin GAIN Transient Response, Top: VGAIN, Bottom: Output Voltage Rev. C | Page 13 of 32 03199-B-044 0 03199-B-041 VOUT (V) RCLMP = 48.1kΩ 2 AD8331/AD8332 2V 50mV 100 90 10 1V Figure 45. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB 1ms 03199-B-048 100ns 03199-B-045 0 Figure 48. Enable Response, Large Signal, Top: VENB, Bottom: VOUT, VINH = 150 mV p-p 0 –10 50mV VPS1, VGAIN = 0.5V –20 100 VPSV, VGAIN = 0.5V PSRR (dB) 90 –30 –40 –50 VPS1, VGAIN = 0V –60 03199-C-049 10 –70 100ns 03199-B-046 0 –80 100k Figure 46. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB 1M 10M FREQUENCY (Hz) 100M Figure 49. PSRR vs. Frequency (No Bypass Capacitor) 60 VGAIN = 0.5V 55 50 AD8332 45 40 35 30 AD8331 25 20 –40 Figure 47. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p 03199-C-050 1ms 03199-B-047 200mV QUIESCENT SUPPLY CURRENT (mA) 2V –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 50. Quiescent Supply Current vs. Temperature Rev. C | Page 14 of 32 100 AD8331/AD8332 TEST CIRCUITS NETWORK ANALYZER 50Ω 50Ω OUT IN 1.8nF 270Ω FB* 120nH 0.1µF 0.1µF 237Ω INH 22pF 28Ω 1:1 DUT LMD 237Ω 0.1µF 03199-C-051 0.1µF 28Ω *FERRITE BEAD Figure 51. Gain and Bandwidth Measurements OSCILLOSCOPE 1.8nF 270Ω 237Ω FB* 120nH 0.1µF 50Ω 0.1µF INH IN 28Ω DUT LMD 1:1 237Ω 0.1µF 0.1µF 03199-C-052 22pF 50Ω 28Ω *FERRITE BEAD Figure 52. Transient Measurements A FB* 0.1µF 120nH 1Ω 50Ω 22pF B 0.1µF 50Ω INH LMD 0.1µF SPECTRUM ANALYZER IN 1:1 DUT 0.1µF *FERRITE BEAD 03199-C-053 49Ω G Figure 53. Used for Noise Measurements Rev. C | Page 15 of 32 AD8331/AD8332 SPECTRUM ANALYZER 1.8nF FB* 120nH 0.1µF INH 22pF 237Ω 50 Ω IN 28Ω 1:1 DUT LMD 237Ω 0.1µF 0.1µF 03199-C-054 50Ω 0.1µF 270Ω 28Ω *FERRITE BEAD Figure 54. Distortion NETWORK ANALYZER 50Ω 50Ω OUT IN 1.8nF FB* 120nH 0.1µF 50Ω 270Ω INH 0.1µF 237Ω 28Ω 22pF LMD DUT 50Ω 1:1 0.1µF 28Ω Figure 55. S11 Measurements Rev. C | Page 16 of 32 03199-C-055 237Ω 0.1µF *FERRITE BEAD AD8331/AD8332 THEORY OF OPERATION 60 OVERVIEW The following discussion applies to all part numbers. Figure 56 and Figure 1 are functional block diagrams of the AD8331 and AD8332, respectively. 4 7 5 VPOS VCM 14 8 HILO 19 11 3.5dB/ 15.5dB VPSL 3 AD8331 HILO = HI 40 GAIN (dB) LON LOP VIP VIN VMID MODE = HI (WHERE AVAILABLE) 50 30 MODE = LO 20 COML 6 ∆G = –48dB to 0dB LNA LMD +21dB 1 LNA BIAS (VMID ) GAIN POST AMP1 GAIN INT BIAS AND INTERPOLATOR 15 VOH 16 VOL CLAMP 9 20 –10 18 12 ENBV RCLMP 19 17 COMM ENBL HILO = LO 0 MODE 10 COMM 10 03199-C-058 VGA 2 0 0.2 0.4 0.6 0.8 1.0 1.1 VGAIN (V) 03199-C-056 INH Figure 58. Gain Control Characteristics Figure 56. Functional Block Diagram — AD8331 Each channel contains an LNA that provides user-adjustable input impedance termination, a differential X-AMP VGA, and a programmable gain postamplifier with adjustable output voltage limiting. Figure 57 shows a simplified block diagram. VIN LON X-AMP VGA PREAMPLIFIER 19dB INH + LMD – POSTAMP 3.5dB/15.5dB [(–48 to 0) + 21] dB VOH LNA VOL VIP LOP RCLMP GAIN INTERFACE* BIAS AND INTERPOLATOR* GAIN VMID VCM CLAMP* HILO *SHARED BETWEEN CHANNELS 03199-B-057 BIAS (VMID) Figure 57. Simplified Block Diagram The linear-in-dB gain control interface is trimmed for slope and absolute accuracy. The overall gain range is 48 dB, extending from –4.5 dB to +43.5 dB or from +7.5 dB to +55.5 dB, depending on the setting of the HILO pin. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V, leading to the following expressions for gain: GAIN (dB) = 50 (dB V ) × VGAIN – 6.5 dB, (HILO = LO ) (1) or GAIN (dB) = 50 (dB V ) × VGAIN + 5.5 dB, (HILO = HI ) (2 ) When MODE is set high, (where available): ( ) ( ) GAIN (dB) = – 50 dB V × VGAIN + 45.5 dB, (HILO = LO ) (3) or GAIN (dB) = – 50 dB V × VGAIN + 57.5 dB, (HILO = HI ) (4) The LNA converts a single-ended input to a differential output with a voltage gain of 19 dB. When only one output is used, the gain is 13 dB. The inverting output is used for active input impedance termination. Each of the LNA outputs is capacitively coupled to a VGA input. The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain, for a net gain range of –27 dB to +21 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. The final stage is a logic programmable amplifier with gains of 3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for 12-bit and 10-bit A/D converter applications, in terms of output-referred noise and absolute gain range. Output voltage limiting may be programmed by the user. LOW NOISE AMPLIFIER (LNA) Good noise performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input matching. The gain characteristics are shown in Figure 58. Rev. C | Page 17 of 32 AD8331/AD8332 A simplified schematic of the LNA is shown in Figure 59. INH is capacitively coupled to the source. An on-chip bias generator centers the output dc levels at 2.5 V and the input voltages at 3.25 V. A capacitor CLMD of the same value as the input coupling capacitor CINH is connected from the LMD pin to ground. CFB RFB LOP VPOS I0 I0 CINH LON INH Q1 LMD Q2 CLMD CSH RS I0 03199-C-059 I0 Figure 59. Simplified LNA Schematic The LNA supports differential output voltages as high as 5 V p-p with positive and negative excursions of ±1.25 V, about a common-mode voltage of 2.5 V. Since the differential gain magnitude is 9, the maximum input signal before saturation is ± 275 mV or 550 mV p-p. Overload protection ensures quick recovery time from large input voltages. Since the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low inputreferred voltage noise of 0.74 nV/√Hz. This is achieved with a modest current consumption of 10 mA per channel (50 mW). On-chip resistor matching results in precise gains of 4.5 per side (9 differential), critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third order distortion. Active Impedance Matching The LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance RIN is given by Equation 5, where A is the single-ended gain of 4.5, and 6 kΩ is the unterminated input impedance. R IN = 6 kΩ × R FB R FB 6 kΩ = 1+ A 33 kΩ + R FB CFB is needed in series with RFB, since the dc levels at Pins LON and INH are unequal. Expressions for choosing RFB in terms of RIN and for choosing CFB are found in the Applications section. CSH and the ferrite bead enhance stability at higher frequencies where the loop gain declines and prevents peaking. Frequency response plots of the LNA are shown in Figure 19 and Figure 20. The bandwidth is approximately 130 MHz for matched input impedances of 50 Ω to 200 Ω and declines at higher source impedances. The unterminated bandwidth (RFB = ∞) is approximately 80 MHz. Each output can drive external loads as low as 100 Ω in addition to the 100 Ω input impedance of the VGA (200 Ω differential). Capacitive loading up to 10 pF is permissible. All loads should be ac-coupled. Typically, Pin LOP output is used as a singleended driver for auxiliary circuits, such as those used for Doppler mode ultrasound imaging, and Pin LON drives RFB. Alternatively, a differential external circuit can be driven from the two outputs, in addition to the active feedback termination. In both cases, important stability considerations discussed in the Applications section should be carefully observed. The impedance at each LNA output is 5 Ω. A 0.4 dB reduction in open-circuit gain results when driving the VGA, and 0.8 dB with an additional 100 Ω load at the output. The differential gain of the LNA is 6 dB higher. If the load is less than 200 Ω on either side, a compensating load is recommended on the opposite output. LNA Noise The input-referred voltage noise sets an important limit on system performance. The short-circuit input voltage noise of the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain), including the VGA noise. The open-circuit current noise is 2.5 pA/√Hz. These measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations in Figure 60. Figure 61 and Figure 62 are simulations extracted from these results, and the 4.1 dB NF measurement with the input actively matched to a 50 Ω source. Unterminated (RFB = ∞) operation exhibits the lowest equivalent input noise and noise figure. Figure 61 shows the noise figure versus source resistance, rising at low RS, where the LNA voltage noise is large compared to the source noise, and again at high RS due to current noise. The VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in all of the curves. (5) Rev. C | Page 18 of 32 AD8331/AD8332 UNTERMINATED The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA’s input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 61 shows their relative noise figure (NF) performance. In this graph, the input impedance has been swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the resistive, active, and unterminated configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB, and 1.0 dB, respectively. RIN RS VIN + VOUT – RESISTIVE TERMINATION RIN RS VIN + RS VOUT – ACTIVE IMPEDANCE MATCH –RS = RIN RFB R IN RS VIN + VOUT – Figure 62 is a plot of the NF versus RS for various values of RIN, which is helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 19 dB and noise spectral density of a 1.0 nV/√Hz, combined with a VGA with 3.75 nV/√Hz, would yield a noise figure degradation of approximately 1.5 dB (for most input impedances), significantly worse than the AD8332 performance. 03199-C-060 RIN = RFB 1 + 4.5 Figure 60. Input Configurations 7 INCLUDES NOISE OF VGA NOISE FIGURE (dB) 6 The equivalent input noise of the LNA is the same for singleended and differential output applications. The LNA noise figure improves to 3.5 dB at 50 Ω without VGA noise, but this is exclusive of noise contributions from other external circuits connected to LOP. A series output resistor is usually recommended for stability purposes, when driving external circuits on a separate board (see the Applications section). In low noise applications, a ferrite bead is even more desirable. RESISTIVE TERMINATION (RS = RIN) 5 4 3 ACTIVE IMPEDANCE MATCH 2 UNTERMINATED 03199-C-061 1 SIMULATION 0 50 100 RS (Ω) VARIABLE GAIN AMPLIFIER 1k The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 2.7 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 63. Figure 61. Noise Figure vs. RS for Resistive, Active Matched, and Unterminated Inputs 7 INCLUDES NOISE OF VGA GAIN 6 GAIN INTERPOLATOR (BOTH CHANNELS) NOISE FIGURE (dB) POST-AMP 5 RIN = 50Ω 4 gm 70Ω VIP R 100Ω 3 200Ω 2 6dB 48dB 2R VIN 03199-C-081 SIMULATION 0 50 100 RS (Ω) POST-AMP 1k Figure 63. Simplified VGA Schematic Figure 62. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched Rev. C | Page 19 of 32 03199-C-063 RFB = ∞ 1 AD8331/AD8332 X-AMP VGA The input of the VGA is a differential R-2R ladder attenuator network, with 6 dB steps per stage and a net input impedance of 200 Ω differential. The ladder is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. LNA outputs are ac-coupled to reduce offset and isolate their common-mode voltage. The VGA inputs are biased through the ladder’s center tap connection to VCM, which is typically set to 2.5 V and is bypassed externally to provide a clean ac ground. The signal level at successive stages in the input attenuator falls from 0 dB to –48 dB, in 6 dB steps. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to –48 dB. This circuit technique results in excellent, linear-in-dB gain law conformance and low distortion levels and deviates ±0.2 dB or less from ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a gain-of-12 feedback amplifier, which completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feedthrough to the output and ensure excellent frequency response uniformity across gain setting (see Figure 8 and Figure 9). Gain Control Position along the VGA attenuator is controlled by a singleended analog control voltage, VGAIN, with an input range of 40 mV to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V (20 mV/dB). Values of VGAIN beyond the control range saturate to minimum or maximum gain values. Both channels of the AD8332 are controlled from a single gain interface to preserve matching. Gain can be calculated using Equations 1 and 2. Gain accuracy is very good since both the scaling factor and absolute gain are factory trimmed. The overall accuracy relative to the theoretical gain expression is ±1 dB for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. The gain error relative to a best-fit line for a given set of conditions is typically ±0.2 dB. Gain matching between channels is better than 0.1 dB (see Figure 7, which shows gain errors in the center of the control range). When VGAIN < 0.1 or > 0.95, gain errors are slightly greater. The gain slope may be inverted, as shown in Figure 58 (available in most versions). The gain drops with a slope of –50 dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications, such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin HI. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in accordance with the quantization noise floor of the ADC. Output and input-referred noise as a function of VGAIN are plotted in Figure 21 and Figure 23 for the short-circuited input condition. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is flat over most of the gain range, since it is dominated by the fixed output-referred noise of the VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz in HI gain mode. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA becomes very small. At lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, since the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. With its low output-referred noise levels, these devices ideally drive low-voltage ADCs. The converter noise floor drops 12 dB for every 2 bits of resolution and drops at lower input full-scale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications section. The preceding noise performance discussion applies to a differential VGA output signal. Although the LNA noise performance is the same in single-ended and differential applications, the VGA performance is not. The noise of the VGA is significantly higher in single-ended usage, since the contribution of its bias noise is designed to cancel in the differential signal. A transformer can be used with single-ended applications when low noise is desired. Rev. C | Page 20 of 32 AD8331/AD8332 POSTAMPLIFIER The final stage has a selectable gain of 3.5 dB or 15.5 dB, set by the logic Pin HILO. These correspond to linear gains of 1.5 or 6. A simplified block diagram of the postamplifier is shown in Figure 64. Separate feedback attenuators implement the two gain settings. These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI gain mode and 300 V/µs in LO gain mode. The feedback networks for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel. F2 VCM F1 VOL – Gm1 03199-B-064 Gm2 Figure 64. Postamplifier Block Diagram Although the quantization noise floor of an ADC depends on a number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. An additional technique, described in the Applications section, can extend the noise floor even lower for possible use with 14-bit ADCs. Output Clamping Outputs are internally limited to a level of 4.5 V p-p differential when operating at a 2.5 V common-mode voltage. The postamp implements an optional output clamp engaged through a resistor from RCLMP to ground. Table shows a list of recommended resistor values. Output clamping can be used for ADC input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V. The user should be aware that distortion products increase as output levels approach the clamping levels and should adjust the clamp resistor accordingly. Also, see the Applications section. The accuracy of the clamping levels is approximately ±5% in LO or HI mode. Figure 65 illustrates the output characteristics for a few values of RCLMP. Noise The topology of the postamplifier provides constant inputreferred noise with the two gain settings and variable outputreferred noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving converters with higher noise floors. The extra gain boosts the output signal levels and noise floor appropriately. When driving circuits with lower input noise floors, the LO gain mode optimizes the output dynamic range. 5.0 4.5 4.0 3.5 RCLMP = ∞ 8.8kΩ 3.5kΩ 3.0 2.5 RCLMP = 1.86kΩ 2.0 1.5 1.0 03199-C-065 An internal bias network connected to a midsupply voltage establishes common-mode voltages in the VGA and postamp. An externally bypassed buffer maintains the voltage. The bypass capacitors form an important ac ground connection, since the VCM network makes a number of important connections internally, including the center tap of the VGA’s differential input attenuator, the feedback network of the VGA’s fixed gain amplifier, and the feedback network of the postamplifier in both gain settings. For best results, use a 1 nF and a 0.1 µF capacitor in parallel, with the 1 nF nearest to Pin VCM. Separate VCM pins are provided for each channel. For dc-coupling to a 3 V ADC, the output common-mode voltage is adjusted to 1.5 V by biasing the VCM pin. VOH Gm1 VOH, VOL (V) Common-Mode Biasing Gm2 + Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and usually only evident when a large signal is present. Its effect is observable only in LO gain mode, where the noise floor is substantially lower. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN input. An external RC filter may be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth. 0.5 0 –3 –2 –1 0 1 2 VINH (V) Figure 65. Output Clamping Characteristics Rev. C | Page 21 of 32 3 AD8331/AD8332 CLMD 0.1µF APPLICATIONS 1 LNA – EXTERNAL COMPONENTS 2 The LMD pin (connected to the bias circuitry) must be bypassed to ground, and signal source to the INH pin capacitively coupled using 2.2 nF to 0.1 μF capacitors (see Figure 66). +5V 3 4 5 33 kΩ × (R IN ) 6 kΩ – (R IN ) 1nF 7 8 9 VGAIN (6) 1nF 10 1nF RFB (Nearest STD 1% Value, Ω) 280 412 562 1.13k 3.01k ∞ 0.1µF CSH (pF) 22 12 8 1.2 None None INH1 VPS2 VPS1 LON2 LON1 LOP2 LOP1 COM2 COM1 VIP2 VIP1 VIN2 VIN1 VCM2 VCM1 GAIN HILO RCLMP ENB 0.1µF CSH* 27 CFB* 26 1n F 5V RFB * 25 0.1 F LNA OUT 24 23 22 0.1µF 0.1µF Table 3. LNA External Component Values for Common Source Impedances RIN (Ω) 50 75 100 200 500 6k INH2 28 11 12 13 14 VOH2 VOL2 COMM VOH1 VOL1 VPSV 21 1nF 20 0.1µF 19 5V 18 5V 17 * 16 * VGA OUT VGA OUT 0.1µF 15 5V 03199-C-066 R FB = 6 LMD1 1nF *SEE TEXT Figure 66. Basic Connections for a Typical Channel (AD8332 Shown) TO EXT CIRCUIT When active input termination is used, a 0.1 µF capacitor (CFB) is required to isolate the input and output bias voltages of the LNA. VIP 5Ω 50Ω LON When a long trace to Pin INH is unavoidable, or if both LNA outputs drive external circuits, a small ferrite bead (FB) in series with Pin INH preserves circuit stability with negligible effect on noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or equivalent). Other values may prove useful. Figure 67 shows the interconnection details of the LNA output. Capacitive coupling between LNA outputs and the VGA inputs is required because of differences in their dc levels and to eliminate the offset of the LNA. Capacitor values of 0.1 µF are recommended. There is 0.4 dB loss in gain between the LNA output and the VGA input due to the 5 Ω output resistance. Additional loading at the LOP and LON outputs will affect LNA gain. 100Ω VCM The shunt input capacitor, CSH, reduces gain peaking at higher frequencies where the active termination match is lost due to the HF gain roll-off of the LNA. Suggested values are shown in Table ; for unterminated applications, reduce the capacitor value by half. LNA CSH 5Ω 100Ω LOP 50Ω VIN TO EXT CIRCUIT 03199-C-067 The unterminated input impedance of the LNA is 6 kΩ. The user may synthesize any LNA input resistance between 50 Ω and 6 kΩ. RFB is calculated according to Equation 6 or selected from Table . LMD2 LNA SOURCE FB Figure 67. Interconnections of the LNA and VGA Both LNA outputs are available for driving external circuits. Pin LOP should be used in those instances when a single-ended LNA output is required. The user should be aware of stray capacitance loading of the LNA outputs, in particular LON. The LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is routed to a remote PC board, it will tolerate a load capacitance up to 100 pF with the addition of a 49.9 Ω series resistor or ferrite 75 Ω/100 MHz bead. Rev. C | Page 22 of 32 AD8331/AD8332 Gain Input Logic Inputs—ENB, MODE, and HILO Pin GAIN is common to both channels of the AD8332. The input impedance is nominally 10 MΩ and a bypass capacitor from 100 pF to1 nF is recommended. The input impedance of all enable pins is nominally 25 kΩ and may be pulled up to 5 V (a pull-up resistor is recommended) or driven by any 3 V or 5 V logic families. The enable pins perform a power-down function, when disabled, the VGA outputs are near ground. Multiple devices may be driven from a common source. Consult the pin-function tables for circuit functions controlled by the enable pins. If gain control noise in LO gain mode becomes a factor, maintaining ≤15 nV/√Hz noise at the GAIN pin will ensure satisfactory noise performance. Internal noise prevails below 15 nV/√Hz at the GAIN pin. Gain control noise is negligible in HI gain mode. VCM Input The common-mode voltage of Pins VCM, VOL, and VOH defaults to 2.5 Vdc. With output ac-coupled applications, the VCM pin will be unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. The VGA outputs may be dc connected to a differential load, such as an ADC. Common-mode output voltage levels between 1.5 V and 3.5 V may be realized at Pins VOH and VOL by applying the desired voltage at Pin VCM. DC-coupled operation is not recommended when driving loads on a separate PC board. The voltage on the VCM pin is sourced by an internal buffer with an output impedance of 30 Ω and a ±2 mA default output current (see Figure 68). If the VCM pin is driven from an external source, its output impedance should be <<30 Ω and its current drive capability should be >>2 mA. If the VCM pins of several devices are connected in parallel, the external buffer should be capable of overcoming their collective output currents. When a common-mode voltage other than 2.5 V is used, a voltage-limiting resistor, RCLMP, is needed to protect against overload. Optional Output Voltage Limiting The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. The peak-to-peak limited voltage is adjusted by a resistor to ground, and Table lists several voltage levels and the corresponding resistor value. Unconnected, the default limiting level is 4.5 V p-p. Note that third harmonic distortion will increase as waveform amplitudes approach clipping. For lowest distortion, the clamp level should be set higher than the converter input span. A clamp level of 1.5 V p-p is recommended for a 1 V p-p linear output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. The best solution will be determined experimentally. Figure 69 shows third harmonic distortion as a function of the limiting level for a 2 V p-p output signal. A wider limiting level is desirable in HI gain mode. INTERNAL CIRCUITRY RO << 30Ω VCM 100pF VGAIN = 0.75V –30 –40 –50 HILO = LO NEW VCM HILO = HI –70 0.1µF AC GROUNDING FOR INTERNAL CIRCUITRY –80 1.5 03199-C-069 30Ω –20 –60 03199-B-068 2mA MAX Pin HILO is compatible with 3 V or 5 V CMOS logic families. It is either connected to ground or pulled up to 5 V, depending on the desired gain range and output noise. HD3 (dBc) Parallel connected devices may be driven by a common voltage source or DAC. Decoupling should take into account any bandwidth considerations of the drive waveform, using the total distributed capacitance. 2.0 2.5 3.0 3.5 4.0 CLAMP LIMIT LEVEL (V p-p) 4.5 5.0 Figure 69. HD3 vs. Clamping Level for 2 V p-p Differential Input Figure 68. VCM Interface Rev. C | Page 23 of 32 AD8331/AD8332 The relative noise and distortion performance of the two gain modes can be compared in Figure 21 and Figure 27 through Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC fullscale voltages as high as 4 V p-p. Since distortion performance remains favorable for output voltages as high as 4 V p-p (see Figure 32), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. The circuit in Figure 71 has an output full-scale range of 2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output noise floor of 24 nV/√Hz, making it suitable for some 14-bit ADC applications. Clamp Level (V p-p) Clamp Resistor Value (kΩ) HILO = LO HILO = HI 1.21 2.74 2.21 4.75 4.02 7.5 6.49 11 9.53 16.9 14.7 26.7 23.2 49.9 39.2 100 73.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.4 Output Filtering and Series Resistor Requirements 4V p-p DIFF, 48n V/ HZ To ensure stability at the high end of the gain control range, series resistors or ferrite beads are recommended for the outputs when driving large capacitive loads, or circuits on other boards,. These components can be part of the external noise filter. Recommended resistor values are 84.5 Ω for LO gain mode and 100 Ω for HI gain mode (see Figure 66) and are placed near Pins VOH and VOL. Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB. Lower values are best selected empirically. An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent. When the ADC resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and mitigates charge kickback from the ADC inputs. Any series resistance beyond that required for output stability should be placed on the ADC board. Figure 70 shows a second order low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC. OPTIONAL BACKPLANE 84.5Ω 84.5Ω 0.1µF 0.1µF 1.5µH 158Ω 1.5µH 158Ω 18pF ADC VOH 2V p-p DIFF, 24n V/ HZ 187Ω 2:1 VOL 187Ω LPF 374Ω ADC AD6644 03199-C-071 Table 4. Clamp Resistor Values Figure 71. Adjusting the Noise Floor for 14-Bit ADCs OVERLOAD These devices respond gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced. Signals larger than ±275 mV at the LNA input are clipped to 5 V p-p differential prior to the input of the VGA. Figure 44 shows the response to a 1 V p-p input burst. The symmetric overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as ±2.5 V without triggering the slow-settling ESD input protection diodes. Both stages of the VGA are susceptible to overload. Postamp limiting is more common and results in the clean-limited output characteristics found in Figure 45. Under more extreme conditions, the X-AMP will overload, causing the minor glitches evident in Figure 46. Recovery is fast in all cases. The graph in Figure 72 summarizes the combinations of input signal and gain that lead to the different types of overload. Figure 70. 20 MHz Second-Order Low-Pass Filter DRIVING ADCS The output drive will accommodate a wide range of ADCs. The noise floor requirements of the VGA will depend on a number of application factors, including bit resolution, sampling rate, full-scale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range can be adjusted by selecting HI or LO gain mode. Rev. C | Page 24 of 32 AD8331/AD8332 POSTAMP OVERLOAD 43.5 X-AMP OVERLOAD 15mV POSTAMP OVERLOAD 25mV X-AMP OVERLOAD 4mV 56.5 LAYOUT, GROUNDING, AND BYPASSING 25mV Due to their excellent high frequency characteristics, these devices are sensitive to their PCB environment. Realizing expected performance requires attention to detail critical to good high speed board design. 41dB 10m 0.1 .275 GAIN (dB) 24.5dB 7.5 1m 1 INPUT AMPLITUDE (V) LNA OVERLOAD HI GAIN MODE 10m 0.1 0.275 INPUT AMPLITUDE (V) 03199-C-072 –4.5 1m 24.5dB LO GAIN MODE LNA OVERLOAD GAIN (dB) 29dB 1 Figure 72. Overload Gain and Signal Conditions The previously mentioned clamp interface controls the maximum output swing of the postamp and its overload response. When no RCLMP resistor is provided, this level defaults to near 4.5 V p-p differential to protect outputs centered at a 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of RCLMP should be chosen for graceful overload. A value of 8.3 kΩ or less is recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode). This limits the output swing to just above 2 V p-p diff. OPTIONAL INPUT OVERLOAD PROTECTION. Applications in which high transients are applied to the LNA input may benefit from the use of clamp diodes. A pair of backto-back Schottky diodes can reduce these transients to manageable levels. Figure 73 illustrates how such a diodeprotection scheme may be connected. 0.1µF RSH 3 CSH 2 1 3 VPS 4 LON MULTIPLE INPUT MATCHING 2 INH COMM 20 ENBL 19 CFB RFB Several critical LNA areas require special care. The LON and LOP output traces must be as short as possible before connecting to the coupling capacitors connected to Pins VIN and VIP. RFB must be placed nearby the LON pin as well. Resistors must be placed as close as possible to the VGA output pins VOL and VOH to mitigate loading effects of connecting traces. Values are discussed in the section entitled Output Filtering and Series Resistor Requirements. Signal traces must be short and direct to avoid parasitic effects. Wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. PCB traces should be kept adjacent when running differential signals over a long distance. BAS40-04 03199-C-072 OPTIONAL SCHOTTKY OVERLOAD CLAMP FB A multilayer board with power and ground plane is recommended, and unused area in the signal layers should be filled with ground. The multiple power and ground pins provide robust power distribution to the device and must all be connected. The power supply pins should each be with multiple values of high frequency ceramic chip capacitors to maintain low impedance paths to ground over a wide frequency range. These should have capacitance values of 0.01 μF to 0.1 μF in parallel with 100 pF to 1 nF, and be placed as close as possible to the pins. The LNA power pins should be decoupled from the VGA using ferrite beads. Together with the decoupling capacitors, ferrite beads help eliminate undesired high frequencies without reducing the headroom, as do small value resistors. Figure 73. Input Overload Clamping When selecting overload protection, the important parameters are forward and reverse voltages and trr (or τrr.). The Infineon BAS40 series shown in Figure 73 has a τrr of 100 ps and VF of 310 mV at 1 mA. Many variations of these specifications can be found in vendor catalogs. Matching of multiple sources with dissimilar impedances can be accomplished as shown in the circuit of Figure 75. A relay and low supply voltage analog switch may be used to select between multiple sources and their associated feedback resistors. An ADG736 dual SPDT switch is shown in this example; however, multiple switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers. DISABLING THE LNA Where accessible, connection of the LNA enable pin to ground will power down the LNA, resulting in a current reduction of about half. In this mode, the LNA input and output pins may be left unconnected, however the power must be connected to all the supply pins for the disabling circuit to function. Figure 74 illustrates the connections using an AD8331 as an example. Rev. C | Page 25 of 32 AD8331/AD8332 NC 1 LMD COMM 20 MEASUREMENT CONSIDERATIONS Figure 51 through Figure 55 show typical measurement configurations and proper interface values for measurements with 50 Ω conditions. AD8331 NC 2 INH ENBL VPS ENBV LON COMM LOP VOL 19 CFB 0.018µF 3 +5V NC NC 4 5 18 Short-circuit input noise measurements are made using Figure 53. The input-referred noise level is determined by dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels since a 50 Ω load is driven directly. The generator is removed when noise measurements are made. +5V 17 16 VOUT 6 0.1µF 7 COML VOH VIP VPOS VIN HILO ULTRASOUND TGC APPLICATION 15 14 The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications, since it provides the means for echolocation of reflected ultrasound energy. +5V VIN 0.1µF 8 MODE 9 MODE CLMP 13 HILO 12 RCLMP 10 GAIN VCM 11 VCM 03199-C-074 GAIN Figure 74. Disabling the LNA ADG736 1.13kΩ Figure 76 through Figure 78 are schematics of a dual, fully differential system using the AD8332 and AD9238 12-bit high speed ADC with conversion speeds as high as 65 MSPS. In this example, the VGA outputs are dc-coupled, using the reference output of the ADC and a level shifter to center the commonmode output voltage to match that of the converter. Consult the data sheet of the converter to determine whether external CMV biasing is required. AC coupling is recommended if the CMV of the VGA and ADC are widely disparate. Using the circuit shown, and a high speed ADC FIFO evaluation kit connected to a laptop PC, an FFT can be performed on the AD8332. With the on-board clock of 20 MHz, and minimal low-pass filtering, and both channels driven with a 1 MHz filtered sine wave, the THD is –75 dB, noise floor –93 dB and HD2 –83 dB. SELECTRFB 280Ω LON 18nF 200Ω 5Ω INH 0.1µF LNA 5Ω LOP AD8332 03199-C-075 LMD 50Ω Figure 75. Accommodating Multiple Sources Rev. C | Page 26 of 32 AD8331/AD8332 S3 EIN2 TP5 AD8332ARU C50 0.1µF TP3 (RED) +5V CFB2 18nF C46 1µF C80 22PF 28 +5VLNA RFB2 274Ω L7 120nH FB +5VGA C41 0.1µF 3 7 7 C79 22 PF VPS2 VPS1 AD8541 LON2 LON1 LOP2 LOP1 COM2 COM1 VIP2 VIP1 VIN2 VIN1 C60 0.1µF S1 EIN1 CFB1 18nF 26 RFB1 274Ω +5VLNA 6 C53 0.1µF TP6 L13 120nH FB 27 C74 1nF 5 C51 0.1µF INH1 JP6 IN1 4 0.1µF INH2 JP5 IN2 L6 120nH FB +5VLNA 3 LMD1 C70 0.1µF 2 + VREF LMD2 L12 120nH FB TB1 +5V TP4 (BLACK) TB2 GND 1 C49 0.1µF 25 24 C42 0.1µF 23 C59 0.1µF 22 6 VCM1 4 8 JP13 C71 1nF VCM1 R22 1kΩ C78 1nF C48 0.1µF JP14 R23 2kΩ 9 VCM2 10 GAIN C83 1nF 18 ENB R27 100Ω VOH2 VOH1 L19 SAT L17 SAT C54 0.1µF L11 120nH FB 13 C67 L20 SAT SAT L18 JP12 SAT C55 0.1µF L10 120nH FB 14 VOL2 VOL1 COM VPSV +5VGA HI GAIN JP10 LO GAIN HILO C68 1nF C69 0.1µF JP8 DC2H JP7 DC2L 19 CLMP 12 OPTIONAL 4-POLE LOW-PASS FILTER C43 0.1µF +5VGA 11 VIN–B 20 C77 1nF R3 (RCLMP) C66 SAT VCM1 VCM TP2 GAIN TP7 GND VIN+B 21 ENABLE JP16 DISABLE 17 R24 100Ω 16 15 JP9 OPTIONAL 4-POLE LOW-PASS FILTER L9 120nH FB C58 0.1µF L1 SAT L15 SAT L8 120nF FB JP17 C56 0.1 µF L14 SAT C64 SAT L16 SAT VIN+A C65 SAT VIN–A R25 100Ω R26 100Ω +5VGA C45 0.1µF C85 1nF Figure 76. Schematic, TGC, VGA Section Rev. C | Page 27 of 32 JP10 03199-C-076 2 AD8331/AD8332 +5V 3 +3.3VCLK + 2 IN +3.3VAVDD L5 120nH FB C22 0.1µF C31 0.1µF 1 OUT GND L4 120nH FB +3.3VADDIG OUT R5 33Ω C30 0.1µF TAB VIN+_A L3 120nH FB +3.3VAVDD 0.1µF 2 3 4 R4 C18 1.5kΩ C17 1nF C33 0.1µF 10µF 6.3V + C40 0.1µF C35 0.1µF +3.3VDVDD 1 R6 33Ω R12 1.5kΩ C1 0.1 µF C36 0.1µF 5 6 C52 10nF TP 9 C32 + 0.1µF VREF C34 10µF 6.3V C38 0.1µF 8 C12 10µF 6.3V 9 C57 10nF C39 10µF C37 0.1µF VIN–B 13 14 15 R7 33Ω +3.3VCLK R18 499Ω 16 17 C20 0.1µF R16 5kΩ R17 49.9Ω C15 1nF C62 18pF VIN+B C63 0.1µF C19 1nF 18 19 R19 499Ω JP 3 JP 11 R20 4.7kΩ 20 R41 4.7kΩ 21 22 +3.3VCLK ADCLK + C86 0.1µF 4 1 VDD OE 20MHz 3 OUT GND C47 10µF 6.3V ADCLK EXT 3 JP 4 2 3 4 1 R9 0Ω 2 TP 13 9 13 12 11 10 2 23 24 25 26 27 28 3 1 JP 1 SPARES D2_B DATA CLK 8 U5 74VHC04 D0_B D1_B U5 74VHC04 U5 74VHC04 6 DNC TP 12 1 INT 5 DNC U5 74VHC04 U5 74VHC04 2 U6 SG-636PCE 11 12 1.5kΩ S2 EXT CLOCK 7 10 C16 1.5kΩ 0.1µF R8 33Ω 29 D3_B 30 D4_B 31 D5_B 32 C26 0.1µF Figure 77. Converter Schematic Rev. C | Page 28 of 32 R11 100Ω R10 JP 2 0Ω SHARED REF Y N AGND AVDD 64 VIN+_A CLK_A 63 VIN –_A SHARED_REF 62 MUX_SELECT 61 R14 4.7kΩ AGND AVDD PDWN_A 60 R15 +3.3VADDIG 0Ω REFT_A OEB_A 59 REFB_A OTRA_A 58 OTR_A D11_A(MSB) 57 D11_A D10_A 56 D10_A D9_A 55 D9_A D8_A 54 D8_A DRGND 53 VREF SENSE REFB_B REFT_B AVDD AGND VIN –_B VIN+_B AGND AVDD DRVDD 52 D7_A 51 D6_A 50 D5_A 49 D4_A 48 +3.3VADDIG C23 0.1µF D6_A D5_A D4_A D3_A DCS D2_A 46 DFS D1_A 45 PDWN_B D0_A 44 DNC 43 DNC 42 DNC DRVDD 41 D0_B DRGND 40 D1_B OTRB_B 39 OTR_B D11_B(MSB) 38 D11_B D10_B 37 D10_B CLK_B OEB_B DNC D2_B DRGND 36 D3_A D2_A D1_A D0_A DNC DNC C13 1nF D9_B D3_B D8_B 35 D8_B D4_B D7_B 34 D7_B D5_B C24 1nF D6_B C14 + 0.1µF C11 10µF 6.3V D9_B DRVDD 33 C25 1nF D7_A 47 +3.3VADDIG U5 74VHC04 ADCLK + C61 18pF VIN–_A C29 L2 120nH FB C2 10µF 6.3V C21 1nF D6_B 03199-C-077 C44 1µF U1 A/D CONVERTER AD9238 VR1 ADP3339AKC-3.3 AD8331/AD8332 20 U10 VCC 74VHC541 10 GND G2 18 2 Y1 A1 17 3 A2 Y2 16 4 A3 Y3 1 DATACLKA 22 × 4 1 2 8 RP 9 7 OTR_A D11_A + C3 0.1µF 6 4 5 5 8 6 7 7 3 6 8 4 5 9 D10_A 1 D9_A D8_A D7_A 2 22 × 4 RP 10 D6_A A4 Y4 A5 Y5 A6 Y6 A7 A8 Y7 Y8 C28 10µF 6.3V D4_A 1 2 22 × 4 3 7 4 6 D3_A 6 5 6 8 7 15 4 5 10 9 14 1 8 12 11 13 2 7 14 13 12 3 6 16 11 4 5 18 G1 4 5 5 D2_A 1 D1_A D0_A 22 × 4 RP 12 6 8 7 7 3 6 8 4 5 9 2 DNC DNC A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 Y8 RP 1 7 U7 VCC 20 74VHC541 10 G2 GND 18 2 Y1 A1 3 17 A2 Y2 8 RP 11 1 3 3 C10 + 0.1µF C8 0.1µF 19 D5_A 8 2 +3.3VDVDD 1 2 4 22 × 4 1 22 × 4 RP2 1 22 × 4 8 20 2 RP 3 7 22 3 6 24 4 5 26 22 × 4 15 17 19 21 23 25 8 28 7 30 29 3 6 32 31 4 5 34 33 36 35 1 C76 10µF 6.3V HEADER UP MALE NO SHROUD 3 R40 22Ω +3.3VDVDD G1 19 2 RP 4 16 15 14 13 27 38 37 40 39 12 SAM080UPM 11 +3.3VDVDD 1 OTR_B 2 22 × 4 RP 13 3 8 7 6 D11_B 4 5 D10_B 22 × 4 8 D8_B 2 7 D7_B 3 6 D6_B 4 5 RP 14 1 D5_B 22 × 4 8 + C7 0.1µF + C9 0.1µF C27 10µF 6.3V 1 46 45 48 47 3 6 50 49 4 5 52 51 8 54 53 1 D4_B 2 7 20 U3 VCC 74VHC541 19 10 G2 GND 18 2 A1 Y1 C4 0.1µF C5 0.1µF C6 0.1µF C75 10µF 6.3V 3 6 4 5 D2_B 1 22 × 4 8 D1_B D0_B DNC 2 RP 16 7 3 4 5 6 3 6 7 4 5 8 DNC 9 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 Y8 RP 6 56 6 58 4 5 60 8 62 7 64 3 6 66 4 5 68 8 70 69 7 72 71 3 6 74 73 4 5 76 75 1 2 D3_B 22 × 4 7 2 + RP 5 3 2 G1 22 × 4 RP 7 22 × 4 RP 8 17 16 15 14 13 12 R39 22Ω 11 DATACLK Figure 78. Interface Schematic Rev. C | Page 29 of 32 43 7 2 1 RP 15 41 44 8 1 +3.3VDVDD 22 × 4 42 HEADER UP MALE NO SHROUD D9_B 1 20 U2 VCC G1 74VHC541 19 10 GND G2 2 18 Y1 A1 3 17 A2 Y2 4 16 A3 Y3 5 15 A4 Y4 6 14 A5 Y5 7 13 A6 Y6 8 12 A7 Y7 9 11 A8 Y8 55 57 59 61 63 65 67 78 77 80 79 SAM080UPM 03199-B-078 1 AD8331/AD8332 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IDENTIFIER LMD 1 20 COMM INH 2 19 ENBL VPSL 3 18 ENBV LON 4 17 COMM LOP 5 16 VOL COML 6 15 VOH VIP 7 14 VPOS VIN 8 13 HILO MODE 9 12 RCLMP GAIN 10 11 VCM AD8331 TOP VIEW (Not to Scale) 03199-C-079 AD8331 Figure 79. 20-Lead QSOP Table 5. 20–Lead QSOP (RQ PACKAGE) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name LMD INH VPSL LON LOP COML VIP VIN MODE GAIN VCM CLMP HILO VPOS VOH VOL COMM ENBV ENBL COMM Description LNA Signal Ground LNA Input LNA 5V Supply LNA Inverting Output LNA Noninverting Output LNA Ground VGA Noninverting Input VGA Inverting Input Gain Slope Logic Input Gain Control Voltage Common-Mode Voltage Output Clamping Level Gain Range Select (HI or LO) VGA 5 V Supply Noninverting VGA Output Inverting VGA Output VGA Ground VGA Enable LNA Enable VGA Ground Rev. C | Page 30 of 32 AD8331/AD8332 VPS2 3 LON2 4 PIN 1 IDENTIFIER 28 LMD1 27 INH1 LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 25 LON1 24 LOP1 LOP2 5 COM2 6 VIP2 7 VIN2 8 21 VIN1 VCM2 9 20 VCM1 GAIN 10 19 HILO RCLMP 11 32 31 30 29 28 27 26 25 26 VPS1 AD8332 TOP VIEW (Not to Scale) 23 COM1 22 VIP1 17 VOH1 VOL2 13 16 VOL1 COMM 14 15 VPSV Figure 80. 28-Lead TSSOP Table 6. 28–Lead TSSOP (AR PACKAGE) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN RCLMP VOH2 VOL2 COMM VPSV VOL1 VOH1 ENB HILO VCM1 VIN1 VIP1 COM1 LOP1 LON1 VPS1 INH1 LMD1 PIN 1 INDICATOR 24 AD8332 TOP VIEW (Not to Scale) 23 22 21 20 19 18 17 COMM VOH1 VOL1 VPSV NC VOL2 VOH2 COMM 9 10 11 12 13 14 15 16 18 ENB VOH2 12 1 2 3 4 5 6 7 8 Description CH2 LNA Signal Ground CH2 LNA Input CH2 Supply LNA 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Control Voltage Output Clamping Resistor CH2 Noninverting VGA Output CH2 Inverting VGA Output VGA Ground (Both Channels) VGA Supply 5 V (Both Channels) CH1 Inverting VGA Output CH1 Noninverting VGA Output Enable—VGA/LNA VGA Gain Range Select (HI or LO) CH1 Common-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground 03199-C-082 2 LOP2 COM2 VIP2 VIN2 VCM2 MODE GAIN RCLMP 1 INH2 03199-B-081 LMD2 LOP1 COM1 VIP1 VIN1 VCM1 HILO ENBL ENBV AD8332 Figure 81. 32-Lead LFCSP Table 7. 32–Lead LFCSP (AC PACKAGE) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Rev. C | Page 31 of 32 Name LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 MODE GAIN RCLMP COMM VOH2 VOL2 NC VPSV VOL1 VOH1 COMM ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 Description CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground CH2 LNA Signal Ground CH2 LNA Input CH2 LNA Supply 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Slope Logic Input Gain Control Voltage Output Clamping Level Input VGA Ground CH2 Noninverting VGA Output CH2 Inverting VGA Output Not Connected VGA Supply 5 V CH1 Inverting VGA Output CH1 Noninverting VGA Output VGA Ground VGA Enable LNA Enable VGA Gain Range Select (HI or LO) CH1 Common-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output AD8331/AD8332 OUTLINE DIMENSIONS 9.80 9.70 9.60 0.341 BSC 20 28 11 0.154 BSC 15 4.50 4.40 4.30 1 PIN 1 6.40 BSC 1 0.236 BSC 10 14 PIN 1 0.065 0.049 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.069 0.053 0.30 0.19 8° 0° 0.20 0.09 SEATING PLANE 0.010 0.004 0.75 0.60 0.45 0.025 BSC 0.012 0.008 COPLANARITY 0.004 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AD COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 82. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.60 MAX 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 0.50 0.40 0.30 12° MAX Figure 84. 20 Lead Shrink Outline [QSOP] (RQ-20) Dimensions shown in millimeters 32 1 3.25 3.10 SQ 2.95 BOTTOM VIEW 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 83. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters ORDERING GUIDE AD8331/AD8332 Models AD8331ARQ AD8331ARQ-REEL AD8331ARQ-REEL7 AD8331-EVAL AD8332ARU AD8332ARU-REEL AD8332ARU-REEL7 AD8332ACP-REEL AD8332ACP-REEL7 AD8332-EVAL Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Shrink Small Outline Package 150 mil Body, 25 mil pitch Shrink Small Outline Package 150 mil Body, 25 mil pitch Shrink Small Outline Package 150 mil Body, 25 mil pitch Evaluation Board with AD8331ARQ Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Evaluation Board with AD8332ARU © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03199-0-11/03(C) Rev. C | Page 32 of 32 Package Outline RQ-20 RQ-20 RQ-20 RU-28 RU-28 RU-28 CP-32 CP-32