5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Transceivers ADM4850–ADM4857 EIA RS-485-/RS-422-compliant Data rate options ADM4850/ADM4854—115 kbps ADM4851/ADM4855—500 kbps ADM4852/ADM4856—2.5 Mbps ADM4853/ADM4857—10 Mbps Half- and full-duplex options Reduced slew rates for low EMI True fail-safe receiver inputs 5 µA (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-z when disabled or powered off −7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with MAX308x Specified over the −40°C to +85°C temperature range Available in 8-lead SOIC and LFCSP packages FUNCTIONAL BLOCK DIAGRAM VCC VCC ADM4850/ADM4851/ ADM4852/ADM4853 ADM4854/ADM4855/ ADM4856/ADM4857 RO R A A RE RO B B DE Z DI DI R D Y D GND GND 04931-001 FEATURES Figure 1. APPLICATIONS Low power RS-485 applications EMI-sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators GENERAL DESCRIPTION The ADM4850−ADM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850−ADM4853 are half-duplex transceivers, which share differential lines and have separate enable inputs for the driver and receiver. The full-duplex ADM4854−ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The parts have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends. The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The parts are fully specified over the commercial and industrial temperature ranges, and are available in 8-lead SOIC and LFCSP packages. Table 1. Selection Table Part No ADM4850 ADM4851 ADM4852 ADM4853 ADM4854 ADM4855 ADM4856 ADM4857 Half-/Full-Duplex Half Half Half Half Full Full Full Full Data Rate 115 kbps 500 kbps 2.5 Mbps 10 Mbps 115 kbp 500 kbps 2.5 Mbps 10 Mbps Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADM4850–ADM4857 TABLE OF CONTENTS Specifications..................................................................................... 3 Circuit Description......................................................................... 12 ADM4850/ADM4854 Timing Specifications........................... 4 Slew-Rate Control ...................................................................... 12 ADM4851/ADM4855 Timing Specifications........................... 4 Receiver Input Filtering............................................................. 12 ADM4852/ADM4856 Timing Specifications........................... 5 Half-/Full-Duplex Operation ................................................... 12 ADM4853/ADM4857 Timing Specifications........................... 5 High Receiver Input Impedance .............................................. 13 Absolute Maximum Ratings............................................................ 6 Three-State Bus Connection..................................................... 13 ESD Caution.................................................................................. 6 Shutdown Mode ......................................................................... 13 Pin Configurations and Function Descriptions ........................... 7 Fail-Safe Operation .................................................................... 13 Test Circuits....................................................................................... 8 Current Limit and Thermal Shutdown ................................... 13 Switching Characteristics ................................................................ 9 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 15 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADM4850–ADM4857 SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DRIVER Differential Output Voltage, VOD Min Typ 2.0 1.5 1.5 ∆|VOD| for Complementary Output States Common-Mode Output Voltage, VO ∆|VO | for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low DRIVER INPUT LOGIC CMOS Input Logic Threshold Low CMOS Input Logic Threshold High CMOS Logic Input Current (DI) DE Input Resistance to GND RECEIVER Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) CMOS Logic Input Current (RE) CMOS Output Voltage Low CMOS Output Voltage High Output Short Circuit Current Three-State Output Leakage Current POWER SUPPLY CURRENT I (115 kbps Options) −200 −200 2.0 1.4 1.4 Unit Test Conditions/Comments VCC 5 5 5 0.2 3 0.2 +200 +200 V V V V V V V mA mA R = ∞, Figure 41 R = 50 Ω (RS-422), Figure 4 R = 27 Ω (RS-485), Figure 4 VTST = −7 V to 12 V, Figure 5 R = 27 Ω or 50 Ω, Figure 4 R = 27 Ω or 50 Ω, Figure 4 R = 27 Ω or 50 Ω, Figure 4 −7 V < VOUT < +12 V −7 V < VOUT < +12 V 0.8 V V µA kΩ ±1 220 −200 96 −125 20 150 −30 −7 V < VM < +12 V −7 V < VM < +12 V −7 V < VM < +12 V VIN = +12 V VIN = −7 V 85 ±2 mV mV kΩ mA mA µA V V mA µA 5 60 160 5 120 200 5 400 500 5 400 500 µA µA µA µA µA µA µA µA µA µA µA µA DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC 0.125 −0.1 ±1 0.4 4.0 7 36 100 I (500 kbps Options) 80 120 I (2.5 Mbps Options) 250 320 I (10 Mbps Options) 250 320 1 Max Guaranteed by design. Rev. 0 | Page 3 of 16 IOUT = +4 mA IOUT = −4 mA VOUT = GND or VCC 0.4 V ≤ VOUT ≤ 2.4 V ADM4850–ADM4857 ADM4850/ADM4854 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPH Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down 1 Min Typ 115 600 600 Max Unit Test Conditions/Comments 2500 70 2400 2000 2000 kbps ns ns ns ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850 RL = 500 Ω, CL = 15 pF, Figure 7, ADM4850 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850 ns ns ns ns ns ns CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850 ADM48501 4000 400 50 5 20 4000 330 1000 255 50 50 3000 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4851/ADM4855 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down 1 Min Typ 500 250 200 Max Unit Test Conditions/Comments 600 40 600 1000 1000 kbps ns ns ns ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851 RL = 500 Ω, CL = 15 pF, Figure 7, ADM4851 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851 ns ns ns ns ns ns CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4851 RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851 RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851 ADM48511 4000 400 50 5 20 4000 330 1000 250 50 50 3000 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. Rev. 0 | Page 4 of 16 ADM4850–ADM4857 ADM4852/ADM4856 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 5. Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down 1 Min Typ 2.5 50 Max Unit Test Conditions/Comments 180 50 140 180 180 Mbps ns ns ns ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4852 RL = 500 Ω, CL = 15 pF, Figure 7, ADM4852 RL =500 Ω, CL = 100 pF, Figure 7, ADM4852 ns ns ns ns ns ns CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852 ADM48521 4000 55 50 5 20 4000 330 190 50 50 50 3000 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4853/ADM4857 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 6. Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down 1 Min Typ 10 0 Max Unit Test Conditions/Comments 30 10 30 35 35 Mbps ns ns ns ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853 RL = 500 Ω, CL = 15 pF, Figure 7, ADM4853 RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853 ns ns ns ns ns ns CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853 RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853 ADM48531 4000 55 50 5 20 4000 330 190 30 50 50 3000 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. Rev. 0 | Page 5 of 16 ADM4850–ADM4857 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter VCC to GND Digital I/O Voltage (DE, RE, DI, ROUT) Driver Output/Receiver Input Voltage Operating Temperature Range Storage Temperature Range θJA Thermal Impedance SOIC LFCSP Lead Temperature Soldering (10 s) Vapour Phase (60 s) Infrared (15 s) Rating 6V −0.3 V to VCC + 0.3 V −9 V to +14 V −40°C to +85°C −65°C to +125°C 110°C/W 62°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 300°C 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 16 ADM4850–ADM4857 ADM4850/ ADM4851/ ADM4852/ ADM4853 RO 1 RE 2 8 VCC 7 B A TOP VIEW DI 4 (Not to Scale) 5 GND DE 3 6 04931-002 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 2. ADM4850–ADM4853 Pin Configuration Table 8. ADM4850–ADM4853 Pin Descriptions Mnemonic RO 2 RE 3 DE 4 DI 5 6 7 8 GND A B VCC Description Receiver Output. When enabled, if (A−B) ≥ −30 mV, then RO = high. If (A−B) ≤ −200 mV, then RO = low. Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high impedance state. Driver Output Enable. A high level enables the driver differential inputs A and B. A low level places it in a high impedance state. Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, while a logic high on DI forces A high and B low. Ground. Noninverting Receiver Input A/Driver Output A. Inverting Receiver Input B/Driver Output B. 5 V Power Supply. VCC 1 RO 2 ADM4854/ ADM4855/ ADM4856/ ADM4857 8 A 7 B Z TOP VIEW GND 4 (Not to Scale) 5 Y DI 3 6 04931-003 Pin No. 1 Figure 3. ADM4854–ADM4857 Pin Configuration Table 9. ADM4854–ADM4857 Pin Descriptions Pin No. 1 2 Mnemonic VCC RO 3 DI 4 5 6 7 8 GND Y Z B A Description 5 V Power Supply. Receiver Output. When enabled, if (A−B) ≥ −30 mV, then RO = high. If (A−B) ≤ −200 mV, then RO = low. Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, while a logic high on DI forces Y high and Z low. Ground. Driver Noninverting Output. Driver Inverting Output. Receiver Inverting Input. Receiver Noninverting Input. Rev. 0 | Page 7 of 16 ADM4850–ADM4857 TEST CIRCUITS VCC A VOD 0V OR 3V VOC 04931-004 DE R RL S2 S1 B CL 04931-007 R VOUT DE IN Figure 4. Driver Voltage Measurement Figure 7. Driver Enable/Disable 375Ω A VTST 375Ω B VOUT RE CL 04931-008 60Ω 04931-005 VOD3 Figure 8. Receiver Propagation Delay Figure 5. Driver Voltage Measurement over Common-Mode Voltage Range +1.5V VCC S1 CL1 RL –1.5V RE B CL2 CL 04931-006 RLDIFF VOUT RE IN Figure 6. Driver Propagation Delay Figure 9. Receiver Enable/Disable Rev. 0 | Page 8 of 16 S2 04931-009 A ADM4850–ADM4857 SWITCHING CHARACTERISTICS 3V 3V 1.5V 0V tPLH 1.5V 1.5V 0V tPHL tLZ tZL 1/2VO VO 2.3V A, B VOL +0.5V A VOL tSKEW = |tPLH –tPHL| 5V tZH VOH 90% POINT 90% POINT A, B 10% POINT 10% POINT tR tF VOH –0.5V 2.3V 04931-010 0V tHZ 0V 04931-012 B DE 1.5V Figure 12. Driver Enable/Disable Timing Figure 10. Driver Propagation Delay, Rise/Fall Timing 3V RE 1.5V 1.5V 0V 0V 0V tPLH tPHL 1.5V R VOL tSKEW = |tPLH –tPHL| tZH R 1.5V VOL 04931-011 1.5V VOL +0.5V O/P LOW VOH RO tLZ tZL O/P HIGH 1.5V tHZ VOH VOH –0.5V 0V Figure 13. Receiver Enable/Disable Timing Figure 11. Receiver Propagation Delay Rev. 0 | Page 9 of 16 04931-013 A, B ADM4850–ADM4857 TYPICAL PERFORMANCE CHARACTERISTICS 0.40 400 350 ADM4853: DE = GND 250 200 ADM4850: DE = VCC 150 100 ADM4850: DE = GND 50 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 0.30 0.25 0.20 0.15 –50 125 Figure 14. Unloaded Supply Current vs. Temperature 04931-017 OUTPUT LOW VOLTAGE (V) 0.35 300 04931-014 UNLOADED SUPPLY CURRENT (µA) ADM4853: DE = VCC –25 0 25 50 TEMPERATURE (°C) 75 100 125 Figure 17. Receiver Output Low Voltage vs. Temperature 50 4.6 4.5 OUTPUT HIGH VOLTAGE (V) 40 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 RECEIVER OUTPUT LOW VOLTAGE (V) 1.8 4.4 4.3 4.2 4.1 4.0 –50 2.0 Figure 15. Output Current vs. Receiver Output Low Voltage 04931-018 35 04931-015 RECEIVER OUTPUT CURRENT (mA) 45 –25 0 25 50 TEMPERATURE (°C) 75 100 125 Figure 18. Receiver Output High Voltage Temperature –5 –10 –15 –20 3.5 4.0 4.5 5.0 RECEIVER OUTPUT HIGH VOLTAGE (V) 5.5 70 60 50 40 30 20 04931-019 0 DRIVER OUTPUT CURRENT (mA) 80 04931-016 RECEIVER OUTPUT CURRENT (mA) 90 5 10 0 0 Figure 16. Output Current vs. Receiver Output High Voltage 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENTIAL OUTPUT VOLTAGE (V) 4.5 5.0 Figure 19. Driver Output Current vs. Differential Output Voltage Rev. 0 | Page 10 of 16 ADM4850–ADM4857 800 120 700 ADM4855 PROPAGATION DELAY (ns) OUTPUT CURRENT (mA) 100 80 60 40 600 500 400 300 200 ADM4853 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 04931-023 04931-020 100 0 –50 5.0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 23. Receiver Propagation Delay vs. Temperature Figure 20. Output Current vs. Driver Low Voltage 3 –30 –50 –70 –90 04931-021 2 –110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 04931-024 OUTPUT CURRENT (mA) –10 4 CH1 1.00VΩBW CH3 2.00VΩBW 5.0 CH2 1.00VΩBW CH4 5.00VΩ M 400ns CH3 2.00V Figure 24. Driver/Receiver Propagation Delay (ADM4855, 500 kbps) Figure 21. Output Current vs. Driver Output High Voltage 450 1 350 ADM4855 300 250 200 150 100 50 ADM4853 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 04931-025 2 04931-022 PROPAGATION DELAY (ns) 400 4 CH1 2.00VΩBW CH3 1.00VΩBW CH2 1.00VΩ CH4 5.00VΩ M 50.0ns CH1 480mV Figure 25. Driver/ Receiver Propagation Delay (ADM4855, 4 Mbps) Figure 22. Driver Propagation Delay vs. Temperature Rev. 0 | Page 11 of 16 ADM4850–ADM4857 CIRCUIT DESCRIPTION The ADM4850–ADM4857 are high speed RS-485/RS-422 transceivers offering enhanced performance over industrystandard devices. All devices in the family contain one driver and one receiver, but offer a choice of performance options. The devices feature true fail-safe operation, which means that a logic high receiver output is guaranteed when the receiver inputs are open-circuit or short-circuit, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe Operation section). RECEIVER INPUT FILTERING SLEW-RATE CONTROL Half-duplex operation implies that the transceiver can transmit and receive, but it can only do one of these at any given time. However, with full-duplex operation, the transceiver can transmit and receive simultaneously. The ADM4850–ADM4853 are half-duplex devices in which the driver and receiver share differential bus terminals. The ADM4854–ADM4857 are fullduplex devices, which have dedicated driver output and receiver input pins. Figure 26 and Figure 27 show typical half- and fullduplex topologies. The ADM4850/ADM4854 feature a controlled slew-rate driver that minimizes electromagnetic interference (EMI) and reduces reflections caused by incorrectly terminated cables, allowing error-free data transmission rates up to 115 kbps. The ADM4851/ ADM4855 offer a higher limit on driver output slew rate, allowing data transmission rates up to 500 kbps. The driver slew rates of the ADM4852/ADM4856 and the ADM4853/ADM4857 are not limited, offering data transmission rates up to 2.5 Mbps and 10 Mbps, respectively. The receivers of all the devices incorporate input hysteresis. In addition, the receivers of the 115 kbps ADM4850/ADM485 and the 500 kbps ADM4851/ADM4855 incorporate input filtering. This enhances noise immunity with differential signals that have very slow rise and fall times. However, it causes the propagation delay to increase by 20%. HALF-/FULL-DUPLEX OPERATION ADM4850/ADM4851/ ADM4852/ADM4853 RO R ADM4850/ADM4851/ ADM4852/ADM4853 R A A RO RE RE DE DE B B B R D RO RE DE DI A D R D RO RE DE DI MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256 Figure 26. Typical Half-Duplex RS-485 Network Topology VDD RO DI A Z B Z Y A Y B ADM4854/ADM4855/ ADM4856/ADM4857 R D D R GND GND Figure 27. Typical Full-Duplex Point-to-Point RS-485 Network Topology Rev. 0 | Page 12 of 16 DI RO 04931-027 VDD ADM4854/ADM4855/ ADM4856/ADM4857 DI B 04931-026 A ADM4850/ADM4851/ ADM4852/ADM4853 D ADM4850/ADM4851/ ADM4852/ADM4853 DI ADM4850–ADM4857 HIGH RECEIVER INPUT IMPEDANCE FAIL-SAFE OPERATION The input impedance of the ADM485x receivers is 96 kΩ, which is 8 times higher than the standard RS-485 unit load of 12 kΩ. This 96 kΩ impedance, enables a standard driver to drive 32 unit loads or be connected to 256 ADM485x receivers. An RS-485 bus, driven by a single standard driver, can be connected to a combination of ADM485x and standard unit load receivers, up to an equivalent of 32 standard unit loads. The ADM4850–ADM4857 offer true fail-safe operation while remaining fully compliant with the ±200 mV EIA/TIA-485 standard. A logic-high receiver output is generated when the receiver inputs are shorted together or open-circuit, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between −30 mV and −200 mV. If the differential receiver input voltage (A-B) is greater than or equal to −30 mV, RO is logic high. If A-B is less than or equal to −200 mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver’s differential input voltage is pulled to 0 V by the ADM485x’s internal circuitry, which results in a logic high with 30 mV minimum noise margin. THREE-STATE BUS CONNECTION The half-duplex parts have a driver enable (DE) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the halfduplex devices have an active-low receiver enable (RE) pin. Taking this pin low enables the receiver, while taking it high puts the receiver outputs into a high impedance state. This allows several driver outputs to be connected to an RS-485 bus. Note that only one driver should be enabled at a time, while many receivers can be enabled. SHUTDOWN MODE The ADM4850–ADM4853 have a low power shutdown mode, which is enabled by taking RE high and DE low. If shutdown mode is not used, the fact that DE is active high and RE is active low offers a convenient way of switching the device between transmit and receive by tying DE and RE together. CURRENT LIMIT AND THERMAL SHUTDOWN The ADM485x incorporates two protection mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current-limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 mA. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150°C, and does not turn them back on until the temperature falls to 130°C. The devices are guaranteed not to enter shutdown mode if DE and RE are driven in this way. If DE is low and RE is high for less than 50 ns, the device does not enter shutdown mode. If DE is low and RE is high for less than 3000 ns, the device is guaranteed to enter shutdown mode. Rev. 0 | Page 13 of 16 ADM4850–ADM4857 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 4 6.20 (0.2440) 5.80 (0.2284) 3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 0.45 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 0.50 (0.0196) × 45° 0.25 (0.0099) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) PIN 1 INDICATOR 0.90 0.85 0.80 COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN SEATING PLANE Figure 28. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) TOP VIEW 2.75 BSC SQ 0.50 BSC 0.25 MIN 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 1.50 REF EXPOSED PAD (BOTTOM VIEW) 5 4 1.60 1.45 1.30 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP] (CP-8-2) Dimensions shown in millimeters Rev. 0 | Page 14 of 16 1.90 1.75 1.60 ADM4850–ADM4857 ORDERING GUIDE Model ADM4850ACP-REEL ADM4850ACP-REEL7 ADM4850AR ADM4850AR-REEL ADM4850AR-REEL7 ADM4851ACP-REEL ADM4851ACP-REEL7 ADM4851AR ADM4851AR-REEL ADM4851AR-REEL7 ADM4852ACP-REEL ADM4852ACP-REEL7 ADM4852AR ADM4852AR-REEL ADM4852AR-REEL7 ADM4853ACP-REEL ADM4853ACP-REEL7 ADM4853AR ADM4853AR-REEL ADM4853AR-REEL7 ADM4854AR ADM4855AR ADM4855AR-REEL ADM4855AR-REEL7 ADM4856AR ADM4856AR-REEL ADM4856AR-REEL7 ADM4857AR ADM4857AR-REEL ADM4857AR-REEL7 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package Rev. 0 | Page 15 of 16 Package Type CP-8-2 CP-8-2 R-8 R-8 R-8 CP-8-2 CP-8-2 R-8 R-8 R-8 CP-8-2 CP-8-2 R-8 R-8 R-8 CP-8-2 CP-8-2 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 Branding M0R M0R M0S M0S M0T M0T M0U M0U ADM4850–ADM4857 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04931–0–10/04(0) Rev. 0 | Page 16 of 16