FEATURES FUNCTIONAL BLOCK DIAGRAMS VCC Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs) Switching rate: 200 Mbps (100 MHz) Supported bus loads: 30 Ω to 55 Ω Choice of 2 receiver types Type 1 (ADN4691E/ADN4693E): hysteresis of 25 mV Type 2 (ADN4696E/ADN4697E): threshold offset of 100 mV for open-circuit and bus-idle fail-safe Conforms to TIA/EIA-899 standard for M-LVDS Glitch-free power-up/power-down on M-LVDS bus Controlled transition times on driver output Common-mode range: −1 V to +3.4 V, allowing communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off Enhanced ESD protection on bus pins ±15 kV HBM (human body model), air discharge ±8 kV HBM (human body model), contact discharge ±10 kV IEC 61000-4-2, air discharge ±8 kV IEC 61000-4-2, contact discharge Operating temperature range: −40°C to +85°C Available in 8-lead (ADN4691E/ADN4696E) and 14-lead (ADN4693E/ADN4697E) SOIC packages ADN4691E/ ADN4696E RO R RE A B DE D 10355-001 DI GND Figure 1. VCC ADN4693E/ ADN4697E RO R A B RE DE DI D GND Z Y 10355-002 Data Sheet 3.3 V, 200 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers ADN4691E/ADN4693E/ADN4696E/ADN4697E Figure 2. APPLICATIONS Backplane and cable multipoint data transmission Multipoint clock distribution Low power, high speed alternative to shorter RS-485 links Networking and wireless base station infrastructure GENERAL DESCRIPTION The ADN4691E/ADN4693E/ADN4696E/ADN4697E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 200 Mbps (100 MHz). The receivers detect the bus state with a differential input of as little as 50 mV over a common-mode voltage range of −1 V to +3.4 V. ESD protection of up to ±15 kV is implemented on the bus pins. The parts adhere to the TIA/EIA-899 standard for M-LVDS and complement TIA/EIA644 LVDS devices with additional multipoint capabilities. The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of hysteresis, so that slow-changing signals or loss of input does not lead to output oscillations. The ADN4696E/ADN4697E are Type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe). The parts are available as half-duplex in an 8-lead SOIC package (the ADN4691E/ADN4696E) or as full-duplex in a 14-lead SOIC package (the ADN4693E/ADN4697E). A selection table for the ADN469xE parts is shown in Table 1. Table 1. ADN469xE Selection Table Part No. ADN4690E ADN4691E ADN4692E ADN4693E ADN4694E ADN4695E ADN4696E ADN4697E Receiver Type 1 Type 1 Type 1 Type 1 Type 2 Type 2 Type 2 Type 2 Data Rate 100 Mbps 200 Mbps 100 Mbps 200 Mbps 100 Mbps 100 Mbps 200 Mbps 200 Mbps SOIC 8-lead 8-lead 14-lead 14-lead 8-lead 14-lead 8-lead 14-lead Duplex Half Half Full Full Half Full Half Full Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Voltage and Current Measurements............................ 11 Applications....................................................................................... 1 Driver Timing Measurements .................................................. 12 Functional Block Diagrams............................................................. 1 Receiver Timing Measurements............................................... 13 General Description ......................................................................... 1 Theory of Operation ...................................................................... 14 Revision History ........................................................................... 2 Half-Duplex/Full-Duplex Operation....................................... 14 Specifications..................................................................................... 3 Three-State Bus Connection..................................................... 14 Receiver Input Threshold Test Voltages .................................... 4 Truth Tables................................................................................. 14 Timing Specifications .................................................................. 5 Glitch-Free Power-Up/Power-Down....................................... 15 Absolute Maximum Ratings............................................................ 6 Fault Conditions ......................................................................... 15 Thermal Resistance ...................................................................... 6 Receiver Input Thresholds/Fail-Safe........................................ 15 ESD Caution.................................................................................. 6 Applications Information .............................................................. 16 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 17 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 17 Test Circuits and Switching Characteristics................................ 11 REVISION HISTORY 3/12—Rev. 0 to Rev. A Added ADN4691E and ADN4693E................................. Universal Changes to Features Section, General Description Section, and Table 1..........................................................................................1 Added Type 1 Receiver Parameters, Table 2 ..................................3 Added Table 3, Renumbered Sequentially .....................................4 Added Type 1 Receiver Parameters, Table 5 ..................................5 Added Table 7.....................................................................................6 Changes to Table 8.............................................................................7 Changes to Figure 33.......................................................................13 Added Table 12 ................................................................................14 Changes to Receiver Input Thresholds/Fail-Safe Section and Figure 36....................................................................................15 Changes to Ordering Guide ...........................................................17 12/11—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E SPECIFICATIONS VCC = 3.0 V to 3.6 V; RL = 50 Ω; TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DRIVER Differential Outputs Differential Output Voltage Magnitude ∆|VOD| for Complementary Output States Common-Mode Output Voltage (Steady State) ΔVOC(SS) for Complementary Output States Peak-to-Peak VOC Maximum Steady-State Open-Circuit Output Voltage Voltage Overshoot Low to High High to Low Output Current Short Circuit High Impedance State, Driver Only Power Off Output Capacitance Differential Output Capacitance Output Capacitance Balance (CY/CZ) Logic Inputs (DI, DE) Input High Voltage Input Low Voltage Input High Current Input Low Current RECEIVER Differential Inputs Differential Input Threshold Voltage Type 1 Receiver (ADN4691E, ADN4693E) Type 2 Receiver (ADN4696E, ADN4697E) Input Hysteresis Type 1 Receiver (ADN4691E, ADN4693E) Type 2 Receiver (ADN4696E, ADN4697E) Differential Input Voltage Magnitude Input Capacitance Differential Input Capacitance Input Capacitance Balance (CA/CB) Logic Output RO Output High Voltage Output Low Voltage High Impedance Output Current Logic Input RE Input High Voltage Input Low Voltage Input High Current Input Low Current Symbol Min |VOD| ∆|VOD| VOC(SS) ΔVOC(SS) VOC(PP) VA(O), VB(O), VY(O), or VZ(O) 480 −50 0.8 −50 Typ 0 Max Unit Test Conditions/Comments 650 +50 1.2 +50 150 2.4 mV mV V mV mV V See Figure 19 See Figure 19 See Figure 20, Figure 23 See Figure 20, Figure 23 See Figure 20, Figure 23 See Figure 21 1.2VSS V V See Figure 24, Figure 27 See Figure 24, Figure 27 VPH VPL −0.2VSS |IOS| IOZ −15 24 +10 mA μA IO(OFF) −10 +10 μA CYZ CY/Z pF 0.99 2.5 1.01 See Figure 22 –1.4 V ≤ (VY or VZ) ≤ 3.8 V, other output = 1.2 V –1.4 V ≤ (VY or VZ) ≤ 3.8 V, other output = 1.2 V, 0 V ≤ VCC ≤ 1.5 V VI = 0.4 sin(30e6πt) V + 0.5 V, 2 other output = 1.2 V, DE = 0 V VAB = 0.4 sin(30e6πt) V,2 DE = 0 V VIH VIL IIH IIL 2 GND 0 0 VCC 0.8 10 10 V V μA μA VIH = 2 V VIL = 0.8 V VTH VTH −50 50 +50 150 mV mV See Table 3, Figure 36 See Table 4, Figure 36 CY or CZ VHYS VHYS |VID| CA or CB CAB CA/B 3 pF 25 0 0.05 VCC 3 0.99 2.5 1.01 VOH VOL IOZ 2.4 −10 0.4 +15 VIH VIL IIH IIL 2 GND −10 −10 VCC 0.8 0 0 Rev. A | Page 3 of 20 mV mV V pF pF VI = 0.4 sin(30e6πt) V + 0.5 V,2 other input = 1.2 V VAB = 0.4 sin(30e6πt) V2 V V μA IOH = –8 mA IOL = 8 mA VO = 0 V or 3.6 V V V μA μA VIH = 2 V VIL = 0.8 V ADN4691E/ADN4693E/ADN4696E/ADN4697E Parameter BUS INPUT/OUTPUT Input Current A (Receiver or Transceiver with Driver Disabled) B (Receiver or Transceiver with Driver Disabled) Differential (Receiver or Transceiver with Driver Disabled) Power-Off Input Current A (Receiver or Transceiver) B (Receiver or Transceiver) Differential Input Capacitance (Transceiver with Driver Disabled) Input Capacitance Balance (CA/CB) (Transceiver with Driver Disabled) POWER SUPPLY Supply Current Only Driver Enabled Both Driver and Receiver Disabled Both Driver and Receiver Enabled Only Receiver Enabled 2 Min IA IB IAB IA(OFF) IB(OFF) Differential (Receiver or Transceiver) Input Capacitance (Transceiver with Driver Disabled) 1 Symbol IAB(OFF) CA or CB Data Sheet Typ Max Unit Test Conditions/Comments 0 −20 −32 0 −20 −32 −4 32 +20 0 32 +20 0 +4 μA μA μA μA μA μA μA VB = 1.2 V, VA = 3.8 V VB = 1.2 V, VA = 0 V or 2.4 V VB = 1.2 V, VA = −1.4 V VA = 1.2 V, VB = 3.8 V VA = 1.2 V, VB = 0 V or 2.4 V VA = 1.2 V, VB = −1.4 V VA = VB, 1.4 V ≤ VA ≤ 3.8 V 0 −20 −32 0 −20 −32 −4 32 +20 0 32 +20 0 +4 μA μA μA μA μA μA μA pF 3 pF 5 CAB CA/B 0.99 1.01 0 V ≤ VCC ≤ 1.5 V VB = 1.2 V, VA = 3.8 V VB = 1.2 V, VA = 0 V or 2.4 V VB = 1.2 V, VA = −1.4 V VA = 1.2 V, VB = 3.8 V VA = 1.2 V, VB = 0 V or 2.4 V VA = 1.2 V, VB = −1.4 V VA = VB, 1.4 ≤ VA ≤ 3.8 V VI = 0.4 sin(30e6πt) V + 0.5 V,2 other input = 1.2 V, DE = 0 V VAB = 0.4 sin(30e6πt) V,2 DE = 0 V DE = 0 V ICC 13 1 16 4 22 4 24 13 mA mA mA mA DE, RE = VCC, RL = 50 Ω DE = 0 V, RE= VCC, RL = no load DE = VCC, RE = 0 V, RL = 50 Ω DE, RE = 0 V, RL = 50 Ω All typical values are given for VCC = 3.3 V and TA = 25°C. HP4194A impedance analyzer (or equivalent). RECEIVER INPUT THRESHOLD TEST VOLTAGES RE = 0 V, H = high, L = low Table 3. Test Voltages for Type 1 Receiver Applied Voltages VA (V) VB (V) 2.4 0 0 2.4 3.8 3.75 3.75 3.8 −1.35 −1.4 −1.4 −1.35 Input Voltage, Differential VID (V) 2.4 −2.4 0.05 −0.05 0.05 −0.05 Input Voltage, Common Mode VIC (V) 1.2 1.2 3.775 3.775 −1.375 −1.375 Rev. A | Page 4 of 20 Receiver Output RO (V) H L H L H L Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E Table 4. Test Voltages for Type 2 Receiver VA (V) +2.4 0 +3.8 +3.8 −1.25 −1.35 Applied Voltages VB (V) 0 +2.4 +3.65 +3.75 −1.4 −1.4 Input Voltage, Differential VID (V) +2.4 −2.4 +0.15 +0.05 +0.15 +0.05 Input Voltage, Common Mode VIC (V) +1.2 +1.2 +3.725 +3.775 −1.325 −1.375 Receiver Output RO (V) H L H L H L TIMING SPECIFICATIONS VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted. 1 Table 5. Parameter DRIVER Maximum Data Rate Propagation Delay Differential Output Rise/Fall Time Pulse Skew |tPHL – tPLH| Part-to-Part Skew 2 Period Jitter, RMS (1 Standard Deviation) 3 Peak-to-Peak Jitter3, 5 Disable Time from High Level Disable Time from Low Level Enable Time to High Level Enable Time to Low Level RECEIVER Propagation Delay Rise/Fall Time Pulse Skew |tRPHL – tRPLH| Type 1 Receiver (ADN4691E, ADN4693E) Type 2 Receiver (ADN4696E, ADN4697E) Part-to-Part Skew2 Period Jitter, RMS (1 Standard Deviation)3 Peak-to-Peak Jitter3, 5 Type 1 Receiver (ADN4691E, ADN4693E) Type 2 Receiver (ADN4696E, ADN4697E) Disable Time from High Level Disable Time from Low Level Enable Time to High Level Enable Time to Low Level Symbol tPLH, tPHL tR, tF tSK tSK(PP) tJ(PER) tJ(PP) tPHZ tPLZ tPZH tPZL tRPLH, tRPHL tR, tF tSK tSK(PP) tJ(PER) tJ(PP) tJ(PP) tRPHZ tRPLZ tRPZH tRPZL Min Typ Max Unit Test Conditions/Comments 200 1 1 1.5 2.4 1.6 100 1 3 130 7 7 7 7 Mbps ns ns ps ns ps ps ns ns ns ns See Figure 24, Figure 27 See Figure 24, Figure 27 See Figure 24, Figure 27 See Figure 24, Figure 27 100 MHz clock input 4 (see Figure 26) 200 Mbps 215 − 1 PRBS input 6 (see Figure 29) See Figure 25, Figure 28 See Figure 25, Figure 28 See Figure 25, Figure 28 See Figure 25, Figure 28 4 6 2.3 ns ns 100 300 ps 300 500 ps 4 1 7 ns ps 300 700 ps 450 800 ps 10 10 15 15 ns ns ns ns 0 2 30 2 1 1 CL = 15 pF (see Figure 30, Figure 33) CL = 15 pF (see Figure 30, Figure 33) CL = 15 pF (see Figure 30, Figure 33) CL = 15 pF (see Figure 30, Figure 33) 100 MHz clock input 7 (see Figure 32) 200 Mbps 215 − 1 PRBS input 8 (see Figure 35) See Figure 31, Figure 34 See Figure 31, Figure 34 See Figure 31, Figure 34 See Figure 31, Figure 34 All typical values are given for VCC = 3.3 V and TA = 25°C. tSK(PP) is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC and temperature, and with identical packages and test circuits. 3 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. 4 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples. 5 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK). 6 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples. 7 |VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples. 8 |VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples. 2 Rev. A | Page 5 of 20 ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, unless otherwise noted. THERMAL RESISTANCE Table 6. Parameter VCC Digital Input Voltage (DE, RE, DI) Receiver Input (A, B) Voltage Half-Duplex (ADN4691E, ADN4696E) Full-Duplex (ADN4693E, ADN4697E) Receiver Output Voltage (RO) Driver Output (A, B, Y, Z) Voltage ESD Rating (A, B, Y, Z Pins) HBM (Human Body Model) Air Discharge Contact Discharge IEC 61000-4-2, Air Discharge IEC 61000-4-2, Contact Discharge ESD Rating (Other Pins, HBM) ESD Rating (All Pins) FICDM Machine Model Operating Temperature Range Storage Temperature Range θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.5 V to +4 V −0.5 V to +4 V Table 7. Thermal Resistance Package Type 8-Lead SOIC 14-Lead SOIC −1.8 V to +4 V −4 V to +6 V −0.3 V to +4 V −1.8 V to +4 V ESD CAUTION ±15 kV ±8 kV ±10 kV ±8 kV ±4 kV ±1.25 kV ±400 V −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 20 θJA 121 86 Unit °C/W °C/W Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RE 3 DE 4 RE 2 DE 3 DI 4 ADN4693E/ ADN4697E TOP VIEW (Not to Scale) 13 VCC 12 A 11 B ADN4691E/ ADN4696E 8 VCC 7 B GND 6 9 Y TOP VIEW (Not to Scale) 6 A GND 7 8 NC 5 GND DI 5 10355-003 RO 1 14 VCC 10 Z NC = NO CONNECT 10355-004 NC 1 RO 2 Figure 4. ADN4693E/ADN4697E Pin Configuration Figure 3. ADN4691E/ADN4696E Pin Configuration Table 8. Pin Function Descriptions ADN4691E/ ADN4696E Pin No. 1 ADN4693E/ ADN4697E Pin No. 2 Mnemonic RO 2 3 RE 3 4 DE 4 5 DI 5 N/A N/A 6 N/A 7 N/A 8 N/A 6, 7 9 10 N/A 12 N/A 11 13, 14 1, 8 GND Y Z A A B B VCC NC Description Receiver Output. Type 1 receiver (ADN4691E/ADN4693E), when enabled: If A − B ≥ 50 mV, then RO = logic high. If A − B ≤ −50 mV, then RO = logic low. Type 2 receiver (ADN4696E/ADN4697E), when enabled: If A − B ≥ 150 mV, then RO = logic high. If A − B ≤ 50 mV, then RO = logic low. Receiver output is undefined outside these conditions. Receiver Output Enable. A logic low on this pin enables the receiver output, RO. A logic high on this pin places RO in a high impedance state. Driver Output Enable. A logic high on this pin enables the driver differential outputs. A logic low on this pin places the driver differential outputs in a high impedance state. Driver Input. Half-duplex (ADN4691E/ADN4696E), when enabled: A logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low. Full-duplex (ADN4693E/ADN4697E), when enabled: A logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low. Ground. Noninverting Driver Output Y. Inverting Driver Output Z. Noninverting Receiver Input A and Noninverting Driver Output A. Noninverting Receiver Input A. Inverting Receiver Input B and Inverting Driver Output B. Inverting Receiver Input B. Power Supply (3.3 V ± 0.3 V). No Connect. Do not connect to these pins. Rev. A | Page 7 of 20 ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 16 DRIVER 14 12 10 8 6 RECEIVER (VID = 250mV, VIC = 1V) 4 0 20 40 60 80 100 120 FREQUENCY (MHz) –20 –25 –30 –35 –40 –45 –50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 RECEIVER HIGH LEVEL OUTPUT VOLTAGE, VOH (V) Figure 8. Receiver Output Current vs. Output Voltage (Output High) (TA = 25°C) 2.0 DIFFERENTIAL OUTPUT VOLTAGE, VOD (V) 20 18 SUPPLY CURRENT, ICC (mA) –15 0 Figure 5. Power Supply Current (ICC) vs. Frequency (VCC = 3.3 V, TA = 25°C; Receiver VID = 250 mV, VIC = 1 V) DRIVER 16 14 12 10 RECEIVER (VID = 250mV, VIC = 1V) 8 6 4 0 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10355-006 2 0 2 2.4 DRIVER PROPAGATION DELAY (ns) 35 30 25 20 15 10 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 RECEIVER LOW LEVEL OUTPUT VOLTAGE, VOL (V) 4.0 8 10 12 2.2 2.0 1.8 1.6 1.4 1.2 –20 0 20 40 60 TEMPERATURE, TA (°C) Figure 10. Driver Propagation Delay vs. Temperature (Data Rate = 2 Mbps, VCC = 3.3 V) Figure 7. Receiver Output Current vs. Output Voltage (Output Low) (TA = 25°C) Rev. A | Page 8 of 20 14 tPHL tPLH 1.0 –40 10355-007 0 6 Figure 9. Driver Differential Output Voltage vs. Output Current (VCC = 3.3 V, TA = 25°C) 40 VCC = 3V VCC = 3.3V VCC = 3.6V 4 OUTPUT CURRENT, IO (mA) Figure 6. Power Supply Current vs. Temperature (Data Rate = 200 Mbps, VCC = 3.3 V; Receiver VID = 250 mV, VIC = 1 V) RECEIVER LOW LEVEL OUTPUT CURRENT, IOL (mA) –10 10355-009 0 10355-005 2 VCC = 3.0V VCC = 3.3V VCC = 3.6V –5 80 10355-010 SUPPLY CURRENT, ICC (mA) 18 0 10355-008 RECEIVER HIGH LEVEL OUTPUT CURRENT (mA) 20 Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E 120 5.0 4.5 4.0 3.5 3.0 2.5 2.0 –50 –30 –10 10 30 50 70 90 TEMPERATURE, TA (°C) 100 80 60 40 20 0 –50 30 50 70 90 2.5 2.0 1.5 1.0 0.5 30 40 50 60 70 80 90 100 FREQUENCY (MHz) 5 4 3 2 1 0 0 ADDED RECEIVER PEAK–TO–PEAK JITTER (ps) 100 80 60 40 60 80 100 120 140 160 180 DATA RATE (Mbps) 200 10355-013 20 40 60 80 100 120 Figure 15. Receiver Jitter (Period) vs. Frequency (VCC = 3.3 V, TA = 25°C, VID = 400 mV) 120 20 40 FREQUENCY (MHz) Figure 12. Driver Jitter (Period) vs. Frequency (VCC = 3.3 V, TA = 25°C, Clock Input) 0 20 800 700 600 500 400 300 200 100 0 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) Figure 16. Receiver Jitter (Peak-to-Peak) vs. Temperature (Data Rate = 200 Mbps, VCC = 3.3 V, VID = 400 mV, VIC = 1.1 V, PRBS 215 − 1 Input) Figure 13. Driver Jitter (Peak-to-Peak) vs. Data Rate (VCC = 3.3 V, TA = 25°C, PRBS 215 − 1 Input) Rev. A | Page 9 of 20 10355-016 0 20 6 10355-015 ADDED RECEIVER PERIOD JITTER (ps) 7 10355-012 ADDED DRIVER PERIOD JITTER (ps) 10 Figure 14. Driver Jitter (Peak-to-Peak) vs. Temperature (Data Rate = 200 Mbps, VCC = 3.3 V, PRBS 215 − 1 Input) 3.0 ADDED DRIVER PEAK-TO-PEAK JITTER (ps) –10 TEMPERATURE, TA (°C) Figure 11. Receiver Propagation Delay vs. Temperature (Data Rate = 2 Mbps, VCC = 3.3 V, VID = 400 mV, VIC = 1.1 V) 0 –30 10355-014 5.5 ADDED DRIVER PEAK-TO-PEAK JITTER (ps) tRPLH tRPHL 10355-011 RECEIVER PROPAGATION DELAY (ns) 6.0 Data Sheet 10355-018 10355-017 500mV/DIV 200mV/DIV ADN4691E/ADN4693E/ADN4696E/ADN4697E 1ns/DIV 2.5ns/DIV Figure 17. ADN4696E Driver Output Eye Pattern (Data Rate = 200 Mbps, PRBS 215 − 1 Input, RL = 50 Ω) Figure 18. ADN4696E Receiver Output Eye Pattern (Data Rate = 200 Mbps, PRBS 215 − 1 Input, CL = 15 pF) Rev. A | Page 10 of 20 Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E TEST CIRCUITS AND SWITCHING CHARACTERISTICS DRIVER VOLTAGE AND CURRENT MEASUREMENTS A/Y 3.32kΩ VOD DI IOS VCC 49.9Ω + 3.32kΩ B/Z A/Y VTEST –1V TO +3.4V S1 DI S2 – 10355-022 10355-019 NOTES 1. 1% TOLERANCE FOR ALL RESISTORS Figure 19. Driver Voltage Measurement over Common-Mode Range A/Y C1 1pF R1 24.9Ω –1V OR +3.4V VTEST B/Z Figure 22. Driver Short Circuit A/Y ≈ 1.3V B/Z ≈ 0.7V DI C3 2.5pF VOC VOC C2 1pF Figure 20. Driver Common-Mode Output Voltage Measurement Figure 23. Driver Common-Mode Output Voltage (Steady State) VCC A/Y S1 S2 VA(O), VB(O), VY(O) OR VZ(O) R1 1.62kΩ ±1% 10355-021 DE B/Z ∆VOC(SS) NOTES 1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUT Y CYCLE; tR, tF ≤ 1ns. 2. VOC(PP) MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz. 10355-020 NOTES 1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY CAPACITANCE LESS THAN 2cm FROM DUT. 2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT, LESS THAN 2cm FROM DUT. VOC(PP) Figure 21. Maximum Steady-State Output Voltage Measurement Rev. A | Page 11 of 20 10355-023 R2 24.9Ω B/Z ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet DRIVER TIMING MEASUREMENTS VCC DI R1 50Ω 0V B/Z 0.5VCC tPLH tPHL VSS C2 1pF 90% VSS OUT 10355-024 NOTES 1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY CAPACITANCE LESS THAN 2cm FROM DUT. 2. R1 IS 1%, METAL FILM, SURFACE MOUNT, LESS THAN 2cm FROM DUT. 0% VSS 90% VSS 0V 0V 10% VSS VPH 10% VSS VPL tR Figure 24. Driver Timing Measurement tF NOTES 1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUT Y CYCLE; tR, tF ≤ 1ns. 2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz. VCC C1 1pF A/Y DI S1 0.5VCC DI C3 0.5pF OUT DE C4 0.5pF OUT B/Z Figure 27. Driver Propagation, Rise/Fall Times and Voltage Overshoot R1 24.9Ω R2 24.9Ω 10355-027 C1 1pF A/Y VCC C3 2.5pF DE C2 1pF 0.5VCC 0.5VCC tPZL tPLZ 0V 0V OUT (DI = 0V) 10355-025 NOTES 1. C1, C2, C3, AND C4 ARE 20% AND INCLUDE PROBE/STRAY CAPACITANCE LESS THAN 2cm FROM DUT. 2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT, LESS THAN 2cm FROM DUT. –0.1V –0.1V ~ –0.6V tPZH Figure 25. Driver Enable/Disable Time tPHZ ~ 0.6V OUT (DI = VCC) VCC 0.1V 0V VCC/2 VCC/2 NOTES 1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUT Y CYCLE; tR, tF ≤ 1ns. 2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz. 0V 1/f0 10355-028 INPUT (CLOCK) 0.1V Figure 28. Driver Enable/Disable Times OUTPUT VA – VB OR VY – VZ (IDEAL) VCC 0V 0V INPUT (PRBS) 0.5VCC 0V 1/f0 OUTPUT VA – VB OR VY – VZ (ACTUAL ) 0.5VCC VA – VB OR VY – VZ 0V OUTPUT 0V VA – VB OR VY – VZ tc(n) 0V 0V tJ(PP) NOTES 1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM; 200Mbps; 215 – 1PRBS. 2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE. Figure 29. Driver Peak-to-Peak Jitter Characteristics Figure 26. Driver Period Jitter Characteristics Rev. A | Page 12 of 20 10355-029 NOTES 1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM; 100MHz; 50% ± 1% DUTY CYCLE. 2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE. 10355-026 tJ(PER) = |tc(n) – 1/f0| Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E RECEIVER TIMING MEASUREMENTS A RO VID B RE CL 15pF VA VOUT VB 10355-030 NOTES 1. CL IS 20%, CERAMIC, SURFACE MOUNT, AND INCLUDES PROBE/STRAY CAPACITANCE < 2cm FROM DUT. Figure 30. Receiver Timing Measurement 0V VID 0V 1.4V B RE VOH CL 15pF RE INPUT tRPHL RL 499Ω RO 1.0V 1.2V VOUT VTEST tRPLH 90% 90% VOUT 0.5VCC 10% VOL 0.5VCC 10% tF tR NOTES 1. INPUT PULSE GENERATOR: 50MHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns. 2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz. 10355-031 NOTES 1. CL IS 20% AND INCLUDES PROBE/STRAY CAPACITANCE < 2cm FROM DUT. 2. RL IS 1% METAL FILM, SURFACE MOUNT, <2cm FROM DUT. 10355-033 A Figure 33. Receiver Propagation and Rise/Fall Times Figure 31. Receiver Enable/Disable Time VCC INPUT (VA – VB) RE INPUT 0V 0.5VCC 0.5VCC 0V tRPZL 1/f0 tRPLZ VOUT (VTEST = VCC) (A = 1V) VOH OUTPUT (IDEAL) 0.5VCC 0.5VCC 0.5VCC tRPZH VOL VOUT (VTEST = 0V) (A = 1.4V) 1/f0 VCC VOL + 0.5V VOL tRPHZ 0.5VCC VOH – 0.5V VOH OUTPUT (ACTUAL) 0.5VCC NOTES 1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUT Y CYCLE; tR, tF ≤ 1ns. 0.5VCC 10355-034 0V VOH Figure 34. Receiver Enable/Disable Times VOL tc(n) VA tJ(PER) = |tc(n) – 1f0| VB VOH OUTPUT 0.5VCC 0.5VCC VOL tJ(PP) NOTES 1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM; 200Mbps; 215 – 1PRBS. 2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE. Figure 35. Receiver Peak-to-Peak Jitter Characteristics Rev. A | Page 13 of 20 10355-035 Figure 32. Receiver Period Jitter Characteristics INPUT (PRBS) 10355-032 NOTES 1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM; 100MHz; 50% ± 1% DUTY CYCLE. 2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE. ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet THEORY OF OPERATION The ADN4691E/ADN4693E/ADN4696E/ADN4697E are transceivers for transmitting and receiving multipoint, low voltage differential signaling (M-LVDS) at high speed (data rates up to 200 Mbps). Each device has a differential line driver and a differential line receiver, allowing each device to send and receive data. Multipoint LVDS expands on the established LVDS low voltage differential signaling method by allowing bidirectional communication between more than two nodes. Up to 32 nodes can be connected on an M-LVDS bus. Driver, Half Duplex (ADN4691E/ADN4696E) Table 10. Transmitting (See Table 9 for Abbreviations) Power Yes Yes Yes Yes Yes ≤1.5 V DE H H H L NC X Inputs DI H L NC X X X A H L L Z Z Z Outputs B L H H Z Z Z HALF-DUPLEX/FULL-DUPLEX OPERATION Half-duplex operation allows a transceiver to transmit or receive, but not both at the same time. However, with fullduplex operation, a transceiver can transmit and receive simultaneously. The ADN4691E/ADN4696E are half-duplex devices in which the driver and the receiver share differential bus terminals. The ADN4693E/ADN4697E are full-duplex devices that have dedicated driver output and receiver input pins. Figure 37 and Figure 38 show typical half- and full-duplex bus topologies, respectively, for M-LVDS. THREE-STATE BUS CONNECTION The outputs of the device can be placed in a high impedance state by disabling the driver or receiver. This allows several driver outputs to be connected to a single M-LVDS bus. Note that, on each bus line, only one driver can be enabled at a time, but many receivers can be enabled at the same time. The driver can be enabled or disabled using the driver enable pin (DE). DE enables the driver outputs when taken high; when taken low, DE puts the driver outputs into a high impedance state. Similarly, an active low receiver enable pin (RE) controls the receiver. Taking RE low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state. Truth tables for driver and receiver output states under various conditions are shown in Table 10, Table 11, Table 12 and Table 13. TRUTH TABLES Driver, Full Duplex (ADN4693E/ADN4697E) Table 11. Transmitting (See Table 9 for Abbreviations) Power Yes Yes Yes Yes Yes ≤1.5 V Y H L L Z Z Z Outputs Z L H H Z Z Z Type 1 Receiver (ADN4691E/ADN4693E) Table 12. Receiving (see Table 9 for Abbreviations) Inputs Power Yes Yes Yes Yes Yes Yes No A−B RE Output RO ≥50 mV ≤−50 mV −50 mV < A − B < 50 mV NC X X X L L L L H NC X H L I I Z Z Z Type 2 Receiver (ADN4696E/ADN4697E) Table 13. Receiving (See Table 9 for Abbreviations) Inputs Table 9. Truth Table Abbreviations Abbreviation H L X I Z NC DE H H H L NC X Inputs DI H L NC X X X Description High level Low level Don’t care Indeterminate High impedance (off ) Disconnected Power Yes Yes Yes Yes Yes Yes No Rev. A | Page 14 of 20 A−B ≥150 mV ≤50 mV 50 mV < A − B < 150 mV NC X X X Output RE L L L L H NC X RO H L I L Z Z Z ADN4691E/ADN4693E/ADN4696E/ADN4697E To minimize disruption to the bus when adding nodes, the M-LVDS outputs of the device are kept glitch-free when the device is powering up or down. This feature allows insertion of devices onto a live M-LVDS bus because the bus outputs are not switched on before the device is fully powered. In addition, all outputs are placed in a high impedance state when the device is powered off. Type 2 receivers (ADN4696E/ADN4697E) have an open circuit and bus-idle fail-safe. The input threshold is offset by 100 mV so that a logic low is present on the receiver output when the bus is idle or when the receiver inputs are open. The different receiver thresholds for the two receiver types are illustrated in Figure 36. See Table 12 and Table 13 for receiver output states under various conditions. FAULT CONDITIONS The ADN4691E/ADN4693E/ADN4696E/ADN4697E contain short-circuit current protection that protects the part under fault conditions in the case of short circuits on the bus. This protection limits the current in a fault condition to 24 mA at the transmitter outputs for short-circuit faults between −1 V and +3.4 V. Any network fault must be cleared to avoid data transmission errors and to ensure reliable operation of the data network and any devices that are connected to the network. RECEIVER INPUT THRESHOLDS/FAIL-SAFE Two receiver types are available, both of which incorporate protection against short circuits. The Type 1 receivers of the ADN4691E/ADN4693E incorporate 25 mV of hysteresis. This ensures that slow-changing signals or a loss of input does not result in oscillation of the receiver output. Type 1 receiver thresholds are ±50 mV; therefore, the state of the receiver output is indeterminate if the differential between A and B is about 0 V. This state occurs if the bus is idle (approximately 0 V on both A and B), with no drivers enabled on the attached nodes. Rev. A | Page 15 of 20 0.25 TYPE 1 RECEIVER OUTPUT TYPE 2 RECEIVER OUTPUT LOGIC 1 LOGIC 1 0.15 UNDEFINED 0.05 0 UNDEFINED –0.05 –0.15 LOGIC 0 LOGIC 0 10355-036 GLITCH-FREE POWER-UP/POWER-DOWN DIFFERENTIAL INPUT VOLTAGE (VIA – VIB) [V] Data Sheet Figure 36. Input Threshold Voltages ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet APPLICATIONS INFORMATION M-LVDS extends the low power, high speed, differential signaling of LVDS (low voltage differential signaling) to multipoint systems where multiple nodes are connected over short distances in a bus topology network. With M-LVDS, a transmitting node drives a differential signal across a transmission medium such as a twisted pair cable. The transmitted differential signal allows other receiving nodes that are connected along the bus to detect a differential voltage that can then be converted back into a single-ended logic signal by the receiver. The communication line is typically terminated at both ends by resistors (RT), the value of which is chosen to match the characteristic impedance of the medium (typically 100 Ω). For half-duplex multipoint applications such as the one shown in Figure 37, only one driver can be enabled at any time. Fullduplex nodes allow a master-slave topology as shown in Figure 38. In this configuration, a master node can concurrently send and receive data to/from slave nodes. At any time, only one slave node can have its driver enabled to concurrently transmit data back to the master node. RT RT A B A B ADN4696E R D RO RE DE DI A B ADN4696E R DI B ADN4696E R D RO RE DE A D RO RE DE DI ADN4696E R D RO RE DE DI 10355-037 NOTES 1. MAXIMUM NUMBER OF NODES: 32. 2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED. Figure 37. ADN4696E Typical Half-Duplex M-LVDS Network (Type 2 Receivers with Threshold Offset for Bus-Idle Fail-Safe) RT RT RT RT MASTER A B Z Y ADN4697E R RO RE DE D DI SLAVE A B Z Y ADN4697E R RO RE DE SLAVE ADN4697E R D DI A B Z Y RO RE DE D DI SLAVE ADN4697E R RO RE DE D DI NOTES 1. MAXIMUM NUMBER OF NODES: 32. 2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED. Figure 38. ADN4697E Typical Full-Duplex M-LVDS Master-Slave Network (Type 2 Receivers with Threshold Offset for Bus-Idle Fail-Safe) Rev. A | Page 16 of 20 10355-038 A B Z Y Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 39. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 060606-A 4.00 (0.1575) 3.80 (0.1496) Figure 40. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 ADN4691EBRZ ADN4691EBRZ-RL7 ADN4693EBRZ ADN4693EBRZ-RL7 ADN4696EBRZ ADN4696EBRZ-RL7 ADN4697EBRZ ADN4697EBRZ-RL7 EVAL-ADN469xEHDEBZ EVAL-ADN469xEFDEBZ 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) 14-Lead Standard Small Outline Package (SOIC_N) Evaluation Board for Half-Duplex (ADN4691E/ADN4696E) Evaluation Board for Full-Duplex (ADN4693E/ADN4697E) Z = RoHS Compliant Part. Rev. A | Page 17 of 20 Package Option R-8 R-8 R-14 R-14 R-8 R-8 R-14 R-14 ADN4691E/ADN4693E/ADN4696E/ADN4697E NOTES Rev. A | Page 18 of 20 Data Sheet Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E NOTES Rev. A | Page 19 of 20 ADN4691E/ADN4693E/ADN4696E/ADN4697E NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10355-0-3/12(A) Rev. A | Page 20 of 20 Data Sheet