ETC AM30LV0064DJ40E2I

Am30LV0064D
64 Megabit (8 M x 8-Bit)
CMOS 3.0 Volt-only Flash Memory with UltraNAND™ Technology
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read, erase, and
program operations
— Separate VCCQ for 5 volt I/O tolerance
■ Operation status byte
— Provides a software method of detecting program or erase
operation completion, program/erase pass/fail condition,
erase suspend status, and the write protect status
■ Automated Program and Erase
— Page program: 512 + 16 bytes
— Block erase: 8 K + 256 bytes
■ Operating current (typical)
— Read: 10 mA (sequential)
— Program: 10 mA
— Erase: 10 mA
— Standby: 10 µA (CMOS)
■ Block architecture
— 8 Kbyte blocks + 256 byte spare area
(separately erasable, readable, and programmable)
— 512 byte page + 16 byte spare area for ECC and other
system overhead information
■ Fast read and program performance (typical values)
— Read: < 7 µs initial, < 50 ns sequential
— Program: 200 µs (full page program at 400 ns/byte)
— Erase: < 2 ms/8 Kbyte block
■ Pinout and package
— Industry Standard NAND compatible pinout with 8-bit
I/O bus and control signals
— TSOP-II 44/40 pin package (standard and reverse)
with copper lead frame for higher reliability
— 40-ball FBGA package provides higher reliability and
“packing density”
■ Command set
— Basic Command set: Read Data, Read ID, Read
Status, Input Data, Program Data, Block Erase, Reset
— Superset Commands: Gapless Sequential Read
Data, Erase Suspend/Resume
■ Block erase suspend/resume
— Suspends an erase operation to read data from, or
program data to, a block that is not being erased, then
resumes the erase operation
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
■ WP# input pin
— At VIL, the device is protected. Program or erase
operations in the device are inhibited
— At VIH, the device is unprotected. Program and erase
operations are allowed
■ Minimum 10,000 program/erase cycles guaranteed
per block, without ECC (> 1 million cycles with ECC)
■ 10-year data retention at 85°C
■ Industrial temperature range, –40°C to +85°C
■ 100% good blocks over product lifetime
Publication# 22203 Rev: C Amendment/+3
Issue Date: October 6, 2000
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am30LV0064D is a 64 Mbit mass storage Flash
memory device, organized as 8 Kbyte (+256 byte)
blocks (1,024 blocks total), each with 16 pages of 512
(+16) bytes (16,384 pages total).
The device is suited to high-density applications in
which data is sequential and requires frequent, fast
write capability. The UltraNAND™ block and page architecture is capable of accommodating applications
requiring IDE disk drive-compatible blocks.
Each device requires only a single 3.0 volt power
supply for read, program, and erase functions. Internally generated and regulated voltages are provided
for program and erase operations. A VCCQ pin is provided to allow 5 volts to be applied to the output buffer
logic. With 5 volt tolerant inputs, the VCCQ pin provides
the Flash device with 5 volt tolerant I/O.
The Am30LV0064D is entirely command set compatible with industry standard NAND instructions and
timing. Commands are written to the command register through the 8-bit I/O bus using standard NAND
write timing. Register contents serve as inputs to an
internal state-machine that controls the read, erase,
and programming circuitry. Write cycles also internally
latch addresses and data needed for the read, programming, and erase operations. Reading data out of the
device is similar to reading from NAND Flash devices. The
device has an initial page read access time of 7 µs, with
subsequent byte accesses of less than 50 ns per byte.
Device programming occurs on a page basis by executing the Input Data and Program Data command
sequences. This initiates the Embedded Program al-
2
gorithm—an internal algorithm that automatically times
the program pulse widths and verifies proper cell margin.
Device erasure is performed on a block basis and occurs
by executing the Block Erase command sequence. This
initiates the Embedded Erase algorithm—an internal
algorithm that automatically executes the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin. The
block erase architecture allows memory blocks to be
erased and reprogrammed without affecting the data
contents of other blocks. The Erase Suspend/Erase
Resume feature enables the user to put erase on hold
for any period of time to read data from, or program
data to, any block that is not selected for erasure. True
background erase can thus be achieved. The device is
fully erased when shipped from the factory.
The host system can detect whether a sequential read,
program, or Block Erase operation is complete by observing the RY/BY# pin or by reading the status
register. After a program or erase cycle has been completed, the device is ready to accept another command.
Hardware data protection is provided by a write protect (WP#) input pin which inhibits all program and
erase operations when asserted (low).
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
Am30LV0064D
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions ................................. 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Pin Description . . . . . . . . . . . . . . . . . . 8
Cell Layout And Address Assignment . . . . . . . . . 9
Figure 1. Mass Storage Device Cell Layout.................. 9
Table 1. Address Assignment .......................................9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations, Command Set, And
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Am30LV0064D Device Bus Operations ........11
Table 3. Am30LV0064D Command Set ......................11
Table 4. Am30LV0064D Command Definitions ..........12
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Operations .................................................. 14
Figure 2. Read Data.................................................... 14
Figure 3. Gapless Read .............................................. 15
Figure 4. Read Spare Area ......................................... 16
Table 5. Am30LV0064D ID Codes ..............................17
Figure 5. Read ID........................................................ 17
Figure 6. Device Status Register Bit Definition ........... 18
Figure 7. Read Status ................................................. 18
Program Operations ............................................. 18
Figure 8. Input Data and Page Program ..................... 19
Figure 9. Program Operations Flow Chart .................. 20
Erase Operations ................................................. 21
Figure 10. Block Erase................................................ 21
Figure 11. Erase Suspend and Erase Resume........... 22
Reset Operation ................................................... 23
Figure 12. Reset.......................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 24
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Maximum Negative
Overshoot Waveform .................................................. 24
Figure 14. Maximum Positive
Overshoot Waveform .................................................. 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Test Specifications ........................................25
Figure 15. Test Setup.................................................. 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Command, Data, and Address Input .................... 26
Normal Operation ................................................. 26
Mode Selection ..................................................... 27
Key To Switching Waveforms . . . . . . . . . . . . . . . 27
Figure 16. Command Input Cycle................................ 28
Figure 17. Address Input Cycle ................................... 28
Figure 18. Data Input Cycle......................................... 29
Figure 19. Serial Read Cycle ...................................... 29
Figure 20. Status Read Cycle ..................................... 30
Figure 21. Read Data .................................................. 30
Figure 22. Read Data (Interrupted by CE#) ................ 31
Figure 23. Read Spare Area ....................................... 31
Figure 24. Sequential Read......................................... 32
Figure 25. Page Program ............................................ 32
Figure 26. Block Erase ................................................ 33
Figure 27. Erase Suspend........................................... 33
Figure 28. Erase Resume ........................................... 34
Figure 29. Sequential Page Program .......................... 34
Figure 30. ID and Manufacturer Read......................... 35
Figure 31. Write Protect (WP#) Timing During
Power Transitions........................................................ 35
Program And Erase Characteristics . . . . . . . . . 36
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 36
TSOP II Pin Capacitance . . . . . . . . . . . . . . . . . . . 36
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37
TS 044—44/40-Pin Standard Thin Small
Outline Package II ................................................ 37
TSR044—44/40-Pin Reverse Thin Small
Outline Package II ................................................ 38
FBE040—40-Ball Fine Pitch Ball Grid Array
(FBGA) 8 x 15 mm package ................................. 39
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision B (December 1998) ............................... 40
Revision B+1 (January 1999) ............................... 40
Revision B+2 (February 1999) ............................. 41
Revision B+3 (March 8, 1999) .............................. 41
Revision B+4 (April 21, 1999) .............................. 41
Revision B+5 (June 17, 1999) .............................. 41
Revision C (May 19, 2000) ................................... 41
Revision C+1 (June 23, 2000) .............................. 41
Revision C+2 (August 14, 2000) .......................... 41
Revision C+3 (October 6, 2000) ........................... 41
Am30LV0064D
3
PRODUCT SELECTOR GUIDE
Family Part Number
Am30LV0064D
Option
J40
Number of Usable Blocks Guaranteed
1024
Percentage of Usable Blocks Guaranteed
100%
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY#
ALE
CLE
Y-Decoder
SE# WP#
Data Register & S/A
X Decoder
High Voltage Pumps
CE#
RE#
WE#
State Machine
Command Register
Memory Array
Data Register & S/A
Y-Decoder
Address Register
Status Register
I/O Register & Buffer
VCC
VCCQ
VSS
22203C
4
Am30LV0064D
I/O7-0
CONNECTION DIAGRAMS
VSS
CLE
ALE
WE#
WP#
RFU
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O0
I/O1
I/O2
I/O3
VSS
VCC
CE#
RE#
RY/BY#
SE#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44/40-Pin Standard
TSOP-II
44/40-Pin Reverse
TSOP-II
Am30LV0064D
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE#
RE#
RY/BY#
SE#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
VCCQ
VSS
CLE
ALE
WE#
WP#
RFU
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O0
I/O1
I/O2
I/O3
VSS
5
CONNECTION DIAGRAMS (Continued)
40-Ball FBGA
Top View, Balls Facing Down
0.8
B
C
D
E
F
G
H
J
K
NC
V CC
NC
NC
NC
NC
NC
NC
V CCQ
NC
NC
CE#
RE# RY/BY# SE#
IO7
IO6
IO5
IO4
NC
6
5
0.8
1.6
4
3
NC
CLE
ALE
WE#
WP#
IO0
IO1
IO2
IO3
NC
NC
V SS
NC
NC
RFU
NC
NC
NC
V SS
NC
8 mm
0.8
A
2
0.8
1
0.8
Ø0.400 mm 0.250 SMD, Ball = 0.3 mm
15 mm
Note: The ball grid array is depopulated to 40 signal balls. The maximum package height is 1.2 mm. The 9 x 9 x 9 x 9 outrigger
balls (shaded) may be required for higher density devices in larger packages. The shaded ball region should be treated as a
“keep out” area with pads placed to allow larger devices to be accommodated.
Special Handling Instructions
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised if the package body is exposed to temperatures
above 150°C for prolonged periods of time.
6
Am30LV0064D
PIN CONFIGURATION
LOGIC SYMBOL
I/O7–I/O0
= 8 Inputs/Outputs
CE#
= Chip Enable input
CE#
RE#
= Read Enable input
RE#
WE#
= Write Enable input
WE#
SE#
= Spare area Enable input
SE#
ALE
= Address Latch Enable input
ALE
CLE
= Command Latch Enable input
CLE
WP#
= Write Protect input
RY/BY#
= Ready/Busy output (open drain)
VCC
= 3.0 Volt-only single power supply for
the Flash device core
WP#
8
I/O7–I/O0
RY/BY#
(see Product Selector Guide for voltage
supply tolerances)
VCCQ
= Single power supply for output buffers
(see VCCQ signal description)
VSS
= Device ground
NC
= Pin not connected internally
RFU
= Reserved for future use
Am30LV0064D
7
FUNCTIONAL PIN DESCRIPTION
Input/Output Pins (I/O7–I/O0)
The eight I/O pins are used to send commands, addresses, and data to the device, and to receive data
during read operations.
Command Latch Enable (CLE)
The CLE input controls activation of the command register for the receipt of commands. When CLE is high,
the command is latched into the command register on
the rising edge of the Write Enable (WE#) signal.
Address Latch Enable (ALE)
The ALE input controls activation of the address register
during the address latch operation, or the data register
during the Input Data operation. When ALE is high, the
address information is latched on the rising edge of
the Write Enable (WE#) signal. When ALE is low (and
the CLE input is low) the Input Data information is
latched on the rising edge of the Write Enable (WE#)
signal. ALE must remain high for the entire address
sequence or device will reset.
Chip Enable (CE#)
The CE# input controls the active/standby mode during command, data, and address inputs. During the
command and address latch operations, CE# must be
low prior to the falling edge of Write Enable (WE#).
During Input Data operations, CE# must remain low
until after the rising edge of WE# during the final Data
In operation. When CE# is high, and an internal operation is not in process, the device goes into standby
mode and current consumption is greatly reduced.
The CE# signal is ignored during program or erase operation, as indicated by the Busy state (RY/BY# =
low).
Read Enable (RE#)
The RE# input controls the serial data output and status from the I/O lines. The data output is triggered on
the falling edge of RE#, with valid data available after
a delay of tREA . The Status output data is also triggered on the falling edge of RE#, with the status
available after a delay of tRLS.
Write Enable (WE#)
The WE# input is used to control the Data/Command
on the I/O lines during write operations. The I/O lines
are latched on the rising edge of the WE# signal.
Write Protect (WP#)
The WP# input provides protection from inadvertent
program/erase commands. The internal voltage regulator is reset when WP# is low, thereby preventing any
program or erase operations from occurring.
8
The WP# input should be kept low (V I L ) during
power-up until VCC is above VCC-min. During
power-down WP# should be driven low (VIL) before
VCC is below VCC-min.
Spare Area Enable (SE#)
The SE# input controls access to the 16 bytes of spare
area on each page. When SE# is not asserted (high),
the spare area for the selected page is not enabled,
and all input or output data is directed towards the primary 512 byte storage space. When SE# is asserted
(low), access to the spare area is enabled, and data
can be transferred to or from the 16 bytes of spare
area for the appropriate page as needed. With SE#
asserted (low) information can still be transferred to or
from the 512 byte main Flash page, but when the end
of the page is reached (byte 511) the device will automatically begin transferring information to or from the
spare area.
During the Read Spare Area command sequence
(50h) the SE# input must be asserted (low) during the
command phase (CLE high). In all other cases when
the spare area is to be accessed, the SE# input must
be asserted (low) at least two access cycles prior to
the spare area access. This would require the SE#
input to be low by the time byte address 510 is selected, and SE# must remain low during the entire
period that the spare area is accessed.
Ready/Busy Output (RY/BY#)
The RY/BY# output indicates the operation status of the
device. When RY/BY# is high, the device is ready to
accept the next operation. When RY/BY# is low, an internal
program, erase, or random read operation is in progress.
RY/BY# is an open drain output pin which allows multiple RY/BY# pins to be wire-ORed together. The
RY/BY# output pin requires an external pull-up resistor
to VCC (or VCCQ) for proper operation.
Device Power Supply (VCC)
The minimum VCC operating voltage for the
Am30LV0064D is 2.7 volts. The device has an operating voltage range from 2.7 volts to 3.6 volts.
Output Buffer Power Supply (VCCQ)
The output voltage generated on the device is determined based on the VCCQ power supply input level. A
VCCQ of 2.7 to 3.6 volts will allow the device to function
as a 3.0 Volt-only device. A V CCQ of 4.5 to 5.5 volts
provides 5 volt I/O tolerance.
All input only signals are 5 volt tolerant by design, independent of the voltage on VCCQ.
Ground (VSS)
The VSS pins on the device must be grounded.
Am30LV0064D
CELL LAYOUT AND ADDRESS ASSIGNMENT
I/O 0
~
I/O 7
512 + 16 Byte
Data Register
256
256
16
16 Pages
(1 Block)
Flash Memory
Array
16,384 Pages
(1,024 Blocks)
528 Bytes
(1 Page)
Note: Device programming is executed on a page basis while erase is performed on a block basis. During read operations, data
is transferred from the Flash array to the internal Data Register on a page basis. Data is then sequentially read from the Data
Register on a Byte basis.
Figure 1.
Mass Storage Device Cell Layout
Table 1.
First Cycle
Second Cycle
Third Cycle
I/O 7
A7
A16
X
I/O 6
A6
A15
X
Address Assignment
I/O 5
A5
A14
A22
I/O 4
A4
A13
A21
I/O 3
A3
A12
A20
I/O 2
A2
A11
A19
I/O 1
A1
A10
A18
I/O 0
A0
A9
A17
Legend:
Axx = specific address bit, X = don’t care (VIH or VIL)
Notes:
1. A8 is automatically set “Low” or “High” by the 00h or 01h command.
2. A22 to A13 specifies the Block Address, A12 to A9 specifies the Page Address within a block, and A7 to A0 identifies the
byte address within half a page.
Am30LV0064D
9
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The Ordering Part Number or
OPN (Valid Combination) is formed by a combination of the elements below.
Am30LV0064D
J40
E2
I
T
PACKING METHOD
T
= Tape and Reel
TEMPERATURE RANGE
I
=
Industrial (–40°C to +85°C)
PACKAGE TYPE
E2
= 44/40-Pin Thin Small Outline Package
(TSOP-II) Standard Pinout (TS 044)
F2
= 44/40-Pin Thin Small Outline Package
(TSOP-II) Reverse Pinout (TSR044)
WG = 40-Ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 15 mm package (FBE040)
PERFORMANCE RANGE
J40 = 1024 (100%) usable blocks
DEVICE NUMBER/DESCRIPTION
Am30LV0064D
64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt Flash Memory with UltraNAND™ Technology
2.7–3.6 Volt with 5 Volt I/O Tolerance
Valid Combinations for TSOP Packages
AM30LV0064DJ40
Valid Combinations for FBGA Packages
E2I, F2I
Order Number
AM30LV0064DJ40
Package Marking
WGI
L064DJ40V
I
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and
to check on newly released combinations.
10
Am30LV0064D
DEVICE BUS OPERATIONS, COMMAND
SET, AND COMMAND DEFINITIONS
This section describes the requirements and use of
the device bus operations, the command set, and the
command definitions. The device bus operations are
initiated through the internal command register which
decodes the command to determine the current operation to be performed. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the
Table 2.
Operation
commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine whose outputs dictate the function of the device.
Table 2 lists the device bus operations including the inputs and control levels they require, and the resulting
output. Table 3 lists the command set, and Table 4 lists
the command definitions. The “Device Operations”
section describes each of these operations in detail.
Am30LV0064D Device Bus Operations
CE#
RE#
WE#
SE#
CLE
ALE
WP#
I/O7–I/O0
Read Data Area
L
L
H
L/H
L
L
X
DOUT
Read Spare Area
L
L
H
L
L
L
X
DOUT
Read ID, Status
L
L
H
X
L
L
X
DOUT
Write Data
L
H
L
L/H
L
L
X
DIN
Write Command
L
H
L
X
H
L
X
CIN
Write Address
L
H
L
X
L
H
X
AIN
VCC ± 0.3 V
X
X
VSS ± 0.3 V
X
X
X
X
X
X
X
X
Standby
Write Protect
VCC ± 0.3 V
VCC ± 0.3 V
VSS ± 0.3 V
High-Z
(See Note)
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, X = Don’t Care, AIN = Address In, CIN = Command In, DIN = Data In, DOUT = Data Out
Note: If WP# = VIL, the Flash device is protected and will not allow program or erase operations to occur. If WP# = VIH, the
device is unprotected and may be programmed or erased.
Table 3. Am30LV0064D Command Set
Operation
Cycle 1
Cycle 2
Valid During Busy
00h/01h
–
No
Gapless Read
02h
–
No
Read Spare Area
50h
–
No
Read ID
90h
–
No
Read Status
70h
–
Yes
Input Data
80h
–
No
Page Program
10h
–
No
Block Erase
60h
D0h
No
Erase Suspend
B0h
–
Yes
Erase Resume
D0h
–
No
Reset
FFh
–
Yes
Read Data
Am30LV0064D
11
Table 4.
Command Sequence
(Note 2)
Read Data Area–First Half Page
Read Data Area–Second Half
Page
Read Data Area–Gapless Read
(Note 3)
Read Spare Area (Note 4)
Read ID
Read Status
Input Data
Program Data
Block Erase (Note 5)
Erase Suspend (Note 6)
Erase Resume (Note 8)
Reset
Am30LV0064D Command Definitions
First
Oper. Data
WR
00
Second
Oper. Data
WR
SA
Bus Cycles (Note 1)
Third
Fourth
Fifth (Note 8)
Sixth
Oper. Data Oper. Data Oper. Data Oper. Data
WR
SA
WR
SA
RD
Data
Etc.
Etc.
WR
01
WR
SA
WR
SA
WR
SA
RD
Data
Etc.
Etc.
WR
02
WR
SA
WR
SA
WR
SA
RD
Data
Etc.
Etc.
WR
WR
WR
WR
WR
WR
WR
WR
WR
50
90
70
80
10
60
B0
D0
FF
WR
WR
RD
WR
SA
00
SR
SA
WR
RD
Etc.
WR
SA
01
Etc.
SA
WR
RD
SA
E6
RD
Data
Etc.
Etc.
WR
SA
WR
Data
Etc.
Etc.
WR
BA
WR
BA
WR
D0
Legend:
WR = Write Cycle Byte, RD = Read Cycle, SA = Starting Address, Etc. = previous sequence continues as needed,
SR = Status Register, AR = Address Register, DR = Data Register, BA = Block Address Byte
Notes:
1. All values are in hexadecimal.
2. See Table 2 for description of bus operations.
3. The Gapless Read command is similar to the Read Data
Area commands except that the 7 µs latency does not
occur when the Page address pointer steps to the next
page to be read. This command requires that the starting
byte address is located within the first half of the selected
Page.
4. For the Read Spare Area command it is necessary for the
SE# pin to be low during the CLE cycle and when actively
reading from the 16 byte Spare Area. For all other
commands the SE# pin must be low at least two cycles
12
5.
6.
7.
8.
prior to the first spare area access at byte address 512 (low
before byte address 510).
The two byte Block Address cycles load address bits
A22–A9 into the device. Since only address bits A22–A13
are required for a Block address, address bits A12–A9 are
don’t care.
The system may read and program in non-erasing Blocks
when in the Erase Suspend mode. The Erase Suspend
command is valid only during a Block erase operation.
The Erase Resume command is valid only during the Erase
Suspend mode
The fifth bus cycle for read operations follows the read
latency delay.
Am30LV0064D
DEVICE OPERATIONS
When the AMD Mass Storage Flash device powers
up, the command decoder is initialized to a wait for
command state. In order to perform any function, the
device must be programmed for the desired operation.
Specific commands must be issued to the device to
select one of the read modes, to input or program
data, to perform one of the block erase functions, or to
reset the device.
There are a number of commands available for reading information from the UltraNAND Flash device.
These include Read Data to read out of the Flash array, Gapless Read to read data in a special high
performance mode, Read Spare Area to read the 16
byte spare area in each page, Read ID to determine
the manufacturer and device ID, and Read Status to
check the device status.
Programming data into the Flash array is a two step
process and requires that two separate command sequences be performed. The data to be programmed
must first be loaded into the Data Registers using the
Input Data command sequence. After the data is
loaded the Page Program command is performed to
transfer the information from the Data Registers to the
Flash array.
Device erasure occurs on an 8 Kbyte block basis, with
each block in the device containing 16 pages and the
respective spare area for each page. During block
erase, the Flash device supports erase suspend and
erase resume to allow time critical tasks to be performed. These time critical tasks can be to read or
program in a block that is not currently selected for
erasure.
The Flash device also supports a reset command sequence to reset the device and return it to the wait for
command state.
All of the commands and their functions supported by
the Flash device are described in the following
sub-sections with simplified timing diagrams included.
The timing diagrams are intended to illustrate the relationship of each of the control, status, and data signals
for each of the command sequences. Please refer to
the AC/DC Characteristics section for more complete
timing information.
In each of the simplified timing diagrams, the polling
period during device busy (RY/BY# = V IL ) is not
shown. During device busy the system can poll the device internal status register or monitor the RY/BY# pin
to determine when the internal operation is complete.
Am30LV0064D
13
Read Operations
Data Register, it may be sequentially read with consecutive 50 ns RE# pulses. Each RE# pulse will
automatically advance the column address by one.
Once the last column has been read, the page address
will automatically increment by one and the Data Register will be updated with information from the new page
after a 7 µs latency period.
Read Data (00h / 01h)
There are two commands available for reading from
the Flash array (via the Data Registers). These are
Read Data—(starting with the) First Half Page (00h)
and Read Data—(starting with the) Second Half Page
(01h).
During the sequential read mode, if the Spare Area
Enable input (SE#) is high, the column address will advance to address 511 and then the page address will
increment by one. If the SE# input is low, the column
address will advance to address 527 before the page
address is incremented. This allows information in the
Spare Area to be read at the end of the page before
the next page of information is transferred into the
Data Registers. In the case of the Read Data command, the SE# input may go low anytime from before
the command is issued to before address 510 is accessed. This allows the Flash internal logic to correctly
enable the Spare Area for reading.
The commands are identical except for the starting region within the selected page. After the command
cycle, three address cycles are used to input the starting address for the read operation. Upon the rising
edge of the final WE# pulse there is a 7 µs latency in
which 528 bytes of information are transferred from
the Flash array page to the 528 byte Data Register.
During the 7 µs latency period the Flash device will appear busy and either the RY/BY# signal or the status
register may be used to monitor the completion of the
data transfer. Only the Reset and Read Status commands are valid during the period that the device is
busy. Once the information has been loaded into the
CE#
CLE
ALE
WE#
RE#
Read Data (00h or 01h)
I/O7-0
CMD
Start Address
Read Page
Read Next Page
SE#
RY/BY#
Data Transfer
Data Transfer
Notes:
1. CE# is don’t care in between WE# and RE# transitions.
2. Falling edge of CE# to valid data must be >45 ns.
3. CE# transition when RY/BY# is low terminates read operation.
4. ALE must remain high for entire address latch operation; no transitions allowed.
Figure 2.
14
Read Data
Am30LV0064D
Data Transfer
Read Next Page
Gapless Read (02h) (Superset Command)
Each RE# pulse will automatically advance the column
address by one. Once the last column has been read,
the page address will automatically increment by one
and the Data Register will be updated with the new
page.
The Gapless Read command is almost identical to the
Read Data command, except that it allows reading
from multiple pages with only one 7 µs latency occurring on the first page transfer. After the command
cycle is used to write the Gapless Read op-code to the
device, three address cycles are used to input the
starting address for the Gapless Read operation.
In the case of the Gapless Read, there is no 7 µs latency period encountered when moving from the
current page to the next sequential page.
The Gapless Read operation requires that the address
entered specifies an address location in the first half of
the selected page. Upon the rising edge of the final
WE# pulse there is a 7 µs latency in which 528 bytes
of information are transferred from the Flash array
page to the 528 byte Data Register. During this 7 µs
period the device will appear busy and either the
RY/BY# signal or the status register may be used to
monitor the completion of the data transfer. Only the
Reset and Read Status commands are valid during
the period that the device is busy. Once the information has been loaded into the Data Register, it may be
sequentially read with consecutive 50 ns RE# pulses.
During the sequential read mode, if the Spare Area
Enable input (SE#) is high, the column address will advance to address 511 and then the page address will
increment by one. If the SE# input is low, the column
address will advance to address 527 before the page
address is incremented. This allows information in the
Spare Area to be read at the end of the page before
the next page of information is transferred into the
Data Registers.
This is an AMD superset command which is not available on competitive devices in the marketplace.
CE#
CLE
ALE
WE#
RE#
Gapless Read (02h)
I/O7-0
CMD
Start Address
Read Page
Read Next Page
Read Next Page
SE#
RY/BY#
Data Transfer
Notes:
1. CE# is don’t care in between WE# and RE# transitions.
2. Falling edge of CE# to valid data must be >45 ns.
3. CE# transition when RY/BY# is low terminates read operation.
4. ALE must remain high for entire address latch operation; no transitions allowed.
Figure 3.
Gapless Read
Am30LV0064D
15
Read Spare Area (50h)
The Read Spare Area command is similar to the Read
Data command, except that it only reads information
from the selected page 16 byte Spare Area (address
locations 512 through 527). After the command cycle
is used to write the Read Spare Area op-code to the
device, three address cycles are used to input the
starting address for the read operation. During the
Read Spare Area command cycle the SE# input must
be low.
Because the Read Spare Area operation only reads
the 16 byte spare area in the page, address bits
A7–A4 are don’t care. Address bits A22–A9 are used
to select the Page, and address bits A3–A0 are used
to select the starting byte within the Spare Area of the
Page. Upon the rising edge of the final WE# pulse
there is a 7 µs latency in which all 528 bytes of information are transferred from the Flash array page to
the 528 byte Data Register. Following the data transfer
the internal address pointer will point to the byte selected in the Spare Area. During the 7 µs data transfer
period the device will appear busy and the RY/BY#
signal or the status register may be used to monitor
the completion of the data transfer. Only the Reset and
Read Status commands are valid during the period
that the device is busy. Once the information has been
loaded into the Data Register, the Spare Area information may be sequentially read with consecutive 50 ns
RE# pulses. Each RE# pulse will automatically advance the Spare Area column address by one. Once
the last column has been read, the page address will
automatically increment by one and the Data Register
will be updated with the new page after a 7 µs latency.
During the sequential read mode, the Spare Area Enable input (SE#) must be low. This is necessary any
time the Spare Area is being read. In this operation,
the column address will advance from the selected
starting byte location to address 527 before the page
address is incremented. After the next page of information is transferred to the Data Register, sequential
read operations will begin in the Data Register at address location 512. Unlike the Read Data and Gapless
Read modes, the Read Spare Area operation requires
that the SE# input be asserted low prior to the command being issued to the device.
CE#
CLE
ALE
WE#
RE#
Read Spare Area (50h)
I/O7-0
CMD
Start Address
Read Spare Area
Read Next Spare Area
Read Next Spare Area
SE#
RY/BY#
Data Transfer
Data Transfer
Figure 4.
16
Read Spare Area
Am30LV0064D
Data Transfer
Read ID (90h)
a 00h value into the device. Upon the rising edge of
the final WE# pulse, the two bytes of information may
be sequentially read with two consecutive 50 ns RE#
pulses.
The Read ID operation is used to read the Manufacturers ID and the Device ID from the Flash device. After
the command cycle, one address cycle is used to input
Table 5.
Manufacturer
Device
I/O7
0
1
I/O6
0
1
Am30LV0064D ID Codes
I/O5
0
1
I/O4
0
0
I/O3
0
0
I/O2
0
1
I/O1
0
1
I/O0
1
0
ID Code
01h
E6h
CE#
CLE
ALE
WE#
RE#
Read ID (90h)
I/O7-0
CMD
00h
Manufacturer’s ID
Device ID
SE#
RY/BY#
Figure 5.
Read ID
Am30LV0064D
17
Read Status (70h)
The Read Status operation is used to read the device
status to determine if the device is ready, in the write
protect mode, erase suspended, or if the previous program/erase operation completed without error. After
the rising edge of the command cycle WE# pulse, the
falling edge of CE# or RE#, whichever occurs last, will
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
output the contents of the status register on the 8 I/O
pins, I/O7–I/O0. The status register is constantly updated and does not require either CE# or RE# to be
toggled. By utilizing the Read Status operation, multiple devices with RY/BY# pins wired together may be
polled to determine their specific status.
I/O0
Program/Erase: 0 = pass, 1 = fail
Not Used
Erase Suspend: 0 = not suspended, 1 = suspended
Ready/Busy: 0 = busy, 1 = ready
Write Protect: 0 = protected, 1 = not protected
Figure 6.
Device Status Register Bit Definition
CE#
CLE
ALE
WE#
RE#
Read Status (70h)
I/O7-0
CMD
Read Status
Read Status
Read Status
Read Status
SE#
RY/BY#
Figure 7.
Program Operations
Input Data (80h)
The Input Data command sequence is the first of two
operations that must be performed to program information into one of the Flash pages. The second
operation, Page Program, is used to transfer information from the Data Registers to the Flash array after
18
Read Status
the Input Data procedure loads the Data Registers. In
order to set the starting region within the Data Registers (first half, second half, or Spare Area), the
appropriate command (00h, 01h, 50h) should be issued prior to the Input Data command being
performed. If a command is not submitted to assign
the starting region, the starting region will be determined by its previous state.
Am30LV0064D
After the command cycle, three address cycles are
used to input the starting address for the Input Data
operation. Upon the rising edge of the final WE# pulse,
between 1 and 528 bytes of information can be loaded
into the Data Register with consecutive 50 ns WE#
pulses. Each WE# pulse will automatically advance
the Data Register address pointer by one. If additional
write pulses are issued after the last address has been
written (511 if SE# is high or 527 if SE# is low), the
Data Register address pointer will wrap around to 0. If
additional WE# pulses are issued, the device will continue to store information into the Data Register until a
new command is issued.
The Spare Area Enable input (SE#) must be low by
the time address 510 is accessed in order to load information into the last 16 bytes of the Data Register. If
the SE# input is high, the Data Register address will
advance to address 511. If the SE# input is low, the
column address will advance to address 527. This allows information that needs to be programmed into the
Spare Area of the page to be loaded into the Data Registers properly. Please refer to Figure 8 for the simplified
timing diagram for Input Data and Page Program.
Page Program (10h)
The Page Program command sequence is issued after
the Input Data operation has loaded the proper data in
the Data Registers. Upon the rising edge of the command
cycle WE# pulse, this operation typically transfers in-
formation from the Data Registers to the Flash array in
200 µs or less, and the Flash device will appear busy
during the data transfer operation. The RY/BY# signal
or the status register may be used to monitor completion of the data transfer. Only the Reset and Read
Status commands are valid during the period that the
device is busy.
Only those bytes loaded with the Input Data command
sequence will be programmed in the Flash array. This
allows partial page programming to be performed as
needed. If no bytes were loaded into the Data Register, or if the Page Program command is issued without
the Input Data command being performed, no program
operation will occur. Unless ECC has been implemented, a given page may not be reprogrammed
without an intervening erase operation being performed on the block that contains that page. After
programming a page, the status register bit I/O0
should be checked to verify that the program operation
completed properly.
The Spare Area Enable input (SE#) must be low in
order to program information into the last 16 bytes of
the page that is selected for programming. If the SE#
input is high, the Spare Area will not be programmed.
Please refer to Figure 8 for the simplified timing diagram
for Input Data and Page Program and to Figure 9 for a
flow chart describing the device program procedure.
CE#
CLE
ALE
WE#
RE#
Input Data (80h)
I/O7-0
CMD
Page Program (10h)
Start Address
Write Page Data (and Spare Area if Required)
SE#
CMD
Low to Write Spare Area
RY/BY#
Page Program
Notes:
1. CE# is don’t care in between WE# and RE# transitions.
2. Falling edge of CE# to valid data must be >45 ns.
3. ALE must remain high for entire address latch operation; no transitions allowed.
Figure 8.
Input Data and Page Program
Am30LV0064D
19
Start
Write the Address
Pointer command
(00h, 01h) to place
pointer in proper
half-page
Write the Input Data
Command (80h) to
the Flash Device
Write the starting
address
Write a Byte of Data
to the Flash
No
Last
Data Byte Written
?
Yes
Write the Program
Data Command (10h)
to the Flash Device
Read Status Register
or Monitor R/B# Pin
Is
Device Busy
?
Yes
No
Read Status Register
May be required to
exceed guaranteed endurance
Is
I/O0 = 0
?
No
Yes
Program Successful
Program Failed
Done
Use User Defined
Procedure to Identify
the Failed Byte
Implement Error
Correction as
Appropriate
Done
Figure 9.
20
Program Operations Flow Chart
Am30LV0064D
Erase Operations
second command cycle, the Flash device will begin
the Block Erase operation.
Block Erase (60h) (D0h)
The Block Erase command sequence is a two command operation procedure that must be performed to
erase information in one of the 16 page Flash blocks.
After the first command cycle, two address cycles are
used to input the block address for the block to be
erased. Since the block address only requires address
bits A22–A13 to determine the block address, bits
A12–A9 are don’t care. After the two address cycles
are complete, the second command cycle is issued.
Upon the rising edge of the final WE# pulse for the
A block typically erases in the Flash array in 2 ms or
less and is guaranteed to erase within 10 ms. The
Flash device appears busy during the Block Erase operation and either the RY/BY# signal or the status
register may be used to monitor completion of the
erase. Only the Erase Suspend, Reset, and Read Status commands are valid during the period that the device
is busy.
After erasing a block, the status register bit I/O0
should be checked to verify that the erase operation
completed properly. Figure 10 shows the simplified
timing for Block Erase.
CE#
CLE
ALE
WE#
RE#
I/O7-0
Block Erase Setup (60h)
Block Erase (D0h)
CMD
CMD
Block Address
SE#
RY/BY#
Block Erase
Figure 10.
Erase Suspend (B0h) (Superset Command)
The Erase Suspend command sequence is only valid
during a Block Erase operation. Upon the rising edge
of the command WE# pulse, the Flash device will suspend the Block Erase operation. Either the RY/BY#
signal or the status register may be used to determine
when the Block Erase has actually been suspended.
Once the Erase Suspend has taken effect, read or
program operations may be performed in blocks that
are not selected for erasure.
Once a Block Erase has been suspended, the suspended Block Erase operation must be completed
before another block can be selected for erasure.
Block Erase
When the Erase Suspend command is issued, the
Block Erase command is inhibited. The Block Erase
will be invalid until an Erase Resume command allows
the suspended erase to complete, the device is reset,
or power is removed from the device. Refer to Figure
11 for a simplified timing diagram showing the sequence of events required to implement Erase
Suspend during a block erase operation. This is an
AMD superset command which is not available on
competitive devices in the marketplace.
Erase Resume (D0h) (Superset Command)
The Erase Resume command sequence is only valid
during an Erase Suspend operation. Upon the rising
Am30LV0064D
21
edge of the command WE# pulse, the Flash device
will resume the Block Erase operation that was suspended. Either the RY/BY# signal or the status register
may be used to determine when the Block Erase
completes.
After the block finishes the erase operation, the status
register bit I/O0 should be checked to verify that the
erase completed properly. Figure 11 is a simplified timing
diagram that describes how to execute an Erase Resume operation during Erase Suspend to allow the
previously suspended block erase to complete. This is
an AMD superset command which is not available on
competitive devices in the marketplace.
CE#
CLE
ALE
WE#
RE#
I/O7-0
Block Erase Setup (60h)
Block Erase (D0h)
CMD
CMD
Block Address
Erase Suspend (B0h)
Erase Resume (D0h)
CMD
CMD
SE#
As Appropriate
RY/BY#
Block Erase Suspended Here
Begin Block Erase
Figure 11.
22
Read or Program
Complete Block Erase
Operations may be performed
Erase Suspend and Erase Resume
Am30LV0064D
Reset Operation
Reset (FFh)
The Reset command sequence can be issued any
time the Flash device needs to be initialized. This may
be required when the device is busy during program,
erase, or data transfer operations. Reset will take
place on the rising edge of the command cycle WE#
pulse. If the WP# input is high, not protected, the Status Register will be set to C0h.
If a second Reset command is issued while a reset is
in process, the second Reset command will be ignored. If a Reset command is issued during a program
or erase operation, the internal high voltages will be
discharged before the device indicates that it is ready
(reset complete).
Either the RY/BY# signal or the status register may be
used to determine when the Reset operation is done.
Figure 12 shows a simplified timing diagram of the
reset command sequence.
CE#
CLE
ALE
WE#
RE#
Reset (FFh)
I/O15-0
CMD
SE#
RY/BY#
Reset in Progress
Figure 12.
Reset
Am30LV0064D
23
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
Industrial (I) Devices
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VCCQ (Note 2) . . . . . . . . . . . . . . . .–0.5 V to +6.0 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot V SS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 13. During voltage transitions, input or I/O
pins may overshoot to V CC +2.0 V for periods up to 20
ns. See Figure 14.
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
VCC Supply Voltages
VCC for full voltage range . . . . . . . . . . . 2.7 V to 3.6 V
VCCQ Supply Voltages
VCCQ for full voltage range . . . . . . . . . . 2.7 V to 3.6 V
VCCQ for 5 volt I/O tolerance . . . . . . . . . 4.5 V to 5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. For 3.0 volt-only applications, VCCQ should be connected
to V CC . To provide 5 V tolerant I/O, V CCQ should be
between 4.5 and 5.5 V.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC+2.0 V
VSS–0.5 V
VCC+0.5 V
VSS–2.0 V
2.0 V
20 ns
20 ns
20 ns
22203
Figure 13. Maximum Negative
Overshoot Waveform
24
22203
Figure 14. Maximum Positive
Overshoot Waveform
Am30LV0064D
DC CHARACTERISTICS
Parameter
Description
Test Conditions
Sequential Read Current
ICC1
Command, Address Input
ICC2
Current
Min
Typ
Max
Unit
tCYCLE=50 ns, CE#=VIL,
IOUT=0 mA
–
10
20
mA
tCYCLE=50 ns, CE#=VIL
–
10
20
mA
ICC3
Data Input Current
–
10
20
mA
ICC4
Program Current
–
10
20
mA
ICC5
Erase Current
–
10
20
mA
ISB1
Standby Current (TTL)
CE#=VIH
–
–
1
mA
ISB2
Standby Current (CMOS)
CE#=VCC–0.2 V,
WP#= SE# = 0V/VCC
–
10
50
µA
ILI
Input Leakage Current
VIN = 0 V to 3.6 V
–
–
10
µA
ILO
Output Leakage Current
VOUT = 0 V to 3.6 V
–
–
10
µA
VIH
Input High Voltage
All I/O Pins
2.0
–
VCCQ + 0.3
V
All Except I/O Pins
2.0
–
VCC + 0.3
V
VIL
Input Low Voltage, All Inputs
–0.3
–
0.8
V
VOH
Output High Voltage
IOH= –400 µA, VCC = VCCQ
VCC – 0.3
–
–
V
VOL
Output Low Voltage
IOL=2.1 mA, VCC = VCCQ
–
–
0.4
V
Output Low Current (RY/BY#)
VOL=0.4 V
8
10
–
mA
IOL (RY/BY#)
TEST CONDITIONS
Table 6.
Test Specifications
Test Conditions
VCC =
3.0 V
± 10%
VCC =
3.3 V
± 10%
3.3 V
Unit
2.7 KΩ
Output Load
Output Load Capacitance, CL
(including jig capacitance)
Input Rise and Fall Times
1 TTL Gate
50
100
pF
5
ns
0.0 – 2.4
V
Input Timing Measurement
Reference Levels
1.5
V
Output Timing Measurement
Reference Levels
1.5
V
Input Pulse Levels
Device
Under Test
CL
Figure 15.
Am30LV0064D
6.2 KΩ
Test Setup
25
AC CHARACTERISTICS
Command, Data, and Address Input
Parameter
JEDEC
Std
Description
Min
Max
Unit
tALS
ALE Setup Time
0
–
ns
tALH
ALE Hold Time
10
–
ns
tCLS
CLE Setup Time
0
–
ns
tCLH
CLE Hold Time
10
–
ns
tCES
CE# Setup Time
0
–
ns
tCEH
CE# Hold Time
10
–
ns
tDS
Data Setup Time
20
–
ns
tDH
Data Hold Time
10
–
ns
tWC
Write Cycle Time
50
–
ns
tWP
WE# Pulse Width
30
–
ns
tWH
WE# Pulse Width High
15
–
ns
Normal Operation
Parameter
JEDEC
Std
Description
Max
Unit
tALRE
ALE to RE# Delay for Data Read
50
–
ns
tAR
ALE to RE# Delay for ID and Manufacturer Read
100
–
ns
tCEH
CE# Pulse Width High (to abort sequential page read latency)
100
–
ns
tCELS
CE# Low to Status Output Valid
–
45
ns
tCHZ
CE# High to Output High Impedance
–
20
ns
tCR
CE# Low to RE# Low
100
–
ns
tCRY
CE# High to RY/BY# High (during abort of sequential page read latency)
–
50 + t (Note 1)
ns
tRC
Read Cycle Time
50
–
ns
tRP
RE# Pulse Width
35
–
ns
tREH
RE# Pulse Width High
15
–
ns
tREA
RE# Access Time for Data Read (Note 2)
–
35
ns
tREA2
RE# Access Time for ID and Manufacturer Read
–
35
ns
tRHZ
RE# High to Output High Impedance
15
30
ns
tRLS
RE# Low to Status Output Valid
–
35
ns
tWHR
WE# High to RE# Low
60
–
ns
tOZR
Output High Impedance to RE# Low
0
–
ns
tRB
Last RE# Rising Edge to RY/BY# Low
–
100
ns
tRR
RY/BY# High to RE# Low
20
–
ns
tWB
WE# High to RY/BY# Low
–
100
ns
tR
Transfer Time from Flash Array to Data Register
–
7
µs
tRST
Reset Time (Read/Program/Erase/after Erase Suspend)
–
5/10/500/5
µs
Notes:
1. Time is dependent on value of pull-up resistor at RY/BY# pin.
2. For customers using VCCQ > 3.6 V, tREA = 40 ns.
26
Min
Am30LV0064D
AC CHARACTERISTICS
Mode Selection
ALE
CLE
L
CE#
RE#
SE#
WP#
RY/BY#
H
L
H
L/X (Note 1)
X
H
H
L
L
H
X
X
H
L
H
L
H
X
H
L/H (Note 2)
H
L
L
H
X
H
H
L
L
L
H
L/H
H
H
Data Input
H
Sequential Read and Data
Output
L
WE#
L
H
L
L/H
X
Mode
Read Mode
Write Mode
Command Input
Address Input
Command Input
Address Input
L
L
H
L
H
L/H
X
L
During Read (Busy)
X
X
X
X
X
L/H
H
L
During Program (Busy)
X
X
X
X
X
X
H
L
During Erase (Busy)
X
X
X
X
X
X
L
X
Write Protect
X
X
X
H
X
X
X
X
Standby
Notes:
1. SE# must be asserted during read mode command input during “Read Spare Area” (50h) CLE cycle.
2. The “RESET” (FFh) or “Read Status” (70h) command may be written to the device during busy (RY/BY# is logic low).
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Am30LV0064D
27
AC CHARACTERISTICS
tCES
tCEH
CE#
tCLS
tCLH
CLE
tALS
tALH
ALE
tWP
WE#
tDS
tDH
I/O7-0
SE#
Command Dependent
Figure 16.
Command Input Cycle
tCES
CE#
tCLS
tWC
CLE
tALS
ALE
tWP
tWH
tALH
WE#
tDS
I/O7-0
A7-A0
tDH
A16-A9
SE#
Figure 17.
28
Address Input Cycle
Am30LV0064D
A22-A17
AC CHARACTERISTICS
tCEH
CE#
tCLH
CLE
tALS
tWC
ALE
tWP
tWH
WE#
tDS
I/O7-0
Din 0
tDH
Din 1
Din 511
SE#
22203C-22
Figure 18.
Data Input Cycle
tCHZ
CE#
RY/BY#
tRC
tRR
tRP
tREH
RE#
tREA
I/O7-0
SE#
tRHZ
Dout
Dout
Dout
Command Dependent
Figure 19.
Serial Read Cycle
Am30LV0064D
29
AC CHARACTERISTICS
tCES
tCEH
tCELS
tCHZ
CE#
tCLS
tCLH
tCR
CLE
tCLS
ALE
tWP
tWHR
WE#
RE#
tDS
I/O7-0
tDH
tOZR
tRLS
70h
tRHZ
Status
RY/BY#
Figure 20.
Status Read Cycle
tCES
tCEH
CE#
tCLH
tCRY
tCLS
tCHZ
CLE
tALH
ALE
tWC
tALRE
WE#
tR
tRC
tRHZ
RE#
tRR
tDH
tWB
tDS
I/O7-0
00h/01h
A7-A0
A16-A9
A22-A17
Dout N
Dout 527
tRB
RY/BY#
SE#
22203C-25
Figure 21.
30
Read Data
Am30LV0064D
AC CHARACTERISTICS
tCES
CE#
tCLH
tCLS
tCHZ
CLE
tALH
tALH
ALE
tALS
tWC
tALRE
WE#
tR
tRC
tRHZ
RE#
tDH
tRR
tWB
tDS
I/O7-0
00h/01h
A7-A0
A16-A9
A22-A17
Dout N
Dout 527
tREA
RY/BY#
SE#
22203C-26
Figure 22.
tCES
Read Data (Interrupted by CE#)
tCEH
CE#
tCLH
tCLS
CLE
tALH
tALH
ALE
tALS
tWC
tALRE
WE#
tR
tRC
RE#
tDS
tRR
tWB
tDH
I/O7-0
50h
A7-A0
A16-A9
A22-A17
Dout 512+N
Dout 527
tREA
RY/BY#
SE#
22203C-27
Figure 23.
Read Spare Area
Am30LV0064D
31
AC CHARACTERISTICS
CE#
CLE
ALE
WE#
RE#
tR
00h
I/O7-0
A7-A0
A16-A9
tR
A22-A17
Dout N
Dout 527
Dout 0
Dout 527
RY/BY#
Page M
Page M + 1
SE#
22203C-28
Figure 24.
Sequential Read
tCES
CE#
tCLS
CLE
tCLH
tALS
ALE
tCLS
tALS
tALH
tWC
Din N
Din 527
WE#
tALH
RE#
tDH
tDS
I/O7-0
80h
A7-A0
tWB
A16-A9
A22-A17
10h
70h
I/O 0
tPGM
RY/BY#
SE#
22203C-29
Figure 25.
32
Page Program
Am30LV0064D
AC CHARACTERISTICS
tCES
CE#
tCLS
CLE
tCLH
tALS
ALE
tCLS
tALS
tALH
WE#
tALH
tWC
RE#
tDS
tDH
I/O7-0
60h
A16-A9
tWB
A22-A17
D0h
70h
I/O 0
tERS
RY/BY#
SE#
22203C-30
Figure 26.
Block Erase
tCES
CE#
tCLS
CLE
tCLH
tALS
ALE
tCLS
tALS
tALH
WE#
tALH
tWC
RE#
tDH
tDS
I/O7-0
60h
A16-A9
tWB
A22-A17
D0h
B0h
I/O 5
RY/BY#
SE#
22203C-31
Figure 27.
Erase Suspend
Am30LV0064D
33
AC CHARACTERISTICS
CE#
CLE
ALE
WE#
RE#
tWB
D0h
I/O7-0
70h
I/O 0
tERS
RY/BY#
SE#
22203C-32
Figure 28.
Erase Resume
CE#
CLE
ALE
WE#
RE#
(Page M)
I/O7-0
Data Input
80h
Data Input
10h
70h
I/O 0
80h
10h
70h
I/O 0
RY/BY#
A7-A0
A22-A17
A16-A9
Program Page M
Figure 29.
34
Sequential Page Program
Am30LV0064D
Program Page M + 1
AC CHARACTERISTICS
tCES
tCEH
tCR
CE#
tCLS
tCLS
CLE
tCLH
tALH
tALS
tAR
ALE
tALH
WE#
RE#
tDS
tDH
I/O7-0
90h
00h
tREA2
tREA2
01h
E6h
RY/BY#
SE#
Figure 30.
VCC
ID and Manufacturer Read
2.5 V (min)
2.5 V (min)
0 ns (min)
0 ns (min)
WP#
ALE, CLE,
CE#, RE#,
WE#
SE#
22203C-35
Figure 31.
Write Protect (WP#) Timing During Power Transitions
Am30LV0064D
35
PROGRAM AND ERASE CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
tR
Read Data Transfer Time
–
6.5
7
µs
tPGM
Page Program Time
–
0.2
1.0
ms
tERS
Block Erase Time
–
2
10
ms
Symbol
Parameter
Min
Typ
Max
Unit
J40 NV/B
Number of Valid Blocks
1024
1024
1024
Blocks
VALID BLOCKS
Note: The J40 device is guaranteed to ship with all valid blocks (no invalid blocks).
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP II PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
36
Am30LV0064D
Test Conditions
Min
Unit
85°C
10
Years
PHYSICAL DIMENSIONS
TS 044—44/40-Pin Standard Thin Small Outline Package II
Dwg rev AA; 10/99
Am30LV0064D
37
PHYSICAL DIMENSIONS
TSR044—44/40-Pin Reverse Thin Small Outline Package II
Dwg rev AA; 10/99
38
Am30LV0064D
PHYSICAL DIMENSIONS
FBE040—40-Ball Fine Pitch Ball Grid Array (FBGA) 8 x 15 mm package
Dwg rev AF; 10/99
Am30LV0064D
39
REVISION SUMMARY
Revision B (December 1998)
Distinctive Characteristics
Fast read and program performance: Noted that specifications are typical.
and 3rd and 4th rows refer to write mode. Changed
the following: SE# for read mode, command input to
L/X; RY/BY# for write mode, command input to L/H;
SE# and WP# for standby mode to X.
Command Set: Moved Erase Suspend/Resume commands from basic to superset commands.
Timing diagrams—all SE# waveforms in section:
Added waveform, or modified existing waveform to
show where input is don’t care.
General Description
Physical Dimensions
Modified description of Embedded Erase.
Added TSOP II package drawings.
Functional Pin Description
Revision B+1 (January 1999)
Address Latch Enable: Clarified description relating to
address and data registers.
General Description
Added second paragraph.
Read Enable: Changed tRSTO to tRLS.
Ordering Information
Cell Layout and Address Assignment
Figure 1: Split 512 byte data register into two 256 byte
registers. Added representation of one page (528
bytes) to figure.
Device Operations
In fourth paragraph, third sentence, deleted the phrase
“during erase.”
Ordering Information
Deleted extended temperature range.
In the fifth paragraph, changed “Read Data” to “Wait
For.”
Command Definitions
Added Note 8 to table.
Noted in the paragraph headings for gapless read,
erase suspend, and erase resume that commands are
superset.
Device Operations
First paragraph: Clarified description of command
decoder.
Timing diagrams—all SE# waveforms in section:
Added waveform, or modified existing waveform to
show where this input is don’t care.
Erase Suspend and Erase Resume: Noted that both
are AMD superset commands.
Figure 9, Program Operations Flow Chart: Noted portion that may be required to exceed guaranteed
endurance.
Operating Ranges
Deleted references to extended temperature and regulated voltage range.
DC Characteristics
Page Program: In the second paragraph, fourth sentence, clarified that after ten consecutive partial
program operations within a given page, the block
containing that page is erased.
Operating Ranges
Added VCCQ supply voltage ratings.
DC Characteristics
Test Specifications table: Split the value column into
two columns describing test conditions for different
voltage ranges.
AC Characteristics
In various figures, added breaks in waveforms where
missing, to match other waveforms in the same figure.
Erase Suspend figure: In the I/O7-0 waveform,
changed the last data to I/O 5.
Added test specifications table and figure.
AC Characteristics
Normal Operation table: Clarified descriptions of tCEH,
tCR, and tCRY.
Mode Selection table: Added notes. Modified mode
column to show 1st and 2nd rows refer to read mode,
40
Added FBGA designator. In performance range description, changed “sectors” to “blocks.”
Status Read Cycle, Read Data, and Read Data (Interrupted by CE#), and Read Spare Area figures:
Changed the beginning of the tWB parameter to match
the beginning of the tALH and tR parameters.
Am30LV0064D
Revision B+2 (February 1999)
Functional Pin Description
Physical Dimensions
Address Latch Enable (ALE): Added ALE signal
equirement for address sequence.
Added the FBE040 drawing.
Revision B+3 (March 8, 1999)
Read Data, Gapless Read, Read Spare Area, and
Input Data and Page Program figures
Ordering Information
Added CE# don’t care areas to waveforms. Added
notes to figures.
Changed nomenclature for the FBE040 FBGA package to WG.
Page Program description
Revision B+4 (April 21, 1999)
In second paragraph, modified statement on partial
page programming.
Physical Dimensions
Program Operations Flow Chart figure
Corrected the BSC length and width dimensions in the
FBE040 drawing for the ball grid array.
Added address pointed command box below Start
box.
Revision B+5 (June 17, 1999)
AC Characteristics
Normal Operation table: Modified note 2.
Global
Deleted references to K40 ordering part number and
commercial temperature range.
Physical Dimensions
Replaced figures with more detailed illustrations.
Distinctive Characteristics
Revision C+1 (June 23, 2000)
Endurance is now 10,000 cycles. Added bullets for industrial range and 100% good blocks.
Ordering Information
AC Characteristics
Corrected valid combination and package marking for
FBGA package.
Changed tWH to 20 ns. Added note for tREA.
Revision C+2 (August 14, 2000)
Revision C (May 19, 2000)
DC Characteristics table
Global
Added VCC = VCCQ as test conditions for VOL and VOH.
Changed the data sheet designation from “advance information” to “preliminary.” Only minor parameter
changes, if any, may occur. Changes to speed, package, and temperature range combinations may also
appear in future data sheet revisions.
AC Characteristics
Command, Address, and Data Input table: Changed
tWP from 25 to 30 ns, and tWH from 20 to 15 ns.
Revision C+3 (October 6, 2000)
Connection Diagrams
Changed NC to RFU (reserved for future use) on the
following: pin 6 on standard TSOP-II, pin 39 on reverse TSOP-II, and ball E1 on FBGA.
Global
Removed “Preliminary” status from data sheet.
DC Characteristics table
Pin Configuration
Deleted RESET# as a test condition for ISB2; the device
does not have that input.
Added definition of RFU.
Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am30LV0064D
41