K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Document Title
16M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
Advance
0.0
Initial issue.
May 28’th 2001
0.1
K9F2808U0B(3.3V device)’s qualification is finished
Jun. 30th 2001
0.2
K9F2808Q0B (1.8V device)
- Changed typical read operation current (Icc1) from 8mA to 5mA
- Changed typical program operation current (Icc2) from 8mA to 5mA
- Changed typical erase operation current (Icc3) from 8mA to 5mA
- Changed typical program time(tPROG) from 200us to 300us
- Changed ALE to RE Delay (ID read, tAR1) from 100ns to 20ns
- Changed CLE hold time(tCLH) from 10ns to 15ns
- Changed CE hold time(tCH) from 10ns to 15ns
- Changed ALE hold time(tALH) from 10ns to 15ns
- Changed Data hold time(tDH) from 10ns to 15ns
- Changed CE Access time(tCEA) from 45ns to 60ns
- Changed Read cycle time(tRC) from 50ns to 70ns
- Changed Write Cycle time(tWC) from 50ns to 70ns
- Changed RE Access time(tREA) from 35ns to 40ns
- Changed RE High Hold time(tREH) from 15ns to 20ns
- Changed WE High Hold time(tWH) from 15ns to 20ns
0.3
1. Device Code is changed
- TBGA package information : ’B’ --> ’D’
ex) K9F2808Q0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0
K9F2808U0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0
2. V IH ,VIL of K9F2808Q0B(1.8 device) is changed
Jul. 30th 2001
K9F2808Q0B
: Preliminary
Aug. 23th 2001
(before revision)
Input High Voltage
V IH
Input Low Voltage,
All inputs
V IL
I/O pins
VccQ-0.4
VccQ
Except I/O pins
V CC-0.4
-
VCC
-
0
-
0.4
(after revision)
I/O pins
Input High Voltage
Input Low Voltage,
All inputs
VccQ
+0.3
VccQ-0.4
V IH
V IL
Except I/O pins
V CC-0.4
-
VCC
+0.3
-
-0.3
-
0.4
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Revision History
Revision No. History
0.4
1. IOL (R/B) of 1.8V device is changed.
Draft Date
Remark
Nov 5th 2001
Preliminary
-min. Value: 7mA -->3mA
-typ. Value: 8mA -->4mA
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
0.5
1. Parameters are changed in 1.8V part(K9F2808Q0B) .
Feb 15th 2002
- tCH is changed from 15ns to 20ns
- tCLH is changed from 15ns to 20ns
- tALH is changed from 15ns to 20ns
- tDH is changed from 15ns to 20ns
0.6
1. Parameters are changed in 1.8V part(K9F2808Q0B) .
May 3rd 2002
- tRP is changed from 25ns to 35ns
- tWB is changed from 100ns to 150ns
- tREA is changed from 40ns to 45ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
16M x 8 Bit Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
K9F2808Q0B-D
1.7 ~ 1.9V
Organization
TBGA
K9F2808U0B-Y
K9F2808U0B-D
PKG Type
X8
2.7 ~ 3.6V
TSOP1
TBGA
K9F2808U0B-V
WSOP1
FEATURES
• Voltage Supply
- K9F2808Q0B : 1.7~1.9V
- K9F2808U0B : 2.7 ~ 3.6 V
• Organization
- Memory Cell Array : (16M + 512K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• 528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access
- K9F2808Q0B : 70ns
- K9F2808U0B : 50ns
• Fast Write Cycle Time
- Program Time
- K9F2808Q0B : 300 µs(Typ.)
- K9F2808U0B : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Package
- K9F2808U0B-YCB0/YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2808X0B-DCB 0/ DIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- K9F2808U0B-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
* K9F2808U0B-V(WSOPI ) is the same device as
K9F2808U0B-Y(TSOP1) except package type.
GENERAL DESCRIPTION
The K9F2808X0B is a 16M(16,777,216)x8bit NAND Flash Memory with a spare 512K(524,288)x8bit. The device is offered in 1.8V or
3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528-byte page in typical 200µs and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in a
page can be read out at 70ns/50ns(K9F2808Q0B:70ns, K9F2808U0B:50ns) cycle time per byte. The I/O pins serve as the ports for
address and data input/output as well as command input. The on-chip write control automates all program and erase functions
including pulse repetition, where required, and internal verification and margining of data. Even write-intensive systems can take
advantage of the K9F2808X0B’s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with
real time mapping-out algorithm.
The K9F2808X0B is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption.
3
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9F2808U0B-YCB0/YIB0
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
#48
#24
#25
0.50
0.0 197
12 .40
MAX
0.488
( 0 .25 )
0.010
#1
12.00
0.472
+0 .0 03
0 .00 8- 0.0 0 1
0.20 -0 .0 3
+0 .07
20.00± 0.20
0.787± 0.008
0.004
MAX
Unit :mm/Inch
+0 .07 5
0~8¡Æ
0.45~0.75
0.018~0.030
+0 .00 3
0.005-0 .0 01
18.40± 0.10
0.724± 0.004
0.1 25 0 .03 5
0 .25
0.010 TYP
1.00± 0.05
0.039 ±0.002
( 0.50 )
0.020
4
1.20
0.047 MAX
0.05
MIN
0.002
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
PIN CONFIGURATION (TBGA)
K9F2808X0B-DCB0/DIB0
DNU DNU
DNU DNU
DNU
DNU DNU
/WP
ALE
NC
/CE
/WE
R/B
NC
/RE
CLE NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O0
NC
NC
I/O1
NC
Vss
I/O2
I/O3 I/O4
NC
NC
VccQ I/O5
I/O6
Vcc
I/O7
Vss
DNU DNU
DNU DNU
DNU DNU
DNU DNU
(Top View)
PACKAGE DIMENSIONS
63-Ball TBGA (measured in millimeters)
Top View
Bottom View
9.00 ±0.10
0.80 x9= 7.20
0.80 x5= 4.00
9.00 ±0.10
6
5
0.80
4
3
2
B
1
0.80
(Datum A)
A
#A1
A
D
2.80
E
F
G
H
63-∅0.45 ±0.05
2.00
0.32 ±0.05
Side View
9.00 ±0.10
0.08MAX
5
0.45 ±0.05
0.90 ±0.10
∅ 0.20 M A B
11.00 ±0.10
C
0.80 x7= 5.60
11.00 ±0.10
(Datum B)
0.80 x11= 8.80
B
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9F2808U0B-VCB0/VIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
0.58± 0.04
15.40± 0.10
#48
#24
#25
+0 .0 7
- 0.0 3
0.16
+0.0 7
-0 .03
#1
0.5 0TY P
(0.50± 0.0 6)
0 .20
1 2.0 0±0 .1 0
°
~8
0°
75
0.10 +0.0
-0 .03 5
(0.1Min)
0.45~0.75
17.00 ±0.20
6
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
PIN DESCRIPTION
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The W E input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
V CCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
V CC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and V SS pins of each device to common power supply outputs.
7
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V CC
V SS
A9 - A 23
X-Buffers
Latches
& Decoders
A0 - A7
Y-Buffers
Latches
& Decoders
128M + 4M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 32768
Page Register & S/A
A8
Y-Gating
Command
Command
Register
Vcc/V CCQ
V SS
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
32K Pages
(=1,024 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Byte
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Byte
1 Device = 528Byte x 32Pages x 1024 Blocks
= 132 Mbits
8 bit
512B Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
16 Byte
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
3rd Cycle
A 17
A 18
A 19
A 20
A 21
A 22
A 23
*L
1st Cycle
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A 8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
8
Column Address
Row Address
(Page Address)
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F2808X0B is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are
located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed
by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program and read
operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists of 1024
blocks, and a block is separately erasable by 16K-byte unit. It indicates that the bit by bit erase operation is prohibited on the
K9F2808X0B.
The K9F2808X0B has addresses multiplexed with 8 I/O ′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O ′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution.
The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low
row address and high row address, in that order. Page Read and Page Program need the same three address cycles following
required command input. In Block Erase operation, however, only two row address cycles are used. Device operations are selected
by writing specific commands into command register. Table 1 defines the specific commands of the K9F2808X0B.
Table 1. COMMAND SETS
1st. Cycle
2nd. Cycle
Read 1
Function
00h/01h (1)
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
Acceptable Command during Busy
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on 2nd half of register by the 01h command, start pointer is automatically moved to
1st half register(00h) on the next cycle.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
O
O
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
K9F2808X0B-YCB0,DCB0
Unit
K9F2808Q0B(1.8V)
K9F2808U0B(3.3V)
V IN/OUT
-0.6 to + 2.45
-0.6 to + 4.6
V
V CC
-0.2 to + 2.45
-0.6 to + 4.6
V
V CCQ
-0.2 to + 2.45
-0.6 to + 4.6
V
Voltage on any pin relative to V SS
Temperature
Under Bias
Rating
Symbol
-10 to + 125
TBIAS
K9F2808X0B-YIB0,DIB 0
°C
-40 to + 125
Storage Temperature
TSTG
°C
-65 to + 150
NOTE:
1. Minimum DC voltage is -0.6V on input/output pins and -0.2V on Vcc and VccQ pins. During transitions, this level may undershoot to -2.0V for periods
<20ns. Maximum DC voltage on input/output pins is V CCQ +0.3V which, during transitions, may overshoot to VC C +2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F2808X0B-YCB0,DCB 0:TA=0 to 70°C, K9F2808X0B-YIB0,DIB0:T A=-40 to 85°C)
Parameter
K9F2808Q0B(1.8V)
Symbol
K9F2808U0B(3.3V)
Unit
Min
Typ.
Max
Min
Typ.
Max
Supply Voltage
V CC
1.7
1.8
1.9
2.7
3.3
3.6
V
Supply Voltage
V CCQ
1.7
1.8
1.9
2.7
3.3
3.6
V
Supply Voltage
V SS
0
0
0
0
0
0
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)
K9F2808Q0B(1.8V)
Parameter
Symbol
Test Conditions
CE=VIL, IOUT=0mA
K9F2808Q0B: tRC=70ns
K9F2808U0B: tRC=50ns
K9F2808U0B(3.3V)
Min
Typ
Max
Min
Typ
Max
-
5
15
-
10
20
Operat- Sequential Read
ing
Current
Program
ICC1
ICC2
-
-
5
15
-
10
20
Erase
ICC3
-
-
5
15
-
10
20
Stand-by Current(TTL)
ISB1
CE=VIH, WP =0V/VCC
-
-
1
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP =0V/V CC
-
10
50
-
10
50
Input Leakage Current
ILI
V IN=0 to Vcc(max)
-
-
±10
-
-
±10
Output Leakage Current
ILO
V OUT=0 to Vcc(max)
-
-
±10
-
-
±10
VccQ+0
.3
2.0
-
V CCQ+0.3
Input High Voltage
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
I/O pins
VccQ-0.4
Except I/O pins
V CC-0.4
-
VCC
+0.3
2.0
-
V CC+0.3
-0.3
-
0.4
-0.3
-
0.8
V CCQ-0.1
-
-
2.4
-
-
-
-
0.1
-
-
0.4
3
4
-
8
10
-
V IH
V IL
V OH
V OL
K9F2808Q0B :I OH=-100µ A
K9F2808U0B :I OH=-400µA
K9F2808Q0B :I OL=100uA
K9F2808U0B :I OL =2.1mA
IOL
K9F2808Q0B :V OL =0.1V
(R/B)
K9F2808U0B :V OL =0.4V
10
Unit
mA
µA
V
mA
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
1004
-
1024
Blocks
NOTE:
1. The K9F2808X0B may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits . Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correcti on.
AC TEST CONDITION
(K9F2808X0B-YCB0, DCB0 :TA=0 to 70°C, K9F2808X0B-YIB0,DIB0:TA=-40 to 85°C
K9F2808Q0B : Vcc=1.7V~1.9V , K9F2808U0B : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2808Q0B
K9F2808U0B
0V to VccQ
0.4V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
5ns
5ns
VccQ/2
1.5V
K9F2808Q0B:Output Load (VccQ:1.8V +/-10%)
K9F2808U0B:Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
K9F2808U0B:Output Load (VccQ:3.3V +/-10%)
-
1 TTL GATE and CL=100pF
Input and Output Timing Levels
CAPACITANCE( TA=25°C, VCC =1.8V/3.3V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
Item
C I/O
V IL =0V
-
10
pF
Input Capacitance
C IN
V IN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
H
L
L
H
H
RE
WP
L
H
X
L
H
X
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
L
L
L
H
H
X
During Read(Busy) on K9F2808U0B_Y or K9F2808U0B_V
X
X
X
X
H
X
During Read(Busy) on the devices except K9F2808U0B_Y
and K9F2808U0B_V
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
X
L
Write Protect
X
X
X
(1)
X
H
WE
X
X
Mode
Read Mode
Command Input
Address Input(3clock)
Write Mode
Command Input
Address Input(3clock)
CC(2)
Stand-by
Symbol
Min
Typ
Max
Unit
-
K9F2808Q0B:3 00
K9F2808U0B:200
500
µs
-
-
2
cycles
-
-
3
cycles
-
2
3
ms
0V/V
NOTE : 1. X can be VIL or V IH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Program Time
Number of Partial Program Cycles
in the Same Page
Block Erase Time
tPROG
Main Array
Nop
Spare Array
tBERS
11
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
K9F2808Q0B
Parameter
Symbol
K9F2808U0B
Min
Max
Min
Max
Unit
CLE Set-up Time
tCLS
0
-
0
-
ns
CLE Hold Time
tCLH
20
-
10
-
ns
CE Setup Time
tCS
0
-
0
-
ns
CE Hold Time
tCH
20
-
10
-
ns
WE Pulse Width
tWP
25 (1)
-
25
-
ns
ALE Setup Time
tALS
0
-
0
-
ns
ALE Hold Time
tALH
20
-
10
-
ns
Data Setup Time
tDS
20
-
20
-
ns
Data Hold Time
tDH
20
-
10
-
ns
Write Cycle Time
tWC
70
-
50
-
ns
WE High Hold Time
tWH
20
-
15
-
ns
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
K9F2808Q0B
Parameter
Symbol
Min
Max
K9F2808U0B
Min
Max
Unit
tR
-
10
-
10
µs
ALE to RE Delay( ID read )
tAR1
20
-
20
-
ns
ALE to RE Delay(Read cycle)
tAR2
50
-
50
-
ns
CLE to RE Delay
tCLR
50
-
50
-
ns
Ready to RE Low
tRR
20
-
20
-
ns
RE Pulse Width
tRP
35
-
25
-
ns
WE High to Busy
tWB
-
150
-
100
ns
Read Cycle Time
tRC
70
-
50
-
ns
CE Access Time
tCEA
-
60
-
45
ns
RE Access Time
tREA
-
45
-
35
ns
RE High to Output Hi-Z
tRHZ
15
30
15
30
ns
CE High to Output Hi-Z
tCHZ
-
20
-
20
ns
RE High Hold Time
tREH
20
-
15
-
ns
tIR
0
-
0
-
ns
WE High to RE Low
tWHR
60
-
60
-
ns
Device Resetting Time (Read/Program/Erase)
tRST
-
5/10/500(1)
-
5/10/500 (1)
µs
tRB
-
100
-
100
ns
-
50 +tr(R/B) (3)
-
50 +tr(R/B) (3)
ns
100
-
100
-
ns
Data Transfer from Cell to Register
Output Hi-Z to RE Low
Last RE High to Busy
(at sequential read)
K9F2808U0B-Y
only
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last
serial read) (2)
tCRY
tCEH
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
12
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding invalid block(s) is so called as the invalid block information. Devices ,regardless of having invalid block(s), have the
same quality level because all valid blocks have same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it’s bit line and common source line is isolated by a select transistor. The system design must be
able to mask out invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be
a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either 1st or 2nd page of every invalid block
has non-FFh data at the column address of 517. Since invalid block information is also erasable in most cases, it is impossible to
recover the information once it was erased. Therefore, system must be able to recognize the invalid block(s) based on the original
invalid block information and create invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the
original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
*
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
13
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for actual
data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, we recommend using ECC without any block replacement in read or verification failure due to single bit error case. Th e
said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Write Data
Wait for tR Time
Write 10h
Verify Data
Read Status Register
No
*
Program Error
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
I/O 0 = 0 ?
Yes
14
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
Erase Error
No
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
{
nth
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
Buffer memory of the controller.
{
Block B
1
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
15
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Pointer Operation of K9F2808X0B
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, starting column address can be set to somewhere of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is entered. But, ’01h’ command is effective only
for one time operation. After any operation of Read, Program, Erase, Reset, Power_Up following ’01h’ command, the address
pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be entered before ’80h’
command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from ’B’ area,
’01h’ command must be entered right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
256 Byte
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’ area can be programmed.
80h
’50h’ command can be omitted.
16
10h
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant saving in power consumption.
Figure 5. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
WE
ALE
I/O0~7
80h
Start Add.(3Cycle)
t CS
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
RE
tWP
WE
I/O0~7
out
Figure 6. Read Operation with CE don’t-care.
On K9F2808U0B_Y or K9F2808U0B_V
CE must be held
low during tR
CLE
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/O0~7
00h
Data Output(sequential)
Start Add.(3Cycle)
17
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
* Command Latch Cycle
CLE
tCLS
tCLH
tCS
t CH
CE
tWP
WE
t ALH
tALS
ALE
t DH
t DS
Command
I/O0 ~7
* Address Latch Cycle
tCLS
CLE
t CS
t WC
tWC
CE
tWP
t WP
tWP
WE
tWH
tALH tALS
tALS
t WH
tALH tALS
tALH
ALE
t DS
I/O 0~7
tDH
tDS
A0~A7
t DH
A9~A16
18
tDS
tDH
A17~A23
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
* Input Data Latch Cycle
t CLH
CLE
tCH
CE
tWC
t ALS
tWP
tWP
≈
ALE
tWP
WE
I/O 0~7
tWH
t DH
DIN 0
t DS
tDH
DIN 1
t DS
≈ ≈
tDS
tDH
DIN 511
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
t RC
≈
CE
tCHZ
tOH
tREH
tREA
≈
t REA
tRP
RE
t REA
I/O0~7
Dout
Dout
≈
t RHZ
t RHZ
t OH
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
19
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
FLASH MEMORY
* Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
t WP
WE
tCEA
tCHZ
t OH
tWHR
RE
t DH
tDS
I/O0 ~7
tIR
tRHZ
tOH
tREA
Status Output
70h
READ1 OPERATION(READ ONE PAGE)
CLE
1)
On K9F2808U0B_Y or K9F2808U0B_V
CE must be held
low during tR
CE
tCEH
t CHZ
t OH
tWC
WE
t WB
t CRY
tAR2
ALE
tR
tRHZ
tOH
tRC
≈
RE
I/O 0~7
00h or 01h A0 ~ A7
A9 ~ A1 6
Column
Address
R/B
A17 ~ A2 4
Dout N
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout 527
tRB
Page(Row)
Address
Busy
1)
NOTE : 1) is only valid on K9F2808U0B_Y or K9F2808U0B_V
20
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
FLASH MEMORY
READ2 OPERATION (READ ONE PAGE)
CLE
On K9F2808U0B_Y or K9F2808U0B_V
CE must be held
low during tR
CE
WE
tR
t WB
t AR2
ALE
≈
t RR
I/O0 ~7
50h
A 0 ~ A7
A 9 ~ A1 6
Dout
511+M
A17 ~ A23
R/B
Dout
511+M+1
≈
RE
Dout 527
Selected
Row
M Address
A0 ~A 3 : Valid Address
A4 ~A 7 : Don′t care
512
16
Start
address M
PAGE PROGRAM OPERATION
CLE
CE
t WC
tWC
tWC
WE
tWB
tPROG
ALE
I/O0 ~7
80h
A0 ~ A7 A 9 ~ A1 6 A17 ~ A2 3
Sequential Data Column
Input Command Address
Page(Row)
Address
Din
N
Din
N+1
≈≈
RE
1 up to 528 Byte Data
Serial Input
10h
70h
Program
Command
21
I/O0
Read Status
Command
≈
R/B
Din
527
I/O0 =0 Successful Program
I/O0 =1 Error in Program
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
t WB
tBERS
ALE
RE
I/O0 ~7
60h
A9 ~ A 16
A1 7 ~ A2 3
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
≈
Page(Row)
Address
Erase Command
Read Status
Command
I/O 0=0 Successful Erase
I/O 0=1 Error in Erase
MANUFACTURE & DEVICE ID READ OPERATION
t CLR
CLE
CE
WE
ALE
t AR1
RE
tREA
I/O 0 ~ 7
90h
Read ID Command
00h
ECh
Address. 1cycle
Maker Code
22
Device
Code*
Device Code
Device
Device Code*
K9F2808Q0B
33h
K9F2808U0B
73h
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing
00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled
when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than
10µ s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data
in a page is loaded into the registers, they may be read out by sequential RE pulse of 70ns/50n(K9F2808Q0B:70ns,
K9F2808U0B:50ns) period cycle. High to low transitions of the RE clock take out the data from the selected column address up to
the last column address.
Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(512 to 527 bytes)
may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of spare area while
addresses A4 to A7 are ignored. To move the pointer back to the main area, Read1 command(00h/01h) is needed. Figures 7
through 8 show typical sequence and timing for each read operation.
Figure 7,8 details the sequence.
Sequential Row Read is available only on K9F2808U0B_Y or K9F2808U0B_V :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µ s
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page
of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 7-1, 8-1 show typical sequence and timings for sequential row read
operation.
Figure 7. Read1 Operation
CLE
On K9F2808U0B_Y or K9F2808U0B_V
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/O 0~7
00h
Start Add.(3Cycle)
Data Output(Sequential)
A 0 ~ A7 & A9 ~ A23
(00h Command)
1st half array
(01h Command)*
2st half array
Data Field
Spare Field
1st half array
2st half array
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
23
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Figure 8. Read2 Operation
CLE
On K9F2808U0B_Y or K9F2808U0B_V
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
50h
I/O0~7
Data Output(Sequential)
Start Add.(3Cycle)
( A4 ~ A7 :
Don′t Care)
A0 ~ A 3 & A9 ~ A 2 3
Spare Field
1st half array
2nd half array
Data Field
Spare Field
tR
R/B
I/O0 ~
7
00h
Start Add.(3Cycle)
01h
≈
Figure 7-1. Sequential Row Read1 Operation (only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block)
tR
Data Output
Data Output
Data Output
1st
2nd
(528 Byte)
Nth
(528 Byte)
A0 ~ A 7 & A9 ~ A 2 4
(GND input=L, 00h Command)
1st half array
(GND input =L, 01h Command)
2nd half array
1st half array
Data Field
Spare Field
(GND input=H, 00h Command)
2nd half array
1st
2nd
Nth
Block
tR
1st half array
2nd half array
1st
2nd
Nth
1st
2nd
Nth
Data Field
24
Spare Field
Data Field
Spare Field
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
I/O0~7
tR
tR
R/B
50h
≈
Figure 8-1. Sequential Row Read2 Operation (GND Input=Fixed Low)
(only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block)
Start Add.(3Cycle)
Data Output
1st
A0 ~ A 3 & A9 ~ A 2 4
tR
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A 4 ~ A7 :
Don ′t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up
to 528, in a single page program cycle. The number of consecutive partial page program operation within the same page without
intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random
order in a block. Page program cycle consists of a serial data loading(up to 528 bytes of data) into the page register, and prog ram of
loaded data into the appropriate cell. Serial data loading can start in 2nd half array by moving pointer. About the pointer operation,
please refer to the attached technical notes. Serial data loading is executed by entering the Serial Data Input command(80h) and
three cycle address input and then serial data loading. The bytes except those to be programmed need not to be loaded. The Page
Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering 80h will not initi ate
program process. The internal write controller automatically executes the algorithms and timings necessary for program and verif ication, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,
with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming
is in progress. When the Page Program is completed, the Write Status Bit(I/O 0) may be checked(Figure 9). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 9 details the sequence.
Figure 9. Program & Read Status Operation
t PROG
R/B
I/O 0~7
80h
Address & Data Input
10h
70h
A0 ~ A7 & A 9 ~ A2 3
528 Byte Data
I/O0
Fail
25
Pass
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2
cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This twostep sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise condition. At the rising edge of WE after erase confirm command input, internal write controller handles erase and erase-verification. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 10 details the sequence.
Figure 10. Block Erase Operation
tBERS
R/B
I/O0~7
60h
Address Input(2Cycle)
I/O0
70h
D0h
Pass
Block Add. : A 9 ~ A2 3
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to command register, a read cycle takes out
the content of the Status Register to the I/O pins on the falling edge of CE or RE. This two line control allows the system to poll the
progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 3 for specific Status Register definitions. The command register remains in Status Read mode
until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00 h or
50h) should be given before sequential page read cycle.
Table3. Read Status Register Definition
I/O #
Status
I/O 0
Program / Erase
Definition
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
I/O 3
"0"
"0"
Reserved for Future
Use
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
I/O 7
Write Protect
26
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command register
remains in Read ID mode until further commands are issued to it.
Figure 11 shows the operation sequence.
Figure 11. Read ID Operation
t CLR
CLE
t CEA
CE
WE
tAR1
ALE
t WHR
RE
I/O 0~7
tREA
90h
00h
ECh
Address. 1cycle
Maker code
Device
Code*
Device code
Device
Device Code*
K9F2808Q0B
33h
K9F2808U0B
73h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when W P is high. Refer to table 4 for device status after reset operation. If the device is
already in reset state, new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 12 below.
Figure 12. RESET Operation
tRST
R/B
I/O 0~7
FFh
Table4. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
27
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
READY/BUSY
The device has a R/ B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/ B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 13). Its value c an be
determined by the following guidance.
Rp
ibusy
V CC
1.8V device - VOL : 0.1V, V OH : VCCq-0.1V
3.3V device - VOL : 0.4V, V OH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Fig 13 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
200n
1.7
2m
tr
100n
30
0.85
120
90
60
0.57
1.7
1K
tf
1.7
1.7
2K
3K
Rp(ohm)
tr ,tf [s]
3m
Ibusy [A]
tr,tf [s]
300n
Ibusy
300n
200n
1.2
300
200
0.8
Rp(min, 3.3V part) =
1m
100n
0.43
100
3.6
1.7
4K
1K
V CC(Max.) - V OL (Max.)
IOL + Σ IL
0.6
tf
3.6
3.6
3.6
2K
3K
Rp(ohm)
4K
1.85V
=
3mA + ΣIL
3.2V
V CC(Max.) - V OL(Max.)
IOL + Σ IL
2m
tr
Rp value guidance
Rp(min, 1.8V part) =
3m
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
28
1m
Ib usy [A]
400
2.4
Ibusy
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0
K9F2808U0B-YCB0,YIB0
K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Data Protection & Powerup sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V/2V(K9F2808Q0B:1.1V, K9F2808U0B:2V). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 1µs is required
before internal circuit gets ready for any command sequences as shown in Figure 14. The two step command sequence for program/
erase provides additional software protection.
≈
Figure 14. AC Waveforms for Power Transition
K9F2808Q0B : ~ 1.5V
K9F2808U0B : ~ 2.5V
VCC
≈
High
≈
WP
10µs
≈
WE
29
K9F2808Q0B : ~ 1.5V
K9F2808U0B : ~ 2.5V