FUJITSU MBM30LV0064-PFTR

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20878-3E
FLASH MEMORY
CMOS
64M (8M × 8) BIT NAND-type
MBM30LV0064
■ DESCRIPTION
The MBM30LV0064 device is a single 3.3 V 8M × 8 bit NAND flash memory organized as 528 byte × 16 pages
× 1024 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to
store ECC code(Specifications indecated are on condition that ECC system would be combined.). Program and
read data is transferred between the memory array and page register in 528 byte increments. A 528 byte page
can be programmed in 200 µs and an 8K byte block can be erased in 2 ms under typical conditions. An internal
controller automates all program and erase operations including the verification of data margins. Data within a
page can be read with a 50 ns cycle time per byte. The I/O pins are utilized for both address and data input/
output as well as command inputs. The MBM30LV0064 is an ideal solution for applications requiring mass nonvolatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other
uses which require high density and non-volatile storage.
■ PRODUCT LINE UP
Part No.
MBM30LV0064
Operating Temperature
–40°C to +85°C
VCC
+2.7 V to +3.6 V
Power Dissipation (Max.)
Read
72 mW
Erase / Program
72 mW
TTL Standby
3.6 mW
CMOS Standby
0.18 mW
■ PACKAGES
44-pin plastic TSOP (II)
Marking Side
Marking Side
(FPT-44P-M07)
(Normal Bend)
(FPT-44P-M08)
(Reverse Bend)
MBM30LV0064
■ FEATURES
• 3.3 V-only operating voltage (2.7 V to 3.6 V)
Minimizes system level power requirements
• Organization
Memory Cell Array : (8M + 256K) ×8 bit
Data Register
: (512 + 16) ×8 bit
• Automatic Program and Erase
Page Program : (512 + 16) Byte
Block Erase : (8K + 256) Byte
• 528 Byte Page Read Operation
Random Access : 7 µs (Max.)
Serial Access
: 35 ns (Max.)
• Fast Program and Erase
Program Time
: 200 µs (Typ.) / page
Block Erase Time : 2 ms (Typ.) / block
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
• 1,000,000 write/erase cycle guaranteed (ECC system required)
• Command Register Operation
• Package
44(40)-pin TSOP Type II (0.8 mm pitch)
Normal/Reverse Type
• Data Retention: 10 years
2
MBM30LV0064
■ PIN ASSIGNMENTS
TOP VIEW
TOP VIEW
Vss
1
44
Vcc
Vcc
44
1
Vss
CLE
2
43
CE
CE
43
2
CLE
ALE
3
42
RE
RE
42
3
ALE
WE
4
41
R/B
R/B
41
4
WE
SE
40
5
WP
WP
5
40
SE
N.C.
6
39
N.C.
N.C.
39
6
N.C.
N.C.
7
38
N.C.
N.C.
38
7
N.C.
N.C.
8
37
N.C.
N.C.
37
8
N.C.
N.C.
9
36
N.C.
N.C.
36
9
N.C.
N.C.
10
35
N.C.
N.C.
35
10
N.C.
11
34
34
11
12
33
33
12
32
N.C.
32
13
N.C.
N.C.
31
14
N.C.
15
N.C.
N.C.
N.C.
13
31
14
N.C.
N.C.
N.C.
15
30
N.C.
N.C.
30
N.C.
16
29
N.C.
N.C.
29
16
N.C.
N.C.
17
28
N.C.
N.C.
28
17
N.C.
I/O0
18
27
I/O7
I/O7
27
18
I/O0
I/O1
19
26
I/O6
I/O6
26
19
I/O1
I/O2
20
25
I/O5
I/O5
25
20
I/O2
I/O4
I/O4
24
21
I/O3
Vccq
Vccq
23
22
Vss
I/O3
Vss
24
21
23
22
FPT-44P-M07
FPT-44P-M08
3
MBM30LV0064
■ PIN DESCRIPTIONS
Pin Number Pin Name
I/O0 to
I/O7
Data Input/Output
The I/O ports are used for transferring command, address, and input/output data into
and out of the device. The I/O pins will be high impedance when the outputs are disabled or the device is not selected.
CLE
Command Latch Enable
The CLE signal enables the acquisition of the made command into the internal command register. When CLE=“H”, command are latched into the command register from
the I/O port upon the rising edge of the WE signal.
ALE
Address Latch Enable
The ALE signal enables the acquisition of either address or data into the internal address/data register. The rising edge of WE latch in addresses when ALE is high and
data when ALE is low.
43
CE
Chip Enable
The CE signal is used to select the device. When CE is high, the device enters a low
power standby mode. If CE transitions high during a read operation, the standby mode
will be entered. However, the CE signal is ignored if the device is in a busy state(R/B=L)
during a program or erase operation.
42
RE
Read Enable
The RE signal controls the serial data output. The falling edge of RE drives the data
onto the I/O bus and increments the column address counter by one.
4
WE
Write Enable
The WE signal controls writes from the I/O port. Data, address, and commands on the
I/O port are latched upon the rising of the WE pulse.
5
WP
Write Protect
The WP signal protects the device against accidental erasure or programming during
power up/down by disabling the internal high voltage generators. WP should be kept
low when the device powers up until VCC is above 2.5 V. During power down, WP
should be low when VCC falls below 2.5 V.
40
SE
Spare Area Enable
The SE input enables the spare area during sequential data input, page program, and
Read 1.
41
R/B
Ready Busy Output
The R/B output signal is used to indicate the operating status of the device. During program, erase, or read, R/B is low and will return high upon the completion of the operation. The output buffer for this signal is an open drain.
23
VCCq
Output Buffer Power Supply
The VCCq input supplies the power to the I/O interface logic. This power line is electrically isolated from VCC for the purpose of supporting 5V tolerant I/O.
44
VCC
Power Supply
1,22
VSS
Ground
6 to 17
28 to 39
N.C.
No Connection
18 to 21
24 to 27
2
3
4
Descriptions
MBM30LV0064
■ BLOCK DIAGRAM
R/B
High Voltage Pumps
Y-Decoder
Data Register & S/A
State Machine
X Decoder
ALE
CLE
SE
WP
CE
RE
WE
Command Register
Memory Array
Data Register & S/A
Y-Decoder
Address Register
Status Register
I/O Register & Buffer
I/O0 to I/O7
VCC
VCCq
VSS
5
MBM30LV0064
■ SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT
The Program operation is implemented in page units while the Erase operation is carried out in block units.
I/O0
Read and Program operation
are executed through Register
Register = 1 page size
Register
512
I/O7
16
Memory Cell
Array
16384 pages
(1024 blocks)
16 pages
→ 1 block
1) A page consists of (512+16) bytes;
- 512 bytes for main memory
- 16 bytes for redundancy or other use
2) A block consists of 16 pages; (8K+256) bytes.
3) Total device density =
528 bytes × 16 pages × 1024 blocks.
8 I/O
528
Figure 1
Schematic Cell Layout
Table 1
Addressing
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
First Cycle
A0
A1
A2
A3
A4
A5
A6
A7
Second Cycle
A9
A10
A11
A12
A13
A14
A15
A16
Third Cycle
A17
A18
A19
A20
A21
A22
X*
X*
A0 to A7 : column address
A9 to A22 : page address A13 to A22 : block address
A9 to A12 : Page address in block
(A8 is automatically set to “Low” or “High” by the “00h” command or the “01h” command in device inside.)
* : X = VIH or VIL
6
MBM30LV0064
■ DEVICE BUS OPERATIONS
Operation Table *1
Table 2
Mode
CLE
ALE
CE
RE
SE
WP
Command Input
H
L
L
H
X *4
X
Address Input (3 clock)
L
H
L
H
X *4
X
During Read (Busy)
L
L
L
H
H
L/H *3
X
Sequential Read & Data Output
L
L
L
H
L/H *3
X
Program/ Command Input
Erase
Address Input (2 or 3 clock)
Mode
H
L
L
H
X *4
H
L
H
L
H
X *4
H
Data Input
L
L
L
H
L/H *3
H
During Program (Busy)
X
X
X
X
X
L/H *3
H
During Erase (Busy)
X
X
X
X
X
X
H
Write Protect
X
X
X
X
X
X
L
Stand-by
X
X
H
X
X
Read
Mode
WE
0 V/VCC*2 0 V/VCC*2
*1: H: VIH, L: VIL, X: VIH or VIL
*2: WP should be biased to CMOS high or CMOS low for standby.
*3: When SE is high, spare area is deselected.
*4: If 50h command is input and read/program operation is executed only for spare area, SE must be low at the
command/address input.
Table 3
Read Mode Operation Status *
CLE
ALE
CE
WE
RE
I/O0 to I/O7
Power Supply
Output Select
L
L
L
H
L
Data Output
Active
Output Deselect
L
L
L
H
H
High Impedance
Active
Standby
X
X
H
X
X
High Impedance
Standby
Operation
*: H: VIH, L: VIL, X: VIH or VIL
7
MBM30LV0064
■ COMMAND OPERATION
Table 4
Function
Command Table
1st Cycle
2nd Cycle
Read (1)
00h *1
—
Read (2)
01h *2
—
Read (3)
50h *3
—
Sequential Data Input
80h
—
Page Program
10h
—
Block Erase
60h
D0h
Reset
FFh
—
Status Read
70h
—
ID Read
90h
—
*1: The 00h Command defines starting Address on the 1st half Page.
*2: The 01h Command defines starting Address on the 2nd half Page.
*3: The 50h Command is valid only When SE is low level.
8
Acceptable Command
During Busy State
MBM30LV0064
■ FUNCTIONAL DESCRIPTION
READ MODE
There are three distinct commands used for the read operation: 00h, 01h, and 50h. After the command cycle,
three address cycles are used to input the starting address. Upon the rising edge of the final WE pulse, there
is a 7 µs latency in which the 528 byte page is transferred to the data register. The R/B signal may be used to
monitor the completion of the data transfer. In the read operation, the CE signal must stay “Low” after the third
address input and during Busy state. If the CE signal goes High during this period, the read operation will be
terminated and then the standby mode will be entered. Once the page of data has been loaded into the data
register, it may be clocked out with consecutive 50 ns RE pulses. Each RE pulse will automatically advance the
column address by one. Once the last column has been read, the page address will automatically increment by
one and the data register will be updated with the new page after 7 µs.
The 00h Read command will set the pointer to the first half page of the array while the 01h Read command will
set it in the second half. It may be logical to think of 00h as a command which sets A8 = 0 while 01h sets A8 =
1. The 50h command set the pointer to the spare area, consisting of columns 512 to 527. During this read mode,
A3 to A0 is used to set the starting address of the spare area. As with the 00h and 01h operations, once the
spare area page is loaded into the data register, it may be read out by RE pulses. Each RE pulse will increment
the column address until the final column (527) is reached. At this time, the pointer will be reset to column 512
while the page address is incriminated and the data register is updated. The 00h or 01h command is required
to move the pointer back into the main array area.
Read (1), (2): 00h/01h
The Read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. This mode
(00h) will be automatically selected when the device powers up.
CE
CLE
ALE
WE
RE
R/B
Starting Address
I/O0
to I/O7
Y
X
Data Output
X
Command 01h
00h
0
255
511 527
Page (Row) X
Address
Y
Y
(Column Address)
Figure 2
Read Mode (1), (2) Operation
9
MBM30LV0064
Read (3): 50h
The Read (3) mode has identical timing to that of Read (1) and (2). However, while Read (1) and (2) are used
to access the array, Read (3) is used to access the 16 byte spare area. When the 50h command is executed,
the pointer will be set to an address space between columns 512 and 527. The values of Y will complete the
address decoding. During this operation, only address bits A3 to A0 are used to determine the starting column
address; A7 to A4 are ignored. A22 to A9 are used to determine the starting row address.
CE
CLE
ALE
WE
RE
R/B
I/O0
to I/O7
Starting Address
Y
X
X
Data Output
Command 50h
0
255
511 527
Page (Row)
X
Address
Y (Column Address)
Figure 3
Read Mode (3) Operation
Sequential Read
Each RE pulse used to output data from the data register will cause the column address pointer to increment
by one. When the final column has been reached, the next page will be automatically loaded into the data register.
The R/B signal may be used to monitor the completion of the data transfer.
R/B
I/O0 to I/O7
00h/01h/50h
0
255
Address Input
511 527 0
00h, SE=L
255
511 527 0
01h, SE=L
Figure 4
10
Data
Data
255
Data
511 527 0
00h, SE=H
Sequential Read
255
511 527
50h, SE=L
MBM30LV0064
Page Program: 80h, 10h
The device is programmed either by the page or partial page. Programming is done by issuing the 80h command
followed by three address cycles then serial data input. The 80h command may be preceded by either 00h, 01h
or 50h to set the pointer to either the first half page, second half page, or spare area respectively. If the pointer
command is not specifically issued, its location is determined by its previous use (see Application Note (2) ).
After the serial data input, any column address which did not receive new data will not be programmed. This
enables a page to be partially programmed. After the data has been entered, the 10h command will initiate the
embedded programming process. If the 10h command is issued without loading any new data, programming
will not be initiated. A given page may not be partially programmed more than ten consecutive times without an
intervening erase operation. During the programming cycle, the R/B pin or Status Register bit I/O6 may be used
to monitor the completion of the programming cycle. Only the Reset and Read Status commands are valid while
programming is in progress. After programming, the Status Register bit I/O0 should be checked to verify whether
the procedure was successful or not.
R/B
I/O0 to I/O7
80h
Address and Data Input
10h
70h
I/O0
0 = Pass
1 = Fail
Figure 5
Page Program
Block Erase: 60h
The device data is erased in a block consisting of sixteen pages. The erase operation begins with the 60h
command followed by two address cycles in which the block to be erased is entered. While the two address
cycles require A22 to A9 to be entered, A12 to A9 are don’t care bits. Once the block address is successfully loaded,
the D0h command is entered to initiate the erase operation. The R/B signal may be used to monitor the completion
of the cycle. Upon completion, the Status Register bit I/O0 should be used to verify a successful erase.
R/B
I/O0 to I/O7
60h
Address Input
D0h
70h
I/O0
0 = Pass
1 = Fail
Figure 6
Block Erase
11
MBM30LV0064
Read ID: 90h
This mode allows the identification of the manufacturer and product. After the 90h command cycle, one address
cycle follows in which 00h is entered. The next two RE pulses will output the manufacturer and device code
respectively.
RE
I/O0 to I/O7
90h
00h
04h
Manufacturer Code
Figure 7
E6h
Device Code
Read ID Operation
Table 5
Code Table
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O 1
I/O0
Code
Manufacturer
0
0
0
0
0
1
0
0
04h
Device
1
1
1
0
0
1
1
0
E6h
Status Read: 70h
The Status Register may be used to determine if the device is ready, in the write protect mode, or passed
program/erase operations. After the 70h command is entered, the more recent falling edge of either CE or RE
will output the contents of the status register to I/O0 to 7. The status register is continually updated and does
not require either CE or RE to be toggled. By utilizing the CE pin, multiple devices with R/B pins wired together
may be polled to determine their specific status.
Table 6
Status
12
Status Output Table
Description
I/O0
Program/Erase
0 = Pass; 1 = Fail
I/O1
Not Used
I/O2
Not Used
I/O3
Not Used
I/O4
Not Used
I/O5
Not Used
I/O6
Ready/Busy
0 = Busy; 1 = Ready
I/O7
Write Protect
0 = Protected; 1 = Unprotected
MBM30LV0064
ALE
CLE
WE
RE
CE(1)
CE(2)
Device(1)
Device(2)
CE(N)
Device(N)
8
I/O0 to I/O7
R/B
R/B
ALE
CLE
WE
CE(1)
CE(N)
RE
I/O0 to I/O7
70h
0/1
70h
Status of Device(1)
Figure 8
0/1
Status of Device(N)
Status Read
Reset
When the device is busy during program, erase, or read, it can be reset by entering the command FFh. If WP =
1, the Status Register will be set to C0h. If a reset command is issued while the device is in the reset state, the
command will be ignored. If the device is reset during the program or erase operations, the internal high voltages
will be discharged before R/B goes high.
R/B
I/O0 to I/O7
FFh
13
MBM30LV0064
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min.
Max.
TA
–40
+85
°C
Storage Temperature
Tstg
–55
+125
°C
Voltage on a I/O pin with Respect to Ground *
VI/O
–0.6
VCCq +0.5
V
Voltage on a pin Except I/O with Respect to
Ground *
VIN
–0.6
VCC +0.5
V
VCC
–0.6
+5.5
VCCq
–0.6
+6.0
Ambient Temperature with Power Applied
Power Supply Voltage
V
*: Minimum DC voltage on input or I/O pins is −0.5V. During voltage transitions, inputs may under shoot Vss to
−2.0 V for periods of up to 20 ns. Maximum DC voltage on input pins is VCC + 0.5 V and on I/O pins are VCCq +
0.5 V. During voltage transitions, input pins may overshoot to VCC +2.0 V for periods of up to 20 ns and I/O
pins may overshoot to VCCq + 2.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min.
Max.
Unit
Supply Voltages
VCC
+2.7
+3.6
V
Supply Voltages
VCCq *
+2.7
+5.5
V
Voltages
VSS
Ambient Temperature
TA
0
–40
V
+85
°C
*: VCCq = 5.0 V ± 10% can be guaranteed on VCC ≥ 3.0 V.
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
14
MBM30LV0064
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Conditions
Sequential Read Current
ICC1
Command Address Input Current
ICC3
Data Input Current
ICC4
Program Current
Value
Unit
Min.
Typ.
Max.
tCYCLE = 50 ns, CE = VIL,
IOUT = 0 mA
—
10
20
mA
tCYCLE = 50 ns, CE = VIL
—
10
20
mA
—
—
10
20
mA
ICC6
—
—
10
20
mA
Erase Current
ICC7
—
—
10
20
mA
Stand-by Current (TTL)
ISB1
CE = VIH,
WP = SE = 0 V/VCC
—
—
1
mA
Stand-by Current (CMOS)
ISB2
CE = VCC –0.2 V,
WP = SE = 0 V/ VCC
—
10
50
µA
Input Leakage Current
ILI
VIN = 0 to 3.6 V
—
—
±10
µA
Output Leakage Current
ILO
VOUT = 0 to 3.6 V
—
—
±10
µA
Input High Voltage
VIH
I/O pins
2.0
—
VCCq +0.3
V
Except I/O pins
2.0
—
VCC +0.3
V
Input Low Voltage
VIL
—
–0.3
—
0.8
V
Output High Voltage Level
VOH
IOH = –400 µA
2.4
—
—
V
Output Low Voltage Level
VOL
IOL = 2.1 mA
—
—
0.4
V
Output Low Current (R/B)
IOL
VOL = 0.4 V
8
10
—
mA
15
MBM30LV0064
2. AC Characteristics (Note 1)
Parameter
Symbol
Value
Min.
Max.
Unit
CLE Setup Time
tCLS
0
—
ns
CLE Hold Time
tCLH
10
—
ns
CE Setup Time
tCS
0
—
ns
CE Hold Time
tCH
10
—
ns
Write Pulse Width
tWP
25
—
ns
ALE Setup Time
tALS
0
—
ns
ALE Hold Time
tALH
10
—
ns
Data Setup Time
tDS
20
—
ns
Data Hold Time
tDH
10
—
ns
Write Cycle Time
tWC
50
—
ns
WE High Hold Time
tWH
15
—
ns
WP High to WE Low
tWW
100
—
ns
Ready to RE Falling Edge
tRR
20
—
ns
Read Pulse Width
tRP
30
—
ns
Read Cycle Time
tRC
50
—
ns
RE Access Time (Serial Data Access)
tREA
—
35
ns
CE High Time for the Last Address in Serial Read Cycle (Note 3)
tCEH
100
—
ns
RE Access Time (ID Read)
tREAID
—
35
ns
RE High to Output High Impedance
tRHZ
15
30
ns
CE High to Output High Impedance
tCHZ
—
20
ns
RE High Hold Time
tREH
15
—
ns
tIR
0
—
ns
RE Access Time (Status Read)
tRSTO
—
35
ns
CE Access Time (Status Read)
tCSTO
—
45
ns
WE High to RE Low
tWHR
60
—
ns
ALE Low to RE Low (ID Read)
tAR1
100
—
ns
CE Low to RE Low (ID Read)
tCR
100
—
ns
Data Transfer from Memory Cell Array to Register
tR
—
7
µs
WE High to Busy
tWB
—
100
ns
Output High Impedance to RE Falling Edge
(Continued)
16
MBM30LV0064
(Continued)
Parameter
Symbol
Value
Min.
Max.
Unit
ALE Low to RE Low (Read Cycle)
tAR2
50
—
ns
RE Last Clock Rising Edge to Busy (in Sequential Read)
tRB
—
100
ns
CE High to Ready (in Case of Interception by CE in Read Mode)
(Note 2)
tCRY
—
50 + tr
(R/B)
ns
Device Resetting Time (Read/Program/Erase)
tRST
—
5/10/500
µs
Notes: 1. AC Test Conditions:
Operating range
VCC = 2.7 to 3.6 V
VCC = 3.0 to 3.6 V
Input level
2.4 V/0.4 V
Input comparison level
1.5 V/1.5 V
Output data comparison level
1.5 V/1.5 V
Output load
Load capacitance (CL)
Transition time (tT)
1TTL
50 pF
100 pF
5 ns
2. The time to go from CE high to Ready depends on the pull-up resister of the R/B pin (see Application
Notes (6)) toward the end of this document.
3. In case that toggling CE to high after access to the last address (address 527) in the resister in the read
mode (1), (2), and (3), the CE high time must be held for 100 ns or more when the delay time of CE with
respect to RE is 0 to 200 ns (see the figure below). When the CE delay time is within 30 ns, the device
is kept in the Ready state and will output no Busy signal.
17
MBM30LV0064
tCEH ≥ 100 ns
*
*: VIH or VIL
CE
RE
A
525
509
526
510
A : 0 to 30 ns → Busy signal is not output.
527
511
R/B
Busy
18
MBM30LV0064
■ ERASE AND PROGRAMMING PERFORMANCE
Parameter
Symbol
Min.
Typ.
Max.
tPROG
—
200
1000
N
—
—
10
tBERASE
—
2
10
P/E
1 × 106
—
—
Average Programming Time
Number of Programming Cycles on Same Page
Block Erasing Time
Value
Number of Program/Erase Cycles
Unit
Remarks
µs
*1
ms
*2
*1: Refer to Application Note (10) toward the end of this document.
*2: Refer to Application Note (13) toward the end of this document.
This specification is on conditions that ECC system would be combined.
■ VALID BLOCKS
The MBM30LV0064 occasionally contains unusable blocks. Refer to Application Note (12) toward the end of this
document.
Value
Parameter
Symbol
Unit
Min.
Typ.
Max.
Valid Block Number
NVB
1014
1020
1024
Block
■ PIN CAPACITANCE
Parameter
Input Capacitance
Output Capacitance
Symbol
CIN
COUT
Condition
Value
Unit
Typ.
Max.
VIN = 0
—
10
pF
VOUT = 0
—
10
pF
Notes: 1. Test conditions TA = 25°C, f = 1.0 MHz
2. Sampled, not 100% tested.
19
MBM30LV0064
■ TIMING DIAGRAMS
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDS
tDH
I/O0 to I/O7
: VIH or VIL
Figure 9
Command Input Cycle Timing Diagram
tCLS
CLE
tWC
tCS
tWC
CE
tWH
tWP
tWH
tWP
tWP
WE
tALS
tALH
ALE
tDS
tDH
A0 to A7
I/O0 to I/O7
tDS
tDH
A9 to A16
tDS
tDH
A17 to A22
: VIH or VIL
Figure 10
20
Address Input Cycle Timing Diagram
MBM30LV0064
tCLH
CLE
tCH
CE
tALS
tWC
ALE
tWH
tWP
tWP
tWP
WE
tDS
tDH
DINN
I/O0 to I/O7
tDS
tDH
DINN+1
tDS
tDH
DIN *
: VIH or VIL
* : SE = GND input : to DIN 527
= VCC input : to DIN 511
Figure 11
Data Input Cycle Timing Diagram
21
MBM30LV0064
tRC
CE
tREH
tRP
tRP
tRP
RE
tCHZ
tREA
tREA
tRHZ
tREA
tRHZ
tRHZ
I/O0 to I/O7
tRR
R/B
Figure 12
Serial Read Cycle Timing Diagram
tCLS
CLE
tCLS
tCLH
CE
tCS
tWP
tCH
tCSTO
WE
tCHZ
tWHR
RE
tDS tDH
tIR
tRHZ
tRSTO
I/O0 to I/O7
70h
Status
Output
R/B
: VIH or VIL
Figure 13
22
Status Read Cycle Timing Diagram
MBM30LV0064
CLE
tCLS
tCEH
tCLH
tCH
CE
tWC
tCS
tR
WE
tALS
tCRY
tALH
tAR2
tWB
tRR
ALE
tALH
RE
tDS tDH
I/O0
to I/O7
tDS
tDS
tDH
tDH
A0 to
A9 to
A7
A16
Column address
N
00h
tRC
tDS
tREA
tDH
A17 to
A22
DOUT
N
DOUT
N+1
**
DOUT
DOUT
N+2
tRB
R/B
**:SE = GND input : DOUT 527
= VCC input : DOUT 511
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 14
CLE
tCLS
Read Cycle (1) Timing Diagram
tCLH
tCH
CE
tWC
tCS
tALS
tALH
ALE
tWB
tALH
RE
tDS
tDS
tDS
tDH
I/O0
to I/O7
tCHZ
tR
WE
00h
tDH
tAR2
tRR
tRC
tDS
tDH
tDH
A0 to
A9 to
A7
A16
Column address
N ***
A17 to
A22
tRHZ
tREA
DOUT
N
DOUT
N+1
DOUT
N+2
R/B
***:Read Operation using 00h Command
Read Operation using 01h Command
N : 0 to 255
N : 256 to 511
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 15
Read Cycle (1) Timing Diagram: Interrupted by CE
23
MBM30LV0064
CLE
tCLS
tCLH
tCH
tCS
CE
tR
WE
tALS
tWB
tAR2
tALH
ALE
tALH
tRC
RE
tDS tDH
tDS tDH
tREA
tRR
I/O0
to I/O7
A0 to A9 to
A7
A16
Column address
M
01h
A17 to
A22
DOUT
**
DOUT
DOUT
256 + M 256 + M + 1
R/B
**: SE = GND input : DOUT 527
= VCC input : DOUT 511
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 16
CLE
tCLS
tCS
Read Cycle (2) Timing Diagram
tCLH
tCH
CE
tR
WE
tALS
tWB
tAR2
tALH
ALE
tALH
tRC
RE
tDS tDH
I/O0
to I/O7
tDS tDH
tREA
tRR
50h
A0 to A9 to
A7
A16
Column address
M
A17 to
A22
DOUT
DOUT
**
DOUT
512 + M 512 + M + 1 527
R/B
**: SE = GND input : DOUT 527
= Do not input VCC
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 17
24
Read Cycle (3) Timing Diagram
MBM30LV0064
CLE
CE
WE
ALE
RE
I/O0
to I/O7
00h
A0 to A9 to A17 to
A7 A16
A22
Column Page
Address Address
N
M
N
N+1
N+2
**
tR
0
1
2
**
tR
R/B
Page M
Access
**: SE = GND input : DOUT 527
= VCC input : DOUT 511
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 18
Sequential Read (1) Timing Diagram
CLE
CE
WE
ALE
RE
I/O0
to I/O7
01h
A0 to A9 to A17 to
A7 A16
A22
Column Page
Address Address
N
M
tR
0
**
256 256 256
+
+
+
N N+1N+2
1
2
**
tR
R/B
Page M
Access
Page M + 1
Access
**: SE = GND input : DOUT 527
= VCC input : DOUT 511
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 19
Sequential Read (2) Timing Diagram
25
MBM30LV0064
CLE
CE
WE
ALE
RE
I/O0
to I/O7
50h
A0 to A9 to A17 to
A7 A16
A22
Column Page
Address Address
N
M
tR
**
512 512 512
+
+
+
N N+1N+2
**
tR
512 513 514
R/B
Page M
Access
Page M + 1
Access
**: SE = GND input : DOUT 527
= Do not input VCC
: VIH or VIL
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Figure 20
26
Sequential Read Cycle (3) Timing Diagram
MBM30LV0064
CLE
tCLS
tCLS tCLS
tCS
tCS
CE
tCH
WE
tALS
tALS
tPROG
tALH
tALH
ALE
tWB
RE
tDH
tDS
I/O0
to I/O7
80h
tDS
tDH
A0 to
A7
A9 to
A16
A17 to
A22
tDH
tDH
tDS
tDS
DIN
N
DIN
N+1
DIN
*
10h
70h
Status
Output
R/B
*: SE = GND input : to DIN 527
= VCC input : to DIN 511
Figure 21
CLE
: VIH or VIL
Auto Program Operation Timing Diagram
tCLS
tCLH
tCLS
CE
tCS
WE
tALS
tALH
ALE
RE
I/O0
to I/O7
tBERASE
tWB
tDS tDH
60h
A9 to
A16
A17 to
A22
D0h
70h
Status
Output
R/B
Auto Block Erase
Setup
Command
Erase Start
Command
Status Read
Command
: VIH or VIL
Figure 22
Auto Block Erase Timing Diagram
27
MBM30LV0064
CLE
tCLS
tCS
tCH
tCLS
CE
tCS
WE
tALS
tALH
tCH
tALH
tCR
tAR1
ALE
RE
tDS
tDH
I/O0
to I/O7
00h
90h
04h
tREAID
Address Input
E6h
tREAID
Maker Code Device Code
: VIH or VIL
Figure 23
28
ID Read Operation Timing Diagram
MBM30LV0064
■ APPLICATION NOTES AND COMMENTS
(1) Prohibition of unspecified commands
The operation commands are listed in Table 4. Data input as a command other than the specified commands
in Table 4 is prohibited. Stored data may be corrupted if an unspecified command is entered during the command
cycle.
(2) Pointer Action for Program Operation
The pointer action can be done for program operation as follows.
Start
Yes
Only 50h area
Program?
Input 50h
Command *1
No
No
Start address is
in 00h area?
*1: If read operation was done setting
start address in 50h area in previous
use, the 50h command input can be
skipped.
*2: If read operation was done at 00h or
(and) 01h area in previous use, the
00h command input can be skipped.
*3: The read command means 00h, 01h
or 50h.
Yes
Input 01h Command
Input 00h Command *2
Program Sequence
No
Continue to
Program?
Yes
Start address area
(00h,01h,50h) is the same
as the previous?
No
Start address
area is changed from
01h to 00h?
No
Yes
0
255
Yes
Input read command *3
511 527
The pointer
is 01h?
Yes
Set 01h command
No
00h
01h
Program Sequence
50h
Yes
Continue to
Program?
No
End
Figure 24
Pointer Action Flow Chart
29
MBM30LV0064
(3) Acceptable commands after serial input command ‘80h’
When the serial input command (80h) is input for program execution, commands other than the program execution
command (10h) or reset command (FFh) should not be input.
80
FF
WE
Address input
R/B
Figure 25
Reset Command After 80h Input
If a command other than ‘10h’ or ‘FFh’ is input, the program operation is not performed.
80
XX
Other command
10
Programming will not be executed.
In case of this operation, the FFh command
is needed.
(4) Status read during the read operation
00
00
[A]
70
CE
WE
R/B
RE
N address
Status read
command input
Status read Status output
Figure 26
Status Read During Read Operation
When the status read command (70h) is input during reading, the next RE clock signal can be input to read the
value of the internal status register.
Since the internal operation mode is held in Status Read, read data will not be output even if the RE clock signal
is input after becoming ready. Status Read is therefore disabled at reading.
When the read command (00h) is input during the period [A], the internal operation mode of the device can be
canceled, making it possible to read data at address N without inputting Add.
(5) Auto program failure
80
10
70
Address Data
M
input
80
Fail
80
If programming at page address (M) fails, data should be programmed at the
page address (N) of another block.
Data input at first programming at page address (M) is lost. So address input
using the 80h command must follow the same procedure as data input.
N
Figure 27
30
10
Address Data
N
input
10
M
I/O
Auto Program Failure
MBM30LV0064
(6) R/B: Termination of the Ready/Busy pin (R/B)
The R/B is open-drain output. When using the R/B, R/B must be pulled up VCC by a resistor.
VCC
VCC
R
Device
R/B
CL
VSS
R=
VCC (Max.) — VOL
IOL + IL
=
Figure 28
3.2 V
8 mA + IL
Termination for R/B
(7) Power On/Off Sequence:
After power-off, each input signal level may be undefined. Use the WP signal as shown in the figure below.
2.7 V
2.5 V
VCC
0V
DON’T
CARE
DON’T
CARE
CE, WE, RE
CLE, ALE
WP
VIH
VIL
Operation
Figure 29
VIL
Power On/Off Sequence
31
MBM30LV0064
(8) Setup for WP Signal
A Low-level WP signal will force erasing and programming to be reset. To control, use the WP signal as shown
below.
Program
WE
DIN
80
10
WP
R/B
tWW
100 ns (Min.)
Program Prohibition
WE
DIN
80
10
WP
R/B
tWW
100 ns (Min.)
Erase
WE
DIN
60
D0
WP
R/B
tWW
100 ns (Min.)
Erase Prohibition
WE
DIN
60
WP
R/B
tWW
100 ns (Min.)
32
D0
MBM30LV0064
(9) Address input in 4 cycles
The device will get addresses in three cycles. If addresses are input in four cycles, address input in the fourth
cycle will be ignored in the chip.
Read operation
CLE
CE
WE
ALE
I/O0 to I/O7
00h, 01h or 50h
ignored
Address input
R/B
Internal read operation starts when WE in the third cycle goes high.
Figure 30
Read Operation when 4 Address Cycles are Input
Program operation
CLE
CE
WE
ALE
I/O0 to I/O7
80h
Address input
Data input
ignored
Figure 31
Program Operation when 4 Address Cycles are Input
33
MBM30LV0064
(10) Divided programming on same page
The device uses the page programming method that allows programming up to ten times on the same page.
The procedure for divided programming (programming on a part of one page) is shown below.
The first programming
Column A
Page N
Column B
Data Pattern 1
“No Input” or “1”
The second programming
Column C
Page N
“No Input” or “1”
Column D
“No Input” or “1”
Data Pattern 2
The third programming
Column E
Page N
“No Input” or “1”
Column F
Data Pattern 3
“No Input”
or “1”
Result
Column A
Page N
Column B Column C
Data Pattern 1
Figure 32
‘1’
Column D Column E
Data Pattern 2
‘1’
Column F
Data Pattern 3
‘1’
Divided Program in the Same Page
(11) Notification for RE Signal
When the device is in the read mode, the RE signal causes the internal column address counter to increment
in synchronization with the RE clock. If the 00h, 01h, or 50h command is input to the device in the read mode,
the internal column address counter will count up even after the RE signal is input prior to address input. At this
mode, at input of the RE signal beyond the last column address, the device will start reading (Memory → register)
even without address input and may output the Busy signal (Sequential Read is started).
Address input
I/O0 to I/O7
00h/01h
/50h
WE
RE
R/B
Figure 33
RE Input Before Address
In this way, once the device enters the read mode, unintentional reading may be started after the RE signal is
input prior to addressing; therefore, the RE signal should be input after address input.
34
MBM30LV0064
(12) Invalid block (bad block)
The device contains unusable blocks. Therefore, the following issues must be recognized:
Bad Block
Bad Block
Some MBM30LV0064 products have invalid blocks (bad blocks) at
shipping. After mounting the device in the system, test whether
there are no bad blocks. If there are any bad blocks, they should
not be accessed.
The bad blocks are connected to sense-amp of the bit lines via the
selector transistors. Good blocks will not be affected unless the bad
blocks are accessed. The effective number of good blocks
specified by Fujitsu is shown below.
Valid (Good) Block Number
Min.
Typ.
Max.
Unit
1014
1020
1024
Block
Figure 36. Shows the Bad Block Test Flow
Figure 34
Bad Block
(13) Failure Phenomena for Program and Erase Operations
Repeated rewriting might cause an error at programming and erasing. Possible error modes, and detection
methods and remedies are listed in the following table. System-based remedies will provide a highly reliable
system.
Failure Mode
Detection and Countermeasure Sequence
Block
Erase Failure
Status Read after Erase → Block Replacement
Page
Program Failure
Status Read after Prog. → Block Replacement
Single Bit*
Program Failure
‘1’ → ‘0’
(1) Block Verify after Prog. → Retry
(2) ECC
* : (1) or (2)
• ECC
Error Correcting code → Hamming Code etc.
Example : 1 bit correction & 2 bit detection.
• Block Replacement
:
Program
error occurs
Buffer
Memory
Block A
If an error occurs in block A, reprogramming from
the external buffer to block B. Block A should not
be accessed after an error occurs.
Block B
Figure 35
Reprogramming to Good Block
Erase
If an error occurs at erasing, like programming, remedies should be executed on a system basis to prevent
access to blocks causing the error.
35
MBM30LV0064
(14) ALE Input Condition during Address Input
The ALE input must remain high once asserted until the last address byte has been written to the device.
Read Operation
CLE
CE
WE
Keep "H"
ALE
Inhibit "L" Input
I/O0 to I/O7
00h, 01h or 50h
Address Input
Program Operation
CLE
CE
WE
Keep "H"
ALE
Inhibit "L" Input
I/O0 to I/O7
80h
Address Input
Erase Operation
CLE
CE
WE
Keep "H"
ALE
Inhibit "L" Input
I/O0 to I/O7
D0h
60h
Address Input
36
MBM30LV0064
(15) Inhibit RE Toggling during Busy State
The RE input cannot be allowed to toggle during the period that a read data transfer operation is in process
(busy state).
If the RE input toggles during that period, the internal column address will increment.
CE
CLE
ALE
WE
Toggling X times (→Inhibiting)
RE
R/B
Start from column
address Y + X
Starting Address Y
I/O0
to I/O7
(16) Restriction on Toggling the WE
The WE input cannot be allowed to toggle past the end of page (byte 511 with SE high or byte 527 with SE low)
during an input data operation. If the WE input toggles past the end of page, the internal address counter will
wrap around to the begging of the page and overwrite the information previously there.
CLE
CE
WE
Inhibit toggling
ALE
RE
I/O0
to I/O7
80h
DIN
DIN
*
10h
70h
Output
Status
R/B
*: DIN for address 511 with SE = "H" or
527 with SE = "L"
: VIH or VIL
: Invalid Data
(17) Reading Past Last Device Page
When the last byte in the last page of the device is read, the internal address counter will wrap around to the
fist page in the device.
37
MBM30LV0064
(18) CE don’t care timing for read and program operation
CE can be don’t-care (“H” or “L”) state during read and program operation as follows.
<Read Operation>
CE
WE
RE
I/O0
to I/O7
A0 to
A7
Command
A9 to
A16
A17 to
A22
DOUT
N
DOUT
N+1
DOUT
N+2
DOUT
R/B
(55 ns Max.)
tCEA
CE
tREA
tCH
tCS
RE
CE
I/O0
to I/O7
DOUT
tWP
WE
<Program Operation>
CE
WE
I/O0
to I/O7
80h
A0 to
A7
A9 to
A16
A17 to
A22
DIN
0
DIN
1
DIN
2
DIN
*
10h
: VIH or VIL
Note: In the read operation, the CE signal must stay “Low” after the third address input and during
Busy state. If the CE signal goes High during this period, the read operation will be
terminated and then the standby mode will be entered.
38
MBM30LV0064
■ BAD BLOCK TEST FLOW
Test Start
Block No. = 0
Page 1 & 2
Blank Check
“All FFh?”
Yes
No
Set as a bad block
Block No. = Block No. + 1
Yes
B No. >
= 511
No
Test End
Figure 36
Bad Block Test Flow
39
MBM30LV0064
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM30LV0064
-PFTN
PACKAGE TYPE
PFTN = 44-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 44-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
DEVICE NUMBER/DESCRIPTION
MBM30LV0064
64 Mega-bit (8M × 8-Bit) CMOS Flash Memory
2.7 V to 3.6 V Read, Write, and Erase
Valid Combinations
Valid Combinations
MBM30LV0064
40
-PFTN
-PFTR
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Fujitsu sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
MBM30LV0064
■ PACKAGE DIMENSIONS
44-pin plastic TSOP (II)
(FPT-44P-M07)
*: Resin protrusion. (Each side: 0.15(.006) Max)
44
35
32
23
Details of "A" part
0.15(.006)
0.25(.010)
0.15(.006)MAX
INDEX
0.40(.016)MAX
"A"
LEAD No.
1
10
13
22
* 18.41±0.10
(.725±.004)
0.30±0.10
(.012±.004)
0.13(.005)
M
0.10(.004)
0.80(.0315)TYP
+0.10
+.004
1.10 –0.05 .043 –.002
(Mounting height)
0(0)MIN
(STAND OFF)
0.50±0.10
(.020±.004)
11.76±0.20
(.463±.008)
10.16±0.10
(.400±.004)
0.15±0.05
(.006±.002)
10.76±0.20
(.424±.008)
16.80(.661)REF
C
2000 FUJITSU LIMITED F44016S-1C-3
Dimensions in mm (inches)
(Continued)
41
MBM30LV0064
(Continued)
44-pin plastic TSOP (II)
(FPT-44P-M08)
44
*: Resin protrusion. (Each side: 0.15(.006) Max)
35
32
23
Details of "A" part
0.15(.006)
0.25(.010)
0.15(.006)MAX
INDEX
0.40(.016)MAX
"A"
LEAD No.
1
10
13
22
16.80(.661)REF
0.80(.0315)TYP
0(0)MIN
(STAND OFF)
0.10(.004)
+0.10
0.30±0.10
(.012±.004)
0.13(.005)
* 18.41±0.10
(.725±.004)
C
42
2000 FUJITSU LIMITED F44017S-1C-3
M
0.50±0.10
(.020±.004)
10.76±0.20
(.424±.008)
+.004
1.10 –0.05 .043 –.002
(Mounting height)
10.16±0.10
(.400±.004)
11.76±0.20
(.463±.008)
0.15±0.05
(.006±.002)
Dimensions in mm (inches)
MBM30LV0064
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0012
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.