a Six-Input Channel Analog Front End AD73360L FEATURES Six 16-Bit A/D Converters Programmable Input Sample Rate Simultaneous Sampling 76 dB SNR 64 kS/s Maximum Sample Rate –95 dB Crosstalk Low Group Delay (25 s Typ per ADC Channel) Programmable Input Gain Flexible Serial Port Which Allows Multiple Devices to Be Connected in Cascade Single (2.7 V to 3.6 V) Supply Operation 80 mW Max Power Consumption at 2.7 V On-Chip Reference 28-Lead SOIC Package metering or multichannel analog inputs. It features six 16-bit A/D conversion channels, each of which provides 76 dB signalto-noise ratio over a dc-to-4 kHz signal bandwidth. Each channel also features a programmable input gain amplifier (PGA) with gain settings in eight stages from 0 dB to 38 dB. APPLICATIONS General-Purpose Analog Input Industrial Power Metering Motor Control Simultaneous Sampling Applications A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry-standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines. The AD73360L is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. The AD73360L also features low group delay conversions on all channels. An on-chip reference voltage is included with a nominal value of 1.2 V. The sampling rate of the device is programmable, with four separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from a master clock of 16.384 MHz). The AD73360L is available in 28-lead SOIC package. GENERAL DESCRIPTION The AD73360L is a six-input channel analog front-end processor for general-purpose applications, including industrial power FUNCTIONAL BLOCK DIAGRAM VINP1 SIGNAL CONDITIONING 0/38dB PGA VINN1 ANALOG ⌺-⌬ MODULATOR DECIMATOR SDI SDIFS VINP2 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR VINN2 VINP3 SCLK SIGNAL CONDITIONING VINN3 RESET REFERENCE REFCAP AD73360L REFOUT MCLK SE VINP4 SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR VINN4 VINP5 SERIAL I/O PORT VINN5 SDO SDOFS VINP6 VINN6 SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD73360L–SPECIFICATIONS1 f (AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz, SCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.) Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance Min 1.08 1.08 1 DC Offset Power Supply Rejection Group Delay4, 5 Input Resistance at VIN2, 4 Phase Mismatch FREQUENCY RESPONSE (ADC)7 Typical Output Frequency (Normalized to fS) 0 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance 1.2 50 130 1.2 1.32 1.32 100 ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Signal to (Noise + Distortion) PGA = 0 dB PGA = 0 dB PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-ADC AD73360LA Typ Max 1.578 –2.85 1.0954 –6.02 V ppm/°C Ω V kΩ pF Test Conditions/Comments 0.1 µF Capacitor Required from REFCAP to AGND2 Unloaded V p-p dBm V p-p dBm Measured Differentially 0.6 dB dB 1.0 kHz 1.0 kHz 76 76 58 dB dB dB 0 Hz to 4 kHz; fS = 8 kHz 0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 Hz 0 Hz to 4 kHz; fS = 64 kHz –71 dB dB dB dB dB +30 –55 mV dB 25 50 95 190 25 0.15 0.01 µs µs µs µs kΩ6 Degrees Degrees 0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 Hz 0 Hz to 2 kHz; fS = 64 kHz; fIN = 60 Hz PGA = 0 dB PGA = 0 dB, fS = 64 kHz; SCLK = 16 MHz ADC1 at Idle ADC2 to ADC6 Input Signal: 60 Hz PGA = 0 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Output Sample Rate 32 kHz Output Sample Rate 16 kHz Output Sample Rate 8 kHz Output Sample Rate DMCLK = 16.384 MHz fIN = 1 kHz fIN = 60 Hz 0 –0.1 –0.25 –0.6 –1.4 –2.8 –4.5 –7.0 –9.5 < –12.5 dB dB dB dB dB dB dB dB dB dB –1.3 71 Unit +0.6 –80 –64 –78 –68 –95 –30 VDD – 0.8 0 VDD 0.8 10 10 –2– Measured Differentially V V µA pF REV. 0 AD73360L AD73360LA Typ Max Parameter Min LOGIC OUTPUT VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current VDD – 0.4 0 –10 2.7 2.7 POWER SUPPLIES AVDD1, AVDD2 DVDD IDD8 Unit Test Conditions/Comments VDD 0.4 +10 V V µA |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA 3.6 3.6 V V See Table I NOTES 1 Operating temperature range is as follows: –40°C to +85°C. Therefore, T MIN = –40°C and T MAX = +85°C. 2 Test conditions: Input PGA set for 0 dB gain (unless otherwise noted). 3 At input to sigma-delta modulator of ADC. 4 Guaranteed by design. 5 Overall group delay will be affected by the sample rate and the external digital filtering. 6 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK. 7 Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB. 8 Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground. Specifications subject to change without notice. Table I. Current Summary (AVDD = DVDD = 3.3 V) Conditions Total Current (Max) SE MCLK ON ADCs Only On REFCAP Only On REFCAP and REFOUT Only On All Sections On All Sections Off All Sections Off 25 1.0 3.5 26.5 1.0 0.05 1 0 0 1 0 0 Yes No No Yes Yes No Comments REFOUT Disabled REFOUT Disabled REFOUT Enabled MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz. TIMING CHARACTERISTICS Parameter Clock Signals t1 t2 t3 Serial Port t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 REV. 0 (AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted.) Limit at TA = –40ⴗC to +85ⴗC Unit 61 24.4 24.4 ns min ns min ns min t1 0.4 × t1 0.4 × t1 20 0 10 10 10 10 30 ns min ns min ns min ns min ns min ns max ns max ns max ns max ns max –3– Description See Figure 1. MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4. SCLK Period SCLK Width High SCLK Width Low SDI/SDIFS Setup before SCLK Low SDI/SDIFS Hold after SCLK Low SDOFS Delay from SCLK High SDOFS Hold after SCLK High SDO Hold after SCLK High SDO Delay from SCLK High SCLK Delay from MCLK AD73360L t1 80 t2 70 60 50 S/(N+D) – dB t3 Figure 1. MCLK Timing 40 30 20 100A IOL 10 0 TO OUTPUT PIN 2.1V CL 15pF 100A –10 –85 IOH –75 –65 –55 –45 –35 VIN – dBm0 –25 –15 –5 5 3.17 Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) Figure 2. Load Circuit for Timing Specifications t2 t1 t3 MCLK t 13 t5 SCLK* t6 t4 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). Figure 3. SCLK Timing SE (I) SCLK (O) THREESTATE t7 SDIFS (I) t8 t8 t7 SDI (I) D15 THREESDOFS (O) STATE SDO (O) THREESTATE t9 D14 D0 D1 D15 t 10 t 11 t 12 D15 D2 D1 D0 D15 D14 Figure 4. Serial Port (SPORT) –4– REV. 0 AD73360L ABSOLUTE MAXIMUM RATINGS* (TA = 25°C unless otherwise noted) AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . . . . . . . . –0.3 V to AVDD Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option AD73360LAR –40°C to +85°C Small Outline IC (SOIC) R-28 PIN CONFIGURATION R-28 VINP2 1 28 VINN3 VINN2 2 27 VINP3 VINP1 3 26 VINN4 VINN1 4 25 VINP4 REOUT 5 24 VINN5 REFCAP 6 AD73360L 23 VINP5 TOP VIEW 22 VINN6 AGND2 8 (Not to Scale) 21 VINP6 AVDD2 7 DGND 9 20 AVDD1 DVDD 10 19 AGND1 RESET 11 18 SE SCLK 12 17 SDI MCLK 13 16 SDIFS SDO 14 15 SDOFS CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73360L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE AD73360L PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2 3 4 5 6 VINP2 VINN2 VINP1 VINN1 REFOUT REFCAP 7 8 9 10 11 AVDD2 AGND2 DGND DVDD RESET 12 SCLK 13 14 MCLK SDO 15 SDOFS 16 SDIFS 17 SDI 18 SE 19 20 21 22 23 24 25 26 27 28 AGND1 AVDD1 VINP6 VINN6 VINP5 VINN5 VINP4 VINN4 VINP3 VINN3 Analog Input to the Positive Terminal of Input Channel 2. Analog Input to the Negative Terminal of Input Channel 2. Analog Input to the Positive Terminal of Input Channel 1. Analog Input to the Negative Terminal of Input Channel 1. Buffered Output of the Internal Reference, which has a nominal value of 1.2 V. Reference Voltage for ADCs. A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin. The internal reference can be overdriven by an external reference connected to this pin if required. Analog Power Supply Connection. Analog Ground/Substrate Connection. Digital Ground/Substrate Connection. Digital Power Supply Connection. Active Low-Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Output Serial Clock, whose rate determines the serial transfer rate to/from the AD73360L. It is used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an integer number—this integer number being the product of the external master clock rate divider and the serial clock rate divider. Master Clock Input. MCLK is driven from an external clock signal. Serial Data Output of the AD73360L. Both data and control information may be output on this pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low. Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. Serial Data Input of the AD73360L. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however, the timing counters and other internal registers are at their reset values. Analog Ground Connection. Analog Power Supply Connection. Analog Input to the Positive Terminal of Input Channel 6. Analog Input to the Negative Terminal of Input Channel 6. Analog Input to the Positive Terminal of Input Channel 5. Analog Input to the Negative Terminal of Input Channel 5. Analog Input to the Positive Terminal of Input Channel 4. Analog Input to the Negative Terminal of Input Channel 4. Analog Input to the Positive Terminal of Input Channel 3. Analog Input to the Negative Terminal of Input Channel 3. –6– REV. 0 AD73360L TERMINOLOGY Absolute Gain ABBREVIATIONS ADC Analog-to-Digital Converter. Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for each ADC. The absolute gain specification is used for gain tracking error specification. BW Bandwidth. CRx A Control Register where x is a placeholder for an alphabetic character (A–E). There are eight read/write control registers on the AD73360L— designated CRA through CRE. CRx:n A bit position, where n is a placeholder for a numeric character (0–7), within a control register; where x is a placeholder for an alphabetic character (A–E). Position 7 represents the MSB and Position 0 represents the LSB. DMCLK Device (Internal) Master Clock. This is the internal master clock resulting from the external master clock (MCLK) being divided by the onchip master clock divider. FSLB Frame Sync Loop-Back—where the SDOFS of the final device in a cascade is connected to the RFS and TFS of the DSP and the SDIFS of first device in the cascade. Data input and output occur simultaneously. In the case of non-FSLB, SDOFS and SDO are connected to the Rx Port of the DSP while SDIFS and SDI are connected to the Tx Port. PGA Programmable Gain Amplifier. SC Switched Capacitor. SNR Signal-to-Noise Ratio. SPORT Serial Port. THD Total Harmonic Distortion. VBW Voice Bandwidth. Crosstalk Crosstalk is due to coupling of signals from a given channel to an adjacent channel. It is defined as the ratio of the amplitude of the coupled signal to the amplitude of the input signal. Crosstalk is expressed in dB. Gain Tracking Error Gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. The absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by definition. Group Delay Group delay is defined as the derivative of radian phase with respect to radian frequency, dø(f)/df. Group delay is a measure of average delay of a system as a function of frequency. A linear system with a constant group delay has a linear phase response. The deviation of group delay from a constant indicates the degree of nonlinear phase response of the system. Idle Channel Noise Idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (measured in the frequency range 0 Hz–4 kHz). Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For final testing, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Power Supply Rejection Power supply rejection measures the susceptibility of a device to noise on the power supply. Power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 dB). Sample Rate The sample rate is the rate at which each ADC updates its output register. It is set relative to the DMCLK and the programmable sample rate setting. SNR + THD Signal-to-noise ratio plus harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in a given frequency range, including harmonics but excluding dc. REV. 0 –7– AD73360L FUNCTIONAL DESCRIPTION General Description Analog Sigma-Delta Modulator The AD73360L input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. The AD73360L is a six-input channel, 16-bit, analog front end. It comprises six independent encoder channels each featuring signal conditioning, programmable gain amplifier, sigma-delta A/D converter and decimator sections. Each of these sections is described in further detail below. Sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73360L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to fS/2 = DMCLK/16 (Figure 6a). This means that the noise in the band of interest is much reduced. Another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. This technique has the effect of pushing the noise from the band of interest to an out-of-band position (Figure 6b). The combination of these techniques, followed by the application of a digital filter, reduces the noise in band sufficiently to ensure good dynamic performance from the part (Figure 6c). Encoder Channel Each encoder channel consists of a signal conditioner, a switched capacitor PGA, and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high-level of oversampling, the input antialias requirements are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest. Signal Conditioner Each analog channel has an independent signal conditioning block. This allows the analog input to be configured by the user depending on whether differential or single-ended mode is used. Programmable Gain Amplifier Each encoder section’s analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table II, may be used to increase the signal level applied to the ADC from low-output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. BAND OF INTEREST fS/2 DMCLK/16 a. The PGA gain is set by bits IGS0, IGS1, and IGS2 in control Registers D, E, and F. NOISE-SHAPING Table II. PGA Settings for the Encoder Channel IxGS2 IxGS1 IxGS0 Gain (dB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 6 12 18 20 26 32 38 BAND OF INTEREST fS/2 DMCLK/16 b. DIGITAL FILTER BAND OF INTEREST ADC Each channel has its own ADC consisting of an analog sigmadelta modulator and a digital antialiasing decimation filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. c. fS/2 DMCLK/16 Figure 6. Sigma-Delta Noise Reduction –8– REV. 0 AD73360L Figure 7 shows the various stages of filtering that are employed in a typical AD73360L application. In Figure 7a we see the transfer function of the external analog antialias filter. Even though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency. This also shows the major difference between the initial oversampling rate and the bandwidth of interest. In Figure 7b, the signal and noise-shaping responses of the sigma-delta modulator are shown. The signal response provides further rejection of any high-frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail of Figure 7c shows the response of the digital decimation filter (sinc-cubed response) with nulls every multiple of DMCLK/ 256, which is the decimation filter update rate. The final detail in Figure 7d shows the application of a final antialias filter in the DSP engine. This has the advantage of being implemented according to the user’s requirements and available MIPS. The filtering in Figures 7a through 7c is implemented in the AD73360L. Decimation Filter The digital filter used in the AD73360L carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high-frequency bitstream to a lower rate 15-bit word. The antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from DMCLK/8 to DMCLK/ 256, and increases the resolution from a single bit to 15 bits. Its Z transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a minimal group delay of 25 µs. Word growth in the decimator is determined by the sampling rate. At 64 kHz sampling, where the oversampling ratio between the sigma-delta modulator and decimator output equals 32, there are five bits per stage of the three-stage Sinc3 filter. Due to symmetry within the sigma-delta modulator, the LSB will always be a zero; therefore, the 16-bit ADC output word will have 2 LSBs equal to zero, one due to the sigma-delta symmetry and the other being a padded zero to make up a 16-bit word. At lower sampling rates, decimator word growth will be greater than the 16-bit sample word, therefore truncation occurs in transferring the decimator output as the ADC word. For example at 8 kHz sampling, word growth reaches 24 bits due to the OSR of 256 between sigma-delta modulator and decimator. This yields eight bits per stage of the three stage Sinc3 filter. ADC Coding FSINIT = DMCLK/8 FB = 4kHz a. Analog Antialias Filter Transfer Function SIGNAL TRANSFER FUNCTION NOISE TRANSFER FUNCTION FB = 4kHz FSINIT = DMCLK/8 The ADC coding scheme is in two’s complement format (see Figure 8). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the final output of the ADC block. In 16-bit Data Mode this value is left shifted with the LSB being set to 0. For input values equal to or greater than positive full scale, however, the output word is set at 0x7FFF, which has the LSB set to 1. In mixed Control/Data Mode, the resolution is fixed at 15 bits, with the MSB of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. b. Analog Sigma-Delta Modulator Transfer Function VREF + (VREF ⴛ 0.32875) ANALOG INPUT VREF VREF – (VREF ⴛ 0.32875) FB = 4kHz VINN VINP 10...00 FSINTER = DMCLK/256 00...00 01...11 ADC CODE DIFFERENTIAL c. Digital Decimator Transfer Function VREF + (VREF ⴛ 0.6575) VINN ANALOG INPUT VINP VREF – (VREF ⴛ 0.6575) FB = 4kHz FSFINAL = 8kHz FSINTER = DMCLK/256 10...00 d. Final Filter LPF (HPF) Transfer Function Figure 8. ADC Transfer Function Figure 7. DC Frequency Responses REV. 0 00...00 01...11 ADC CODE SINGLE-ENDED –9– AD73360L Note: As each AD73360L has its own SPORT section, the register settings in all SPORTs must be programmed. The registers that control SPORT and sample rate operation (CRA and CRB) must be programmed with the same values, otherwise incorrect operation may occur. Voltage Reference The AD73360L reference, REFCAP, is a bandgap reference that provides a low noise, temperature-compensated reference to the ADC. A buffered version of the reference is also made available on the REFOUT pin and can be used to bias other external analog circuitry. The reference has a default nominal value of 1.2 V. The reference output (REFOUT) can be enabled for biasing external circuitry by setting the RU bit (CRC:6) of CRC. Serial Port (SPORT) The AD73360Ls communicate with a host processor via the bidirectional synchronous serial port (SPORT) which is compatible with most modern DSPs. The SPORT is used to transmit and receive digital data and control information. Two AD73360Ls can be cascaded together to provide additional input channels. In both transmit and receive modes, data is transferred at the serial clock (SCLK) rate with the MSB being transferred first. Due to the fact that the SPORT of each AD73360L block uses a common serial register for serial input and output, communications between an AD73360L and a host processor (DSP engine) must always be initiated by the AD73360Ls themselves. In this configuration the AD73360Ls are described as being in Master mode. This ensures that there is no collision between input data and output samples. SPORT Overview The AD73360L SPORT is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow up to eight AD73360L devices to be connected in cascade, to a single DSP via a six-wire interface. It has a very flexible architecture that can be configured by programming two of the internal control registers in each device. The AD73360L SPORT has three distinct modes of operation: Control Mode, Data Mode and Mixed Control/Data Mode. MCLK DMCLK (INTERNAL) MCLK DIVIDER SCLK DIVIDER SE RESET SERIAL PORT (SPORT) SDIFS SDOFS SDO SERIAL REGISTER SDI 2 3 8 CONTROL REGISTER A SCLK 8 8 CONTROL REGISTER B 8 8 8 CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H Figure 9. SPORT Block Diagram In Program Mode (CRA:0 = 0), the device’s internal configuration can be programmed by writing to the eight internal control registers. In this mode, control information can be written to or read from the AD73360L. In Data Mode (CRA:0 = 1), any information that is sent to the device is ignored, while the encoder section (ADC) data is read from the device. In this mode, only ADC data is read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1) allows the user to send control information and receive either control information or ADC data. This is achieved by using the MSB of the 16-bit frame as a flag bit. Mixed mode reduces the resolution to 15 bits with the MSB being used to indicate whether the information in the 16-bit frame is control information or ADC data. The SPORT features a single 16-bit serial register that is used for both input and output data transfers. As the input and output data must share the same register, some precautions must be observed. The primary precaution is that no information must be written to the SPORT without reference to an output sample event, which is when the serial register will be overwritten with the latest ADC sample word. Once the SPORT starts to output the latest ADC word, it is safe for the DSP to write new control words to the AD73360L. In certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial register—see section on interfacing devices. The serial clock rate (CRB:2–3) defines how many 16-bit words can be written to a device before the next output sample event will happen. The SPORT block diagram, shown in Figure 9, details the blocks associated with AD73360L including the eight control registers (A–H), external MCLK to internal DMCLK divider and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73360L features a master clock divider that allows users the flexibility of dividing externally available high-frequency DSP or CPU clocks to generate a lower frequency master clock internally in the AD73360L which may be more suitable for either serial transfer or sampling rate requirements. The master clock divider has five divider options (÷ 1 default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by loading the master clock divider field in Register B with the appropriate code (see Table XIII). Once the internal device master clock (DMCLK) has been set using the master clock divider, the sample rate and serial clock settings are derived from DMCLK. The SPORT can work at four different serial clock (SCLK) rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8, where DMCLK is the internal or device master clock resulting from the external or pin master clock being divided by the master clock divider. Care should be taken when selecting Master Clock, Serial Clock, and Sample Rate divider settings to ensure that there is sufficient time to read all the data from the AD73360L before the next sample interval. –10– REV. 0 AD73360L Table III. Control Register Map Address (Binary) Name Description Type Width Reset Setting (Hex) 000 001 010 011 100 101 110 111 CRA CRB CRC CRD CRE CRF CRG CRH Control Register A Control Register B Control Register C Control Register D Control Register E Control Register F Control Register G Control Register H R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Table IV. Control Word Description 15 14 C/D R/W 13 12 11 10 DEVICE ADDRESSS 9 8 7 6 5 REGISTER ADDRESS 4 3 2 1 0 REGISTER DATA Control Frame Description Bit 15 Control/Data Bit 14 Read/Write Bits 13–11 Device Address Bits 10–8 Bits 7–0 Register Address Register Data When set high, it signifies a control word in Program or Mixed Program/Data Modes. When set low, it signifies an invalid control word in Program Mode. When set low, it tells the device that the data field is to be written to the register selected by the register field setting provided the address field is zero. When set high, it tells the device that the selected register is to be written to the data field in the serial register and that the new control word is to be output from the device via the serial output. This 3-bit field holds the address information. Only when this field is zero is a device selected. If the address is not zero, it is decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the eight control registers on the AD73360L. This 8-bit field holds the data that is to be written to the selected register provided the device address field is zero. Table V. Control Register A Description CONTROL REGISTER A REV. 0 7 RESET 6 DC2 5 DC1 4 DC0 3 SLB 2 RES 1 MM 0 DATA/PGM Bit Name Description 0 1 2 3 4 5 6 7 Operating Mode (0 = Program; 1 = Data Mode) Mixed Mode (0 = OFF; 1 = Enabled) Must Be Programmed to Zero (0) SPORT Loop-Back Mode (0 = OFF; 1 = Enabled) Device Count (Bit 0) Device Count (Bit 1) Device Count (Bit 2) Software Reset (0 = OFF; 1 = Initiates Reset) DATA/PGM MM Reserved SLB DC0 DC1 DC2 RESET –11– AD73360L Table VI. Control Register B Description CONTROL REGISTER B 7 6 5 4 3 2 1 0 CEE MCD2 MCD1 MCD0 SCD1 SCD0 DR1 DR0 Bit Name Description 0 1 2 3 4 5 6 7 Decimation Rate (Bit 0) Decimation Rate (Bit 1) Serial Clock Divider (Bit 0) Serial Clock Divider (Bit 1) Master Clock Divider (Bit 0) Master Clock Divider (Bit 1) Master Clock Divider (Bit 2) Control Echo Enable (0 = OFF; 1 = Enabled) DR0 DR1 SCD0 SCD1 MCD0 MCD1 MCD2 CEE Table VII. Control Register C Description CONTROL REGISTER C 7 RES 6 RU 5 PUREF 4 RES 3 RES 2 RES 1 RES 0 GPU Bit Name Description 0 1 2 3 4 5 6 7 Global Power-Up Device (0 = Power Down; 1 = Power Up) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) REF Power (0 = Power Down; 1 = Power Up) REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT) Must Be Programmed to Zero (0) GPU Reserved Reserved Reserved Reserved PUREF RU Reserved Table VIII. Control Register D Description CONTROL REGISTER D 7 PUI2 6 I2GS2 5 I2GS1 4 I2GS0 3 PUI1 2 I1GS2 Bit Name Description 0 1 2 3 4 5 6 7 ADC1:Input Gain Select (Bit 0) ADC1:Input Gain Select (Bit 1) ADC1:Input Gain Select (Bit 2) Power Control (ADC1); 1 = ON, 0 = OFF ADC2:Input Gain Select (Bit 0) ADC2:Input Gain Select (Bit 1) ADC2:Input Gain Select (Bit 2) Power Control (ADC2); 1 = ON, 0 = OFF I1GS0 I1GS1 I1GS2 PUI1 I2GS0 I2GS1 I2GS2 PUI2 –12– 1 I1GS1 0 I1GS0 REV. 0 AD73360L Table IX. Control Register E Description CONTROL REGISTER E 7 6 5 4 3 2 1 0 PUI4 I4GS2 I4GS1 I4GS0 PUI3 I3GS2 I3GS1 I3GS0 1 I5GS1 0 I5GS0 Bit Name Description 0 1 2 3 4 5 6 7 ADC3:Input Gain Select (Bit 0) ADC3:Input Gain Select (Bit 1) ADC3:Input Gain Select (Bit 2) Power Control (ADC3); 1 = ON, 0 = OFF ADC4:Input Gain Select (Bit 0) ADC4:Input Gain Select (Bit 1) ADC4:Input Gain Select (Bit 2) Power Control (ADC4); 1 = ON, 0 = OFF I3GS0 I3GS1 I3GS2 PUI3 I4GS0 I4GS1 I4GS2 PUI4 Table X. Control Register F Description CONTROL REGISTER F 7 PUI6 6 I6GS2 5 I6GS1 4 I6GS0 3 PUI5 2 I5GS2 Bit Name Description 0 1 2 3 4 5 6 7 ADC5:Input Gain Select (Bit 0) ADC5:Input Gain Select (Bit 1) ADC5:Input Gain Select (Bit 2) Power Control (ADC5); 1 = ON, 0 = OFF ADC6:Input Gain Select (Bit 0) ADC6:Input Gain Select (Bit 1) ADC6:Input Gain Select (Bit 2) Power Control (ADC6); 1 = ON, 0 = OFF I5GS0 I5GS1 I5GS2 PUI5 I6GS0 I6GS1 I6GS2 PUI6 Table XI. Control Register G Description CONTROL REGISTER G REV. 0 7 SEEN 6 RMOD 5 CH6 4 CH5 3 CH4 Bit Name Description 0 1 2 3 4 5 6 7 Channel 1 Select Channel 2 Select Channel 3 Select Channel 4 Select Channel 5 Select Channel 6 Select Reset Analog Modulator Enable Single-Ended Input Mode CH1 CH2 CH3 CH4 CH5 CH6 RMOD SEEN –13– 2 CH3 1 CH2 0 CH1 AD73360L Table XII. Control Register H Description CONTROL REGISTER H 7 6 5 4 3 2 1 0 INV TME CH6 CH5 CH4 CH3 CH2 CH1 Bit Name Description 0 1 2 3 4 5 6 7 Channel 1 Select Channel 2 Select Channel 3 Select Channel 4 Select Channel 5 Select Channel 6 Select Test Mode Enable Enable Invert Channel Mode CH1 CH2 CH3 CH4 CH5 CH6 TME INV REGISTER BIT DESCRIPTIONS Control Register A CRA:0 CRA:1 CRA:2 CRA:3 CRA:4–6 CRA:7 Data/Program Mode. This bit controls the operating mode of the AD73360L. If CRA:1 is 0, a 0 in this bit places the part in Program Mode. If CRA:1 is 0, a 1 in this bit places the part in Data Mode. Mixed Mode. If this bit is a 0, the operating mode is determined by CRA:0. If this bit is a 1, the part operates in Mixed Mode. Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation. SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation. Device Count Bits. These bits tell the AD73360L how many devices are used in a cascade. Both devices in the cascade should be programmed to the same value ensure correct operation. See Table XVI. Reset. Writing a 1 to this bit will initiate a software reset of the AD73360L. Control Register B CRB:0–1 CRB:2–3 CRB:4–6 CRB:7 Decimation Rate. These bits are used to set the decimation of the AD73360L. See Table XV. Serial Clock Divider. These bits are used to set the serial clock frequency. See Table XIV. Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table XIII. Control Echo Enable. Setting this bit to a 1 will cause the AD73360L to write out any control words it receives. This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode. Control Register C CRC:0 CRC:6 Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360L to power up, regardless of the status of the Power Control Bits in CRD-CRF. If fewer than six channels are required, this bit should be set to 0 and the Power Control Bits of the relevant channels should be set to 1. Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation. Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the reference. A 0 in this bit will power down the reference. Note that the reference is automatically powered up if any channel is enabled. Reference Output. When this bit is set to 1, the REFOUT pin is enabled. CRC:7 Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation. CRC:1–4 CRC:5 Control Register D CRD:0–2 CRD:3 CRD:4–6 CRD:7 Input Gain Selection. These bits select the input gain for ADC1. See Table II. Power Control for ADC1. A 1 in this bit powers up ADC1. Input Gain Selection. These bits select the input gain for ADC2. See Table II. Power Control for ADC2. A 1 in this bit powers up ADC2. Control Register E CRE:0–2 CRE:3 CRE:4–6 CRE:7 Input Gain Selection. These bits select the input gain for ADC3. See Table II. Power Control for ADC3. A 1 in this bit powers up ADC3. Input Gain Selection. These bits select the input gain for ADC4. See Table II. Power Control for ADC4. A 1 in this bit powers up ADC4. –14– REV. 0 AD73360L Control Register F CRF:0–2 CRF:3 CRF:4–6 CRF:7 Input Gain Selection. These bits select the input gain for ADC5. See Table II. Power Control for ADC5. A 1 in this bit powers up ADC5. Input Gain Selection. These bits select the input gain for ADC6. See Table II. Power Control for ADC6. A 1 in this bit powers up ADC6. Control Register G CRG:0–5 Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit (CRG:6) is 1, a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the SingleEnded Enable Mode bit (CRG:7) is 1, a 1 in a Channel Select bit location will put that channel into Single-Ended Mode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-Ended Mode and will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7. CRG:6 Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel Select bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation. Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel Select bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels. CRG:7 Control Register H CRH:0–5 CRH:6 CRH:7 Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1, a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel Select bit set to 0, the channel will not be inverted regardless of the state CRH:7. Test Mode Enable. This bit should be set to 0 to ensure normal operation. Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit (CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels. SPORT Register Maps There are eight control registers for the AD73360L, each eight bits wide. Table III shows the control register map for the AD73360L. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. They hold settings for parameters such as bit rate, internal master clock rate, and device count. If two AD73360Ls are cascaded, Registers CRA and CRB on each device must be programmed with the same setting to ensure correct operation (this is shown in the programming examples). The other six registers; CRC through CRH are used to hold control settings for the Reference, Power Control, ADC channel, and PGA sections of the device. It is not necessary that the contents of CRC through CRH on each AD73360L are similar. Control registers are written to on the negative edge of SCLK. Master Clock Divider The AD73360L features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5 to produce an internal master clock signal (DMCLK) that is used to calculate the sampling and serial clock rates. The master clock divider is programmable by setting CRB:4-6. Table XIII shows the division ratio corresponding to the various bit settings. The default divider ratio is divide-by-one. REV. 0 Table XIII. DMCLK (Internal) Rate Divider Settings MCD2 MCD1 MCD0 DMCLK Rate 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MCLK MCLK/2 MCLK/3 MCLK/4 MCLK/5 MCLK MCLK MCLK Serial Clock Rate Divider The AD73360L features a programmable serial clock divider that allows users to match the serial clock (SCLK) rate of the data to that of the DSP engine or host processor. The maximum SCLK rate available is DMCLK and the other available rates are: DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK rate. The serial clock divider is programmable by setting bits CRB:2–3. Table XIV shows the serial clock rate corresponding to the various bit settings. Table XIV. SCLK Rate Divider Settings –15– SCD1 SCD0 SCLK Rate 0 0 1 1 0 1 0 1 DMCLK/8 DMCLK/4 DMCLK/2 DMCLK AD73360L Decimation Rate Divider The AD73360L features a programmable decimation rate divider that allows users flexibility in matching the AD73360L’s ADC sample rates to the needs of the DSP software. The maximum sample rate available is DMCLK/256 and the other available rates are: DMCLK/512, DMCLK/1024, and DMCLK/2048. The slowest rate (DMCLK/2048) is the default sample rate. The sample rate divider is programmable by setting bits CRB:0-1. Table XV shows the sample rate corresponding to the various bit settings. Table XV. Decimation Rate Divider Settings DR1 DR0 Sample Rate 0 0 1 1 0 1 0 1 DMCLK/2048 DMCLK/1024 DMCLK/512 DMCLK/256 OPERATION General Description The AD73360L inputs and outputs data in a Time Division Multiplexing (TDM) format. When data is being read from the AD73360L each channel has a fixed time slot in which its data is transmitted. If a channel is not powered up, no data is transmitted during the allocated time slot and the SDO line will be three-stated. When the AD73360L is first powered up or reset it will be set to Program Mode and will output an SDOFS. After a reset the SDOFS will be asserted once every sample period (125 µs assuming 16.384 MHz master clock). If the AD73360L is configured in Frame Sync Loop-Back Mode, one control word can be transmitted after each SDOFS pulse. Figure 10a shows the SDO and SDOFS lines after a reset. The serial data sent by SDO will not contain valid ADC data until the AD73360L is put into Data Mode or Mixed Mode. Control Registers D through F allow channels to be powered up individually. This gives greater flexibility and control over power consumption. Figure 10b shows the SDOFS and SDO of the AD73360L when all channels are powered up and Figure 10c shows SDOFS and SDO with Channels 1, 3, and 5 powered up. Resetting the AD73360L The RESET pin resets all the control registers. All registers are reset to zero, indicating that the default SCLK rate (DMCLK/8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP engines can communicate effectively. As well as resetting the control registers using the RESET pin, the device can be reset using the RESET bit (CRA:7) in Control Register A. Both hardware and software resets require four DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0 (default condition) thus enabling Program Mode. The reset conditions ensure that the device must be programmed to the correct settings after power-up or reset. Following a reset, the SDOFS will be asserted approximately 2070 master (MCLK) cycles after RESET goes high. The data that is output following the reset and during Program Mode is random and contains no valid information until either data or mixed mode is set. Power Management The individual functional blocks of the AD73360L can be enabled separately by programming the power control register CRC. It allows certain sections to be powered down if not required, which adds to the device’s flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. The power control registers provide individual control settings for the major functional blocks on each analog front-end unit and also a global override that allows all sections to be powered up/down by setting/clearing the bit. Using this method the user could, for example, individually enable a certain section, such as the reference (CRC:5), and disable all others. The global power-up (CRC:0) can be used to enable all sections but if power-down is required using the global 1/FSAMPLE SE SDOFS SDO Figure 10a. Output Timing After Reset (Program Mode) SE SDOFS SDO CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 Figure 10b. Output Timing: All Channels Powered Up (Data/Mixed Mode) SE SDOFS SDO CHANNEL 1 CHANNEL 5 CHANNEL 3 Figure 10c. Output Timing: Channels 1, 3, and 5 Powered Up (Data/Mixed Mode) –16– REV. 0 AD73360L control, the reference will still be enabled; in this case, because its individual bit is set. Refer to Table VII for details of the settings of CRC. CRD–CRF can be used to control the power status of individual channels allowing multiple channels to be powered down if required. Operating Modes Three operating modes are available on the AD73360L. They are Program, Data, and Mixed Program/Data. The device configuration—register settings—can be changed only in Program and Mixed Program/Data Modes. In all modes, transfers of information to or from the device occur in 16-bit packets, therefore the DSP engine’s SPORT will be programmed for 16-bit transfers. Program (Control) Mode In Program Mode, CRA:0 = 0, the user writes to the control registers to set up the device for desired operation—SPORT operation, cascade length, power management, input gain, etc. In this mode, the 16-bit information packet sent to the device by the DSP engine is interpreted as a control word whose format is shown in Table IV. In this mode, the user must address the device to be programmed using the address field of the control word. This field is read by the device and if it is zero (000 bin), the device recognizes the word as being addressed to it. If the address field is not zero, it is then decremented and the control word is passed out of the device—either to the next device in a cascade or back to the DSP engine. This 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade. If the AD73360L is used in a stand-alone configuration connected to a DSP, the device address corresponds to 0. If, on the other hand, the AD73360L is configured in a cascade of two devices, its device address corresponds with its hardwired position in the cascade. Following reset, when the SE pin is enabled, the AD73360L responds by raising the SDOFS pin to indicate that an output sample event has occurred. Control words can be written to the device to coincide with the data being sent out of the SPORT, as shown in Figure 12 (Directly Coupled), or they can lag the output words by a time interval that should not exceed the sample interval (Indirectly Coupled). Refer to the Digital Interface section for more information. After reset, output frame sync pulses will occur at a slower default sample rate, which is DMCLK/ 2048, until Control Register B is programmed, after which the SDOFS will be pulsed at the selected rate. This is to allow slow controller devices to establish communication with the AD73360L. During Program Mode, the data output by the device is random and should not be interpreted as ADC data. Data Mode Once the device has been configured by programming the correct settings to the various control registers, the device may exit Program Mode and enter Data Mode. This is done by programming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to 0. Once the device is in Data Mode, the input data is ignored. When the device is in normal Data Mode (i.e., Mixed Mode disabled), it must receive a hardware reset to reprogram any of the control register settings. Mixed Program/Data Mode This mode allows the user to send control words to the device while receiving ADC words. This permits adaptive control of the device whereby control of the input gains can be affected by reprogramming the control registers. The standard data frame remains 16 bits, but now the MSB is used as a flag bit to indicate that the remaining 15 bits of the frame represent control information. Mixed Mode is enabled by setting the MM bit (CRA:1) to 1 and the DATA/PGM bit (CRA:0) to 1. In the case where control setting changes will be required during normal operation, this mode allows the ability to load control information with the slight inconvenience of formatting the data. Note that the output samples from the ADC will also have the MSB set to zero to indicate it is a data word. A description of a single device operating in mixed mode is detailed in Appendix B, while Appendix D details the initialization and operation of an analog front-end cascade operating in mixed mode. Note that it is not essential to load the control registers in Program Mode before setting mixed mode active. Mixed Mode may be selected with the first write by programming CRA and then transmitting other control words. Channel Selection The ADC channels of the AD73360L can be powered up or down individually by programming the PUIx bit of registers CRD to CRF. If the AD73360L is being used in Mixed Data/Control Mode individual channels may be powered up or down as the program requires. In Data Mode, the number of channels selected while the AD73360L was in Program Mode is fixed and cannot be altered without resetting and reprogramming the AD73360L. In all cases, ADC Channel 1 must be powered up as the frame sync pulse generated by this channel defines the start of a new sample interval. INTERFACING The AD73360L can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompanying frame synchronization signal that is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. The serial clock (SCLK) is an output from the AD73360L and is used to define the serial transfer rate to the DSP’s Tx and Rx ports. Two primary configurations can be used: the first is shown in Figure 11 where the DSP’s Tx data, Tx frame sync, Rx data, and Rx frame sync are connected to the AD73360L’s SDI, SDIFS, SDO, and SDOFS respectively. This configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data. When programming the DSP serial port for this configuration, it is necessary to set the Rx frame sync as an input to the DSP and the Tx frame sync as an output generated by the DSP. This configuration is most useful when operating in mixed mode, as the DSP has the ability to decide how many words can be sent to the AD73360L(s). This means that full control can be implemented over the device configuration in a given sample interval. Appendix C details the initialization and operation of an analog front-end cascade in normal Data Mode. REV. 0 –17– AD73360L TFS TFS DT DT ADSP-21xx DSP SCLK DR RFS SDIFS SDIFS SDI SDI SCLK ADSP-21xx DSP AD73360L SCLK SCLK DR SDO SDO RFS SDOFS SDOFS FL0 RESET FL1 AD73360L ANALOG FRONT-END SE Figure 11. Indirectly Coupled or Nonframe Sync LoopBack Configuration Figure 13. AD73360L Connected to ADSP-21xx FSX TFS DT ADSP-21xx DSP SDIFS SCLK SCLK DR SDO RFS DX SDI CLKX TMS320C5x DSP AD73360L SDI SCLK CLKR DR SDOFS SDIFS SDO FSR SDOFS XF RESET AD73360L ANALOG FRONT-END SE Figure 12. Directly Coupled or Frame Sync LoopBack Configuration Figure 14. AD73360L Connected to TMS320C5x The second configuration (shown in Figure 12) has the DSP’s Tx data and Rx data connected to the AD73360L’s SDI and SDO, respectively, while the DSP’s Tx and Rx frame syncs are connected to the AD73360L’s SDIFS and SDOFS. In this configuration, referred to as directly coupled or frame sync loop-back, the frame sync signals are connected together and the input data to the AD73360L is forced to be synchronous with the output data from the AD73360L. The DSP must be programmed so that both the Tx and Rx frame syncs are inputs as the AD73360L’s SDOFS will be input to both. This configuration guarantees that input and output events occur simultaneously and is the simplest configuration for operation in normal Data Mode. Note that when programming the DSP in this configuration it is advisable to preload the Tx register with the first control word to be sent before the AD73360L is taken out of reset. This ensures that this word will be transmitted to coincide with the first output word from the device(s). Digital Interfacing The AD73360L is designed to easily interface to most common DSPs. The SCLK, SDO, SDOFS, SDI, and SDIFS must be connected to the SCLK, DR, RFS, DT, and TFS pins of the DSP respectively. The SE pin may be controlled from a parallel output pin or flag pin such as FL0–2 on the ADSP-21xx (or XF on the TMS320C5x) or, where SPORT power-down is not required, it can be permanently strapped high using a suitable pull-up resistor. For consistent performance the SE should be synchronized to the rising edge of MCLK using a circuit similar to that of Figure 19. The RESET pin may be connected to the system hardware reset structure or it may also be controlled using a dedicated control line. In the event of tying it to the global system reset, it is necessary to operate the device in mixed mode, which allows a software reset, otherwise there is no convenient way of resetting the device. Figures 11 and 12 show typical connections to an ADSP-2181 while Figures 13 and 14 show typical connections to an ADSP-21xx and a TMS320C5x, respectively. –18– REV. 0 AD73360L SE SCLK SDOFS SDO UNDEFINED DATA UNDEFINED DATA CONTROL WORD CONTROL WORD SDIFS SDI Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register) SE SCLK SDOFS SDO UNDEFINED DATA READ RESULT REGISTER READ INSTRUCTION 0x7FFF OR CONTROL WORD SDIFS SDI Figure 15b. Interface Signal Timing for Program Mode Operation (Reading a Register) SE SCLK SDOFS SDO CHANNEL 1 ADC SAMPLE WORD CHANNEL 6 ADC SAMPLE WORD CONTROL WORD CONTROL WORD SDIFS SDI Figure 16a. Interface Signal Timing for Mixed Mode Operation SE SCLK SDOFS SDO CHANNEL 1 ADC SAMPLE WORD CHANNEL 6 ADC SAMPLE WORD DON'T CARE DON'T CARE SDIFS SDI Figure 16b. Interface Signal Timing for Data Mode Operation REV. 0 –19– AD73360L Cascade Operation The AD73360L has been designed to support two devices in a cascade connected to a single serial port (see Figure 17). The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hardware overhead for control signals or addressing. A cascade can be formed in either of the two modes previously discussed. SDIFS TFS MCLK DT ADSP-21xx DSP SDI SCLK DR RFS FL0 SCLK AD73360L SDO DEVICE 1 SE RESET SDOFS FL1 SDIFS When two devices are connected in cascade there are also restrictions concerning which ADC channels can be powered up. In all cases the cascaded devices must all have the same channels powered up (i.e., for a cascade requiring Channels 1 and 2 on Device 1 and Channel 5 on Device 2, Channels 1, 2, and 5 must be powered up on both devices to ensure correct operation). Figure 18 shows the timing sequence for two devices in cascade. In all cases Channel 1 of all devices must be powered up. MCLK SDI AD73360L SCLK SDO SE DEVICE 2 RESET SDOFS Q0 D0 74HC74 D1 In Cascade Mode, both devices must know the number of devices in the cascade to be able to output data at the correct time. Control Register A contains a 3-bit field (DC0–2) that is programmed by the DSP during the programming phase. The default condition is that the field contains 000b, which is equivalent to a single device in cascade (see Table XVI). However, for cascade operation this field must contain a binary value that is one less than the number of devices in the cascade. With a cascade, each device takes a turn to send an ADC result to the DSP. For example, the data will be output as Device 2-Channel 1, Device 1-Channel 1, Device 2-Channel 2, Device 1-Channel 2 etc. When the first device in the cascade has transmitted its channel data there is an additional SCLK period during which the last device asserts its SDOFS as it begins its transmission of the next channel. This will not cause a problem for most DSPs as they count clock edges after a frame sync and hence the extra bit will be ignored. Q1 Table XVI. Device Count Settings CLK Figure 17. Connection of Two AD73360Ls Cascaded to ADSP-21xx There may be some restrictions in cascade operation due to the sample clock and the serial clock rate chosen. The formula below gives an indication of whether the combination of sample rate and serial clock can be successfully cascaded. This assumes a directly coupled frame sync arrangement as shown in Figure 12 and does not take any interrupt latency into account. 1 fS ≥ 6 × [((Device Count − 1) × 16 ) + 17] SCLK When using the indirectly coupled frame sync configuration in cascaded operation it is necessary to be aware of the restrictions in sending control word data to all devices in the cascade. The user should ensure that there is sufficient time for all the control words to be sent between reading the last ADC sample and the start of the next sample period. 1 2 3 4 5 DC2 DC1 DC0 Cascade Length 0 0 0 0 0 1 1 2 Connection of a cascade of devices to a DSP, as shown in Figure 17, is no more complicated than connecting a single device. Instead of connecting the SDO and SDOFS to the DSP’s Rx port, these are now daisy-chained to the SDI and SDIFS of the next device in the cascade. The SDO and SDOFS of the second device in the cascade are connected to the DSP’s Rx port to complete the cascade. SE and RESET on both devices are fed from the signals that were synchronized with the MCLK using the circuit of Figure 19. The SCLK from only one device need be connected to the DSP’s SCLK input(s) as both devices will be running at the same SCLK frequency and phase. 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 DEVICE 2 – CHANNEL 1 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 DEVICE 1 – CHANNEL 1 6 7 8 DEVICE 2 – CHANNEL 2 Figure 18. Cascade Timing for a Two-Device Cascade –20– REV. 0 AD73360L DSP CONTROL TO SE D Q SE SIGNAL SYNCHRONIZED TO MCLK 1/2 74HC74 MCLK CLK DSP CONTROL TO RESET D Q The sampling rate can be varied by programming the Decimation Rate Divider settings in CRB. For a DMCLK of 16.384 MHz sample rates of 64 kHz, 32 kHz, 16 kHz and 8 kHz are available. Figure 21 shows the final spectral response of a signal sampled at 8 kHz using the maximum oversampling rate. 0 RESET SIGNAL SYNCHRONIZED TO MCLK SNR = 78dB (DC TO 4kHz) –20 1/2 74HC74 MCLK –40 CLK –60 dB Figure 19. SE and RESET Sync Circuit for Cascaded Operation –80 PERFORMANCE –100 As the AD73360L is designed to provide high-performance, low-cost conversion, it is important to understand the means by which this high performance can be achieved in a typical application. This section will, by means of spectral graphs, outline the typical performance of the device and highlight some of the options available to users in achieving their desired sample rate, either directly in the device or by doing some post-processing in the DSP, while also showing the advantages and disadvantages of the different approaches. Encoder Section The encoder section samples at DMCLK/256, which gives a 64 kHz output rate for DMCLK equal to 16.384 MHz. The noise-shaping of the sigma-delta modulator also depends on the frequency at which it is clocked, which means that the best dynamic performance in a particular bandwidth is achieved by oversampling at the highest possible rate. If we assume that the signals of interest are in the bandwidth of dc–4 kHz, then sampling at 64 kHz gives a spectral response which ensures good SNR performance in that bandwidth, as shown in Figure 20. –120 –140 0 2 FREQUENCY – kHz 4 Figure 21. FFT (ADC 8 kHz Internally Decimated from 64 kHz) It is possible to generate lower sample rates through reducing the oversampling ratio by programming the DMCLK Rate Divider Settings in CRB (MCD2-MCD1). This will have the effect of spreading the quantization noise over a lesser bandwidth resulting in a degradation of dynamic performance. Figure 22 shows a FFT plot of a signal sampled at 8 kHz rate produced by reducing the DMCLK Rate. 0 SNR = 72.2dB (DC TO fS/2) –20 –40 0 –60 dB SNR = 59.0dB (DC TO fS/2) SNR = 78.2dB (DC TO 4kHz) –20 –80 –40 –100 dB –60 –120 –80 –140 0 –100 4 Figure 22. FFT (ADC 8 kHz Sampling with Reduced DMCLK Rate) –120 –140 0 8 16 FREQUENCY – kHz 24 32 Figure 20. FFT (ADC 64 kHz Sampling) REV. 0 2 FREQUENCY – kHz –21– AD73360L Figure 23 shows a comparison of SNR results achieved by varying either the Decimation Rate Setting or the DMCLK Rate Settings. 100⍀ 100⍀ VIN 0.047F TO INPUT BIAS CIRCUITRY 81 DMCLK = MCLK 80 VINPx VINNx 0.047F REFOUT 0.1F REFCAP VOLTAGE REFERENCE 79 SNR – dB 78 Figure 24. Example Circuit for Differential Input (DC Coupling) 77 The AD73360L’s on-chip 38 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by bits IGS0–2 of CRD. The total gain must be configured to ensure that a full-scale input signal produces a signal level at the input to the sigma-delta modulator of the ADC that does not exceed the maximum input range. 76 REDUCED DMCLK 75 74 73 72 71 8 16 24 32 40 48 SAMPLING FREQUENCY – kHz 56 The dc biasing of the analog input signal is accomplished with an on-chip voltage reference. If the input signal is not biased at the internal reference level (via REFOUT), then it must be ac-coupled with external coupling capacitors. CIN should be 0.1 µF or larger. The dc biasing of the input can then be accomplished using resistors to REFOUT as in Figure 25. 64 Figure 23. Comparison of DMCLK and Decimation Rate Settings Encoder Group Delay The AD73360L implementation offers a very low level of group delay, which is given by the following relationship: CIN Group Delay (Decimator) = Order × ((M – 1)/2) × Tdec VIN CIN where: 100⍀ VINPx 10k⍀ 100⍀ VINNx 10k⍀ 0.047F Order is the order of the decimator (= 3), 0.047F M is the decimation factor (= 32), and TO INPUT BIAS CIRCUITRY Tdec is the decimation sample interval (= 1/2.048e6). REFOUT 0.1F => Group Delay (Decimator) = 3 × (32 – 1)/2 × (1/2.048e6) = 22.7 µs If final filtering is implemented in the DSP, the final filter’s group delay must be taken into account when calculating overall group delay. REFCAP VOLTAGE REFERENCE Figure 25. Example Circuit for Differential Input (AC Coupling) Figures 26 and 27 detail ac- and dc-coupled input circuits for single-ended operation respectively. DESIGN CONSIDERATIONS Analog Inputs CIN 100⍀ VINPx VIN The AD73360L features six signal conditioning inputs. Each signal conditioning block allows the AD73360L to be used with either a single-ended or differential signal. The applied signal can also be inverted internally by the AD73360L if required. The analog input signal to the AD73360L can be dc-coupled, provided that the dc bias level of the input signal is the same as the internal reference level (REFOUT). Figure 24 shows the recommended differential input circuit for the AD73360L. The circuit of Figure 24 implements first-order low-pass filters with a 3 dB point at 34 kHz; these are the only filters that must be implemented external to the AD73360L to prevent aliasing of the sampled signal. Since the ADC uses a highly oversampled approach that transfers the bulk of the antialiasing filtering into the digital domain, the off-chip antialiasing filter need only be of a low order. It is recommended that for optimum performance the capacitors used for the antialiasing filter be of high-quality dielectric (NPO). 0.047F 10k⍀ VINNx REFOUT 0.1F REFCAP VOLTAGE REFERENCE Figure 26. Example Circuit for Single-Ended Input (AC Coupling) 100⍀ VINPx 0.047F VINNx VIN REFOUT 0.1F REFCAP VOLTAGE REFERENCE Figure 27. Example Circuit for Differential Input (DC Coupling) –22– REV. 0 AD73360L Digital Interface As there are a number of variations of sample rate and clock speeds that can be used with the AD73360L in a particular application, it is important to select the best combination to achieve the desired performance. High-speed serial clocks will read the data from the AD73360L in a shorter time, giving more time for processing at the expense of injecting some digital noise into the circuit. Digital noise can also be reduced by connecting resistors (typ <50 Ω) in series with the digital input and output lines. The noise can be minimized by good grounding and layout. Typically, the best performance is achieved by selecting the slowest sample rate and SCLK frequency for the required application as this will produce the least amount of digital noise. Figure 28 shows combinations of sample rate and SCLK frequency which will allow data to be read from all six channels in one sample period. These figures correspond to setting DMCLK = MCLK. SAMPLE RATE SCLK 8kSPS 32kSPS 64kSPS 2MHz YES 16kSPS YES NO NO 4MHz YES YES YES NO 8MHz YES YES YES YES 16MHz YES YES YES YES NOTE: SOME COMBINATIONS OF SCLK AND SAMPLE RATE WILL NOT BE SUFFICIENT TO READ DATA FROM ALL SIX CHANNELS IN THE ALLOTTED TIME. THESE ARE DEPICTED AS NO. Figure 28. SCLK and Sample Rates Grounding and Layout Since the analog inputs to the AD73360L are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies of the AD73360L are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filters on the encoder section will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. However, because the resolution of the AD73360L’s ADC is high, and the noise levels from the AD73360L are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD73360L should be designed so the analog and digital sections are separated and confined to certain sections of the board. The AD73360L pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package. This facilitates the use of ground planes that can be easily separated, as shown in Figure 29. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place. If this connection is close to the device, it is recommended to use a ferrite bead inductor as shown in Figure 29. REV. 0 ANALOG GROUND DIGITAL GROUND Figure 29. Ground Plane Layout Avoid running digital lines under the device for they will couple noise onto the die. The analog ground plane should be allowed to run under the AD73360L to avoid noise coupling. The power supply lines to the AD73360L should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important when using high-speed devices. All analog and digital supplies should be decoupled to AGND and DGND respectively, with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum capacitors. To achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against it. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD73360L, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD73360L and AGND and the recommended digital supply decoupling capacitors between the DVDD pin and DGND. DSP Programming Considerations This section discusses some aspects of how the serial port of the DSP should be configured and the implications of whether Rx and Tx interrupts should be enabled. DSP SPORT Configuration Following are the key settings of the DSP SPORT required for the successful operation with the AD73360L: • • • • • Configure for external SCLK. Serial Word Length = 16 bits. Transmit and Receive Frame Syncs required with every word. Receive Frame Sync is an input to the DSP. Transmit Frame Sync is an: Input—in Frame Sync Loop-Back Mode, Output—in Nonframe Sync Loop-Back Mode. • Frame Syncs occur one SCLK cycle before the MSB of the serial word. • Frame Syncs are active high. –23– AD73360L DSP SPORT Interrupts DSP MICROPROCESSOR If SPORT interrupts are enabled, it is important to note that the active signals on the frame sync pins do not necessarily correspond with the positions in time of where SPORT interrupts are generated. IC DAC TORQUE & FLUX CONTROL LOOP CALCULATIONS On ADSP-21xx processors, it is necessary to enable SPORT interrupts and use Interrupt Service Routines (ISRs) to handle Tx/Rx activity, while on the TMS320CSx processors it is possible to poll the status of the Rx and Tx registers, which means that Rx/Tx activity can be monitored using a single ISR that would ideally be the Tx ISR as the Tx interrupt will typically occur before the Rx ISR. IB DRIVE CIRCUITRY DAC VC VB IA DAC THREEPHASE MOTOR VA ISOLATION AMPLIFIERS TORQUE SETPOINT FLUX SETPOINT VIN1 VIN2 TRANSFORMATION TO TORQUE & FLUX CURRENT COMPONENTS APPLICATIONS EXAMPLES Vector Motor Control The current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. For optimal performance of the motor, these two components should be controlled independently. In conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three-phase drive currents into separate torque and flux components. The AD73360L, with its six-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. AD73360L VIN3 VIN4 VIN5 VIN6 VOLTAGE ATTENUATORS Figure 30. Vector Motor Control Using the AD73360L Industrial Power Metering The AD73360L can be used to measure the voltage and current in all three phases of a three-phase supply. The simultaneous sampling architecture of the AD73360L is ideal for this application where simultaneous sampling is critical to maintaining the relative phase information between the three voltage and three current phases. Figure 31 shows a block diagram of a threephase metering system. The VIN1, VIN2, and VIN3 channels are used to measure the voltages in each phase (via voltage attenuators). The current flowing in each phase can be detected by the use of current-sensing isolation amplifiers, transformers or Hall-effect sensors. VIN4, VIN5, and VIN6 are used to digitize this information. A DSP microprocessor is used to perform the mathematical calculations on the information provided by the AD73360L. A block diagram of a vector motor control application using the AD73360L is shown in Figure 30. The position of the field is derived by determining the current in each phase of the motor. VIN1, VIN2, and VIN3 of the AD73360L are used to digitize this information. Simultaneous sampling is critical to maintain the relative phase information between the channels. A current-sensing isolation amplifier, transformer or Hall-effect sensor is used between the motor and the AD73360L. Rotor information is obtained by measuring the voltage from the three inputs to the motor. VIN4, VIN5, and VIN6 of the AD73360L are used to obtain this information. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD73360L. IC 3 THREEPHASE SUPPLY IB 2 IA 1 VC VB VA ISOLATION AMPLIFIERS VIN1 VIN2 DSP MICROPROCESSOR AD73360L VIN3 VIN4 VIN5 VIN6 VOLTAGE ATTENUATORS Figure 31. Three-Phase Power Metering –24– REV. 0 AD73360L APPENDIX A Programming a Single AD73360L for Data Mode Operation This section describes a typical sequence in programming a single AD73360L to operate in normal Data Mode. It details the control (program) words that are sent to the device to configure its internal registers and shows the typical output data received during both Program and Data Modes. The device is connected in Frame Sync Loop-Back Mode (see Figure 12), which forces an input word from the DSP’s Tx register each time the AD73360L outputs a word via the SDO/SDOFS lines (while the AD73360L is in Program Mode the data transmitted will be invalid ADC data and will, in fact, be a modified version of the last control word written in by the DSP). In each case the DSP’s Tx register is preloaded with the data before the frame pulse is received. In Step 1, the part has just been reset and on the first output event the AD73360L presents an invalid output word*. The DSP’s Tx register contains a control word that programs CRB with the data byte 0x03. This sets the sample rate at 8 kHz (with a master clock of 16.384 MHz). In Step 2, the control word in the DSP’s Tx register will cause all the AD73360Ls channels to power up. This data is received by the AD73360L with the next frame sync pulse. An invalid ADC word is also received at the DSP’s Rx register. Step 3 selects the settings for each channel of the AD73360L. This set can be repeated as necessary to program all the channels to the desired settings. Steps 4 and 5 program the modes of each channel (i.e., singleended or differential mode and normal or inverted). Step 6 puts the AD73360L into Data Mode and in Step 7 the first valid ADC word is received. *This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled. It is important to ensure there is no latency (separation) between control words in a cascade configuration. This is especially the case when programming Control Register B, as it contains settings for SCLK and DMCLK rates. SET 8kHz SAMPLING DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0001 0000 0011 ADC WORD 1* 0000 0000 0000 0000 DON'T CARE 0000 0000 0000 0000 STEP 1 GLOBAL POWER-UP DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0010 0000 0001 ADC WORD 1* 1011 1111 0000 0011 DON'T CARE 1011 1111 0000 0011 STEP 2 SET CHANNEL GAINS DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0011 1000 1111 ADC WORD 1* 1011 1010 0000 0001 DON'T CARE 1011 1010 0000 0001 STEP 3 SET CHANNEL MODE DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0110 0011 1111 ADC WORD 1* 1011 1011 1000 1111 DON'T CARE 1011 1011 1000 1111 STEP 4 SET CHANNEL INVERSION DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0111 0011 1111 ADC WORD 1* 1011 1111 0011 1111 DON'T CARE 1011 1110 0011 1111 STEP 5 SET DATA MODE DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0000 0000 0001 ADC WORD 1* 1011 1111 0011 1111 DON'T CARE 1011 1111 0011 1111 STEP 6 RECEIVE VALID ADC DATA DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 0111 1111 1111 1111 ADC WORD 1 1000 0000 0000 0000 ADC WORD 1 1000 0000 0000 0000 STEP 7 *ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS. Figure 32. Programming a Single AD73360L for Operation in Data Mode REV. 0 –25– AD73360L APPENDIX B Programming a Single AD73360L for Mixed Mode Operation This section describes a typical sequence in programming a single AD73360L to operate in Mixed Mode. The device is configured in Nonframe Sync Loop-Back (see Figure 11), which allows the DSP’s Tx Register to determine how many words are sent to the device during one sample interval. In Nonframe Sync Loop-Back mode, care must be taken when writing to the AD73360L that an ADC result or register read result contained in the device’s serial register is not corrupted by a write. The best way to avoid this is to only write control words when the AD73360L has no more data to send. This can limit the number of times a DSP can write to the AD73360L and is dependant on the SCLK speed and the number of channels powered up. In this example it is assumed that there are only two channels powered up and that there is adequate time to transmit data after the ADC results have been read. In Step 1, the device has just been reset and the on first output event the AD73360L presents an invalid ADC sample word*. Once this word has been received the DSP can begin transmitting programming information to the AD73360L. The first control word sets the sampling rate at 8 kHz. In Step 2, the DSP instructs the AD73360L to power up channels 1 and 2 and sets the gain of each. No data is read from the AD73360L at this point. Steps 3 and 4 set the reference and places the part into Mixed Mode. In Steps 5 and 6 valid ADC results are read from the AD73360L and in Step 7 the DSP sends an instruction to the AD73360L to change the gain of Channel 1. *This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled. It is important to ensure there is no latency (separation) between control words in a cascade configuration. This is especially the case when programming Control Register B, as it contains settings for SCLK and DMCLK rates. SET 8kHz SAMPLING DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0001 0000 0011 ADC WORD 1* 0000 0000 0000 0000 DON'T CARE 0000 0000 0000 0000 STEP 1 POWER-UP CHANNEL 1 AND 2 AND SET GAINS DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0011 1111 1010 ADC WORD 1* 1011 1001 0000 0011 DON'T CARE 0000 0000 0000 0000 STEP 2 POWER-UP REFERENCE DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0010 1110 0000 ADC WORD 1* 1011 1011 1111 1010 DON'T CARE 0000 0000 0000 0000 STEP 3 SET MIXED MODE DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0000 0000 0010 ADC WORD 1* 1011 1010 1110 0000 DON'T CARE 0000 0000 0000 0000 STEP 4 RECEIVE VALID ADC DATA DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 0111 1111 1111 1111 ADC WORD 1 1000 0000 0000 0000 ADC WORD 1 1000 0000 0000 0000 STEP 5 RECEIVE VALID ADC DATA DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 0111 1111 1111 1111 ADC WORD 2 1111 0000 0000 0000 ADC WORD 2 1111 0000 0000 0000 STEP 6 CHANGE GAIN ON CHANNEL 1 DSP Tx REG DEVICE 1 DSP Rx REG CONTROL WORD 1000 0011 1000 0010 INVALID DATA xxxx xxxx xxxx xxxx ADC WORD 2 1111 0000 0000 0000 STEP 7 *ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS. Figure 33. Programming a Single AD73360L for Operation in Mixed Mode –26– REV. 0 AD73360L APPENDIX C Configuring a Cascade of Two AD73360Ls to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360Ls to set them up for operation. It is not intended to be a definitive initialization sequence, but will show users the typical input/output events that occur in the programming and operation phases*. This description panel refers to Figure 34. In Step 1, we have the first output sample event following device reset. The SDOFS signal is raised on both devices simultaneously, which prepares the DSP Rx register to accept the ADC word from Device 2, while SDOFS from Device 1 becomes an SDIFS to Device 2. As the SDOFS of Device 2 is coupled to the DSP’s TFS and RFS, and to the SDIFS of Device 1, this event also forces a new control word to be output from the DSP Tx register to Device 1. The control word loaded to Device 1 is addressed to Device 2 (i.e., the address field is 001). Device 1 will decrement the address field and pass it to Device 2 when the next frame sync arrives. As the DSP is transmitting a control word, Device 2 is outputting an invalid ADC word. (Note that the AD73360L will not output valid ADC words until the device is placed in either mixed mode or data mode. Any ADC values received during the programming phase should be discarded.) At the same time, Device 1 will output its ADC result to Device 2. Once all the data has been transferred, Device 1 will contain an instruction for Device 2 (which instructs the part to set its SCLK frequency), Device 2 will have received an ADC result from Device 1 and the DSP will have received an ADC result from Device 2. In Step 2, Device 2 will begin transmitting the ADC word it received from Device 1. This will cause the DSP to transmit a second command word, which tells Device 1 to change its serial clock. Simultaneously, Device 1 passes the first control word on to Device 2. In this manner both devices receive control word instructions and act upon them at the same time. In Step 4, Device 2 will transmit the invalid ADC sample it received from Device 1 while receiving a control word from Device 1 at the same time. Device 2 transmitting will cause the DSP to transmit a control word for Device 1. This should be similar to the control word transmitted in Step 3 except that this word is intended for Device 1. When transmission is complete both devices have received instructions to power up all channels and set the reference etc. Steps 3 and 4 can be repeated, as necessary, to program other registers concerned with the analog section. Step N is the first stage of changing the operating modes of the devices to Data Mode. As Device 2 outputs an ADC word the DSP will transmit a control word intended for CRA of Device 2 to Device 1. As in Step 1, Device 1 will decrement the address field and pass on the control word on the next frame sync. In Step N + 1, Device 2 transmits an ADC word it received from Device 1. This causes the DSP to transmit a control word to Device 1 (intended for its CRA register). At the same time Device 2 is receiving its control word from Device 1. Both devices simultaneously receive commands to change from Program Mode to Data Mode and the number of devices in the cascade is also programmed here. In Step N + 2, we begin to receive valid ADC data. Note that the data comes from the last device in the chain (Device 2) first. As Device 2 transmits its ADC data, it is receiving ADC data from Device 1. Any data transmitted from the DSP will be ignored from now on. In Step N + 3, Device 2 has received an ADC sample from Device 1 and transmits it to the DSP. Steps N + 2 and N + 3 are repeated as long as samples are required. *This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled . It is important to ensure that there is no latency (separation) between control words in a cascade configuration. This is especially the case when programming Control Register B as it contains settings for SCLK and DMCLK rates. Step 3 is similar to Step 1 in that the DSP transmits a control word for Device 2. Device 1 passes an invalid ADC result to Device 2 and Device 2 transmits its own invalid ADC result to the DSP. REV. 0 –27– AD73360L DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1 1000 1001 0000 0011 ADC WORD 1* 0000 0000 0000 0000 ADC WORD 2* 0000 0000 0000 0000 ADC WORD 2* 0000 0000 0000 0000 STEP 1 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1 1000 0001 0000 0011 ADC WORD 1* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx ADC WORD 1* xxxx xxxx xxxx xxxx STEP 2 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 2 1000 1010 1110 0001 ADC WORD 1* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx STEP 3 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1000 0010 1110 0001 ADC WORD 1* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx ADC WORD 1* xxxx xxxx xxxx xxxx STEP 4 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1000 1000 0001 0001 ADC WORD 1* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx STEP N DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1000 0000 0001 0001 ADC WORD 1* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx ADC WORD 1* xxxx xxxx xxxx xxxx STEP N + 1 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 0111 1111 1111 1111 ADC WORD 1 0000 0011 0101 1110 ADC WORD 2* 0000 0011 0101 1110 ADC WORD 2 0000 0011 0101 1110 STEP N + 2 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 0111 1111 1111 1111 ADC WORD 1 0011 1100 1111 1110 ADC WORD 2 0000 0011 0101 1110 ADC WORD 1 0000 0011 0101 1110 STEP N + 3 *ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS. Figure 34. Programming Two AD73360Ls in Cascade for Data Mode Operation –28– REV. 0 AD73360L APPENDIX D In Step 4, another sample interval has occurred and the SDOFS on both devices are raised. Device 2 sends an ADC result to the DSP and Device 1 sends an ADC result to Device 2. The remaining time before the next sample interval can be used to program more registers in the AD73360Ls. Care must be taken that the subsequent writes do not overlap the next sample interval to avoid corrupting the data. The control words are written as Device 2, Device 1, Device 2, etc. Configuring a Cascade of Two AD73360Ls to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360Ls to configure them for operation in Mixed Mode. It is not intended to be a definitive initialization sequence, but will show users the typical input/output events that occur in the programming and operation phases*. This description panel refers to Figure 35. In Step 1, we have the first output sample event following device reset. The SDOFS signal is raised on both devices simultaneously, which prepares the DSP Rx register to accept the ADC word from Device 2 while SDOFS from Device 1 becomes an SDIFS to Device 2. The cascade is configured as nonFSLB, which means that the DSP has control over what is transmitted to the cascade. The DSP will receive an invalid ADC word from Device 2 and simultaneously Device 2 is receiving an invalid ADC word from Device 1. As both AD73360Ls are in Program Mode there is only one output event per sample period. The DSP can now send a control word to the AD73360Ls. In Step 2, the DSP has finished transmitting the control word to Device 1. Device 1 recognizes that this word is not intended for it so it will decrement the address field and generate and SDOFS and proceed to transmit the control word to the next device in the chain. At this point the DSP should transmit a control word for Device 1. This will ensure that both devices receive, and act upon, the control words at the same time. Step 3 shows completion of the first series of control word writes. The DSP has now received an ADC word from Device 2 and each device has received a control word that addresses Control Register B and sets the SCLK and Sample Rate. When programming a cascade of AD73360Ls in NonFSLB it is important to ensure that control words which affect the operation of the serial port are received by all devices simultaneously. REV. 0 Step 5 shows the DSP starting to program the ADC Control Register to select channel gains, operating modes etc. In this case the first write operation programs Control Register D to power up ADC Channels 1 and 2 with gains of 0 dBs. This step can be repeated until all the registers have been programmed. The devices should be programmed in the order Device 2, Device 1, Device 2, etc. In Step 6, the DSP transmits a control word for Device 2. This control word set the Device count to 2 and instructs the AD73360L to go into Mixed Mode. When Device 1 receives this control word, it will decrement the address field and generate an SDOFS to pass it on to Device 2. In Step 7, the DSP transmits a control word for Device 1. This should happen as Device 1 is transmitting the control word for Device 2 to ensure that both devices change into Mixed Mode at the same time. In Step 8, we begin receiving the first valid ADC words from the cascade. It is assumed that there is sufficient time to transmit all the required Control Words in the allotted time. *This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled. It is important to ensure there is no latency (separation) between control words in a cascade configuration. This is especially the case when programming Control Register B, as it contains settings for SCLK and DMCLK rates. –29– AD73360L DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1 1000 1001 0000 0011 ADC WORD 1* 0000 0000 0000 0000 ADC WORD 2* 0000 0000 0000 0000 DON'T CARE xxxx xxxx xxxx xxxx STEP 1 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 2 1000 0001 0001 0011 CONTROL WORD 1* 1000 1001 0001 0011 ADC WORD 2* xxxx xxxx xxxx xxxx DON'T CARE xxxx xxxx xxxx xxxx STEP 2 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 2 1000 0001 0001 0011 ADC WORD 1* 1000 1001 0001 0011 ADC WORD 2* 1000 1001 0001 0011 DON'T CARE xxxx xxxx xxxx xxxx STEP 3 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1000 0010 1110 0001 ADC WORD 1* xxxx xxxx xxxx xxxx ADC WORD 2* xxxx xxxx xxxx xxxx DON'T CARE xxxx xxxx xxxx xxxx STEP 4 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1000 1011 1000 1000 ADC WORD 1* 1000 1011 1000 1000 ADC WORD 2* xxxx xxxx xxxx xxxx DON'T CARE xxxx xxxx xxxx xxxx STEP 5 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1000 1000 0001 0011 ADC WORD 1* 1000 1000 0001 0011 ADC WORD 2* xxxx xxxx xxxx xxxx DON'T CARE xxxx xxxx xxxx xxxx STEP 6 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1 1000 0000 0001 0011 ADC WORD 1** 1000 1001 0001 0011 ADC WORD 2* 1000 0000 0001 0011 ADC WORD 2 0000 0011 0101 1110 STEP 7 DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1 0111 1111 1111 1111 ADC WORD 1 0011 1100 1111 1110 ADC WORD 2 0000 0011 0101 1110 ADC WORD 2 0000 0011 0101 1110 STEP 8 *ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS. **THIS CONTROL WORD IS NOT INTENDED FOR THE DEVICE THAT HAS RECEIVED IT. ITS ADDRESS FIELD WILL BE DECREMENTED AND THE DATA WILL BE TRANSMITTED TO THE NEXT DEVICE IN THE CASCADE. Figure 35. Programming Two AD73360Ls in Cascade for Mixed Mode –30– REV. 0 AD73360L APPENDIX E HISTOGRAMS OF SNR RESULTS fS = 8kHz fIN = 1kHz SCLK = 16MHz fS = 8kHz FREQUENCY OF OCCURRENCE FREQUENCY OF OCCURRENCE fIN = 1kHz SCLK = 8MHz –83 –82 –81 –80 –79 –78 –84 THD – dB FREQUENCY OF OCCURRENCE –82 –81 –80 –79 THD – dB Figure 36. fS = 8 kHz, fIN = 1 kHz, SCLK = 8 MHz Figure 39. fS = 8 kHz, fIN = 1 kHz, SCLK = 16 MHz fS = 8kHz fS = 8kHz fIN = 1kHz fIN = 1kHz FREQUENCY OF OCCURRENCE SCLK = 8MHz 76 76.5 77 77.5 78 SNR – dB –83 78.5 SCLK = 16MHz 74.5 75 75.5 76 76.5 77 SNR – dB Figure 37. fS = 8 kHz, fIN = 1 kHz, SCLK = 8 MHz 77.5 Figure 40. fS = 8 kHz, fIN = 1 kHz, SCLK = 16 MHz fS = 64kHz FREQUENCY OF OCCURRENCE FREQUENCY OF OCCURRENCE fIN = 1kHz SCLK = 8MHz BW = dc TO 4kHz 58 58.5 59 59.5 SNR – dB 1.16 1.17 1.18 1.19 1.2 1.21 1.22 1.23 1.24 1.25 REFOUT VOLTAGE – V 60 Figure 38. fS = 64 kHz, fIN = 1 kHz, SCLK = 8 MHz, Gain = 38 dB REV. 0 Figure 41. Typical REFOUT Voltage (V) –31– AD73360L TABLE OF CONTENTS Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 8 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal Conditioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . 8 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . 8 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPORT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REGISTER BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . 14 SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 15 Decimation Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 16 Topic Page OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resetting the AD73360L . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Encoder Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Encoder Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Programming Considerations . . . . . . . . . . . . . . . . DSP SPORT Configuration . . . . . . . . . . . . . . . . . . . . . . DSP SPORT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATIONS EXAMPLES . . . . . . . . . . . . . . . . . . . . . Vector Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . Industrial Power Metering . . . . . . . . . . . . . . . . . . . . . . . APPENDIX A (Single Device Data Mode Operation) . . . APPENDIX B (Single Device Mixed Mode Operation) . . . . APPENDIX C (Two Devices in Data Mode Operation) . . . APPENDIX D (Two Devices in Mixed Mode Operation) . . APPENDIX E (Histograms of SNR Results) . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 16 17 17 17 17 17 17 18 20 21 21 22 22 22 23 23 23 23 24 24 24 24 25 26 27 29 31 32 C01039–2.5–10/00 (rev. 0) Topic OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PRINTED IN U.S.A. Small Outline IC (SOIC) (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 1 14 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.4193 (10.65) 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 8ⴗ 0ⴗ 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) –32– 0.0291 (0.74) ⴛ 45ⴗ 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40) REV. 0