AD AD1847

a
Serial-Port 16-Bit
SoundPort Stereo Codec
AD1847
FEATURES
Single-Chip Integrated SD Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSP
I
S
A
ASIC
AD1847
B
U
S
DSP
Figure 1. Example System Diagram
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑∆ analog-to-digital converters (ADCs) and a stereo pair of ∑∆ digital-to-analog converters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs’ output can be digitally
mixed with the DACs’ input.
PRODUCT OVERVIEW
The AD1847 SoundPort® Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multimedia applications requiring operation from a single +5 V supply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
The pair of 16-bit outputs from the ADCs is available over a serial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit µ-law or A-law
companded digital data.
(Continued on page 7)
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
ANALOG
I/O
ANALOG
SUPPLY
CLOCK
OUT
DIGITAL
SUPPLY
2
OSCILLATORS
LINE 2 L
INPUT R
AUX 1 L
INPUT R
M
U
X
L
R
L
L
∑
R
R
L
GAIN/ATTEN
/MUTE
R
GAIN/ATTEN
/MUTE
∑
POWER
DOWN
GAIN
∑∆ A/D
CONVERTER
µ/A
LAW
GAIN
∑∆ A/D
CONVERTER
µ/A
LAW
ATTEN
GAIN/ATTEN/MUTE
AUX 2
INPUT
2
RESET
LINE 1 L
INPUT R
LINE
OUTPUT
DIGITAL
I/O
CRYSTALS
ATTEN/
MUTE
∑∆ D/A
CONVERTER
ATTEN/
MUTE
∑∆ D/A
CONVERTER
ATTEN
ATTEN
µ/A
LAW
∑
∑
µ/A
LAW
BUS
MASTER
S
E
R
I
A
L
TIME SLOT
INPUT
P
O
R 2
T
SERIAL DATA
INPUT
TIME SLOT
OUTPUT
SERIAL DATA
OUTPUT
EXTERNAL
CONTROL
SERIAL BIT
CLOCK
FRAME
SYNC
AD1847
REFERENCE
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2.25V
® Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD1847–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
Digital Supply (VDD)
Analog Supply (VCC)
Word Rate (FS )
Input Signal
Analog Output Passband
FFT Size
VIH
VIL
VOH
VOL
25
5.0
5.0
48
1007
20
4096
2.4
0.8
2.4
0.4
°C
V
V
kHz
Hz
Hz to 20 kHz
DAC Output Conditions
0 dB Attenuation
Full-Scale Digital Inputs
16-Bit Linear Mode
No Output Load
Mute Off
ADC Input Conditions
0 dB Gain
–3.0 dB Relative to Full Scale
Line Input
16-Bit Linear Mode
V
V
V
V
ANALOG INPUT
Min
Typ
Max
Units
2.54
1
2.8
3.10
V rms
V p-p
Full-Scale Input Voltage (RMS Values Assume Sine Wave Input)
Line1, Line2, AUX1, AUX2
Input Impedance
Line1, Line2, AUX1, AUX2†
Input Capacitance†
10
kΩ
pF
15
PROGRAMMABLE GAIN AMPLIFIER—ADC
Step Size (All Steps Tested, –30 dB Input)
PGA Gain Range Span†
Min
Typ
Max
Units
1.10
21.0
1.5
1.90
24.0
dB
dB
AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS
Step Size (+12 dB to –28.5 dB, Referenced to DAC Full Scale)
(–30 dB to –34.5 dB, Referenced to DAC Full Scale)
Input Gain/Attenuation Range Span†
AUX Input Impedance†
Min
Typ
Max
Units
1.3
1.1
45.5
10
1.5
1.5
1.7
1.9
47.5
dB
dB
dB
kΩ
DIGITAL DECIMATION AND INTERPOLATION FILTERS†
Passband
Passband Ripple
Transition Band
Stopband
Stopband Rejection
Group Delay
Group Delay Variation Over Passband
Min
Max
Units
0
–0.1
0.4 3 FS
0.6 3 FS
74
0.4 3 FS
+0.1
0.6 3 FS
∞
Hz
dB
Hz
Hz
dB
30/FS
0
–2–
µs
REV. B
AD1847
ANALOG-TO-DIGITAL CONVERTERS
Min
Resolution
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
THD+N (Referenced to Full Scale)
Typ
Max
16
70
0.040
–68
Signal-to-Intermodulation Distortion†
ADC Crosstalk†
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line1 to Line2 (Input Line1, Ground and Select Line2, Read Both Channels)
Line to AUX1
Line to AUX2
Line to DAC
Gain Error (Full-Scale Span Relative to VREFI)
Interchannel Gain Mismatch (Difference of Gain Errors)
DC Offset
83
–80
–80
–80
–80
–80
± 10
± 0.2
± 55
Units
Bits
dB
%
dB
dB
dB
dB
dB
dB
dB
%
dB
LSB
DIGITAL-TO-ANALOG CONVERTERS
Min
Resolution
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
THD+N (Referenced to Full Scale)
Typ
Max
16
76
0.025
–72
Signal-to-Intermodulation Distortion†
Gain Error (Full-Scale Span Relative to VREFI)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk† (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)
Total Out-of-Band Energy† (Measured from 0.6 3 FS to 100 kHz)
Audible Out-of-Band Energy (Measured from 0.6 3 FS to 22 kHz, Tested at FS = 5.5 kHz)
86
± 10
± 0.2
–80
–50
–55
Units
Bits
dB
%
dB
dB
%
dB
dB
dB
dB
DAC ATTENUATOR
Step Size (0 dB to –22.5 dB) (Tested at Steps 0 dB, –19.5)
Step Size (–24 dB to –94 dB)
Output Attenuation Range Span†
Min
Typ
Max
Units
1.3
1.0
–93
1.5
1.5
1.7
2.0
95
dB
dB
dB
Min
Typ
Max
Units
1.3
1.0
–93.5
1.5
1.5
1.7
2.0
95.5
dB
dB
dB
DIGITAL MIX ATTENUATOR
Step Size (0 dB to –22.5 dB) (Tested at Steps 0 dB, –19.5)
Step Size (–24 dB to –94 dB)
Output Attenuation Range Span†
ANALOG OUTPUT
Full-Scale Line Output Voltage
VREFI = 2.35*
Line Output Impedance†
External Load Impedance
Output Capacitance†
External Load Capacitance
VREF (Clock Running)
VREF Current Drive
VREFI
Mute Attenuation of 0 dB
Fundamental† (LOUT)
Mute Click†
(|Muted Output Minus Unmuted
Midscale DAC Output|)
Min
Typ
1.80
0.707
2
–80
8
mV
15
100
2.50
2.00
100
2.35
–3–
Units
V rms
V p-p
Ω
kΩ
pF
pF
V
µA
V
dB
2.20
600
10
*Full-scale line output voltage scales with V REF (e.g., V OUT (typ) – 2.0 V 3 (VREF/2.35)).
†Guaranteed, Not Tested.
REV. B
Max
AD1847
SYSTEM SPECIFICATIONS
Min
Typ
Max
Units
± 0.3
System Frequency Response†
(Line In to Line Out, 20 Hz to 20 kHz)
Differential Nonlinearity†
Phase Linearity Deviation†
dB
± 1/2
Bit
Degrees
1
STATIC DIGITAL SPECIFICATIONS
Min
High Level Input Voltage (VIH)
Digital Inputs
XTAL1/2I
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 4 mA
Input Leakage Current (GO/NOGO Tested)
Output Leakage Current (GO/NOGO Tested)
Max
Units
0.8
VDD
0.4
+10
+10
V
V
V
V
V
µA
µA
2.0
2.4
2.4
–10
–10
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)
Min
Serial Frame Sync Period (t1)
Clock to Frame Sync [SDFS] Propagation Delay (tPD1)
Data Input Setup Time (tS)
Data Input Hold Time (tH)
Clock to Output Data Valid (tDV)
Clock to Output Three-State [High-Z] (tHZ)
Clock to Time Slot Output [TSO] Propagation Delay (tPD2)
RESET and PWRDOWN Lo Pulse Width (tRPWL)
Typ
Max
1/0.5 FS
20
15
15
25
20
20
100
Units
µs
ns
ns
ns
ns
ns
ns
ns
POWER SUPPLY
Power Supply Range – Digital & Analog
Power Supply Current – Operating (10 kΩ Line Out Load)
Analog Supply Current – Operating (10 kΩ Line Out Load)
Digital Supply Current – Operating (10 kΩ Line Out Load)
Analog Power Supply Current – Power Down
Digital Power Supply Current – Power Down
Power Dissipation – Operating (Current 3 Nominal Supply)
Power Dissipation – Power Down (Current 3 Nominal Supply)
Power Supply Rejection (@ 1 kHz)†
(At Both Analog and Digital Supply Pins, ADCs)
(At Both Analog and Digital Supply Pins, DACs)
Min
Max
Units
4.75
5.25
140
70
70
400
400
750
4
V
mA
mA
mA
µA
µA
mW
mW
45
55
dB
dB
CLOCK SPECIFICATIONS†
Min
Input Clock Frequency
Recommended Clock Duty Cycle
Initialization/Sample Rate Change Time
16.9344 MHz Crystal Selected at Power-Up
24.576 MHz Crystal Selected at Power-Up
16.9344 MHz Crystal Selected Subsequently
24.576 MHz Crystal Selected Subsequently
Max
Units
27
± 10
MHz
%
171
171
6
6
ms
ms
ms
ms
†Guaranteed, not tested.
Specifications subject to change without notice.
–4–
REV. B
AD1847
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Min Max
Power Supplies
Digital (VDD)
Analog (VCC)
Input Current
(Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Units
Model
Temperature
Range
Package
Description
Package
Option*
0°C to +70°C
0°C to +70°C
44-Lead PLCC
44-Lead TQFP
P-44A
ST-44
–0.3 6.0
–0.3 6.0
V
V
AD1847JP
AD1847JST
± 10.0
–0.3 (VA+) + 0.3
–0.3 (VD+) + 0.3
0
+70
–65 +150
mA
V
V
°C
°C
*P = PLCC; ST = TQFP.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1847 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PINOUTS
1
44 43 42 41 40
44 SDFS
43 SDO
42 SDI
41 GNDD
40 VDD
39 SCLK
38 CLKOUT
37 XTAL2O
36 XTAL2I
35 XTAL1O
34 XTAL1I
XTAL1O
2
XTAL1I
3
XTAL2O
SCLK
CLKOUT
4
XTAL2I
VDD
5
SDI
6
44-Lead TQFP
GNDD
SDFS
SDO
44-Lead PLCC
TSO
7
39 VDD
TSI
8
38 GNDD
VDD
9
37 XCTL1
GNDD 10
36 XCTL0
RESET 11
AD1847JP
35 GNDD
PWRDOWN 12
Top View
(Not to Scale)
34 VDD
VCC 13
TSO
TSI
VDD
GNDD
RESET
PWRDOWN
VCC
5
6
7
GNDA 8
VREFI 9
VREF 10
R_LINE1 11
33 BM
GNDA 14
32 L_AUX2
VREFI 15
31 R_AUX2
VREF 16
30 L_OUT
AD1847JST
Top View
(Not to Scale)
N/C = NO CONNECT
–5–
L_LINE1 17
GNDA 18
V CC 19
L_AUX1 20
R_AUX1 21
R_OUT 22
R_OUT
R_AUX1
VCC
L_AUX1
GNDA
L_LINE1
L_LINE2
LFILT
GNDA
RFILT
R_LINE2
N/C = NO CONNECT
33
32
31
30
29
28
27
26
25
24
VDD
GNDD
XCTL1
XCTL0
GNDD
VDD
BM
L_AUX2
R_AUX2
L_OUT
23 N/C
29 N/C
18 19 20 21 22 23 24 25 26 27 28
REV. B
PIN 1 IDENTIFIER
R_LINE2 12
RFILT 13
GNDA 14
LFILT 15
L_LINE2 16
R_LINE1 17
1
2
3
4
AD1847
PIN DESCRIPTIONS
Parallel Interface
Pin Name
PLCC TQFP
I/O
Description
SCLK
1
39
I/O
SDFS
6
44
I/O
SDI
4
42
I
SDO
5
43
O
RESET
11
5
I
PWRDOWN
12
6
I
BM
33
27
I
TSO
7
1
O
TSI
8
2
I
CLKOUT
44
38
O
Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output to the
serial bus when the Bus Master (BM) pin is driven HI and accepts the clock as an input
when the BM pin is driven LO. The serial clock output is fixed at 12.288 MHz when
XTAL1 is selected, and 11.2896 MHz when XTAL2 is selected. SCLK runs continuously. An AD1847 should always be configured as the serial bus master unless it is a slave
in a daisy-chained multiple codec system.
Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame synchronization signal as an output to the serial bus when the Bus Master (BM) pin is driven HI
and accepts the frame synchronization signal as an input when the BM pin is driven LO.
The SDFS frequency powers up at one half of the AD1847 sample rate (i.e., FRS bit = 0)
with two samples per frame and can be programmed to match the sample rate (i.e., FRS
bit = 1) with one sample per frame. An AD1847 should always be configured as the serial
bus master unless it is a slave in a daisy-chained multiple codec system.
Serial Data Input. SDI is used by peripheral devices such as the host CPU or a DSP to
supply control and playback data information to the AD1847. All control and playback
transfers are 16 bits long, MSB first.
Serial Data Output. SDO is used to supply status/index readback and capture data information to peripheral devices such as the host CPU or a DSP. All status/index readback
and capture data transfers are 16 bits long, MSB first. Three-state output driver.
Reset. The RESET signal is active LO. The assertion of this signal will initialize the
on-chip registers to their default values. See the “Control Register Definitions” section for
a description of the contents of the control registers after RESET is deasserted.
Powerdown. The PWRDOWN signal is active LO. The assertion of this signal will reset
the on-chip control registers (identically to the RESET signal) and will also place the
AD1847 in a low power consumption mode. VREF and all analog circuitry are disabled.
Bus Master. The assertion (HI) of this signal indicates that the AD1847 is the serial bus
master. The AD1847 will then supply the serial clock (SCLK) and the frame sync (SDFS)
signals for the serial bus. One and only one AD1847 should always be configured as the
serial bus master. If BM is connected to logic LO, the AD1847 is configured as a bus
slave, and will accept the SCLK and SDFS signals as inputs. An AD1847 should only be
configured as a serial bus slave when an AD1847 serial bus master already exists, in
daisy-chained multiple codec systems.
Time Slot Output. This signal is asserted HI by the AD1847 coincidentally with the LSB
of the last time slot used by the AD1847. Used in daisy-chained multiple codec systems.
Time Slot Input. The assertion of this signal indicates that the AD1847 should immediately use the next three time slots (TSSEL = 1) or the next six time slots (TSSEL = 0)
and then activate the TSO pin to enable the next device down the TDM chain. TSI
should be driven LO when the AD1847 is the bus master or in single codec systems. Used
in daisy-chained multiple codec systems.
Clock Output. This signal is the buffered version of the crystal clock output and the frequency is dependent on which crystal is selected. This pin can be three-stated by driving
the BM pin LO or by programming the CLKTS bit in the Pin Control Register. See the
“Control Registers” section for more details. The CLKOUT frequency is 12.288 MHz
when XTAL1 is selected and 16.9344 MHz when XTAL2 is selected.
Analog Signals
Pin Name
PLCC
TQFP
I/O
Description
L_LINE1
R_LINE1
L_LINE2
R_LINE2
L_AUX1
R_AUX1
L_AUX2
R_AUX2
L_OUT
R_OUT
23
17
22
18
26
27
32
31
30
28
17
11
16
12
20
21
26
25
24
22
I
I
I
I
I
I
I
I
O
O
Left Line Input #1. Line level input for the #1 left channel.
Right Line Input #1. Line level input for the #1 right channel.
Left Line Input #2. Line level input for the #2 left channel.
Right Line Input #2. Line level input for the #2 right channel.
Left Auxiliary Input #1. Line level input for the AUX1 left channel.
Right Auxiliary Input #1. Line level input for the AUX1 right channel.
Left Auxiliary Input #2. Line level input for the AUX2 left channel.
Right Auxiliary Input #2. Line level input for the AUX2 right channel.
Left Line Output. Line level output for the left channel.
Right Line Output. Line level output for the right channel.
–6–
REV. B
AD1847
Miscellaneous
Pin Name
PLCC
TQFP
I/O
Description
XTAL1I
XTAL1O
XTAL2I
XTAL2O
XCTL1:O
40
41
42
43
37 & 36
34
35
36
37
31 & 30
I
O
I
O
O
VREF
16
10
O
VREFI
L_FILT
15
21
9
15
I
I
R_FILT
19
13
I
NC
29
23
24.576 MHz Crystal #1 Input.
24.576 MHz Crystal #1 Output.
16.9344 MHz Crystal #2 Input.
16.9344 MHz Crystal #2 Output.
External Control. These TTL signals reflect the current status of register bits inside the
AD1847. They can be used for signaling or to control external logic.
Voltage Reference. Nominal 2.25 volt reference available externally as a voltage datum
for dc-coupling and level-shifting. VREF should not have any signal dependent load.
Voltage Reference Internal. Voltage reference filter point for external bypassing only.
Left Channel Filter Capacitor. This pin requires a 1.0 µF capacitor to analog ground
for proper operation.
Right Channel Filter Capacitor. This pin requires a 1.0 µF capacitor to analog ground
for proper operation.
No Connect. Do not connect.
Power Supplies
Pin Name
PLCC
TQFP
I/O
Description
VCC
GNDA
VDD
GNDD
13 & 25
14, 20, 24
2, 9, 34, 39
3, 10, 35, 38
7 & 19
8, 14, 18
40, 3, 28, 33
41, 4, 29, 32
I
I
I
I
Analog Supply Voltage (+5 V).
Analog Ground.
Digital Supply Voltage (+5 V).
Digital Ground.
(Continued from page 1)
Analog Mixing
The ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images are removed from the DACs’
analog stereo output by on-chip switched-capacitor and
continuous-time filters. Two stereo pairs of auxiliary line-level
inputs can also be mixed in the analog domain with the DAC
output.
AUX1 and AUX2 analog stereo signals can be mixed in the analog domain with the DAC output. Each channel of each auxiliary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post-mixed DAC output is available on L_OUT and R_OUT
externally and as an input to the ADCs.
Even if the AD1847 is not playing back data from its DACs, the
analog mix function can still be active.
The AD1847 serial data interface uses a Time Division Multiplex (TDM) scheme that is compatible with DSP serial ports
configured in Multi-Channel Mode with 32 16-bit time slots
(i.e., SPORT0 on the ADSP-2101, ADSP-2115, etc.).
Analog-to-Digital Datapath
The ∑∆ ADCs incorporate a proprietary fourth-order modulator. A single pole of passive filtering is all that is required for
antialiasing the analog input because of the ADC’s high 64
times oversampling ratio. The ADCs include digital decimation
filters that low-pass filter the input to 0.4 3 FS. (“FS’’ is the
word rate or “sampling frequency.”) ADC input overrange conditions will cause status bits to be set that can be read.
AUDIO FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1847 and is
intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Digital-to-Analog Datapath
The ∑∆ DACs contain a programmable attenuator and a lowpass digital interpolation filter. The anti-imaging interpolation
filter oversamples and digitally filters the higher frequency images. The attenuator allows independent control of each DAC
channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute.
The DACs’ ∑∆ noise shapers also oversample and convert the
signal to a single-bit stream. The DAC outputs are then filtered
in the analog domain by a combination of switched-capacitor
and continuous-time filters. These filters remove the very high
frequency components of the DAC bitstream output. No external components are required.
Analog Inputs
The AD1847 SoundPort Stereo Codec accepts stereo line-level
inputs. All inputs should be capacitively coupled (ac-coupled) to
the AD1847. LINE1, LINE2, and AUX1, and post-mixed DAC
output analog stereo signals are multiplexed to the internal programmable gain amplifier (PGA) stage.
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left-channel inputs appearing at
both channel outputs.
REV. B
–7–
AD1847
Changes in DAC output attenuation take effect only on zero
crossings of the digital signal, thereby eliminating “zipper” noise
on playback. Each channel has its own independent zero-crossing
detector and attenuator change control circuitry. A timer guarantees that requested volume changes will occur even in the absence of an input signal that changes sign. The time-out period
is 8 milliseconds at a 48 kHz sampling rate and 48 milliseconds
at an 8 kHz sampling rate. (Time-out [ms] ≈ 384/FS [kHz]).
specified in the Codec’s internal registers. Note that when µ-law
compressed data is expanded to a linear format, it requires 14
bits. A-law data expanded requires 13 bits.
Analog Outputs
A stereo line-level output is available at external pins. Other
output types such as headphone and speaker must be implemented in external circuitry. The stereo line-level outputs
should be capacitively coupled (ac-coupled) to the external circuitry. Each channel of this output can be independently
muted. When muted, the outputs will settle to a dc value near
VREF, the midscale reference voltage.
Digital Data Types
The AD1847 supports four global data types: 16-bit twoscomplement linear PCM, 8-bit unsigned linear PCM,
companded µ-law, and 8-bit companded A-law, as specified by
control register bits. Eight-bit data is always left-justified in 16bit fields; in other words, the MSBs of all data types are always
aligned; in yet other words, full-scale representations in all four
formats correspond to equivalent full-scale signals. The eight
least significant bit positions of 8-bit data in 16-bit fields are ignored on digital input and zoned on digital output (i.e., truncated).
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded µ-law and A-law data formats use nonlinear
coding with less precision for large-amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
7
0
LSB
3/2
MSB
EXPANSION
2/1
0
2/1
0
LSB
3/2
15
DAC INPUT
MSB
LSB
000 / 00
Figure 2. A-Law or µ -Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
15
Sixty-four steps of –1.5 dB attenuation are supported to
–94.5 dB. The digital mix datapath can also be completely
muted, preventing any mixing of the digital input with the digital output. Note that the level of the mixed signal is also a function of the input PGA settings, since they affect the ADCs’
output.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because
both stereo signals are mixed before the output attenuators, mix
data is attenuated a second time by the DACs’ datapath
attenuators.
MSB
15
Digital Mixing
Stereo digital output from the ADCs can be mixed digitally with
the input to the DACs. Digital output from the ADCs going out
of the serial data port is unaffected by the digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both channels of the monitor data are attenuated by the same amount.
(Note that internally the AD1847 always works with 16-bit
PCM linear data, digital mixing included; format conversions
take place at the input and output.)
8
15
COMPRESSED
INPUT DATA
ADC OUTPUT
0
MSB
LSB
15
TRUNCATION
15
COMPRESSION
3/2
MSB
MSB
0
2/1
LSB
8
LSB
7
0
00000000
Figure 3. A-Law or µ -Law Compression
Note that all format conversions take place at input or output.
Internally, the AD1847 always uses 16-bit linear PCM representations to maintain maximum precision.
Power Supplies and Voltage Reference
The AD1847 operates from +5 V power supplies. Independent
analog and digital supplies are recommended for optimal performance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the Codec and its
2.25 V buffered output is available on an external pin (VREF).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference must be externally bypassed
to analog ground at the VREFI pin, and must not be used to bias
external circuitry.
Clocks and Sample Rates
The AD1847 operates from two external crystals, XTAL1 and
XTAL2. The two crystal inputs are provided to generate a wide
range of sample rates. The oscillators for these crystals are on
the AD1847, as is a multiplexer for selecting between them.
They can be overdriven with external clocks by the user, if so
desired. At a minimum, XTAL1 must be provided since it is selected as the reset default. If XTAL2 is not used, the XTAL2
input pin should be connected to ground. The recommended
crystal frequencies are 16.9344 MHz and 24.576 MHz. From
them, the following sample rates can be selected: 5.5125, 6.615,
8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8,
44.1, 48 kHz.
On input, 8-bit companded data is expanded to an internal linear representation, according to whether µ-law or A-law was
–8–
REV. B
AD1847
Figure 5 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL =
1. Note that the six 16-bit registers “share” three time slots.
TSSEL = 1 is used when the SDI and SDO pins are independent inputs and output (i.e., “2-wire” system). This configuration is inefficient in terms of component interconnect (two
unidirectional wires for serial data input and output), but efficient in terms of time slot usage (three slots consumed on each
of two unidirectional TDM serial buses). When TSSEL = 1, serial data input to the AD1847 occurs concurrently with serial
data output from the AD1847 (i.e., Control Word reception on
the SDI pin occurs simultaneously with Status Word/lndex
Readback transmission on the SDO pin).
CONTROL REGISTERS
Control Register Mapping
The AD1847 has six 16-bit and thirteen 8-bit on-chip useraccessible control registers. Control information is sent to the
AD1847 in the 16-bit Control Word. Status information is sent
from the AD1847 in the 16-bit Status Word. Playback Data and
Capture Data each have two 16-bit registers for the right and
left channels. Additional 8-bit Index Registers are accessed via
indirect addressing in the AD1847 Control Word. [Index Registers are reached with indirect addressing.] The contents of an
indirect addressed Index Register may be readback by the host
CPU or DSP (during the Status Word/Index Readback time
slot) by setting the Read Request (RREQ) bit in the Control
Word. Note that each 16-bit register is assigned its own time
slot, so that the AD1847 always consumes six 16-bit time slots.
Figure 4 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL = 0.
TSSEL = 0 is used when the SDI and SDO pins are tied together (i.e., “1-wire” system). This configuration is efficient in
terms of component interconnect (one bidirectional wire for serial data input and output), but inefficient in terms of time slot
usage (six slots consumed on single bidirectional Time Division
Multiplexed [TDM] serial bus). When TSSEL = 0, serial data
input to the AD1847 occurs sequentially with serial data output
from the AD1847 (i.e., Control Word, Left Playback and Right
Playback data is received on the SDI pin, then the Status Word/
lndex Readback, Left Capture and Right Capture data is transmitted on the SDO pin).
Slot
0
1
2
3
4
5
Slot
0
1
2
0
1
2
Control Word Input
Left Playback Data Input
Right Playback Data Input
Status Word/Index Readback Output
Left Capture Data Output
Right Capture Data Output
Figure 5. Control Register Mapping with TSSEL = 1
An Index Register readback request to an invalid index address
(11, 14 and 15) will return the contents of the Status Word. Attempts to write to an invalid index address (11, 14 and 15) will
have no effect on the AD1847. As mentioned above, the RREQ
bit of the Control Word is used to request Status Word output
or Index Register readback output during either time slot 3
(TSSEL = 0) or time slot 0 (TSSEL = 1). RREQ is set for Index Register readback output, and reset for Status Word output.
When Index Register readback is requested, the Index Readback
bit format is the same as the Control Word bit format. All status
bits are updated by the AD1847 before a new Control Word is
received (i.e., at frame boundaries). Thus, if TSSEL = 0 and
the Control Word written at slot 0 causes some status bits to
change, the change will show up in the Status Word transmitted
at slot 3 of the same sample.
Register Name (16-Bit)
Control Word Input
Left Playback Data Input
Right Playback Data Input
Status Word/Index Readback Output
Left Capture Data Output
Right Capture Data Output
Figure 4. Control Register Mapping with TSSEL = 0
REV. B
Register Name (16-Bit)
–9–
AD1847
Control Word (16-Bit)
Data 15
CLOR
Data 7
DATA7
Data 14
MCE
Data 6
DATA6
Data 13
RREQ
Data 5
DATA5
Data 12
res
Data 4
DATA4
Data 11
IA3
Data 3
DATA3
Data 10
IA2
Data 2
DATA2
Data 9
IA1
Data 1
DATA1
Data 8
IA0
Data 0
DATA0
DATA7:0 Index Register Data. These bits are the data for the desired AD1847 Index Register referenced by the Index Address.
Written by the host CPU or DSP to the AD1847.
IA3:0
Index Register Address. These bits define the indirect address of the desired AD1847 Index Register. Written by the host
CPU or DSP to the AD1847.
RREQ
Read Request. Setting this bit indicates that the current transfer is a request by the host CPU or DSP for readback of the
contents of the indirect addressed Index Register. When this bit is set (RREQ = HI), the AD1847 will not transmit its
Status Word in the following Status Word Index readback slot, but will instead transmit the data in the Index Register
specified by the Index Address. Although the Index Readback is transmitted in the following Status Word/Index
Readback time slot, the format of the Control Word is used (i.e., CLOR, MCE, RREQ and the Index Register Address
in the most significant byte, and the readback Index Register Data in the least significant byte). When this bit is reset
(RREQ = LO), the AD1847 will transmit its Status Word in the following Status Word Index Readback time slot.
A read request is serviced in the next available Index Readback time slot. If TSSEL = 0, the Index Register readback
data is transmitted in slot 3 of the same sample. If TSSEL = 1, Index Register readback data is transmitted in slot 0 of
the next sample. If TSSEL changes from 0 to 1, Index Register readback will occur twice, in slot 3 of the current sample,
and slot 0 of the next. If TSSEL changes from 1 to 0, the last read request is lost.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
MCE
Mode Change Enable. This bit must be set (MCE = HI) whenever protected control register bits of the AD1847 are
changed. The Data Format register, the Miscellaneous Information register, and the ACAL bit of the Interface Configuration register can NOT be changed unless this bit is set. The DAC outputs will be muted when MCE is set. The user
must mute the AUX1 and AUX2 channels when this bit is set (no audio activity should occur). Written by the host CPU
or DSP to the AD1847. This bit is HI after reset.
CLOR
Clear Overrange. When this bit is set (CLOR = HI), the overrange bits in the Status Word are updated every sample.
When this bit is reset (CLOR = LO), the overrange bits in the Status Word will record the largest overrange value. The
largest overrange value is sticky until the CLOR bit is set. Written by the host CPU or DSP to the AD1847. Since there
can be up to 2 samples in the data pipeline, a change to CLOR may take up to 2 samples periods to take effect. This bit
is HI after reset.
Immediately after reset, the contents of this register is: 1100 0000 0000 0000 (C000h).
Left/Right Playback/Capture Data (16-Bit)
The data formats for Left Playback, Right Playback, Left Capture and Right Capture are all identical.
Data 15
DATA15
Data 7
DATA7
Data 14
DATA14
Data 6
DATA6
Data 13
DATA13
Data 5
DATA5
Data 12
DATA12
Data 4
DATA4
Data 11
DATA11
Data 3
DATA3
Data 10
DATA10
Data 2
DATA2
Data 9
DATA9
Data 1
DATA1
Data 8
DATA8
Data 0
DATA0
DATA15:0 Data Bits. These registers contain the 16-bit, MSB first data for capture and playback. The host CPU or DSP reads the
capture data from the AD1847. The host CPU or DSP writes the playback data to the AD1847. For 8-bit linear or 8-bit
companded modes, only DATA15:8 contain valid data; DATA7:0 are ignored during capture, and are zeroed during
playback. Mono mode plays back the same audio sample on both left and right channels. Mono capture only captures
data from the left audio channel. See “Serial Data Format” Timing Diagram.
Immediately after reset, the content of these registers is: 0000 0000 0000 0000 (0000h).
–10–
REV. B
AD1847
Status Word (16-Bit)
Data 15
res
Data 7
res
INIT
Data 14
res
Data 6
res
Data 13
RREQ
Data 5
ORR1
Data 12
res
Data 4
ORR0
Data 11
ID3
Data 3
ORL1
Data 10
ID2
Data 2
ORL0
Data 9
ID1
Data 1
ACI
Data 8
ID0
Data 0
INIT
Initialization. This bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is
set HI on the last valid frame. It is reset LO for all other frames. Read by the host CPU or DSP from the AD1847.
The INIT bit is set HI on the last sample before the serial interface is inactivated. The only condition under which the
INIT bit is set is when a different sample rate is programmed. If FRS = 0 (32 slots per frame, two samples per frame)
and the sample rate is changed in the first sample of the 32 slot frame (i.e., during slots 0 through 15), the INIT bit will
be set on the second sample of that frame (i.e., during slots 16 through 31). If FRS = 0 and the sample rate is changed in
the second sample of the 32 slot frame, the INIT bit will be set on the second sample of the following frame.
ACI
Autocalibrate In-Progress. This bit indicates that autocalibration is in progress or the Mode Change Enable (MCE) state
has been recently exited. When exiting the MCE state with the ACAL bit set, the ACI bit will be set HI for 384 sample
periods. When exiting the MCE state with the ACAL bit reset, the ACAL bit will be set HI for 128 sample periods, indicating that offset and filter values are being restored. Read by the host CPU or DSP from the AD1847.
0
Autocalibration not in progress
1
Autocalibration is in progress
ACI clear (i.e., reset or LO) should be recognized by first polling for a HI on the sample after the MCE bit is reset, and
then polling for a LO. Note that it is important not to start polling until one sample after MCE is reset, because if MCE
is set while ACI is HI, an ACI LO on the following sample will suggest a false clear of ACI.
ORL1:0
ORR1:0
Overrange Left Detect. These bits indicate the overrange on the left input channel. Read by the host CPU or DSP from
the AD1847.
0
Greater than –1.0 dB underrange
1
Between –1.0 dB and 0 dB underrange
2
Between 0 dB and 1.0 dB overrange
3
Greater than 1.0 dB overrange
Overrange Right Detect. These bits indicate the overrange on the right input channel. Read by the host CPU or DSP
from the AD1847.
0
Greater than –1.0 dB underrange
1
Between –1.0 dB and 0 dB underrange
2
Between 0 dB and 1.0 dB overrange
3
Greater than 1.0 dB overrange
ID3:0
AD1847 Revision ID. These four bits define the revision level of the AD1847. The first version of the AD1847 is designated ID = 0001. Read by the host CPU or DSP from the AD1847.
RREQ
This bit is reset LO for the Status Word, echoing the RREQ state written by the host CPU or DSP in the previous Control Word. Read by the host CPU or DSP from the AD1847.
res
Reserved for future expansion. All reserved bits read zero (LO).
Immediately after reset, the contents of this register is: 0000 0001 0000 0000 (0100h).
REV. B
–11–
AD1847
Index Readback (16-Bit)
Data 15
CLOR
Data 7
DATA7
Data 14
MCE
Data 6
DATA6
Data 13
RREQ
Data 5
DATA5
Data 12
res
Data 4
DATA4
Data 11
IA3
Data 3
DATA3
Data 10
IA2
Data 2
DATA2
Data 9
IA1
Data 1
DATA1
Data 8
IA0
Data 0
DATA0
DATA7:0 Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index
Address from the previous Control Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
IA3:0
Index Register Address. These bits echo the indirect address (written during the previous Control Word (with the RREQ
bit set) of the desired AD1847 Index Register to be readback. Read by the host CPU or DSP from the AD1847.
RREQ
Read Request. This bit is set HI for Index Readback, echoing the RREQ state written by the host CPU or DSP in the
previous Control Word. Read by the host CPU or DSP from the AD1847.
res
Reserved for future expansion. All reserved bits read zero (LO).
MCE
Mode Change Enable. This bit echoes the MCE state written by the host CPU or DSP during the previous* Control
Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
CLOR
Clear Overrange. This bit echoes the CLOR state written by the host CPU or DSP during the previous Control Word
(with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
Immediately after reset, the contents of this register is: 1110 0000 0000 0000 (E000h).
Indirect Mapped Registers
Following in Figure 6 is a table defining the mapping of AD1847 8-bit Index Registers to Index Address. These registers are accessed
by writing the appropriate 4-bit Index Address in the Control Word.
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Register Name
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #l Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left DAC Control
Right DAC Control
Data Format
Interface Configuration
Pin Control
Invalid Address
Miscellaneous Information
Digital Mix Control
Invalid Address
Invalid Address
Figure 6. Index Register Mapping
A detailed description of each of the Index Registers is given below.
–12–
REV. B
AD1847
Left Input Control Register (Index Address 0)
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
0000
LSS1
LSS0
res
res
LIG3
LIG2
LIG1
LIG0
LIG3:0
Left Input Gain Select. The least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is
+22.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LSS1:0
Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC.
0
1
2
3
Left Line 1 Source Selected
Left Auxiliary 1 Source Selected
Left Line 2 Source Selected
Left Line 1 Post-Mixed Output Loopback Source Selected
This register’s initial state after reset is: 0000 0000 (00h).
Right Input Control Register (Index Address 1)
IA3:0
0001
Data 7
RSS1
Data 6
RSS0
Data 5
res
Data 4
res
Data 3
RIG3
Data 2
RIG2
Data 1
RIG1
Data 0
RIG0
RIG3:0
Right Input Gain Select. The least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is
+22.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RSS1:0
Right Input Source Select. These bits select the input source for the right gain stage preceding the right ADC.
0
1
2
3
Right Line 1 Source Selected
Right Auxiliary 1 Source Selected
Right Line 2 Source Selected
Right Line 1 Post-Mixed Output Loopback Source Selected
This register’s initial state after reset is: 0000 0000 (00h).
Left Auxiliary #1 Input Control Register (Index Address 2)
IA3:0
0010
Data 7
LMX1
Data 6
res
Data 5
res
Data 4
LX1G4
Data 3
LX1G3
Data 2
LX1G2
Data 1
LX1G1
Data 0
LX1G0
LX1G4:0 Left Auxiliary Input #1 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
LX1G4:0 = 0 produces a +12 dB gain. LX1G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LMX1
Left Auxiliary #1 Mute. This bit, when set HI, will mute the left channel of the Auxiliary #1 input source. This bit is set
HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right Auxiliary #1 Input Control Register (Index Address 3)
IA3:0
0011
Data 7
RMX1
Data 6
res
Data 5
res
Data 4
RX1G4
Data 3
RX1G3
Data 2
RX1G2
Data 1
RX1G1
Data 0
RX1G0
RX1G4:0 Right Auxiliary Input #1 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
RX1G4:0 = 0 produces a +12 dB gain. RX1G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RMX1
Right Auxiliary #1 Mute. This bit, when set to HI, will mute the right channel of the Auxiliary #1 input source. This bit is
set to HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
REV. B
–13–
AD1847
Left Auxiliary #2 Input Control Register (Index Address 4)
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
0100
LMX2
res
res
LX2G4
LX2G3
LX2G2
LX2G1
LX2G0
LX2G4:0 Left Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
LX2G4:0 = 0 produces a +12 dB gain. LX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LMX2
Left Auxiliary #2 Mute. This bit, when set HI, will mute the left channel of the Auxiliary #2 input source. This bit is HI
after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right Auxiliary #2 Input Control Register (Index Address 5)
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
0101
RMX2
res
res
RX2G4
RX2G3
RX2G2
RX2G1
RX2G0
RX2G4:0 Right Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
RX2G4:0 = 0 produces a +12 dB gain. RX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RMX2
Right Auxiliary #2 Mute. This bit, when set HI, will mute the right channel of the Auxiliary #2 input source. This bit is
HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Left DAC Control Register (Index Address 6)
IA3:0
0110
Data 7
LDM
Data 6
res
Data 5
LDA5
Data 4
LDA4
Data 3
LDA3
Data 2
LDA2
Data 1
LDA1
Data 0
LDA0
LDA5:0 Left DAC Attenuate Select. The least significant bit of this 64-level attenuate select represents –1.5 dB. LDA5:0 = 0 produces a 0 dB attenuation. Maximum attenuation is –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LDM
Left DAC Mute. This bit, when set HI, will mute the left channel output. Auxiliary inputs are muted independently with
the Left Auxiliary Input Control Registers. This bit is HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
Right DAC Control Register (Index Address 7)
IA3:0
0111
Data 7
RDM
Data 6
res
Data 5
RDA5
Data 4
RDA4
Data 3
RDA3
Data 2
RDA2
Data 1
RDA1
Data 0
RDA0
RDA5:0 Right DAC Attenuate Select. The least significant bit of this 64-level attenuate select represents –1.5 dB. RDA5:0 = 0
produces a 0 dB attenuation. Maximum attenuation must be at least –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RDM
Right DAC Mute. This bit, when set HI, will mute the right DAC output. Auxiliary inputs are muted independently with
the Right Auxiliary Input Control Registers. This bit is HI after reset.
This register’s initial state after reset is: 1000 0000 (80h).
–14–
REV. B
AD1847
Data Format Register (Index Address 8)
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
1000
res
FMT
C/L
S/M
CFS2
CFS1
CFS0
CSL
The contents of this register can NOT be changed except when the AD1847 is in the Mode Change Enable (MCE) state (i.e., the MCE bit in
the Control Word is HI). Write attempts to this register when the AD1847 is not in the MCE state will not be successful.
CSL
CFS2:0
Clock Source Select. This bit selects the clock source to be used for the audio sample rate.
0
XTAL1 (24.576 MHz)
1
XTAL2 (16.9344 MHz)
Clock Frequency Divide Select. These bits select the audio sample rate frequency. The audio sample rate depends on
which clock source is selected and the frequency of the clock source.
CFS2:0
Divide
Factor
XTAL1
24.576 MHz
XTAL2
16.9344 MHz
0
1
2
3
4
5
6
7
3072
1536
896
768
448
384
512
2560
8.0 kHz
16.0 kHz
27.42857 kHz
32.0 kHz
Not Supported
Not Supported
48.0 kHz
9.6 kHz
5.5125 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.615 kHz
Note that the AD1847’s internal oscillators can be overdriven by external clock sources at the crystal inputs. This is the
configuration used by serial bus slave codecs in daisy-chained multiple codec systems. If an external clock source is applied, it will be divided down by the selected Divide Factor. The external clock need not be at the recommended crystal
frequencies.
S/M
Stereo/Mono Select. This bit determines how the audio data streams are formatted. Selecting stereo will result with alternating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels.
Mono capture only captures data from the left audio channel.
0
1
C/L
Companded/Linear Select. This bit selects between a linear digital representation of the audio signal or a nonlinear, companded format for all input and output data. The type of linear PCM or the type of companded format is defined by the
FMT bits.
0
1
FMT
Mono
Stereo
Linear PCM
Companded
Format Select. This bit defines the format for all digital audio input and output based on the state of the C/L bit.
0
1
res
Linear PCM (C/L = 0)
Companded (C/L = 1)
8-bit unsigned linear PCM
16-bit signed linear PCM
8-bit µ-law companded
8-bit A-law companded
Reserved for future expansion. Write zeros (LO) to all reserved bits.
This register’s initial state after reset is: 0000 0000 (00h).
REV. B
–15–
AD1847
Interface Configuration Register (Index Address 9)
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
1001
res
res
res
res
ACAL
res
res
PEN
PEN
Playback Enable. This bit will enable the playback of data in the format selected. PEN may be set and reset without
setting the MCE bit.
0
1
ACAL
Playback Disabled
Playback Enabled
Autocalibrate Enable. This bit determines whether the AD1847 performs an autocalibrate when exiting from the Mode
Change Enable (MCE) state. If the ACAL bit is not set, the previous autocalibration values are used when returning from
the Mode Change Enable (MCE) state and no autocalibration takes place. Autocalibration must be preformed after initial
power-up for proper operation. This bit is HI after reset.
0
No autocalibration
1
Autocalibration allowed
NOTE: The ACAL bit can only be changed when the AD1847 is in the Mode Change Enable (MCE) state.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
This register’s initial state after reset is: 0000 1000 (08h).
Pin Control Register (Index Address 10)
IA3:0
1010
CLKTS
Data 7
XCTL1
Data 6
XCTL0
Data 5
CLKTS
Data 4
res
Data 3
res
Data 2
res
Data 1
res
Data 0
res
Clock Three-State. If the BM bit is HI, and the CLKTS bit is HI, then the CLKOUT pin will be three-stated. If the BM
bit is HI, and the bit CLKTS is LO, then the CLKOUT pin is not three-stated. If the BM bit is LO, then the CLKOUT
pin is always three-stated.
XCTL1:0 External Control. The state of these independent bits is reflected on the respective XCTL1 and XCTL0 pins of the
AD1847.
res
0
TTL logic LO on XCTL1, XCTL0 pins
1
TTL logic HI on XCTL1, XCTL0 pins
Reserved for future expansion. Write zeros (LO) to all reserved bits.
This register’s initial state after reset is: 0000 0000 (00h).
Invalid Address (Index Address 11)
IA3:0
1011
inval
Data 7
inval
Data 6
inval
Data 5
inval
Data 4
inval
Data 3
inval
Data 2
inval
Data 1
inval
Data 0
inval
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
–16–
REV. B
AD1847
Miscellaneous Information Register (Index Address 12)
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
1100
FRS
TSSEL
res
res
res
res
res
res
The Miscellaneous Information Register can only be changed when the AD1847 is in the Mode Change Enable (MCE) state. Changes to this
register are updated at the next Serial Data Frame Sync (SDFS) boundary. If FRS is LO (i.e., 32 slots per frame), and either TSSEL or FRS
change in the first sample of a frame, the change is not updated at the second sample of the same frame, but at the first sample of the next frame.
TSSEL
Transmit Slot Select. This bit determines which TDM time slots the AD1847 should transmit on.
0
Transmit on time slots 3, 4 and 5. Used when SDI and SDO are tied together (i.e., “1-wire” system).
1
Transmit on slots 0, 1 and 2. Used when SDI and SDO are independent inputs and outputs
(i.e., “2-wire” system).
FRS
Frame Size. This bit selects the number of time slots per frame.
0
Selects 32 slots per frame (two samples per frame sync or frame sync at half the sample rate).
1
Selects 16 slots per frame (one sample per frame sync or frame sync at the sample rate).
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
This register’s initial state after reset is: 0000 0000 (00h).
Digital Mix Control Register (Index Address 13)
IA3:0
1101
DME
Data 7
DMA5
Data 6
DMA4
Data 5
DMA3
Data 4
DMA2
Data 3
DMA1
Data 2
DMA0
Data 1
res
Data 0
DME
Digital Mix Enable. This bit enables the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data
from the ADCs is digitally mixed with other data being delivered to the DACs (regardless of whether or not playback
[PEN] is enabled, i.e., set). If there is a capture overrun, then the last sample captured before overrun will be used for
the digital mix. If playback is enabled (PEN set) and there is a playback underrun, then a midscale zero will be added to
the digital mix data.
0
1
Digital mix disabled (muted)
Digital mix enabled
DMA5:0
Digital Mix Attenuation. These bits determine the attenuation of the ADC output data mixed with the DAC input data.
The least significant bit of this 64-level attenuate select represents –1.5 dB. Maximum attenuation is –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
This register’s initial state after reset is: 0000 0000 (00h).
Invalid Address (Index Address 14)
IA3:0
1110
inval
Data 7
inval
Data 6
inval
Data 5
inval
Data 4
inval
Data 3
inval
Data 2
inval
Data 1
inval
Data 0
inval
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
Invalid Address (Index Address 15)
IA3:0
1111
inval
REV. B
Data 7
inval
Data 6
inval
Data 5
inval
Data 4
inval
Data 3
inval
Data 2
inval
Data 1
inval
Data 0
inval
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
–17–
AD1847
Serial Data Interface
The AD1847 serial data interface uses a Time Division Multiplex (TDM) scheme that is compatible with DSP serial ports
configured in Multi-Channel Mode with either 32 or 16 16-bit
time slots. An AD1847 is always the serial bus master, transmitting the serial clock (SCLK) and the serial data frame sync
(SDFS). The AD1847 always receives control and playback
data in time slots 0, 1 and 2. The AD1847 will transmit status
or index register readback and capture data in time slots 0, 1
and 2 if TSSEL = 1, and will transmit status or index register
readback and capture data in time slots 3, 4 and 5 if TSSEL =
0. The following table in Figure 7 shows an example of how the
time slots might be assigned.
In this example design, which uses the ADSP-21xx DSP, each
frame is divided into 32 time slots of 16-bits each (FRS = 0).
Two audio samples are contained in the 32 time slots, with a
single frame sync (SDFS) at the beginning of the frame. The
ADSP-21xx serial port (SPORT0) supports 32 time slots. The
format of the first 16 time slots (sample N) is the same as the
format of the second 16 time slots (sample N+1). In this example, 24 time slots are used, as indicated below. Note that
time slots 12 through 15 and 28 through 31 are unused in this
example, and that Figure 7 presumes that TSSEL = 0 (“1-wire”
system).
Slot Number Source
0, 16
1, 17
ASIC
2, 18
3, 19
Destination
4,
5,
0,
1,
2,
3,
20
21
16
17
18
19
AD1847
ASIC
DSP
AD1847
4,
5,
6,
7,
20
21
22
23
AD1847
DSP
ASIC
DSP
AD1847
8, 24
9, 25
10, 26
11, 27
DSP
ASIC
Format
AD1847 Control Word
Left Playback Data
Right Playback Data
AD1847 Status Word/
Index Readback
Left Capture Data
Right Capture Data
AD1847 Control Word
Left Playback Data
Right Playback Data
AD1847 Status Word/
Index Readback
Left Capture Data
Right Capture Data
DSP Control
Left Processed
Playback Data
Right Processed
Playback Data
DSP Status
Left Processed
Capture Data
Right Processed
Capture Data
Note that in this “1-wire” system example, the Digital Signal
Processor (DSP) and ISA Bus Interface ASIC (ASIC) use the
same slots to communicate to the AD1847. This reduces the
number of total time slots required and eliminates the need for
the AD1847 to distinguish between DSP data and ASIC data.
Also, in this example the ASIC and the DSP do not send data to
the AD1847 at the same time, so separate slots are unnecessary.
The digital data in the serial interface is pipelined up to 2
samples deep. This pipelining is required to properly resolve the
interface between the relatively fast fixed SCLK rate, and the
relatively slow sample rates (and therefore frame sync rates) at
which the AD1847 is capable of running. At low sample rates,
two samples of data can be serviced in a fraction of a sample period. For example, at an 8 kHz sample rate, 32 time slots only
consume 32 × 16 × (1/12.288 MHz) = 41.67 µs out of a 125 µs
period. The two-deep data pipeline thus allows sample overrun
(capture) and sample underrun (playback) to be avoided.
Figure 8 represents a logical view of the slot utilization between
devices.
AD1847
0, 1, 2, 16, 17, 18
SDI
ASIC
SDO
3, 4, 5, 19, 20, 21
0, 1, 2,
16, 17, 18
9, 10, 11,
25, 26, 27
6, 7, 8,
22, 23, 24
3, 4, 5,
19, 20, 21
ADSP-21XX
DR
DT
DT
DR
NOTE: DSP MUST HAVE TWO SERIAL PORTS
Figure 8. Time Slot Allocation Example
Note that this is a system specific 1-wire example. For non-DSP
operation, the DSP is either not present or disabled. If the DSP
is present, the ASIC configures the DSP through slot 6 (and slot
22) to three-state its outputs in time slots 0, 1 and 2 (and slots
16, 17 and 18). The ASIC can then enable its drivers for time
slots 0, 1 and 2 (and slots 16, 17 and 18). For DSP operation,
the ASIC three-states its outputs for time slots 0, 1 and 2 (and
slots 16, 17 and 18) and enables the DSP drivers for slots 0, 1
and 2 (and slots 16, 17, and 18).
An application note is available from Analog Devices with additional information on interfacing to the AD1847 serial port.
This application note can be obtained through your local Analog Devices representative, or downloaded from the DSP Bulletin Board Service at (617) 461-4258 (8 data bits, no parity, 1
stop bit, 300/1200/2400/4600 baud).
Figure 7. Time Slot Assignment Example
–18–
REV. B
AD1847
Control Word
Data 15
CLOR
Data 14
MCE
Data 13
RREQ
Data 12
res
Data 11
IA3
Data 10
IA2
Data 9
IA1
Data 8
IA0
Data 7
DATA7
Data 6
DATA6
Data 5
DATA5
Data 4
DATA4
Data 3
DATA3
Data 2
DATA2
Data 1
DATA1
Data 0
DATA0
Data 15
DATA15
Data 14
DATA14
Data 13
DATA13
Data 12
DATA12
Data 11
DATA11
Data 10
DATA10
Data 9
DATA9
Data 8
DATA8
Data 7
DATA7
Data 6
DATA6
Data 5
DATA5
Data 4
DATA4
Data 3
DATA3
Data 2
DATA2
Data 1
DATA1
Data 0
DATA0
Data 15
DATA15
Data 14
DATA14
Data 13
DATA13
Data 12
DATA12
Data 11
DATA11
Data 10
DATA10
Data 9
DATA9
Data 8
DATA8
Data 7
DATA7
Data 6
DATA6
Data 5
DATA5
Data 4
DATA4
Data 3
DATA3
Data 2
DATA2
Data 1
DATA1
Data 0
DATA0
Data 15
res
Data 14
res
Data 13
RREQ
Data 12
res
Data 11
ID3
Data 10
ID2
Data 9
ID1
Data 8
ID0
Data 7
res
Data 6
res
Data 5
ORR1
Data 4
ORR0
Data 3
ORL1
Data 2
ORL0
Data 1
ACI
Data 0
INIT
Data 15
CLOR
Data 14
MCE
Data 13
RREQ
Data 12
res
Data 11
IA3
Data 10
IA2
Data 9
IA1
Data 8
IA0
Data 7
DATA7
Data 6
DATA6
Data 5
DATA5
Data 4
DATA4
Data 3
DATA3
Data 2
DATA2
Data 1
DATA1
Data 0
DATA0
Data 15
DATA15
Data 14
DATA14
Data 13
DATA13
Data 12
DATA12
Data 11
DATA11
Data 10
DATA10
Data 9
DATA9
Data 8
DATA8
Data 7
DATA7
Data 6
DATA6
Data 5
DATA5
Data 4
DATA4
Data 3
DATA3
Data 2
DATA2
Data 1
DATA 1
Data 0
DATA0
Left Playback Data
Right Playback Data
Status Word
Index Readback
Left Capture Data
Right Capture Data
REV. B
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
Data 7
DATA7
Data 6
DATA6
Data 5
DATA5
Data 4
DATA4
Data 3
DATA3
Data 2
DATA2
Data 1
DATA1
Data 0
DATA0
–19–
AD1847
IA3:0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Index
0000
LSS1
LSS0
res
res
LIG3
LIG2
LIG1
LIG0
0
0001
RSS1
RSS0
res
res
RIG3
RIG2
RIG1
RIG0
1
0010
0011
LMX1
RMX1
res
res
res
res
LX1G4
RX1G4
LX1G3
RX1G3
LX1G2
RX1G2
LX1G1
RX1G1
LX1G0
RX1G0
2
3
0100
LMX2
res
res
LX2G4
LX2G3
LX2G2
LX2G1
LX2G0
4
0101
RMX2
res
res
RX2G4
RX2G3
RX2G2
RX2G1
RX2G0
5
0110
LDM
res
LDA5
LDA4
LDA3
LDA2
LDA1
LDA0
6
0111
RDM
res
RDA5
RDA4
RDA3
RDA2
RDA1
RDA0
7
1000
res
FMT
C/L
S/M
CFS2
CFS1
CFS0
CSL
8
1001
1010
res
XCTL1
res
XCTL0
res
CLKTS
res
res
ACAL
res
res
res
res
res
PEN
res
9
10
1011
1100
1101
1110
1111
inval
FRS
DMA5
inval
inval
inval
TSSEL
DMA4
inval
inval
inval
res
DMA3
inval
inval
inval
res
DMA2
inval
inval
inval
res
DMA1
inval
inval
inval
res
DMA0
inval
inval
inval
res
res
inval
inval
inval
res
DME
inval
inval
11
12
13
14
15
Figure 9. Register Map Summary
Figure 10 illustrates the connection between master and slave(s)
in a daisy-chained, multiple Codec system. Note that the TSI
pin of the master Codec should be tied to digital ground. The
XTAL1I pin of the slaves should be connected to digital
ground, and XTAL1O pin should be left unconnected, while
the XTAL2I pin should be connected to the CLKOUT pin of
the AD1847 master, and the XTAL2O pin generates a driven
version of the CLKOUT signal applied to the XTAL2I pin.
Control Register Mapping Summary
A detailed map of the control register bit assignments is summarized for reference in Figure 9.
Daisy-Chained Multiple Codecs
Multiple AD1847s can be configured in a daisy-chain system
with a single master Codec and one or more slave Codecs.
Codecs in a daisy-chained configuration are synchronized at the
sample level.
The master and slave AD1847s should be powered-up together.
If this is not possible, the slave(s) should power-up before the
master Codec, such that the slave(s) are ready when the master
starts to drive the serial interface, and a serial data frame sync
(SDFS) can synchronize the master and slave(s).
INITIALIZATION AND PROCEDURES
Reset and Power Down
The sample rate for the master and slave(s) should be programmed together. If this is not possible, the slave(s) should be
programmed before the master AD1847. A slave AD1847 enters
a time-out period after a new sample rate has been selected.
During this time-out period, a slave will ignore any activity on
the SDFS signal (i.e., frame syncs). There is no software means
to determine when a slave has exited from this time-out period
and is ready to respond to frame syncs. However, as long as the
AD1847 master is driving the serial interface, a frame sync will
not occur before the slave Codec(s) are ready.
Note that the time slots for all slave AD1847s must be assigned
to those slots which immediately follow the time slots consumed
by the master AD1847 so that the TSO (Time Slot Output)/TSI
(Time Slot Input) signaling operates properly. For example, in a
2-wire system with one master and one slave, the time slot assignment should be 0, 1, 2 (16, 17, 18) for the master AD1847,
and 3, 4, 5 (19, 20, 21) for the slave AD1847.
A total reset of the AD1847 is defined as any event which
requires both the digital and analog section of the AD1847 to
return to a known and stable state. Total reset mode, as well as
power down, occurs when the PWRDOWN pin of the AD1847
has been asserted low for minimum power consumption. When
the PWRDOWN signal is deasserted, the AD1847 must be calibrated by setting the ACAL bit and exiting from the Mode
Change Enable (MCE) state.
The reset occurs, and only resets the digital section of the
AD1847, when the RESET pin of the AD1847 has been asserted LO to initialize all registers to known values. See the register definitions for the exact values initialized. The register reset
defaults include TSSEL = 0 (1-wire system) and FRS = 0
(32 slots per frame). If the target application requires a 2-wire
system design or 16 slots per frame, the AD1847 can be
bootstrapped into these configurations.
–20–
REV. B
AD1847
24.576
MHz
2
MCE bit set HI, IA3:0 = “1100” to address the Miscellaneous
Information Index Register, and DATA7:0 = “1X00 0000” to
set the FRS bit HI.
16.9344
MHz
2
The host CPU or DSP must maintain the MCE bit set HI in
slot 16, which is the Control Word of the second sample of
the frame, so that the AD1847 does not initiate autocalibration
prematurely. At the next frame sync, the AD1847 will be
reconfigured.
XTAL1I,O XTAL2I,O
SCLK
TSI
SDFS
AD1847
SDI
SDO (MASTER)
TSO
TSI
CLKOUT
The AD1847 must be reset after power up. When the RESET
signal is deasserted, the AD1847 will autocalibrate when the
MCE bit is reset LO (i.e., when exiting the Mode Change Enable state) only if the ACAL bit is set. If the ACAL bit is not
set, the previous autocalibration values will be used.
XTAL2I
SCLK
XTAL1O
N/C
SDFS
XTAL2O
SDI
SDO (SLAVE 1)
TSO
TSI
The AD1847 will not function properly unless an autocalibration is performed after power up.
XTAL1I
During power down, the serial port digital output pins and the
analog output pins take the following states:
XTAL2I
SCLK
XTAL1O
SDFS
XTAL2O N/C
SDI
SDO (SLAVE 2)
TSO
SCLK–LO if BM is HI (i.e., bus master), input pin if BM is
LO (i.e., bus slave)
SDFS–LO if BM is HI, input pin if BM is LO
SDO–three-state
TSO–three-state
CLKOUT–LO if BM HI, three-state if BM is LO
VREF–pulled to analog ground
L_OUT, R_ OUT– pulled to analog ground
XTAL1I
Figure 10a. One-Wire Daisy-Chained Codec Interconnect
24.576
MHz
2
16.9344
MHz
Clock Connections and Clock Rates
When the AD1847 is configured as a bus slave (BM = LO), the
XTAL1I pin should be connected to digital ground, and the
XTAL2I pin should be tied to the CLKOUT of the AD1847
bus master. The XTAL1O and the XTAL2O pins should be left
unconnected. When the AD1847 is configured as a bus master
(BM = HI), the XTAL1I and the XTAL1O pin should be connected to a 24.576 MHz crystal, and the XTAL2I and
XTAL2O pin should be connected to a 16.9344 MHz crystal.
2
XTAL1I, O XTAL2I, O
SCLK
TSI
SDFS
AD1847
SDI
SDO (MASTER)
TSO
TSI
CLKOUT
When XTAL1 is selected (by resetting the CSL bit LO in the
Data Format Register) as the clock source, the SCLK pin will
generated a serial clock at 12.288 MHz (or one half of the crystal frequency applied at XTAL1), and the CLKOUT pin will
also generate a clock output at 12.288 MHz when the AD1847
is in bus master mode (BM = HI). When XTAL2 is selected (by
setting the CSL bit HI in the Data Format Register) as the clock
source, the SCLK pin will generate a serial clock at 11.2896 MHz
(or two thirds of the crystal frequency applied at XTAL2), and
the CLKOUT pin will generate a clock output at 16.9344 MHz
when the AD1847 is in bus master mode (BM = HI). The
CLKOUT pin will be three-stated when the AD1847 is placed
in bus slave mode (BM = LO).
XTAL2I
SCLK
XTAL1O
N/C
SDFS
XTAL2O
SDI
SDO (SLAVE 1)
TSO
TSI
XTAL1I
XTAL2I
SCLK
XTAL1O
N/C
SDFS
XTAL2O
SDI
SDO (SLAVE 2)
TSO
XTAL1I
Figure 10b. Two-Wire Daisy-Chained Codec Interconnect
To bootstrap into TSSEL = 1 (i.e., 2-wire system design), the
host CPU or DSP must transmit to the AD1847 in slot 0 a
Control Word with the MCE bit set HI, IA3:0 = “1100” to
address the Miscellaneous Information Index Register, and
DATA7:0 = “X100 000” to set the TSSEL bit HI. To bootstrap
into FRS = 1 (i.e., 16 slots per frame), the host CPU or DSP
must transmit to the AD1847 in slot 0 a Control Word with the
REV. B
When the selected frame size is 32 slots per frame (by resetting
the FRS bit LO in the Miscellaneous Information Register), the
SDFS pin will generate a serial data frame sync at the frequency
of the selected sample rate divided by two, when the AD1847 is
in bus master mode (BM = HI). When the selected frame size is
16 slots per frame (by setting the FRS bit HI in the Miscellaneous Information Register), the SDFS pin will generate a serial
data frame sync at the frequency of the selected sample rate,
when the AD1847 is in bus master mode (BM = HI).
–21–
AD1847
If ACAL is not set, the AD1847 is muted for 128 sample periods after resetting the MCE bit, and the ACI bit in the Status
Word is set HI during this 128 sample periods. Autocalibration
must be performed after power-up to ensure proper operation of
the AD1847.
When the AD1847 is in bus slave mode (BM = LO), the TSI
pin should be connected to the TSO pin of the AD1847 master
or slave which has been assigned to the preceding time slots.
The signal on the TSO pin is essentially the signal received on
the TSI pin, but delayed by 3 or 6 time slots from TSI (depending on the state of TSSEL). The frequency of the transitions on
the TSI and TSO lines is equivalent to the frequency on the
SDFS pin.
Exiting from the MCE state always causes ACI to go HI. If the
ACAL bit is set when MCE state is exited, then the ACI bit will
be HI for 384 sample periods. If the ACAL bit is reset when
MCE is exited, then the ACI bit will be HI for 128 sample
periods.
When the AD1847 is in bus master mode (BM = HI), the TSI
pin should be connected to digital ground. The signal on the
TSO pin is essentially the same as the signal output on the
SDFS pin, but delayed by 3 or 6 time slots from SDFS (again,
depending on the state of TSSEL).
Changing Sample Rates
The internal states of the AD1847 are synchronized by the
selected sample frequency defined in the Data Format Register.
The changing of either the clock source or the clock frequency
divide requires a special sequence for proper AD1847 operation.
Mode Change Enable State
The AD1847 must be in the Mode Change Enable (MCE) state
before any changes to the ACAL bit of the Interface Configuration Register, the Data Format Register, or the Miscellaneous
Information Register are allowed. Note that the MCE bit does
not have to be reset LO in order for changes to take effect.
1. Mute the outputs of the AD1847 and enter the Mode Change
Enable (MCE) state by setting the MCE bit of the AD1847
Control Word.
2. During a single atomic or nondivisible write cycle, change the
Clock Frequency Divide Select (CFS) and/or the Clock
Source Select (CSL) bits of the Data Format Register to the
desired values. CFS and CSL can be programmed in the
same Control Word as MCE.
Digital Mix
Digital mix is enabled via the DME bit in the Digital Mix Control Register. The digital mix routes the digital data from the
ADCs to the DACs. The mix can be digitally attenuated via bits
also in the Digital Mix Control Register. The ADC data is
summed with the DAC data supplied at the digital bus interface. When digital mix is enabled and the PEN bit is not set,
ADC data is summed with zeros to produce the DAC output.
3. The INIT bit in the Status Word will be set HI at the last
sample of the next frame to indicate that the serial port will be
disabled for a timeout period.
4. The AD1847 requires a period of time to resynchronize its
internal states to the newly selected clock. During this time,
the AD1847 will be unable to respond at its serial interface
port (i.e., no frame syncs will be generated). The time-out
period is 221 3 SCLK ≈ 170 ms after power-up, and ≈ 5 ms
for subsequent changes of sample rate.
If the sum of the digital mix (ADC output and DAC input from
the serial bus interface) is greater than full scale, the AD1847
will send a positive or negative full scale value to the DACs,
whichever is appropriate (clipping).
Autocalibration
The AD1847 has the ability to calibrate its ADCs and DACs for
greater accuracy by minimizing dc offsets. Autocalibration occurs whenever the AD1847 exits from the Mode Change Enable
(MCE) state AND the ACAL bit in the Interface Configuration
Register has been set.
5. Exit the Mode Change Enable state by resetting the MCE bit.
Upon exiting the MCE state, an autocalibration of duration
384 sample periods or an output mute of duration 128 sample
periods occurs, depending on the state of the ACAL bit.
The completion of the autocalibration sequence can be determined by polling the Autocalibration In-Progress (ACI) bit in
the Status Word. This bit will be HI while the autocalibration is
in progress and LO once autocalibration has completed. The
autocalibration sequence will take at least 384 sample periods.
6. Poll the ACI bit in the AD1847 Status Word for a HI (indicating that autocalibration is in progress) then poll the ACI
bit for a LO (indicating that autocalibration has completed).
Once the ACI bit has been read back LO, normal operation of
the Codec can resume.
The autocalibration procedure is as follows:
The CSL and CFS bits cannot be changed unless the AD1847
is in the Mode Change Enable state (i.e., the MCE bit in the
AD1847 Control Word is set). Attempts to change the contents
of the Data Format Register without MCE set will result in the
write cycle not being recognized (the bits will not be updated).
1. Mute both left and right AUX1 and AUX2 inputs via the Left
Auxiliary Input and Right Auxiliary Input Control Registers.
2. Place the AD1847 in the Mode Change Enable (MCE) state
using the MCE bit of the AD1847 Control Word. Set the
ACAL bit in the Interface Configuration Register.
3. Exit from the Mode Change Enable state by resetting the
MCE bit.
4. Poll the ACI bit in the AD1847 Status Word for a HI
(autocalibration in progress), then poll the ACI bit for a LO
(autocalibration complete).
The MCE bit should not be reset until after the INIT bit in the
AD1847 Status Word is detected HI. After the INIT bit is detected HI, the serial port is disabled. When the next frame sync
arrives (after the time-out period), all internal clocks are stable
and the serial port is ready for normal operation.
5. Unmute the AUX inputs, if used.
–22–
REV. B
AD1847
DATA FORMAT DEFINITIONS
8-Bit Companded Formats
There are four data formats supported by the AD1847: 16-bit
signed, 8-bit unsigned, 8-bit companded µ-law, and 8-bit companded A-law. The AD1847 supports these four formats because
each of them have found wide use in important applications.
The 8-bit companded formats (µ-law and A-law) are used in the
telecommunications industry. Both of these formats are used in
ISDN communications and workstations; µ-law is the standard
for the United States and Japan while A-law is used in Europe.
Companded audio allows either 64 dB or 72 dB of dynamic
range using only 8-bits per sample. This is accomplished using a
nonlinear formula which assigns more digital codes to lower amplitude analog signals at the expense of resolution of higher amplitude signals. The µ-law format of the AD1847 conforms to
the Bell System µ = 255 companding law while the A-law format
conforms to CCITT “A” law models. Figure 13 shows approximately how both the µ-law and A-law companding schemes behave. Refer to the standards mentioned above for an exact
definition.
16-Bit Signed Format
The 16-bit signed format (also called 16-bit twos-complement)
is the standard method of representing 16-bit digital audio. This
format yields 96 dB of dynamic range and is common in consumer compact disk audio players. This format uses the value
– 32768 (8000h) to represent minimum analog amplitude while
32767 (7FFFh) represents maximum analog amplitude. Intermediate values are a linear interpolation between minimum and
maximum amplitude values.
MAX
ANALOG VALUE
ANALOG VALUE
MAX
MIN
8000h
0000h
DIGITAL VALUE
MIN
00h
2Ah
7FFFh
FFh
D5h
80h µ-law
AAh A-law
DIGITAL VALUE
Figure 11. 16-Bit Signed Format
Figure 13. 8-Bit Companded Format
8-Bit Unsigned Format
The 8-bit unsigned format is commonly used in the personal
computer industry. This format delivers 48 dB of dynamic
range. The value 0 (00h) is used to represent minimum analog
amplitude while 255 (FFh) is used to represent maximum analog amplitude. Intermediate values are a linear interpolation between minimum and maximum amplitude values. The least
significant byte of the 16-bit internal data is truncated to create
the 8-bit output samples.
ANALOG VALUE
MAX
MIN
00h
7Fh
DIGITAL VALUE
APPLICATIONS CIRCUITS
The AD1847 Stereo Codec has been designed to require a minimum of external circuitry. The recommended circuits are shown
in Figures 14 through 22. Analog Devices estimates that the total cost of all the components shown in these Figures, including
crystals, to be less than $3 in 10,000 quantities.
Industry-standard compact disc “line-levels” are 2 Vrms centered
around analog ground. (For other audio equipment, “line level”
is much more loosely defined.) The AD1847 SoundPort is a
+5 V only powered device. Line level voltage swings for the
AD1847 are defined to be 1 Vrms for a sine wave ADC input and
0.707 Vrms for a sine wave DAC output. Thus, 2 Vrms input analog signals must be attenuated and either centered around the
reference voltage intermediate between 0 V and +5 V or
ac-coupled. The VREF pin will be at this intermediate voltage,
nominally 2.25 V. It has limited drive but can be used as a voltage datum to an op amp input. Note, however, that dc-coupled
inputs are not recommended, as they provide no performance
benefits with the AD1847 architecture. Furthermore, dc offset
differences between multiple dc-coupled inputs create the potential for “clicks” when changing the input mux selection.
FFh
Figure 12. 8-Bit Unsigned Format
REV. B
–23–
AD1847
Circuits for 2 Vrms line-level inputs and auxiliaries are shown in
Figure 14 and Figure 15. Note that these are divide-by-two
resistive dividers. The input resistor and 560 pF (1000 pF)
capacitor provide the single-pole of antialias filtering required
for the ADCs. If line-level inputs are already at the 1 Vrms levels
expected by the AD1847, the resistors in parallel with the
560 pF (1000 pF) capacitors can be omitted. If the application
does not route the AUX2 inputs to the ADCs, then no antialias
filtering is required (only the 1 µF ac coupling capacitor).
0.33 µF
5.1k
560pF
NPO
Figure 17 shows ac-coupled line outputs. The resistors are
used to center the output signals around analog ground. If
dc-coupling is desired, VREF could be used with op amps as
mentioned previously.
1µF
L_OUT
47k
1µF
R_OUT
L_LINE1
L_LINE2
47k
5.1k
Figure 17. Line Output Connections
0.33 µF
5.1k
560pF
NPO
A circuit for headphone drive is illustrated in Figure 18. Drive is
supplied by +5 V operational amps. The circuit shown ac
couples the headphones to the line output.
R_LINE1
R_LINE2
5.1k
18k
20k
1µF
3.3k
1000pF
NPO
470µF
L_OUT
Figure 14. 2 Vrms Line-Level Input Circuit for Line Inputs
HEADPHONE
LEFT
VREF
L_AUX1
L_AUX2
SSM2135
470µF
20k
HEADPHONE
RIGHT
R_OUT
4.3k
18k
1µF
3.3k
1000pF
NPO
R_AUX1
R_AUX2
Figure 18. Headphone Drive Connections
Figure 19 illustrates reference bypassing. VREFI should only be
connected to its bypass capacitors.
4.3k
VREF
VREFI
Figure 15. 2 Vrms Line-Level Input Circuit for AUX Inputs
Figure 16 illustrates one example of how an electret condenser
microphone requiring phantom power could be connected to
the AD1847. VREF is shown buffered by an op amp; a transistor
like a 2N4124 will also work well for this purpose. Note that if a
battery-powered microphone is used, the buffer and R2s are not
needed. The values of R1, R2, and C should be chosen in light
of the mic characteristics and intended gain. Typical values for
these might be R1 = 20 kΩ, R2 = 2 kΩ, and C = 220 pF.
0.1µF
10µF
10µF
Figure 19. Voltage Reference Bypassing
Figure 20 illustrates signal-path filtering capacitors, L_FILT
and R_FILT. The AD1847 must use 1.0 µF capacitors. The
1.0 µF capacitors required by the AD1847 can be of any type.
LFILT
C
1.0µF
RFILT
1.0µF
R1
1µF
LEFT
ELECTRET
CONDENSER
MICROPHONE
INPUT
5k
0.33µF
L_LINE1
L_LINE2
1/2 SSM2135
OR AD820
R2
Figure 20. External Filter Capacitor Connections
VREF
1/2 SSM2135
OR AD820
C
R2
R1
RIGHT
ELECTRET
CONDENSER
MICROPHONE
INPUT
1µF
5k
0.33µF
1/2 SSM2135
OR AD820
R_LINE1
R_LINE2
VREF
Figure 16. “Phantom-Powered” Microphone Input Circuit
–24–
REV. B
AD1847
The crystals shown in the crystal connection circuitry of Figure
21 should be fundamental-mode and parallel-tuned. Two
sources for the exact crystals specified are Component Marketing Services in Massachusetts, U.S. at 617/762-4339 and
Cardinal Components in New Jersey, U.S. at 201/746-0333.
Note that using the exact data sheet frequencies is not required
and that external clock sources can be used to overdrive the
AD1847s internal oscillators. (See the description of the CFS2:0
control bits above.) If using an external clock source, apply it to
the crystal input pins while leaving the crystal output pins unconnected. Attention should be paid to providing low-jitter external input clocks .
XTAL1I
XTAL1O
20 64pF
20
XTAL2I
64pF
XTAL2O
20 64pF
24.576MHz
Analog Devices recommends a split ground plane as shown in
Figure 23. The analog plane and the digital plane are connected
directly under the AD1847. Splitting the ground plane directly
under the SoundPort Codec is optimal because analog pins will
be located directly above the analog ground plane and digital
pins will be located directly above the digital ground plane for
the best isolation. The digital and analog grounds should be tied
together in the vicinity of the AD1847. Other schemes may also
yield satisfactory results. If the split ground plane recommended
here is not possible, the AD1847 should be entirely over the
analog ground plane with the ASIC and DSP over the digital
plane.
20
DIGITAL
GROUND
PLANE
64pF
BM
L_AUX2
ANALOG
GROUND
PLANE
16.9344MHz
Figure 21. Crystal Connections
AD1847
Analog Devices also recommends a pull-down resistor on the
PWRDOWN signal.
Good, standard engineering practices should be applied for
power-supply decoupling. Decoupling capacitors should be
placed as close as possible to package pins. If a separate analog
power supply is not available, the circuit shown in Figure 22 is
recommended when using a single +5 V supply. Ferrite beads
suffice for the inductors shown. This circuitry should be as close
to the supply pins as is practical.
+5V SUPPLY
FERRITE
0.1µF
1µF
0.1µF
VDD
0.1µF
0.1µF
VDD
0.1µF
VDD
1.6
FERRITE
0.1µF
VDD
1µF
1µF
0.1µF
VCC
VCC
Figure 22. Recommended Power Supply Bypassing
REV. B
–25–
PWRDOWN
VCC
Figure 23. Recommended Ground Plane
AD1847
FREQUENCY RESPONSE PLOTS
10
10
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
dB
–50
dB
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0
0.1
SAMPLE FREQUENCY – F S
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Figure 26. AD1847 Digital-to-Analog Frequency Response
(Full-Scale Inputs, 0 dB Attenuation)
10
10
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
dB
–60
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
0.40
0.3
SAMPLE FREQUENCY – F S
Figure 24. AD1847 Analog-to-Digital Frequency Response
(Full-Scale Line-Level Inputs, 0 dB Gain)
dB
0.2
0.44
0.48
0.52
0.56
0.60
0.64
SAMPLE FREQUENCY – F S
–120
0.40
0.68 0.70
Figure 25. AD1847 Analog-to-Digital Frequency Response
–Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain)
0.44
0.48
0.52
0.56
0.60
0.64
SAMPLE FREQUENCY – F S
0.68 0.70
Figure 27. AD1847 Digital-to-Analog Frequency Response
–Transition Band (Full-Scale Inputs, 0 dB Attenuation)
–26–
REV. B
AD1847
tRPWL
RESET
PWRDOWN
SCLK
Figure 30. Reset and Power Down Timing Diagram
SDFS
tS
tPD1
tH
BIT 15
SDI
TIME
SLOT 0
BIT 0
BIT 14
tHZ
tDV
TIME
SLOT 1
TIME
SLOT 2
SCLK
SDO
BIT 15
BIT 14
BIT 0
SDFS
Figure 28. Time Slot Timing Diagram
16-BIT
STEREO
SCLK
SDFS
16-BIT
MONO
tPD1
SDI or
SDO
15 14 13
CONTROL
LEFT
PLAYBACK
RIGHT
PLAYBACK
SDO
STATUS
LEFT
CAPTURE
RIGHT
PLAYBACK
SDI/
CONTROL
LEFT
PLAYBACK
SDO
STATUS
LEFT
CAPTURE
SDI/
CONTROL
LEFT
PB
SDO
STATUS
LEFT
CAP
SDI/
CONTROL
LEFT
PB
SDO
STATUS
LEFT
CAP
SDI/
3 2 1 0 15 14 13
8-BIT
STEREO
LAST VALID TIME SLOT
TSO
8-BIT
MONO
tPD2
LEFT
CAPTURE
RIGHT
PB
0
RIGHT
CAP
0
0
LEFT
CAP
0
Figure 29. TSO Timing Diagram
Figure 31. Serial Data Format, 2-Wire System (TSSEL = 1)
TIME
SLOT 0
TIME
SLOT 1
TIME
SLOT 2
TIME
SLOT 3
TIME
SLOT 4
TIME
SLOT 5
RIGHT
STATUS
LEFT
RIGHT
STATUS
LEFT
LEFT
SCLK
SDFS
16-BIT
SDI/
SDO STEREO
CONTROL
LEFT
16-BIT
MONO
CONTROL
LEFT
SDI/
SDO
SDI/
8-BIT
SDO STEREO
CONTROL LEFT
8-BIT
MONO
CONTROL LEFT
SDI/
SDO
RIGHT
PLAYBACK
STATUS
LEFT
0
RIGHT
0
STATUS
LEFT
0
LEFT
0
CAPTURE
Figure 32. Serial Data Format, 1-Wire System (TSSEL = 0)
REV. B
–27–
INDEX
PAGE
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . 1
AD1847 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 2
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AUDIO FUNCTIONAL DESCRIPTION . . . . . . . . . . . 7
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . 7
Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . 7
Digital Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supplies and Voltage Reference . . . . . . . . . . . . . 8
Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . 8
CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . 9
Control Register Mapping . . . . . . . . . . . . . . . . . . . . . . 9
Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Left/Right Playback/Capture Data . . . . . . . . . . . . . . . 10
Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 11
Index Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Indirect Mapped Registers . . . . . . . . . . . . . . . . . . . . . 12
Left Input Control Register . . . . . . . . . . . . . . . . . . . . 13
Right Input Control Register . . . . . . . . . . . . . . . . . . . 13
Left Auxiliary #1 Input Control Register . . . . . . . . . . 13
Right Auxiliary #1 Input Control Register . . . . . . . . . 13
Left Auxiliary #2 Input Control Register . . . . . . . . . . 14
Right Auxiliary #2 Input Control Register . . . . . . . . . 14
Left DAC Control Register . . . . . . . . . . . . . . . . . . . . . 14
Right DAC Control Register . . . . . . . . . . . . . . . . . . . . 14
Data Format Register . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interface Configuration Register . . . . . . . . . . . . . . . . . 16
Pin Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Invalid Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Miscellaneous Information Register . . . . . . . . . . . . . . 17
Digital Mix Control Register . . . . . . . . . . . . . . . . . . . 17
Invalid Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Control Register Mapping Summary . . . . . . . . . . . . . 20
Daisy-Chained Multiple Codecs . . . . . . . . . . . . . . . . . 20
INITIALIZATION AND PROCEDURES . . . . . . . . . . 21
Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Connections and Clock Rates . . . . . . . . . . . . . . 21
Mode Change Enable State . . . . . . . . . . . . . . . . . . . . 22
Digital Mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Changing Sample Rates . . . . . . . . . . . . . . . . . . . . . . . 22
DATA FORMAT DEFINITIONS . . . . . . . . . . . . . . . . 23
16-Bit Signed Format . . . . . . . . . . . . . . . . . . . . . . . . . 23
8-Bit Unsigned Format . . . . . . . . . . . . . . . . . . . . . . . . 23
8-Bit Companded Formats . . . . . . . . . . . . . . . . . . . . . 23
APPLICATIONS CIRCUITS . . . . . . . . . . . . . . . . . . . . 23
FREQUENCY RESPONSE PLOTS . . . . . . . . . . . . . . . 26
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . 27
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 28
44-Lead PLCC
(P-44A)
0.048 (1.21)
0.042 (1.07)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
6
0.025 (0.63)
0.015 (0.38)
40
PIN 1
IDENTIFIER
7
0.048 (1.21)
0.042 (1.07)
39
0.021 (0.53)
0.013 (0.33)
0.63 (16.00)
0.59 (14.99)
0.032 (0.81)
0.026 (0.66)
TOP VIEW
0.050
(1.27)
BSC
29
17
18
28
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.656 (16.66)
SQ
0.650 (16.51)
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
SQ
0.685 (17.40)
44-Terminal Plastic Thin Quad Flatpack (TQFP)
(ST-44)
0.063 (1.60)
MAX
0.472 (12.00) SQ
0.030 (0.75)
0.018 (0.45)
33
23
34
22
SEATING
PLANE
0.394
(10.0)
SQ
TOP VIEW
(PINS DOWN)
44
12
1
0.006 (0.15)
0.002 (0.05)
0.057 (1.45)
0.053 (1.35)
0.031 (0.80)
BSC
11
0.018 (0.45)
0.012 (0.30)
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
–28–
REV. B
PRINTED IN U.S.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1871b–2–8/96
AD1847