a FEATURES 14-Bit, 40/65 MSPS ADC Low Power: 550 mW at 65 MSPS 300 mW at 40 MSPS On-Chip Reference and Sample-and-Hold 750 MHz Analog Input Bandwidth SNR > 73 dBc to Nyquist @ 65 MSPS SFDR > 86 dBc to Nyquist @ 65 MSPS Differential Nonlinearity Error = ⴞ0.7 LSB Guaranteed No Missing Codes over Full Temperature Range 1 V to 2 V p-p Differential Full-Scale Analog Input Range Single 5 V Analog Supply, 3.3 V/5 V Driver Supply Out-of-Range Indicator Straight Binary or Twos Complement Output Data Clock Duty Cycle Stabilizer Output Enable Function 48-Lead LQFP Package APPLICATIONS Communications Subsystems (Microcell, Picocell) Medical and High End Imaging Equipment Ultrasound Equipment 14-Bit, 40/65 MSPS A/D Converter AD9244 FUNCTIONAL BLOCK DIAGRAM DRVDD REFT REFB AVDD AD9244 TEN STAGE PIPELINE ADC VIN+ SHA VIN– DFS 14 CLK+ CLK– OUTPUT REGISTER TIMING OTR DCS D13–D0 14 REFERENCE OEB AGND CML VR VREF SENSE REF GND DGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9244 is a monolithic, single 5 V supply, 14-bit, 40 MSPS/65 MSPS analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. The AD9244 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy at 40 MSPS/65 MSPS data rates and guarantees no missing codes over the full operating temperature range. Low Power—The AD9244, at 550 mW, consumes a fraction of the power of presently available ADCs in existing high speed solutions. The AD9244 has an on-board, programmable voltage reference. An external reference can also be used to suit the dc accuracy and temperature drift requirements of the application. Pin Compatibility—The AD9244 offers a seamless migration from the 12-bit, 65 MSPS AD9226. A differential or single-ended clock input is used to control all internal conversion cycles. The digital output data can be presented in straight binary or in twos complement format. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9244 is available in a 48-lead low profile quad flatpack package (LQFP) and is specified for operation over the industrial temperature range (–40°C to +85°C). IF Sampling—The AD9244 delivers outstanding performance at input frequencies beyond the first Nyquist zone. Sampling at 65 MSPS with an input frequency of 100 MHz, the AD9244 delivers 71 dB SNR and 86 dB SFDR. On-Board Sample-and-Hold (SHA)—The versatile SHA input can be configured for either single-ended or differential inputs. Out-of-Range (OTR)—The OTR output bit indicates when the input signal is beyond the AD9244’s input range. Single Supply—The AD9244 uses a single 5 V power supply, simplifying system power supply design. It also features a separate digital output driver supply to accommodate 3.3 V and 5 V logic families. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9244–SPECIFICATIONS DC SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V, External Reference, Differential Analog Inputs, unless otherwise noted.) Parameter Temp Test Level AD9244BST-65 Min Typ Max Min RESOLUTION Full VI 14 14 Full Full Full Full 25°C Full VI VI VI VI V V TEMPERATURE DRIFT Offset Error Gain Error (EXT VREF)1 Gain Error (INT VREF)3 Full Full Full V V V INTERNAL VOLTAGE REFERENCE Output Voltage Error (2 VREF) Load Regulation @ 1 mA Output Voltage Error (1 VREF) Load Regulation @ 0.5 mA Input Resistance Full Full Full Full Full VI V IV V V INPUT REFERRED NOISE VREF = 2 V VREF = 1 V 25°C 25°C ANALOG INPUT Input Voltage Range (Differential) VREF = 2 V VREF = 1 V Common-Mode Voltage Input Capacitance4 Input Bias Current5 Analog Bandwidth (Full Power) DC ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD IDRVDD PSRR POWER CONSUMPTION DC Input6 Sine Wave Input Guaranteed ± 0.3 ± 1.4 ± 0.6 ± 2.0 ± 1.0 ± 0.7 ± 1.4 AD9244BST-40 Typ Max Bits Guaranteed ± 0.3 ± 0.6 ± 0.6 ± 1.3 ± 2.0 ± 2.3 ± 25 Unit ± 1.4 ± 2.0 ± 1.0 ± 2.0 ± 2.3 ± 25 ± 29 Bits % FSR % FSR LSB LSB LSB ppm/°C ppm/°C ppm/°C ± 29 0.25 5 0.25 5 mV mV mV mV kΩ V V 0.8 1.5 0.8 1.5 LSB rms LSB rms Full Full Full 25°C 25°C 25°C V V V V V V 2 1 2 1 V p-p V p-p V pF µA MHz Full Full IV IV Full Full Full V V V 109 12 ± 0.05 Full Full V VI 550 590 0.5 0.5 ± 15 0.5 4 ± 15 0.5 10 500 750 4.75 2.7 5 4 10 500 750 5.25 5.25 4.75 2.7 5 5.25 5.25 64 8 ± 0.05 640 300 345 V V mA mA % FSR 370 mW mW NOTES 1 Gain error is based on the ADC only (with a fixed 2.0 V external reference). 2 Measured at maximum clock rate, f IN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Includes internal voltage reference error. 4 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2d for the equivalent analog input structure. 5 Input bias current is due to the inputs looking like a resistor that is dependent on the clock rate. 6 Measured with dc input at maximum clock rate. Specifications subject to change without notice. –2– REV. A AD9244 AC SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V, External Reference, AIN = –0.5 dBFS, Differential Analog Inputs, unless otherwise noted.) Parameter Temp Test Level Full 25°C Full 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C VI I IV V VI I IV I IV V V V Full 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C VI I VI I IV I IV V V V 72.2 Full 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C VI I VI I IV I IV V V V 11.7 fIN = 100 MHz fIN = 200 MHz Full 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C VI I VI I IV I IV V V V WORST 2 or 3 fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz 25°C 25°C 25°C 25°C 25°C 25°C V V V V V V SNR fIN = 2.4 MHz fIN = 15.5 MHz (–1 dBFS) fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz SINAD fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz ENOB fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz THD fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz REV. A Min AD9244BST-65 Typ Max 72.4 Min AD9244BST-40 Typ Max 73.4 74.8 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 75.3 72.0 73.7 72.1 74.7 70.8 73.0 69.9 72.2 71.2 67.2 72.8 68.3 73.2 74.7 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 75.1 72 74.4 70.6 72.6 69.7 71.9 71 59.8 72.4 56.3 11.9 12.1 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 12.2 11.7 12.1 11.4 11.8 11.3 11.7 11.5 9.6 11.7 9.1 –78.4 –90.0 –80.7 –89.7 –80.4 –89.4 –79.2 –84.6 –78.7 –84.1 –83.0 –60.7 –94.5 –86.5 –86.1 –86.2 –60.7 –3– –83.2 –56.6 –93.7 –92.8 –84.5 –56.6 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9244 AC SPECIFICATIONS (continued) Parameter SFDR fIN = 2.4 MHz fIN = 15.5 MHz (–1 dBFS) fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz Temp Test Level Full 25°C Full 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C VI I IV V IV I IV I IV V V V DIGITAL SPECIFICATIONS Min AD9244BST-65 Typ Max 78.6 Min AD9244BST-40 Typ Max Unit 82.5 94.5 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 93.7 83 90 81.4 91.8 80.0 86.4 79.5 86.1 86.2 60.7 84.5 56.6 (AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, External Reference, unless otherwise noted.) Parameter Temp Test Level AD9244BST-65 Min Typ Max AD9244BST-40 Min Typ Max DIGITAL INPUTS Logic 1 Voltage (OEB, DRVDD = 3 V) Logic 1 Voltage (OEB, DRVDD = 5 V) Logic 0 Voltage (OEB) Logic 1 Voltage (DFS, DCS) Logic 0 Voltage (DFS, DCS) Input Current Input Capacitance Full Full Full Full Full Full Full IV IV IV IV IV IV V 2 3.5 2 3.5 Full Full Full IV IV V 0.4 0.25 Full Full Full Full IV IV V V 2 Full Full Full Full IV IV IV IV 4.5 Full Full Full Full IV IV IV IV 2.95 CLOCK INPUT PARAMETERS Differential Input Voltage CLK–Voltage1 Internal Clock Common-Mode Single-Ended Input Voltage Logic 1 Voltage Logic 0 Voltage Input Capacitance Input Resistance DIGITAL OUTPUTS (DRVDD = 5 V)2 Logic 1 Voltage (IOH = 50 µA) Logic 0 Voltage (IOL = 50 µA) Logic 1 Voltage (IOH = 0.5 mA) Logic 0 Voltage (IOL = 1.6 mA) 5 V V V V V µA pF 1.6 V p-p V V 0.8 3.5 0.8 3.5 0.8 10 0.8 10 5 0.4 0.25 1.6 2 0.8 0.8 5 100 5 100 4.5 0.1 2.4 0.1 2.4 0.4 Unit 0.4 V V pF kΩ V V V V 2 DIGITAL OUTPUTS (DRVDD = 3 V) Logic 1 Voltage (IOH = 50 µA) Logic 0 Voltage (IOL = 50 µA) Logic 1 Voltage (IOH = 0.5 mA) Logic 0 Voltage (IOL = 1.6 mA) 2.95 0.05 2.8 0.05 2.8 0.4 0.4 V V V V NOTES 1 See Clock section of Theory of Operation for more details. 2 Output voltage levels measured with 5 pF load on each output. Specifications subject to change without notice. –4– REV. A AD9244 SWITCHING SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.) Parameter Temp Test Level AD9244BST-65 Min Typ Max AD9244BST-40 Min Typ Max CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate Clock Period1 Clock Pulsewidth High2 Clock Pulsewidth Low2 Clock Pulsewidth High3 Clock Pulsewidth Low3 Full Full Full Full Full Full Full VI V V V V V V 65 40 DATA OUTPUT PARAMETERS Output Delay (tPD)4 Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Enable Delay Full Full Full Full Full V V V V V OUT-OF-RANGE RECOVERY TIME Full V 500 15.4 4 4 6.9 6.9 500 25 4 4 11.3 11.3 3.5 7 3.5 7 8 1.5 0.3 15 ns Clock Cycles ns ps rms ns 2 1 Clock Cycles N+3 N+2 N+4 N N+5 ANALOG INPUT N+6 N+9 N+7 N+8 tA CLOCK DATA N–9 OUT N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N tPD Figure 1. Input Timing REV. A –5– MHz kHz ns ns ns ns ns 8 1.5 0.3 15 NOTES 1 The clock period may be extended to 2 µs with no degradation in specified performance at 25°C. 2 With duty cycle stabilizer enabled. 3 With duty cycle stabilizer disabled. 4 Measured from clock 50% transition to data 50% transition with 5 pF load on each output. Specifications subject to change without notice N+1 Unit N+1 AD9244 ABSOLUTE MAXIMUM RATINGS 1 EXPLANATION OF TEST LEVELS Test Level Mnemonic With Respect to Min Max Unit ELECTRICAL AVDD DRVDD AGND AVDD REFGND CLK+, CLK–, DCS DFS VIN+, VIN– VREF SENSE REFB, REFT CML VR OTR D0–D13 OEB AGND DGND DGND DRVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND DGND DGND DGND V V V V V V V V V V V V V V V V ENVIRONMENTAL2 Junction Temperature Storage Temperature Operating Temperature Lead Temperature (10 sec) –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 +0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 DRVDD + 0.3 DRVDD + 0.3 150 –65 +150 –40 +85 300 I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. °C °C °C °C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical thermal impedances; JA = 50.0°C/W; JC = 17.0°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9244BST-65 AD9244BST-40 AD9244BSTRL-65 AD9244BSTRL-40 AD9244-65PCB AD9244-40PCB –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C ST-48 ST-48 ST-48 ST-48 48-Lead Low Profile Quad Flatpack Package 48-Lead Low Profile Quad Flatpack Package 48-Lead Low Profile Quad Flatpack Package 48-Lead Low Profile Quad Flatpack Package Evaluation Board Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9244 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. A AD9244 VR VIN– VIN+ CML NIC DCS REFT REFT REFB REFB REFGND VREF PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 SENSE AGND 2 35 DFS AVDD 3 34 AVDD AVDD 4 33 AGND AGND 5 32 AGND CLK– 6 AD9244 31 AVDD CLK+ 7 TOP VIEW (NOT TO SCALE) 30 DGND 29 DRVDD NIC 8 28 OTR OEB 9 D0 (LSB) 10 27 D13 (MSB) 26 D12 D1 11 15 16 17 18 19 20 21 22 23 24 D4 D5 D6 D7 D8 D9 DGND DRVDD D10 D3 14 DRVDD 25 D11 13 DGND D2 12 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 2, 5, 32, 33 3, 4, 31, 34 6, 7 8, 44 9 10 11–13, 16–21, 24–26 14, 22, 30 15, 23, 29 27 28 35 36 37 38 39–42 43 AGND AVDD CLK–, CLK+ NIC OEB D0 (LSB) D1–D3, D4–D9, D10–D12 DGND DRVDD D13 (MSB) OTR DFS SENSE VREF REFGND REFB, REFT DCS Analog Ground. Analog Supply Voltage. Differential Clock Inputs. No Internal Connection. Digital Output Enable (Active Low). Least Significant Bit, Digital Output. Digital Outputs. 45 46, 47 48 CML VIN+, VIN– VR REV. A Digital Ground. Digital Supply Voltage. Most Significant Bit, Digital Output. Out-of-Range Indicator (Logic 1 indicates OTR). Data Format Select. Connect to AGND for straight binary, AVDD for twos complement. Internal Reference Control. Internal Reference. Reference Ground. Internal Reference Decoupling. 50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for external control of both clock edges. Common-Mode Reference (0.5 × AVDD). Differential Analog Inputs. Internal Bias Decoupling. –7– AD9244 sampled signal does not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (noise caused by jitter increases as the input frequency increases). TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Aperture Delay The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Voltage Range Minimum Conversion Rate The peak-to-peak differential voltage must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and taking the peak measurement again. Then the difference is found between the two peak measurements. The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Nyquist Sampling When the frequency components of the analog input are below the Nyquist frequency (fCLOCK/2), this is often referred to as Nyquist sampling. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Dual Tone SFDR* The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Power Supply Rejection Ratio The change in full scale from the value with the supply at its minimum limit to the value with the supply at its maximum limit. Effective Number of Bits (ENOB) The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula: Signal-to-Noise-and-Distortion (SINAD)* The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. N = (SINAD – 1.76) / 6.02 Signal-to-Noise Ratio (SNR)* Gain Error The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last code transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Spurious-Free Dynamic Range (SFDR)* The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Temperature Drift Common-Mode Rejection Ratio (CMRR) The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Common-mode (CM) signals appearing on VIN+ and VIN– are ideally rejected by the differential front end of the ADC. With a full-scale CM signal driving both VIN+ and VIN–, CMRR is the ratio of the amplitude of the full-scale input CM signal to the amplitude of signal that is not rejected, expressed in dBFS. Total Harmonic Distortion (THD)* The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. IF Sampling Due to the effects of aliasing, an ADC is not necessarily limited to Nyquist sampling. Higher sampled frequencies will be aliased down into the first Nyquist zone (DC–fCLOCK/2) on the output of the ADC. Care must be taken that the bandwidth of the Offset Error The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN–. Offset error is defined as the deviation of the actual transition from that point. *AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). –8– REV. A AD9244 DRVDD AVDD DRVDD DRVDD DGND a. D0–D13, OTR AVDD CLK BUFFER 200⍀ 200⍀ DGND AGND b. Three-State (OEB) AVDD c. CLK+, CLK– AVDD 200⍀ AGND AGND d. VIN+, VIN– e. DFS, DCS, SENSE Figure 2. Equivalent Circuits REV. A –9– AGND f. VREF, REFT, REFB, VR, CML AD9244–Typical Performance Characteristics (AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Duty Cycle Stabilizer Enabled, TA = 25ⴗC, Differential Analog Input, Common-Mode Voltage (VCM) = 2.5 V, Input Amplitude (AIN) = –0.5 dBFS, VREF = 2.0 V External, FFT length = 8 K, unless otherwise noted.) 0 100 SNR = 74.8dBc SFDR = 93.6dBc –20 90 –40 80 SFDR – dBFS dBFS AND dBc AMPLITUDE – dBFS SFDR – dBc –60 –80 SNR – dBFS 70 SFDR = 90dBc REFERENCE LINE 60 –100 50 –120 40 0 5 10 15 20 FREQUENCY – MHz 25 30 32.5 –30 TPC 1. Single-Tone FFT, fIN = 5 MHz –25 –20 –15 AIN – dBFS –10 –5 0 TPC 4. Single-Tone SNR/SFDR vs. AIN, fIN = 5 MHz 0 100 SNR = 74.0dBc SFDR = 87.0dBc SFDR – dBFS –20 90 –40 80 dBFS AND dBc AMPLITUDE – dBFS SNR – dBc –60 –80 SNR – dBFS 70 SFDR – dBc SFDR = 90dBc REFERENCE LINE 60 50 –100 SNR – dBc –120 0 5 10 15 20 FREQUENCY – MHz 40 –30 30 32.5 25 TPC 2. Single-Tone FFT, fIN = 31 MHz –25 –20 –15 AIN – dBFS –10 –5 0 TPC 5. Single-Tone SNR/SFDR vs AIN, fIN = 31 MHz 0 100 SNR = 68.0dBc SFDR = 59.5dBc –20 90 dBFS AND dBc AMPLITUDE – dBFS SFDR – dBFS –40 –60 –80 80 70 SNR – dBFS SFDR – dBc 60 SFDR = 90dBc REFERENCE LINE SNR – dBc –100 50 –120 0 5 10 15 20 FREQUENCY – MHz 25 40 –30 30 30.72 TPC 3. Single-Tone FFT, fIN = 190 MHz, fSAMPLE = 61.44 MSPS –25 –20 –15 AIN – dBFS –10 –5 0 TPC 6. Single-Tone SNR/SFDR vs. AIN, fIN = 190 MHz, fSAMPLE = 61.44 MSPS –10– REV. A 75 12.2 75 73 11.8 73 71 11.5 11.2 SNR – dBc 2V SPAN 69 ENOB – Bits SINAD – dBc AD9244 2V SPAN 71 69 1V SPAN 1V SPAN 10.8 67 10.5 140 65 67 65 0 20 40 60 80 100 120 0 20 INPUT FREQUENCY – MHz TPC 7. SINAD/ENOB vs. Input Frequency 40 60 80 100 INPUT FREQUENCY – MHz 120 140 TPC 10. SNR vs. Input Frequency –100 100 –95 95 –90 90 SFDR – dBc THD – dBc 1V SPAN 1V SPAN –85 –80 –75 80 2V SPAN 0 20 40 60 80 100 INPUT FREQUENCY – MHz 85 120 2V SPAN 75 140 0 TPC 8. THD vs. Input Frequency 20 40 60 80 100 INPUT FREQUENCY – MHz 120 140 TPC 11. SFDR vs. Input Frequency –92 77 –90 75 –88 +25ⴗC +25ⴗC 73 THD – dBc SNR – dBc –86 –40ⴗC 71 –40ⴗC –84 –82 –80 +85ⴗC –78 69 +85ⴗC 67 –76 –74 0 20 40 60 80 100 INPUT FREQUENCY – MHz 120 0 140 TPC 9. SNR vs. Temperature and Input Frequency REV. A 20 40 60 80 100 INPUT FREQUENCY – MHz 120 140 TPC 12. THD vs. Temperature and Input Frequency –11– AD9244 100 –100 95 FOURTH HARMONIC SFDR, DCS ON 90 THIRD HARMONIC SNR/SFDR – dBc HARMONICS – dBc –95 –90 –85 85 SFDR, DCS OFF 80 75 SNR, DCS ON 70 SECOND HARMONIC –80 65 SNR, DCS OFF –75 0 20 40 60 80 100 120 60 140 30 35 40 INPUT FREQUENCY – MHz 70 fIN = 2MHz 12.17 96 11.83 73 fIN = 20MHz 72 11.67 71 11.50 70 0 20 40 60 SAMPLE RATE – MSPS 80 SFDR – dBc fIN = 10MHz ENOB – Bits 12.00 74 SINAD – dBc 65 100 12.33 fIN = 2MHz 75 60 TPC 16. SNR/SFDR vs. Duty Cycle, fIN = 2.5 MHz TPC 13. Harmonics vs. Input Frequency 76 45 50 55 DUTY CYCLE – % 92 fIN = 10MHz 88 fIN = 20MHz 84 11.34 100 80 0 20 40 60 80 100 SAMPLE RATE – MSPS TPC 17. SFDR vs. Sample Rate TPC 14. SINAD vs. Sample Rate 1.5 1.0 0.8 1.0 0.6 0.4 DNL – LSB INL – LSB 0.5 0 0.2 0 –0.2 –0.5 –0.4 –0.6 –1.0 –0.8 –1.5 0 4096 8192 12288 –1.0 16384 CODES – 14-Bit 0 4096 8192 12288 16384 CODES – 14-Bit TPC 15. Typical INL TPC 18. Typical DNL –12– REV. A AD9244 TYPICAL IF SAMPLING PERFORMANCE 0 100 SFDR – dBFS SNR = 67.5dBc SFDR = 79.4dBc 90 –20 80 –40 dBFS AND dBc AMPLITUDE – dBFS SFDR – dBc –60 –80 SNR – dBFS 70 SFDR = 90dBc REFERENCE LINE 60 SNR – dBc 50 –100 –120 0 5 10 15 20 FREQUENCY – MHz 25 40 –30 30 32.5 TPC 19. Dual-Tone FFT with fIN–1 = 44.2 MHz and fIN–2 = 45.6 MHz (AIN1 = AIN2 = –6.5 dBFS) –20 –15 AIN – dBFS –25 –10 –6 TPC 22. Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 44.2 MHz and fIN–2 = 45.6 MHz 0 100 –20 90 –40 80 dBFS AND dBc AMPLITUDE – dBFS SNR = 67.0dBc SFDR = 78.2dBc –60 –80 70 SFDR – dBFS SNR – dBFS SFDR – dBc 60 –100 50 –120 40 –30 SFDR = 90dBc REFERENCE LINE SNR – dBc 0 5 10 15 20 FREQUENCY – MHz 25 30 32.5 TPC 20. Dual-Tone FFT with fIN–1 = 69.2 MHz and fIN–2 = 70.6 MHz (AIN1 = AIN2 = –6.5 dBFS) –20 –15 AIN – dBFS –10 –6 TPC 23. Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 69.2 MHz and fIN–2 = 70.6 MHz 0 100 SNR = 65.0dBc SFDR = 69.1dBc SFDR – dBFS –20 90 –40 80 dBFS AND dBc AMPLITUDE – dBFS –25 –60 –80 SNR – dBFS 70 SFDR – dBc 60 –100 50 –120 40 SFDR = 90dBc REFERENCE LINE SNR – dBc 0 5 10 15 20 FREQUENCY – MHz 25 –30 30 32.5 TPC 21. Dual-Tone FFT with fIN–1 = 139.2 MHz and fIN–2 = 140.7 MHz (AIN1 = AIN2 = –6.5 dBFS) REV. A –25 –20 –15 AIN – dBFS –10 –6 TPC 24. Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 139.2 MHz and fIN–2 = 140.7 MHz –13– AD9244 0 100 –20 90 –40 80 dBFS AND dBc AMPLITUDE – dBFS SNR = 62.6dBc SFDR = 60.7dBc –60 –80 –100 SFDR – dBFS SNR – dBFS 70 SFDR – dBc 60 SFDR = 90dBc REFERENCE LINE 50 SNR – dBc –120 0 5 10 15 20 FREQUENCY – MHz 25 40 –30 30 32.5 –20 –15 AIN – dBFS –25 –10 –6 TPC 28. Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 239.1 MHz and fIN–2 = 240.7 MHz TPC 25. Dual-Tone FFT with fIN–1 = 239.1 MHz and fIN–2 = 240.7 MHz (AIN–1 = AIN2 = –6.5 dBFS) 95 0 SFDR – dBFS SNR = 73.0dBFS THD = –89.5dBFS 90 –20 SFDR – dBc AMPLITUDE – dBFS 85 dBFS AND dBc –40 NOTE: SPUR FLOOR BELOW 90dBFS @ 240MHz –60 –80 80 SNR – dBFS 75 70 SFDR = 90dBc REFERENCE LINE 65 –100 SNR – dBc 60 –120 0 5 10 15 20 FREQUENCY – MHz 25 55 –21 30 32.5 –18 –15 –12 –9 AIN – dBFS –6 –3 0 TPC 29. Driving ADC Inputs with Transformer and Balun SNR/SFDR vs. AIN, fIN = 240 MHz TPC 26. Driving ADC Inputs with Transformer and Balun, fIN = 240 MHz, AIN = –8.5 dBFS 105 95 100 90 95 85 90 80 SFDR – dBc dBFS AND dBc AMPLITUDE – dBFS SFDR – dBFS 85 80 SNR – dBFS 75 70 75 65 70 60 SFDR = 90dBc REFERENCE LINE SNR – dBc 65 0 50 100 150 INPUT FREQUENCY – MHz 200 55 –21 250 –18 –15 –12 –9 AIN – dBFS –6 –3 0 TPC 30. Driving ADC Inputs with Transformer and Balun SNR/SFDR vs. AIN, fIN = 190 MHz TPC 27. CMRR vs. Input Frequency (AIN = 0 dBFS and CML = 2.5 V) –14– REV. A AD9244 THEORY OF OPERATION 2.5V The AD9244 is a high performance, single-supply 14-bit ADC. In addition to high dynamic range Nyquist sampling, it is designed for excellent IF undersampling performance with an analog input as high as 240 MHz. 1.5V AD9244 33⍀ VIN+ 0.1F 20pF 50⍀ The AD9244 uses a calibrated 10-stage pipeline architecture with a patented wideband, input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC along with a switched capacitor DAC and interstage residue amplifier (MDAC). The MDAC amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. 0.1F 2V 2.5V + VREF 10F + REFB 0.1F 10F 1.5V REFT VIN– 33⍀ 0.1F SENSE REFGND Figure 3a. 2 V p-p Differential Input, Common-Mode Voltage = 2 V 3.0V 1.0V The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. While the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and appear at the output as illustrated in Figure 1. This latency is not a concern in many applications. The digital output, together with the OTR indicator, is latched into an output buffer to drive the output pins. The output drivers of the AD9244 can be configured to interface with 5 V or 3.3 V logic families. AD9244 33⍀ 33⍀ VIN+ 20pF 0.1F VIN– REFT 2V + VREF 0.1F 10F 0.1F SENSE + 10F REFB 0.1F REFGND Figure 3b. 2 V p-p Single-Ended Input, Common-Mode Voltage = 2 V The AD9244 has a duty clock stabilizer (DCS) that generates its own internal falling edge to create an internal 50% duty cycle clock, independent of the externally applied duty cycle. Control of straight binary or twos complement output format is accomplished with the DFS pin. 2.5V AD9244 CML 3.0V 0.1F 2.0V The ADC samples the analog input on the rising edge of the clock. While the clock is low, the input SHA is in sample mode. When the clock transitions to a high logic level, the SHA goes into the hold mode. System disturbances just prior to or immediately after the rising edge of the clock and/or excessive clock jitter may cause the SHA to acquire the wrong input value and should be minimized. 33⍀ VIN+ 50⍀ 0.1F 20pF VIN– 33⍀ 0.1F 2V 3.0V 3.0V 2.5V 2.0V 2.0V + REFT + REFB 0.1F 10F 10F VREF 0.1F SENSE ANALOG INPUT AND REFERENCE OVERVIEW REFGND The differential input span of the AD9244 is equal to the potential at the VREF pin. The VREF potential may be obtained from the internal AD9244 reference or an external source. In differential applications, the center point of the input span is the common-mode level of the input signals. In single-ended applications, the center point is the dc potential applied to one input pin while the signal is applied to the opposite input pin. Figures 3a to 3c show various system configurations. Figure 3c. 2 V p-p Differential Input, Common-Mode Voltage = 2.5 V Figure 4 is a simplified model of the AD9244 analog input, showing the relationship between the analog inputs, VIN+, VIN–, and the reference voltage, VREF. Note that this is only a symbolic model and that no actual negative voltages exist inside the AD9244. Similar to the voltages applied to the top and bottom of the resistor ladder in a flash ADC, the value VREF/2 defines the minimum and maximum input voltages to the ADC core. AD9244 VIN+ +VREF/2 + – VIN– ⌺ 14 V CORE ADC CORE –VREF/2 Figure 4. Equivalent Analog Input of AD9244 REV. A –15– AD9244 A differential input structure allows the user to easily configure the inputs for either single-ended or differential operation. The ADC’s input structure allows the dc offset of the input signal to be varied independent of the input span of the converter. Specifically, the input to the ADC core can be defined as the difference of the voltages applied at the VIN+ and VIN– input pins. Therefore, the equation VCORE = VIN + – VIN – (1) defines the output of the differential input stage and provides the input to the ADC core. The voltage, VCORE, must satisfy the condition – VREF/ 2 < VCORE < VREF/ 2 For additional information showing the relationship between VIN+, VIN–, VREF, and the analog input range of the AD9244, see Tables I and II. ANALOG INPUT OPERATION Figure 5 shows the equivalent analog input of the AD9244, which consists of a 750 MHz differential SHA. The differential input structure of the SHA is flexible, allowing the device to be configured for either a differential or single-ended input. The analog inputs VIN+ and VIN– are interchangeable, with the exception that reversing the inputs to the VIN+ and VIN– pins results in a data inversion (complementing the output word). (2) S where VREF is the voltage at the VREF pin. CH In addition to the limitations placed on the input voltages VIN+ and VIN– by Equations 1 and 2, boundaries on the inputs also exist based on the power supply voltages according to the conditions S CS VIN+ CPIN, PAR AGND – 0.3 V < VIN + < AVDD + 0.3 V S VIN– CPIN, PAR – H + CS CH (3) AGND – 0.3 V < VIN – < AVDD + 0.3 V S where AGND is nominally 0 V and AVDD is nominally 5 V. The range of valid inputs for VIN+ and VIN– is any combination that satisfies both Equations 2 and 3. Figure 5. Analog Input of AD9244 SHA Table I. Analog Input Configuration Summary Input Connection Input Range (V) Input Coupling Span (V) VIN+* VIN–* Input CM Voltage Comments Single-Ended DC or AC 1.0 2.0 Differential DC or AC 1.0 2.0 0.5 to 1.5 1.0 1.0 Best for stepped input response applications. 1 to 3 2.0 2.0 Optimum noise performance for single-ended mode, often requires low distortion op amp with VCC > 5 V due to its headroom issues. 2.25 to 2.75 2.75 to 2.25 2.5 Optimum full-scale THD and SFDR performance well beyond the ADC’s Nyquist frequency. 2.0 to 3.0 Optimum noise performance for differential mode Preferred mode for applications. 3.0 to 2.0 2.5 *VIN+ and VIN– can be interchanged if data inversion is required. Table II. Reference Configuration Summary Reference Operating Mode Internal Internal Internal External Connect To Resulting VREF (V) Input Span (VIN+ – VIN–) (V p-p) SENSE SENSE R1 R2 SENSE VREF VREF AGND VREF and SENSE 1 2 1 ⱕ VREF ⱕ 2.0 VREF = (1 + R1/R2) 1 ⱕ VREF ⱕ 2.0 1 2 1 ⱕ SPAN ⱕ 2 (SPAN = VREF) SPAN = EXTERNAL REF SENSE and REFGND AVDD EXTERNAL REF –16– REV. A AD9244 The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 2 V input span) and matched input impedance for VIN+ and VIN–. Only a slight degradation in dc linearity performance exists between the 2 V and 1 V input spans; however, the SNR is lower in the 1 V input span. When the ADC is driven by an op amp and a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recovers, ringing may occur. To remedy the situation, a series resistor, RS, can be inserted between the op amp and the SHA input as shown in Figure 6. A shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the sampling capacitor, CS, further reducing current transients seen at the op amp’s output. VCC RS 33⍀ AD9244 VIN+ RS 33⍀ VEE + 20pF VIN– Since not all applications have a signal precondition for differential operation, there is often a need to perform a single-ended-todifferential conversion. In systems that do not require dc coupling, an RF transformer with a center tap is the best method for generating differential input signals for the AD9244. This provides the benefit of operating the ADC in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC. The differential input characterization for this data sheet was performed using the configuration in Figure 7. The circuit uses a Mini-Circuits® RF transformer, model T1–1T, which has an impedance ratio of 1:1. This circuit assumes that the signal source has a 50 Ω source impedance. The secondary center tap of the transformer allows a dc common-mode voltage to be added to the differential input signal. In Figure 7, the center tap is connected to a resistor divider providing a half supply voltage. It could also be connected to the CML pin of the AD9244. It is recommended for IF sampling applications (70 MHz < fIN < 200 MHz) that the 20 pF differential capacitor between VIN+ and VIN– be reduced or removed. VREF 10F AVDD RS 33⍀ 0.1F SENSE 1k⍀ 0.1F VIN+ REFCOM REFT 50⍀ 0.1F 1k⍀ 20pF AD9244 Figure 6. Resistors Isolating SHA Input from Op Amp 10F + REFB VIN– The optimum size of this resistor is dependent on several factors, including the ADC sampling rate, the selected op amp, and the particular application. In most applications, a 30 Ω to 100 Ω resistor is sufficient. 0.1F RS 33⍀ MINI-CIRCUITS T1–1T Figure 7. Transformer-Coupled Input For noise sensitive applications, the very high bandwidth of the AD9244 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the ADC’s input by forming a low-pass filter. The source impedance driving VIN+ and VIN– should be matched. Failure to provide matching may result in degradation of the SNR, THD, and SFDR performance. The circuit shown in Figure 8 shows a method for applying a differential direct-coupled signal to the AD9244. An AD8138 amplifier is used to derive a differential signal from a singleended signal. 10F + 10F + 0.1F 1k⍀ The AD9244 has a very flexible input structure, allowing it to interface with single-ended or differential inputs. 5V 0.1F Differentially Driving the Analog Inputs 0V 0.1F 1k⍀ 1V p-p 499⍀ AVDD 33⍀ REFT 20pF AD8138 50⍀ 0.1F VIN+ 475⍀ The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular application’s performance requirements as well as power supply options. AD9244 0.1F + 10F REFB 499⍀ 0.1F VIN– 499⍀ Differential operation requires that VIN+ and VIN– be simultaneously driven with two equal signals that are 180° out of phase with each other. Differential modes of operation (ac-coupled or dc-coupled input) provide the best SFDR performance over a wide frequency range. They should be considered for the most demanding spectral-based applications (i.e., direct IF conversion to digital). REV. A 0.1F –17– 33⍀ Figure 8. Direct-Coupled Drive Circuit with AD8138 Differential Op Amp AD9244 REFERENCE OPERATION Pin Programmable Reference The AD9244 contains a band gap reference that provides a pinstrappable option to generate either a 1 V or 2 V output. With the addition of two external resistors, the user can generate reference voltages between 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance as described later in this section. Figure 9a shows a simplified model of the internal voltage reference of the AD9244. A reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. As stated earlier, the voltage on the VREF pin determines the full-scale differential input span of the ADC. By shorting the VREF pin directly to the SENSE pin, the internal reference amplifier is placed in a unity gain mode and the resulting VREF output is 1 V. By shorting the SENSE pin directly to the REFGND pin, the internal reference amplifier is configured for a gain of 2.0 and the resulting VREF output is 2.0 V. Figure 10 shows an example of how to generate a reference voltage other than 1.0 V or 2.0 V with the addition of two external resistors. Use the equation VREF = 1 V × (1 + R1/R 2) to determine the appropriate values for R1 and R2. These resistors should be in the 2 kΩ to 10 kΩ range. For the example shown, R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above, the resulting reference voltage on the VREF pin is 1.5 V. This sets the differential input span to 1.5 V p-p. The midscale voltage can also be set to VREF by connecting VIN– to VREF. AD9244 TO ADC REFT 2.5V Resistor Programmable Reference A2 REFB 3.25V VIN+ 1.75V VREF 20pF 2.5V 1.5V R 10F SENSE DISABLE A1 LOGIC 0.1F R1 2.5k⍀ REFT VREF 0.1F SENSE R2 5k⍀ R 0.1F VIN– 33⍀ A1 1V AD9244 33⍀ 10F REFB 0.1F REFGND REFGND Figure 10. Resistor Programmable Reference (1.5 V p-p Input Span, Differential Input with VCM = 2.5 V) Figure 9a. Equivalent Reference Circuit Using an External Reference The voltage appearing at the VREF pin and the state of the internal reference amplifier, A1, are determined by the voltage present at the SENSE pin. The logic circuitry contains comparators that monitor the voltage at the SENSE pin. The various reference modes are summarized in Table II and are described in the next few sections. The actual reference voltages used by the internal circuitry of the AD9244 appear on the REFT and REFB pins. The voltages on these pins are symmetrical about midsupply or CML. For proper operation, it is necessary to add a capacitor network to decouple these pins. Figure 9b shows the recommended decoupling network. The turn-on time of the reference voltage appearing between REFT and REFB is approximately 10 ms and should be taken into consideration in any power-down mode of operation. The VREF pin should be bypassed to the REFGND pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor. 0.1F VREF + 10F 0.1F REFT AD9244 0.1F* + To use an external reference, the internal reference must be disabled by connecting the SENSE pin to AVDD. The AD9244 contains an internal reference buffer, A2 (see Figure 9a), that simplifies the drive requirements of an external reference. The external reference must be able to drive a 5 kΩ (± 20%) load. The bandwidth of the reference is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to drive VREF externally with high frequencies. Figure 11 shows an example of an external reference driving both VIN– and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. Both the input span and the center of the input span are equal to the external VREF. Thus the valid input range extends from (VREF + VREF/2) to (VREF – VREF/2). For example, if the precision reference part, REF191, a 2.048 V external reference, is used, the input span is 2.048 V. In this case, 1 LSB of the AD9244 corresponds to 0.125 mV. It is essential that a minimum of a 10 µF capacitor, in parallel with a 0.1 µF low inductance ceramic capacitor, decouple the reference output to AGND. 10F REFGND REFB VREF + VREF/2 0.1F 33⍀ VREF – VREF/2 20pF *LOCATE AS CLOSE AS POSSIBLE TO REFT/REFB PINS 5V 0.1F Figure 9b. Reference Decoupling AD9244 VIN+ VREF 10F 33⍀ 0.1F REFT VIN– 0.1F VREF 0.1F 10F + REFB 0.1F AVDD SENSE Figure 11. Using an External Reference –18– REV. A AD9244 Table III. Output Data Format Input (V) Condition (V) VIN+ – VIN– VIN+ – VIN– VIN+ – VIN– VIN+ – VIN– VIN+ – VIN– < –VREF – 0.5 LSB = –VREF =0 = +VREF – 1.0 LSB > +VREF – 0.5 LSB Binary Output Mode Twos Complement Mode OTR 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 1 0 0 0 1 DIGITAL INPUTS AND OUTPUTS Digital Outputs OTR DATA OUTPUTS 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 Table III details the relationship among the ADC input, OTR, and digital output format. +FS – 1 LSB OTR –FS + 1/2 LSB Data Format Select (DFS) 0 0 1 The AD9244 may be programmed for straight binary or twos complement data on the digital outputs. Connect the DFS pin to AGND for straight binary and to AVDD for twos complement. 0000 0000 0001 0000 0000 0000 0000 0000 0000 –FS +FS +FS – 1/2 LSB –FS – 1/2 LSB Digital Output Driver Considerations Figure 12. OTR Relation to Input Voltage and Output Data The AD9244 output drivers can be configured to interface with 5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V, respectively. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. Table IV. Output Data Format Out-of-Range (OTR) An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OTR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OTR has the same pipeline latency as the digital data. OTR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in Figure 12. OTR will remain high until the analog input returns to within the input range and another conversion is completed. By logically AND-ing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table IV is a truth table for the overrange/underrange range circuit in Figure 13, which uses NAND gates. Systems requiring programmable gain conditioning of the AD9244 can, after eight clock cycles, detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration. REV. A OTR MSB Analog Input Is 0 0 1 1 0 1 0 1 Within Range Within Range Underrange Overrange MSB OVER = 1 OTR MSB UNDER = 1 Figure 13. Overrange/Underrange Logic Digital Output Enable Function (OEB) The AD9244 has three-state ability. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. It is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage. –19– AD9244 CLOCK OVERVIEW Clock Input Considerations The AD9244 has a flexible clock interface that accepts either a single-ended or differential clock. An internal bias voltage facilitates ac coupling using two external capacitors. To remain backward compatible with the single-pin clock scheme of the AD9226, the AD9244 can be operated with a dc-coupled, single-pin clock by grounding the CLK– pin and driving CLK+. The analog input is sampled on the rising edge of the clock. Timing variations, or jitter, on this edge causes the sampled input voltage to be in error by an amount proportional to the slew rate of the input signal and to the amount of the timing variation. Thus, to maintain the excellent high frequency SFDR and SNR characteristics of the AD9244, it is essential that the clock edge be kept as clean as possible. When the CLK– pin is not grounded, the CLK+ and CLK– pins function as a differential clock receiver. When CLK+ is greater than CLK–, the SHA is in hold mode; when CLK+ is less than CLK–, the SHA is in track mode (see timing in Figure 14). The rising edge of the clock (CLK+ – CLK–) switches the SHA from track to hold and timing jitter on this transition should be minimized, especially for high frequency analog inputs. It is often difficult to maintain a 50% duty cycle to the ADC, especially when driving the clock with a single-ended or sine wave input. To ease the constraint of providing an accurate 50% clock, the ADC has an optional internal duty cycle stabilizer (DCS) that allows the rising clock edge to pass through with minimal jitter and interpolates the falling edge, independent of the input clock falling edge. The DCS is described in greater detail in a later section. The clock should be treated like an analog signal. Clock drivers should not share supplies with digital logic or noisy circuits. The clock traces should not run parallel to noisy traces. Using a pair of symmetrically routed, differential clock signals can help to provide immunity from common-mode noise coupled from the environment. The clock receiver functions like a differential comparator. At the CLK inputs, a slowly changing clock signal will result in more jitter than a rapidly changing one. Driving the clock with a low amplitude sine wave input is not recommended. Running a high speed clock through a divider circuit will provide a fast rise/fall time, resulting in the lowest jitter in most systems. Clock Input Modes Figures 15a to 15e illustrate the modes of operation of the clock receiver. Figure 15a shows a differential clock directly coupled to CLK+ and CLK–. In this mode, the common mode of the CLK+ and CLK– signals should be close to 1.6 V. Figure 15b illustrates a single-ended clock input. The capacitor decouples the internal bias voltage on the CLK– pin (about 1.6 V), establishing a threshold for the CLK+ pin. Figure 15c provides backward compatibility with the AD9226. In this mode, CLK– is grounded and the threshold for CLK+ is 1.5 V. Figure 15d shows a differential clock ac-coupled by connecting through two capacitors. AC coupling a single-ended clock can also be accomplished using the circuit in Figure 15e. When using the differential clock circuits of Figure 15a or Figure 15d, if CLK– drops below 250 mV, the mode of the clock receiver may change, causing conversion errors. It is essential that CLK– remain above 250 mV when the clock is ac-coupled or dc-coupled. CLK+ AD9244 CLK– Figure 15a. Differential Clock Input—DC-Coupled CLK+ AD9244 1.6V CLK– 0.1F AGND CLK– Figure 15b. Single-Ended Clock Input—DC-Coupled CLK+ SHA IN HOLD SHA IN TRACK CLK+ AD9244 CLK– CLK– CLK+ AGND Figure 14. SHA Timing Figure 15c. Single-Ended Input—Retains Pin Compatibility with AD9226 –20– REV. A AD9244 speed. When the stabilizer is disabled, the internal switching will be directly affected by the clock state. If CLK+ is high, the SHA will be in hold mode; if CLK+ is low, the SHA will be in track mode. TPC 16 shows the benefits of using the clock stabilizer. Connecting the DCS pin to AVDD implements the internal clock stabilization function in the AD9244. If the DCS pin is connected to ground, the AD9244 will use both edges of the external clock in its internal timing circuitry (see Specifications for timing requirements). CLK+ AD9244 CLK– 100pF – 0.1F Figure 15d. Differential Clock Input—AC-Coupled 0.1F GROUNDING AND DECOUPLING Analog and Digital Grounding Proper grounding is essential in high speed, high resolution systems. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power distribution. The use of power and ground planes offers distinct advantages, including: CLK+ AD9244 1.6 V CLK– • The minimization of the loop area encompassed by a signal and its return path. • The minimization of the impedance associated with ground and power paths. • The inherent distributed capacitor formed by the power plane, PCB material, and ground plane. 0.1F AGND Figure 15e. Single-Ended Clock Input—AC-Coupled Clock Power Dissipation Most of the power dissipated by the AD9244 is from the analog power supplies. However, lower clock speeds will reduce digital supply current. Figure 16 shows the relationship between power and clock rate. 600 550 AD9244-65 500 It is important to design a layout that minimizes noise from coupling onto the input signal. Digital input signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9244 features separate analog and digital ground pins, it should be treated as an analog component. The AGND and DGND pins must be joined together directly under the AD9244. A solid ground plane under the ADC is acceptable if the power and ground return currents are carefully managed. POWER – mW Analog Supply Decoupling 450 The AD9244 features separate analog and digital supply and ground circuits, helping to minimize digital corruption of sensitive analog signals. In general, AVDD (analog power) should be decoupled to AGND (analog ground). The AVDD and AGND pins are adjacent to one another. Figure 17 shows the recommended decoupling for each pair of analog supplies; 0.1 µF ceramic chip and 10 µF tantalum capacitors should provide adequately low impedance over a wide frequency range. The decoupling capacitors (especially 0.1 µF) should be located as close to the pins as possible. 400 350 AD9244-40 300 250 200 0 10 20 30 40 50 SAMPLE RATE – MHz 60 70 Figure 16. Power Consumption vs. Sample Rate 10F + AVDD 0.1F* Clock Stabilizer (DCS) The clock stabilizer circuit in the AD9244 desensitizes the ADC from clock duty cycle variations. System clock constraints are eased by internally restoring the clock duty cycle to 50%, independent of the clock input duty cycle. Low jitter on the rising edge (sampling edge) of the clock is preserved while the falling edge is generated on-chip. It may be desirable to disable the clock stabilizer and may be necessary when the clock frequency is varied or completely stopped. Note that stopping the clock is not recommended with ac-coupled clocks. Once the clock frequency is changed, over 100 clock cycles may be required for the clock stabilizer to settle to the new REV. A AD9244 AGND *LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS Figure 17. Analog Supply Decoupling Digital Supply Decoupling The digital activity on the AD9244 falls into two categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses when the output bits change state. The size and duration of these currents are a function of the load on the output bits; large capacitive loads should be avoided. –21– AD9244 For the digital decoupling shown in Figure 18, 0.1 µF ceramic chip and 10 µF tantalum capacitors are appropriate. The decoupling capacitors (especially 0.1 µF) should be located as close to the pins as possible. Reasonable capacitive loads on the data pins are less than 20 pF per bit. Applications involving greater digital loads should consider increasing the digital decoupling and/or using external buffers/latches. A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the power supply connector to reduce low frequency ripple to insignificant levels. 10F + DRVDD 0.1F* AD9244 DGND *LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS Figure 18. Digital Supply Decoupling from single-ended signals to differential. Optimal AD9244 performance is achieved above 500 kHz by using the input transformer. To drive the AD9244 via the transformer, connect solderable Jumpers JP45 and JP46. DC bias is provided by the Resistors R8 and R28. The evaluation board has positions for through-hole and surfacemount transformers. For applications requiring lower frequencies or dc applications, the AD8138 can be used. The AD8138 will provide good distortion and noise performance, as well as input buffering, up to 30 MHz. For more information, refer to the AD8138 data sheet. To use the AD8138 to drive the AD9244, remove the transformer (T1 or T4) and connect solderable Jumpers JP42 and JP43. The AD9244 can be driven single-ended directly via S3 and can be ac-coupled or dc-coupled by removing or inserting JP5. To run the evaluation board in this way, remove the transformer (T1 or T4) and connect solderable Jumpers JP40 and JP41. The Resistors R40, R41, R8, and R28 are used to bias the AD9244 inputs to the correct common-mode levels in this application. CML Reference Configuration The AD9244 has a midsupply reference point. This is used within the internal architecture of the AD9244 and must be decoupled with a 0.1 µF capacitor. It will source or sink a load of up to 300 µA. If more current is required, the CML pin should be buffered with an amplifier. As described in the Analog Input and Reference Overview section earlier in this data sheet, the AD9244 can be configured to use its own internal or an external reference. An external reference, D3, and reference buffer, U5, are included on the AD9244 evaluation board. Jumpers JP8 and JP22–JP24 can be used to select the desired reference configuration (Table VI). VR VR is an internal bias point on the AD9244. It must be decoupled to AGND with a 0.1 µF capacitor. CML 0.1F AD9244 Clock Configuration VR 0.1F Figure 19. CML/VR Decoupling EVALUATION BOARD Analog Input Configuration Table V provides a summary of the analog input configuration. The analog inputs of the AD9244 on the evaluation board can be driven differentially through a transformer via Connector S4, or the AD8138 amplifier via Connector S2, or driven single-ended directly via Connector S3. When using the transformer or AD8138 amplifier, a single-ended source may be used as both of these devices are configured on the AD9244 evaluation board to convert The AD9244 evaluation board was designed to achieve optimal performance as well as to be easily configurable by the user. To configure the clock input, begin by connecting the correct combination of solderable Jumpers JP11–JP15 (Table VII). The specific jumper configuration is dependent on the application and can be determined by referring to the clock input modes section. If the differential clock input mode is selected, an external sine wave generator applied to S5 can be used as the clock source. The clock buffer/drive MC10EL16 from ON Semiconductor is used on the evaluation board to buffer and square the clock input. If the single-ended clock configuration is used, an external clock source can be applied to S1. The AD9244 evaluation board generates a buffered clock at TTL/CMOS levels for use with a data capture system, such as the HSC-ADC-EVAL-SC system. The clock buffering is provided by U4 and U7 and is configured by Jumpers JP3, JP4, JP9, and JP18 (Table VII). –22– REV. A AD9244 Table V. Analog Input Jumper Configuration Differential: Transformer Differential: Amplifier Single-Ended Input Connector Jumpers Notes S4 S2 S3 45, 46 42, 43 5, 40, 41 R8, R28 Provide DC Bias. Optimal for 500 kHz+. Remove T1 or T4. Used for low input frequencies. Remove T1 or T4. JP5: connected for dc-coupled, not connected for ac-coupling. Table VI. Reference Jumper Configuration Reference Voltage Jumpers Notes Internal Internal Internal External 2V 1V 1 V ≤ VREF ≤ 2 V 1 V ≤ VREF ≤ 2 V 23 24 25 8, 22 JP8 Not Connected. JP8 Not Connected. JP8 Not Connected. VREF = 1 + R1/R2. Set VREF with R26. Table VII. Clock Jumper Configuration Input Connector Jumpers DUT Clock Differential Single-Ended S5 S1 11, 13 12, 15 Data Capture Clock Internal Diff DUT Clock SE DUT Clock External NA NA S6 9, 18A 9, 18B 3 or 4 5V + AVDD REFIN SIGNAL SYNTHESIZER 2.5MHz, 0.8V p-p HP8644 2.5MHz BAND-PASS FILTER S4 INPUT xFMR 5V – – 3V + – 3V + GND DUT GND DUT AVDD DVDD AD9244 EVALUATION BOARD 10MHz REFOUT CLK SYNTHESIZER 65MHz, 1V p-p HP8644 CLOCK DIVIDER S1/S5 INPUT CLOCK Figure 20. Evaluation Board Connections REV. A –23– – + DVDD OUTPUT BUSS J1 DSP EQUIPMENT C27 10F 10V C28 0.1F –IN 7 D3 AVDD U5 AD822 OUT AGND; 4 AVDD; 8 –24– DVDDIN TB1 6 AGND TB1 4 DRVDDIN TB1 5 AVDDIN TB1 1 AGND TB1 3 DUTAVDDIN TB1 2 6 +IN C6 22F 25V C48 22F 25V C47 22F 25V L2 L3 L4 C14 0.1F FBEAD C53 0.1F FBEAD C52 0.1F FBEAD C59 0.1F L1 C29 0.1F FBEAD R26 2k⍀ C58 22F 25V 2 1 R16 2.55k⍀ AVDD CW 5 DUTAVDD RED DVDD RED DIFFA SECLK C21 10F 10V C30 0.1F DIFFB SHEET2 R4 DNP R3 DNP TP5 WHT JP8 TP11 TP12 TP13 TP14 BLK BLK BLK BLK TP4 DUTDRVDD RED AVDD RED TP3 TP1 TP2 1 U5 AD822 OUT AGND; 4 AVDD; 8 R20 2k⍀ –IN +IN R17 2k⍀ 2 3 JP15 JP13 JP14 JP11 JP12 C23 10F 10V C22 10F 10V C50 0.1F C36 0.1F VIN+ SHEET3 VIN– C39 0.001F DUTDRVDD C1 10F 10V C41 0.001F DUTAVDD C42 0.001F C33 0.1F JP22 C38 0.1F C32 0.1F C20 0.1F 10V DUTAVDD C34 0.1F C35 0.1F JP24 JP25 JP23 DRVDD DRVDD DGND C45 0.001F 28 27 26 25 24 21 20 19 18 17 16 13 12 11 10 8 9 48 35 43 5 44 NIC 15 DRVDD 14 DGND AVDD OTR AVDD MSB-D13 AGND D12 AGND D11 SENSE D10 VREF D9 REFGND D8 REFB D7 REFB D6 REFT D5 REFT D4 CML D3 VIN+ D2 VIN– D1 CLK+ LSB-D0 CLK– NIC AGND OEB AGND VR AVDD DFS AVDD DCS DGND AGND C37 0.1F 3 4 1 2 36 37 38 39 40 41 42 45 46 47 7 6 32 33 31 34 30 29 23 22 U1 AD9226/AD9244 C40 0.001F OTRO D13O D12O D11O D10O D9O D8O D7O D6O D5O D4O D3O D2O D1O D0O C56 + 10F 10V R10 1k⍀ R6 1k⍀ R42 1k⍀ JP2 JP1 JP6 C2 0.1F AVDD C57 0.1F AD9244 Figure 21. AD9244 Evaluation Board, ADC, External Reference, and Power Supply Circuitry REV. A REV. A –25– 3 B R29 49.9⍀ JP18 2 A 2 C31 0.1F 74VHC04 U4 S6 DATACLK 1 R15 90⍀ R18 4k⍀ VCC Q Q VEE R30 10k⍀ RESET CLK CLK VBB U4 4 JP3 JP4 74VHC04 R27 2k⍀ CW AVDD 74VHC04 74VHC04 U4 13 12 3 C26 10F 10V C60 0.01F R38 10k⍀ AVDD JP9 R9 22⍀ R7 22⍀ U3 DECOUPLING AVDD; 14 AGND; 7 U4 5 6 AVDD 4 3 2 1 C18 0.1F AVDD C19 0.1F R39 49.9⍀ R44 CW 100⍀ R45 10k⍀ U3 MC10EL16 R43 100⍀ AVDD 5 6 7 8 R13 113⍀ AVDD CW R2 5k⍀ WHT TP7 R19 4k⍀ C17 0.1F R25 33⍀ R23 33⍀ C61 0.1F D0O C3 10F 10V RP6 4 22⍀ 5 RP6 3 22⍀ 6 RP6 2 22⍀ 7 RP6 1 22⍀ 8 RP5 4 22⍀ 5 RP5 3 22⍀ 6 RP5 2 22⍀ 7 RP5 1 22⍀ 8 RP4 4 22⍀ 5 RP4 3 22⍀ 6 RP4 2 22⍀ 7 RP4 1 22⍀ 8 RP3 4 22⍀ 5 RP3 3 22⍀ 6 RP3 2 22⍀ 7 U4 DECOUPLING C10 0.1F AVDD SECLK D1O D2O D3O D4O D5O D6O D7O D8O D9O D10O D11O D12O D13O OTRO RP3 1 22⍀ 8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 9 U4 OTR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 8 9 8 7 6 5 4 3 2 19 1 9 8 7 6 5 4 3 2 19 1 A8 A7 A6 A5 A4 Y3 A2 G2 A1 G1 74VHC04 10 11 12 13 14 15 16 10 Y8 Y7 Y6 Y5 Y4 Y3 Y2 11 12 13 14 15 16 17 GND 18 Y1 VCC 20 C5 C11 0.1F 10F 10V + Y8 Y7 Y6 Y5 Y4 Y3 Y2 17 GND 18 Y1 U7 74VHC541 A8 A7 A6 A5 A4 Y3 A2 G2 A1 VCC 20 C4 C12 0.1F 10F 10V + U6 74VHC541 G1 74VHC04 U4 11 10 D10 D11 D12 D13 OTR 16 16 9 OTR CLK 9 8 RP2 22⍀ MSB 7 RP2 22⍀ 10 6 RP2 22⍀ 11 5 RP2 22⍀ 12 4 RP2 22⍀ 13 3 RP2 22⍀ 14 2 RP2 22⍀ 15 1 RP2 22⍀ 8 RP1 22⍀ 7 RP1 22⍀ 10 6 RP1 22⍀ 11 5 RP1 22⍀ 12 4 RP1 22⍀ 13 3 RP1 22⍀ 14 2 RP1 22⍀ 15 1 RP1 22⍀ DVDD 2 9 7 5 3 1 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 SAM040RAM J1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 HEADER RIGHT ANGLE MALE NO EJECTORS R1 49.9⍀ 1 R14 90⍀ C13 0.1F C49 0.1F R12 113⍀ SECLK S1 AVDD DIFFB C46 0.1F R11 49.9⍀ DIFFA DIFFCLK S5 AD9244 Figure 22. AD9244 Evaluation Board, Clock Input, and Digital Output Buffer Circuitry AD9244 AVDD JP5 C7 0.1F R40 1k⍀ SINGLE INPUT S3 C9 R5 49.9⍀ 0.33F JP42 JP40 C15 10F 10V AVDD R41 1k⍀ AVDD VIN+ R32 10k⍀ 3 1 AMP INPUT R34 523⍀ 8 S2 R31 49.9⍀ R35 499⍀ +IN C43 DNP R46 33⍀ 4 VOCM OUT– V– JP41 JP43 OUT+ U2 AD8138 SHEET 1 VIN– C8 0.1F R37 499⍀ V+ –IN R33 10k⍀ C24 20pF R22 33⍀ JP45 C69 0.1F C44 DNP R21 33⍀ JP45 2 R47 33⍀ 5 6 ADT4-6T 1 R36 499⍀ P T4 S 6 5 3 AVDD 4 NC= 2 XFMRINPUT CW S4 T1-1TX65 5 R24 49.9⍀ P 1 S NC = 5 4 2 R28 2k⍀ 3 T1 R8 500⍀ C25 0.33F C16 0.1F Figure 23. AD9244 Evaluation Board, Analog Input Circuitry –26– REV. A AD9244 Figure 24. AD9244 Evaluation Board, PCB Assembly, Top REV. A –27– AD9244 Figure 25. AD9244 Evaluation Board, PCB Assembly, Bottom –28– REV. A AD9244 Figure 26. AD9244 Evaluation Board, PCB Layer 1 (Top) REV. A –29– AD9244 Figure 27. AD9244 Evaluation Board, PCB Layer 2 (Ground Plane) –30– REV. A AD9244 Figure 28. AD9244 Evaluation Board, PCB Layer 3 (Power Plane) REV. A –31– AD9244 Figure 29. AD9244 Evaluation Board, PCB Layer 4 (Bottom) –32– REV. A AD9244 OUTLINE DIMENSIONS 8-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 1.45 1.40 1.35 0.15 0.05 10ⴗ 6ⴗ 2ⴗ SEATING PLANE PIN 1 SEATING PLANE 7ⴗ 3.5ⴗ 0ⴗ 0.08 MAX COPLANARITY (PINS DOWN) VIEW A 25 12 13 0.50 BSC VIEW A ROTATED 90ⴗ CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC REV. A 7.00 BSC SQ TOP VIEW 0.20 0.09 –33– 24 0.27 0.22 0.17 AD9244 Revision History Location Page 6/03—Data Sheet changed from REV. 0 to REV. A Changes to AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 –34– REV. A –35– –36– C02404–0–6/03(A)