14-Bit, 80 MSPS, 3 V A/D Converter AD9245 FUNCTIONAL BLOCK DIAGRAM FEATURES Single 3 V supply operation (2.7 V to 3.6 V) SNR = 72.7 dBc to Nyquist SFDR = 87.6 dBc to Nyquist Low power: 366 mW Differential input with 500 MHz bandwidth On-chip reference and sample-and-hold DNL = ± 0.5 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer AVDD DRVDD AD9245 VIN+ VIN– MDAC1 SHA 8-STAGE 1 1/2-BIT PIPELINE 4 A/D 16 3 A/D REFT REFB CORRECTION LOGIC OTR 14 OUTPUT BUFFERS D13 (MSB) VREF D0 (LSB) APPLICATIONS High end medical imaging equipment IF sampling in communications receivers: WCDMA, CDMA-One, CDMA-2000, TDS-CDMA Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes Power sensitive military applications GENERAL DESCRIPTION The AD9245 is a monolithic, single 3 V supply, 14-bit, 80 MSPS analog-to-digital converter featuring a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and common modes, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels, and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9245 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining SENSE 0.5V REF SELECT AGND CLOCK DUTY CYCLE STABILIZER CLK MODE SELECT PDWN MODE DGND 03583-B-001 Figure 1. Functional Block Diagram excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9245 is available in a 32-lead LFCSP and is specified over the industrial temperature range (–40°C to +85°C). PRODUCT HIGHLIGHTS 1. The AD9245 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. Operating at 80 MSPS, the AD9245 consumes a low 366 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz, and can be configured for single-ended or differential operation. 4. The AD9245 is pin compatible with the AD9215, AD9235, and AD9236. This allows a simplified migration from 10 bits to 14 bits and 20 MSPS to 80 MSPS. 5. The clock DCS maintains overall ADC performance over a wide range of clock pulsewidths. 6. The OTR output bit indicates when the signal is beyond the selected input range. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD9245 TABLE OF CONTENTS AD9245–DC Specifications ............................................................ 3 Analog Input and Reference Overview ................................... 14 AD9245–AC Specifications............................................................. 4 Clock Input Considerations...................................................... 15 AD9245–Digital Specifications....................................................... 5 Jitter Considerations .................................................................. 16 AD9245–Switching Specifications ................................................. 6 Power Dissipation and Standby Mode .................................... 16 Explanation of Test Levels........................................................... 6 Digital Outputs ........................................................................... 16 Absolute Maximum Ratings............................................................ 7 Timing ......................................................................................... 17 Thermal Resistance ...................................................................... 7 Voltage Reference ....................................................................... 17 ESD Caution.................................................................................. 7 Internal Reference Connection ................................................ 17 Definitions of Specifications ........................................................... 8 External Reference Operation .................................................. 18 Pin Configuration and Functional Descriptions.......................... 9 Operational Mode Selection ..................................................... 18 Equivalent Circuits ......................................................................... 10 Evaluation Board ........................................................................ 18 Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 25 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 25 REVISION HISTORY Revision B 10/03—Data Sheet Changed from REV. A to REV. B Changes to Figure 33 ..................................................................... 17 5/03—Data Sheet Changed from REV. 0 to REV. A Changes to Figure 30 .................................................................... 15 Changes to Figure 37 ..................................................................... 19 Changes to Figure 38..................................................................... 20 Changes to Figure 39...................................................................... 21 Changes to Table 10 ....................................................................... 24 Changes to the ORDERING GUIDE........................................... 25 Rev. B | Page 2 of 28 AD9245 AD9245–DC SPECIFICATIONS Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless otherwise noted AD9245BCP Typ Parameter Temp Test Level RESOLUTION ACCURACY No Missing Codes Offset Error1 Gain Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error1 Gain Error Gain Error1 INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION Low Frequency Input4 Standby Power5 Full VI Full Full 25°C Full Full Full VI VI V VI VI VI Guaranteed ±0.30 ±0.28 ±0.70 ±0.5 ±1.4 Full Full Full V V V ±10 ±12 ±17 Full 25°C 25°C 25°C VI V V V ±3 ±2 ±6 ±1 25°C 25°C V V 1.86 1.17 LSB rms LSB rms Full Full Full Full IV IV V V 1 2 7 7 V p-p V p-p pF kΩ Full Full IV IV Full 25°C 25°C 25°C 25°C Min 14 Unit Bits ±1.2 ±4.16 ±1.0 ±5.15 % FSR % FSR % FSR LSB LSB ppm/°C ppm/°C ppm/°C ±34 mV mV mV mV 3.0 2.5 3.6 3.6 V V VI V V 122 9 ±0.01 138 mA mA % FSR V V 366 1.0 1 2.7 2.25 Max mW mW With a 1.0 V internal reference. Measured at the maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 4 Measured at AC Specification conditions without output drivers. 5 Standby power is measured with a dc input, CLK pin inactive (i.e., set to AVDD or AGND). 2 Rev. B | Page 3 of 28 AD9245 AD9245–AC SPECIFICATIONS Table 2. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, AIN = –0.5 dBFS, DCS Off, unless otherwise noted Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz WORST SECOND OR THIRD fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz Temp Test Level Min Full 25°C 25°C Full 25°C 25°C VI V V IV V V 71.1 Full 25°C 25°C Full 25°C 25°C VI V V IV V V Full 25°C 25°C Full 25°C 25°C VI V V IV V V Full 25°C 25°C Full 25°C 25°C VI V V IV V V Full 25°C 25°C Full 25°C 25°C VI V V IV V V Rev. B | Page 4 of 28 AD9245BCP Typ Max dB dB dB dB dB dB 73.3 72.7 70.5 71.7 70.2 70.7 dB dB dB dB dB dB 73.2 72.5 69.9 71.2 69.6 11.5 Bits Bits Bits Bits Bits Bits 11.9 11.8 11.3 11.5 11.3 –76.5 –92.8 –87.6 –75.7 –81.6 –79.0 76.5 92.8 87.6 75.7 81.6 79.0 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9245 AD9245–DIGITAL SPECIFICATIONS Table 3. AVDD = 3 V, DRVDD = 2.5 V, 1.0 V External Reference, unless otherwise noted Parameter LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUT BITS (D0–D13, OTR)1 DRVDD = 3.3 V High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 µA) DRVDD = 2.5 V High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 µA) 1 Temp Test Level Min Full Full Full Full Full IV IV IV IV V 2.0 Full Full Full Full IV IV IV IV 3.29 3.25 Full Full Full Full IV IV IV IV 2.49 2.45 Output voltage levels measured with 5 pF load on each output. Rev. B | Page 5 of 28 AD9245BCP Typ Max 0.8 +10 +10 –10 –10 2 Unit V V µA µA pF 0.2 0.05 V V V V 0.2 0.05 V V V V AD9245 AD9245–SWITCHING SPECIFICATIONS Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulsewidth High1 CLK Pulsewidth Low1 DATA OUTPUT PARAMETERS Output Propagation Delay (tPD)2 Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME 1 2 3 Temp Test Level Min Full Full Full Full Full VI V V V V 80 Full Full Full Full Full Full V V V V V V AD9245BCP Typ Max Unit MSPS MSPS ns ns ns 1 12.5 4.6 4.6 4.2 7 1 0.3 7 2 ns Cycles ns ps rms ms Cycles With duty cycle stabilizer (DCS) enabled. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. N N+1 N+2 N–1 tA ANALOG INPUT N+8 N+3 N+7 N+4 N+5 N+6 CLK DATA OUT N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N tPD = 6.0ns MAX 2.0ns MIN 03583-B-002 Figure 2. Timing Diagram EXPLANATION OF TEST LEVELS Test Level I II III IV V VI Definitions 100% production tested. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. B | Page 6 of 28 AD9245 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. AD9245 Absolute Maximum Ratings Parameter With Respect to ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD D0–D13 DGND CLK, MODE AGND VIN+, VIN– AGND VREF AGND SENSE AGND REFT, REFB AGND PDWN AGND ENVIRONMENTAL Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Min Max Unit –0.3 –0.3 –0.3 –3.9 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 V V V V V V V V V V V –65 –40 +125 +85 °C °C 300 150 °C °C θJA is specified for the worst-case conditions on a 4-layer board in still air, in accordance with EIA/JESD51-1. Table 6. Thermal Resistance Package Type CP-32 θJA 32.5 θJC 32.71 Unit °C/W Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 28 AD9245 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth)—The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA)—The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ)—The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL)—The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges. Offset Error—The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is defined as the deviation of the actual transition from that point. Effective Number of Bits (ENOB)—The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: ENOB = (SINAD − 1.76 ) 6.02 Signal-to-Noise Ratio (SNR)1 —The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR)1—The difference in dB between the rms input signal amplitude and the peak spurious signal. The peak spurious component may or may not be a harmonic. Two-Tone SFDR1—The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulsewidth and Duty Cycle—Pulsewidth high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulsewidth low is the minimum time the clock pulse should be left in the Logic 0 state. At a given clock rate, these specifications define an acceptable clock duty cycle. Gain Error—The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Minimum Conversion Rate—The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Temperature Drift—The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Output Propagation Delay (tPD)—The delay between the clock rising edge and the time when all bits are within valid logic levels. Power Supply Rejection Ratio—The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Out-of-Range Recovery Time—The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Total Harmonic Distortion (THD)1—The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Maximum Conversion Rate—The clock rate at which parametric testing is performed. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Signal-to-Noise and Distortion (SINAD)1—The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Rev. B | Page 8 of 28 AD9245 25 REFB 26 REFT 27 AVDD 28 AGND 29 VIN+ 30 VIN– 31 AGND 32 AVDD PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS DNC 1 24 VREF CLK 2 23 SENSE DNC 3 22 MODE AD9245 PDWN 4 21 OTR CSP (LSB) D0 5 20 D13 (MSB) TOP VIEW (Not to Scale) D1 6 19 D12 DRVDD 16 DGND 15 D9 14 D8 13 D7 12 D6 11 17 D10 D4 9 18 D11 D3 8 D5 10 D2 7 03583-B-022 Figure 3. 32-Lead LFCSP Table 7. Pin Function Descriptions—32-Lead LFCSP (CP Package) Pin No. 1, 3 2 4 5 to 14, 17 to 20 15 16 21 22 23 24 25 26 27, 32 28, 31 29 30 Mnemonic DNC CLK PDWN D0 (LSB) to D13 (MSB) DGND DRVDD OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN– Description Do Not Connect Clock Input Pin Power-Down Function Select Data Output Bits Digital Output Ground Digital Output Driver Supply Out-of-Range Indicator Data Format Select and DCS Mode Selection (see Table 9) Reference Mode Selection (see Table 8) Voltage Reference Input/Output Differential Reference (–) Differential Reference (+) Analog Power Supply Analog Ground Analog Input Pin (+) Analog Input Pin (–) Rev. B | Page 9 of 28 AD9245 EQUIVALENT CIRCUITS AVDD DRVDD D13-D0, OTR VIN+, VIN– 03583-B-005 03583-B-003 Figure 6. Equivalent Digital Output Circuit Figure 4. Equivalent Analog Input Circuit AVDD AVDD CLK, PDWN MODE 20kΩ 03583-B-004 03583-B-006 Figure 5. Equivalent MODE Input Circuit Figure 7. Equivalent Digital Input Circuit Rev. B | Page 10 of 28 AD9245 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, DCS Disabled, TA = 25°C, 2 V p-p Differential Input, AIN = –0.5 dBFS, VREF = 1.0 V External, unless otherwise noted 0 100 AIN = –0.5dBFS SNR = 73.2dBc ENOB = 11.8 BITS SFDR = 92.8 dBc –10 –20 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) –30 AMPLITUDE (dBFS) SFDR (dBFS) –40 –50 –60 –70 –80 –90 SNR (dBFS) 80 70 SFDR = 90dBc REFERENCE LINE 60 SNR (dBc) 50 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 –20 100 –5 0 03583-B-033 SFDR (dBFS) 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) –30 AMPLITUDE (dBFS) –20 –15 –10 INPUT AMPLITUDE (dBFS) Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz AIN = –0.5dBFS SNR = 72.7dBc ENOB = 11.8 BITS SFDR = 87.6 dBc –10 –25 03583-B-032 Figure 8. Single Tone 8K FFT @ 2.5 MHz 0 40 –30 40 –40 –50 –60 –70 –80 –90 SNR (dBFS) 80 70 SFDR = 90dBc REFERENCE LINE 60 SNR (dBc) 50 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 –20 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 0 03583-B-034 Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz 100 AIN = –0.5dBFS SNR = 71.7dBc ENOB = 11.5 BITS SFDR = 81.6 dBc –10 –25 03583-B-023 Figure 9. Single Tone 8K FFT @ 39 MHz 0 40 –30 40 SFDR (DIFF) 90 SFDR (SE) –40 SNR/SFDR (dBc) AMPLITUDE (dBFS) –30 –50 –60 –70 –80 SNR (DIFF) 80 70 SNR (SE) –90 60 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 50 40 03583-B-024 Figure 10. Single Tone 8K FFT @ 70 MHz 0 20 40 60 SAMPLE RATE (MSPS) 80 Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz Rev. B | Page 11 of 28 100 03583-B-025 AD9245 100 0 AIN = –6.5dBFS SNR = 73.4dBFS SFDR = 86.0dBFS –10 –20 90 SNR/SFDR (dBc AND dBFS) –30 AMPLITUDE (dBFS) SFDR (dBFS) –40 –50 –60 –70 –80 –90 SFDR (dBc) 80 70 SNR (dBFS) SFDR = 90dBc REFERENCE LINE 60 SNR (dBc) 50 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –30 40 0 –9 –6 03583-B-031 SFDR (dBFS) 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) –30 AMPLITUDE (dBFS) –21 –18 –15 –12 INPUT AMPLITUDE (dBFS) 100 AIN = –6.5dBFS SNR = 72.7dBFS SFDR = 78.8dBFS –20 –24 Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz –10 –27 03583-B-029 –40 –50 –60 –70 –80 –90 80 70 SNR (dBFS) SFDR = 90dBc REFERENCE LINE 60 SNR (dBc) 50 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –30 40 –27 03583-B-030 Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz –24 –21 –18 –15 INPUT AMPLITUDE (dBFS) –12 –9 –6 03583-B-027 Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz 1.0 1.5 0.8 1.0 0.6 0.4 DNL (LSB) INL (LSB) 0.5 0 –0.5 0.2 0 –0.2 –0.4 –0.6 –1.0 –0.8 –1.5 –1.0 0 2048 4096 6144 8192 CODE 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE 03583-B-028 03583-B-026 Figure 19. Typical DNL Figure 16. Typical INL Rev. B | Page 12 of 28 AD9245 75 100 74 –40°C 73 95 +25°C 72 SNR (dBc) SFDR (dBc) 90 71 +85°C 70 69 68 85 –40°C 80 +25°C +85°C 67 75 66 65 0 25 50 75 INPUT FREQUENCY (MHz) 100 70 125 0 Figure 20. SNR vs. Input Frequency 90 –20 –30 AMPLITUDE (dBFS) SNR/SFDR (dBc) 125 03583-B-038 –10 84 SFDR (DCS OFF) 82 80 78 76 –40 –50 –60 –70 –80 –90 74 SNR (DCS OFF) –100 72 –110 SNR (DCS ON) 35 40 45 50 55 DUTY CYCLE (%) 60 65 –120 70 0 –20 –20 –30 –30 –40 –40 AMPLITUDE (dBFS) 0 –10 –50 –60 –70 –80 03583-B-060 –60 –70 –80 –90 –100 –100 –110 –110 –120 –120 28.8 38.4 –50 –90 19.2 28.8 Figure 24. Two 32K FFT CDMA-2000 Carriers @ FIN = 46.08 MHz; Sample Rate = 61.44 MSPS 0 FREQUENCY (MHz) 19.2 FREQUENCY (MHz) –10 9.6 9.6 03583-B-037 Figure 21. SNR/SFDR vs. Clock Duty Cycle AMPLITUDE (dBFS) 100 0 SFDR (DCS ON) 86 0 50 75 INPUT FREQUENCY (MHz) Figure 23. SFDR vs. Input Frequency 88 70 30 25 03583-B-036 38.4 0 9.6 19.2 28.8 FREQUENCY (MHz) 03583-B-059 Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS Rev. B | Page 13 of 28 Figure 25. Two 32K FFT WCDMA Carriers @ FIN = 76.8 MHz; Sample Rate = 61.44 MSPS 38.4 03583-B-061 AD9245 THEORY OF OPERATION The AD9245 architecture consists of a front-end sample and hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be accoupled or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. Referring to Figure 27, the clock signal alternately switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be reduced or removed. In combination with the driving source impedance, they would limit the input bandwidth. H T T 5pF VIN– CPAR T H 03583-B-012 Figure 27. Switched-Capacitor SHA Input The analog input to the AD9245 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range (VCM) and maintain excellent performance, as shown in Figure 26. An input common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance. 100 95 For best dynamic performance, the source impedances driving VIN+ and VIN– should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as follows: SFDR (2.5MHz) 90 1 REFT = ( AVDD + VREF ) 2 1 REFB = ( AVDD − VREF ) 2 Span = 2 × (REFT − REFB ) = 2 × VREF 85 SNR/SFDR (dBc) T CPAR ANALOG INPUT AND REFERENCE OVERVIEW SFDR (39MHz) 80 75 SNR (2.5MHz) 70 SNR (39MHz) 65 It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage, and, by definition, the input span is twice the value of the VREF voltage. 60 55 50 0.5 5pF VIN+ 1.0 1.5 2.0 COMMON-MODE LEVEL (V) 2.5 Figure 26. SNR, SFDR vs. Common-Mode Level 3.0 03583-B-039 The internal voltage reference can be pin strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9245 set Rev. B | Page 14 of 28 AD9245 to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. 33Ω The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as VCM MIN = VCM MAX = 2V p-p 49.9Ω 10pF 33Ω AVDD VIN+ AD9245 VIN– AGND 1kΩ VREF 2 0.1µF 1kΩ 03583-B-014 ( AVDD + VREF ) Figure 29. Differential Transformer-Coupled Configuration 2 The minimum common-mode input level allows the AD9245 to accommodate ground referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be applied to VIN+ or VIN–. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN–. The AD9245 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing (see Figure 13). However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 30 details a typical single-ended input configuration. Differential Input Configurations 1kΩ As previously detailed, optimum performance is achieved while driving the AD9245 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal. 2V p-p 0.33µF 1kΩ 49.9Ω 20pF 1kΩ + 10µF 33Ω 0.1µF 33Ω AVDD VIN+ AD9245 VIN– 1kΩ AGND 03583-B-015 Figure 30. Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS 1V p-p 49.9Ω 499Ω 33Ω 499Ω AD8138 1kΩ 33Ω 523Ω 0.1µF 20pF 1kΩ 499Ω AVDD VIN+ AD9245 VIN– AGND 03583-B-013 Figure 28. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9245. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependent on the input frequency and source impedance and should be reduced or removed. An example is shown in Figure 29. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9245 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9245. As shown in Figure 21, noise and distortion performance is nearly flat for a 30% to 70% duty cycle with the DCS on. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. Rev. B | Page 15 of 28 AD9245 140 425 JITTER CONSIDERATIONS ] In the equation, the rms aperture jitter represents the root-mean square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter (see Figure 31). 375 80 60 350 40 325 20 DIGITAL CURRENT 300 10 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9245. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 0.2ps MEASURED SNR 65 SNR (dBc) 0.5ps 60 30 40 50 60 70 SAMPLE RATE (MSPS) 80 90 0 100 03583-B-035 Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 32 was taken with the same operating conditions as the Typical Performance Characteristics, and with a 5 pF load on each output driver. 1.0ps Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 10 µF decoupling capacitors on REFT and REFB, it takes approximately 1 second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation. 1.5ps 55 2.0ps 2.5ps 50 3.0ps 45 40 20 By asserting the PDWN pin high, the AD9245 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9245 to its normal operational mode. 75 70 100 TOTAL POWER CURRENT (mA) [ SNR = 20 log 2 πf INPUT × t J 120 400 TOTAL POWER (mW) High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated with the following equation: ANALOG CURRENT 1 10 100 INPUT FREQUENCY (MHz) 1000 03583-B-041 Figure 31. SNR vs. Input Frequency and Jitter POWER DISSIPATION AND STANDBY MODE As shown in Figure 32, the power dissipated by the AD9245 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as I DRVDD = VDRVDD × C LOAD × f CLK × N where N is the number of output bits, 14 in the case of the AD9245. This maximum current occurs when every output bit switches on every clock cycle, i.e., a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current will be established by the average number of output bits switching, which will be determined by the sample rate and the characteristics of the analog input signal. DIGITAL OUTPUTS The AD9245 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. As detailed in Table 9, the data format can be selected for either offset binary or twos complement. Rev. B | Page 16 of 28 AD9245 TIMING The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+ The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9245. These transients can degrade the converter’s dynamic performance. VIN– + 10µF 0.1µF SELECT LOGIC SENSE 0.5V AD9245 03583-B-017 Figure 33. Internal Reference Configuration If the internal reference of the AD9245 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 34 depicts how the internal reference voltage is affected by loading. 0.05 0 –0.05 ERROR (%) A comparator within the AD9245 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table 8. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 33), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 35, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as follows: + 0.1µF VREF A stable and accurate 0.5 V voltage reference is built into the AD9245. The input range can be adjusted by varying the reference voltage applied to the AD9245 using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized Table 8 and described in the following sections. INTERNAL REFERENCE CONNECTION 0.1µF REFB 10µF If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). 0.1µF ADC CORE The lowest typical conversion rate of the AD9245 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. VOLTAGE REFERENCE REFT 0.5V ERROR (%) –0.10 1.0V ERROR (%) –0.15 –0.20 R2 VREF = 0.5 × 1 + R1 –0.25 0 0.5 1.0 1.5 LOAD (mA) 2.0 2.5 3.0 03583-B-019 Figure 34. VREF Accuracy vs. Load Table 8. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference SENSE Voltage AVDD VREF 0.2 V to VREF Internal Switch Position N/A SENSE SENSE Resulting VREF (V) N/A 0.5 Internal Fixed Reference AGND to 0.2 V Internal Divider 1.0 R2 (See Figure 35) 0 . 5 × 1 + R1 Rev. B | Page 17 of 28 Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF 2.0 AD9245 OPERATIONAL MODE SELECTION VIN+ VIN– REFT 0.1µF ADC CORE + 0.1µF 10µF REFB 0.1µF VREF + 10µF 0.1µF Table 9. Mode Selection SELECT LOGIC R2 As discussed earlier, the AD9245 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock duty cycle stabilizer (DCS). The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 9. SENSE R1 MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) 0.5V AD9245 Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled 03583-B-018 Figure 35. Programmable Reference Configuration EVALUATION BOARD EXTERNAL REFERENCE OPERATION The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. Figure 36 shows the typical drift characteristics of the internal reference in both 1.0 V and 0.5 V modes. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1.0 V. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. The AD9245 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). An alternative differential analog input path using an AD8351 op amp is included in the layout, but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3, and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9245 allows the user to optimize the frequency response of the op amp for the application. 1.0 0.9 0.8 0.7 VREF ERROR (%) The AD9245 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. 0.6 0.5 0.4 0.3 VREF = 1.0V 0.2 0.1 VREF = 0.5V 0 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 03583-B-040 Figure 36. Typical VREF Drift Rev. B | Page 18 of 28 GND J1 Figure 37. LFCSP Evaluation Board Schematic—Analog Inputs and DUT PRI SEC PRI SEC R10 36Ω E 45 XOUT R11 36Ω R18 25Ω 0.1µF C11 R2 XX C18 0.10µF GND GND C21 10pF R15 33Ω AVDD R13 1kΩ C23 10pF P4 P3 R25 1kΩ GND AVDD 3 2 4 P1 AVDD GND VIN+ VIN– R6 1kΩ R7 1kΩ R5 1kΩ GND GND 15pF C19 OR L1 FOR FILTER GND R4 33Ω R36 1kΩ R26 1kΩ C22 10µF GND GND C13 0.10µF AVDD GND D R SINGLE ENDED R3 0Ω GND C5 0.1µF C26 10pF AMPINB R3, R17, R18 ONLY ONE SHOULD BE ON BOARD AT A TIME XOUTB GND C7 0.1µF GND R12 0Ω GND P10 C C29 10µF E P7 A B C9 0.10µF AMPIN C16 0.1µF R42 0Ω 6 2 CT 4 T1 ADT1–1WT XFRIN1 1 5 NC 3 GND C6 0.1µF GND 0.1µF C12 OPTIONAL XFR T2 FT C1–1–13 5 1 XOUT X FRIN 2 CT 3 4 GND XOUTB C15 AMP 0.1µF L1 10nH GND R9 10kΩ R1 10kΩ AVDD GND P11 P9 P8 P6 MODE 2 P5 31 AGND 32 AVDD 28 AGND 29 VIN+ 30 VIN– 25 REFB 26 REFT 27 AVDD GND GND AVDD P14 CLK C8 0.1µF U4 AD9245 P13 R8 1kΩ 15 14 16 GND D5 10 D4 9 13 D7 12 D6 11 DVDD DGND D9 D8 1 AVDD 6 5 4 GND 3 2.5V DRVDD 2 GND (LSB) 12 11 10 9 6 7 8 RP1 220Ω 13 5 10 9 7 8 4 11 6 15 14 12 5 16 13 4 2 3 15 14 1 16 MODE PIN SOLDERABLE JUMPER: 5 TO 1: TWOS COMPLEMENT/DCS OFF 5 TO 2: TWOS COMPLEMENT/DCS ON 5 TO 3: OFFSET BINARY/DCS ON 5 TO 4: OFFSET BINARY/DCS OFF 03583-B-050 D0X D1X D2X D4X D3X D6X D5X D8X D7X D9X D10X D12X D11X DRX D13X H4 MTHOLE6 H3 MTHOLE6 H2 MTHOLE6 H1 MTHOLE6 2 3 RP2 220Ω GND 1 P2 SENSE PIN SOLDERABLE JUMPER: E TO A: EXTERNAL VOLTAGE DIVIDER E TO B: INTERNAL 1V REFERENCE (DEFAULT) E TO C: EXTERNAL REFERENCE E TO D: INTERNAL 0.5V REFERENCE DRVDD GND (MSB) OVERRANGE BIT 3.0V 1 1 DNC 2 CLK D12 19 D11 18 D10 17 VDL 2.5V AVDD VREF 24 SENSE 23 MODE 22 OTR 21 D13 20 3 DNC 4 PDWN Rev. B | Page 19 of 28 5 D0 6 D1 7 D2 8 D3 VAMP 5.0V EXTREF 1V MAX E1 AD9245 LSB MSB Figure 38. LFCSP Evaluation Board Schematic—Digital Path Rev. B | Page 20 of 28 GND R19 50Ω AMP 2CLK IN 1 U1 2OE 24 OUT 23 2Q7 22 GND 21 2Q6 20 2Q5 19 VCC 18 2Q4 17 2Q3 16 GND 15 2Q2 14 2Q1 13 1Q8 12 1Q7 11 GND 10 1Q6 9 1Q5 VCC 8 7 1Q4 6 1Q3 5 GND 4 1Q2 3 1Q1 2 1OE 1 2QB GND R35 25Ω R40 10kΩ GND C35 0.10µF C28 0.1µF R41 10kΩ VAMP POWER DOWN USE R40 OR R41 2DB 26 2D7 27 GND 28 2D6 29 2D5 30 V 31 CC 2D4 32 2D3 33 GND 34 2D2 35 2D1 36 1D8 37 1D7 38 GND 39 1D6 40 1D5 41 VCC 42 1D4 43 1D3 44 GND 45 1D2 46 1D1 47 1CLK 48 25 AMP IN CLKLAT/DAC GND D0X DRVDD D2X D1X D4X D3X GND D5X D7X D6X GND D8X D10X D9X DRVDD D11X GND D12X DRX D13X CLKAT/DAC 74LVTH162374 R33 RPG2 5 25Ω INLO 4 INHI 3 PWDN 1 RGP1 2 GND GND DRVDD GND GND DRVDD GND GND R34 1.2kΩ U3 AD8351 GND VAMP DRY 6 COMM 7 OPLO 9 VPOS 8 OPHI 10 VOCM C44 0.1µF R38 1kΩ GND R14 25Ω VAMP R39 1kΩ C45 0.1µF C24 10µF R17 0Ω R16 0Ω GND GND GND MSB GND C17 0.1µF C27 0.1µF GND DRY GND DR AMPIN AMPINB 11 9 7 3 5 1 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 35 35 37 37 39 39 11 12 7 9 10 8 1 4 6 HEADER 40 3 5 2 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 36 36 38 38 40 40 12 10 8 4 6 2 03583-B-051 GND AD9245 C4 10µF GND Figure 39. LFCSP Evaluation Board Schematic—Clock Input Rev. B | Page 21 of 28 J2 GND R29 50Ω C43 0.1µF ENC ENCX GND R30 1kΩ R31 1kΩ VDL R27 0Ω R28 0Ω VDL VDL E43 E44 E35 E51 E52 VDL E31 VDL E50 CLK ENC C33 C14 0.1µF 0.001µF ANALOG BYPASSING C32 0.001µF CLOCK TIMING ADJUSTMENTS GND ENCODE C25 10µF GND AVDD FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 AVDD C3 10µF DUT BYPASSING C10 22µF VDL DRVDD R20 1kΩ GND GND R24 1kΩ GND R21 1kΩ GND E53 GND R32 1kΩ C41 0.1µF DRVDD C30 0.001µF 5 9 10 12 13 3A 3B 4A 4B 2B 1 1A 2 1B 4 2A C31 0.1µF GND U5 14 8 11 6 7 3 C34 0.1µF 4Y PWR 3Y 2Y 1Y 74VCX86 DIGITAL BYPASSING C2 22µF VDL GND ENCX C36 0.1µF R23 0Ω C1 C39 0.001µF 0.1µF CLKLAT/DAC R37 25Ω Rx DNP VDL DR R22 0Ω GND C49 0.001µF LATCH BYPASSING C47 0.1µF SCHEMATIC SHOWS TWO GATE DELAY SETUP. FOR ONE DELAY, REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0Ω). C38 0.001µF C48 0.001µF GND VAMP C20 10µF C40 0.001µF 03583-B-052 C46 10µF C37 0.1µF AD9245 AD9245 03583-B-055 03583-B-053 Figure 42. LFCSP Evaluation Board Layout, Ground Plane Figure 40. LFCSP Evaluation Board Layout, Primary Side 03583-B-056 03583-B-054 Figure 43. LFCSP Evaluation Board Layout, Power Plane Figure 41. LFCSP Evaluation Board Layout, Secondary Side Rev. B | Page 22 of 28 AD9245 03583-B-057 03583-B-058 Figure 44. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 45. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. B | Page 23 of 28 AD9245 Table 10. LFCSP Evaluation Board Bill of Materials Item Qty. Omit1 Reference Designator C1, C5, C7, C8, C9, C11, C12, 18 C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 1 C6, C18, C27, C17, 8 C28, C35, C45, C44 C2, C3, C4, C10, C20, C22, 8 C25, C29 2 2 C46, C24 C14, C30, C32, C38, 3 8 C39, C40, C48, C49 4 3 C19, C21, C23 Device Package Value Chip Capacitor 0603 0.1 µF Tantalum Capacitor TAJD 10 µF Chip Capacitor 0603 0.001 µF 5 6 Chip Capacitor 0603 10 pF 1 C26 Chip Capacitor 0603 10 pF 9 E31, E35, E43, E44, E50, E51, E52, E53 Header EHOLE J1, J2 SMA Connector/50 Ω SMA L1 Inductor 0603 2 7 2 8 1 Recommended Vendor/Part Number Jumper Blocks E1, E45 10 nH Coilcraft/0603CS10NXGBU 9 1 P2 Terminal Block TB6 Wieland/25.602.2653.0, z5-530-0625-0 10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND Chip Resistor 0603 0Ω R4, R15 Chip Resistor R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, Chip Resistor R36 R10, R11 Chip Resistor 0603 33 Ω 0603 1 kΩ 0603 36 Ω Chip Resistor 0603 50 Ω 220 Ω 11 5 12 2 13 14 14 2 15 R3, R12, R23, R28, Rx 6 1 R16, R17, R22, R27, R42, R37 R29 1 Supplied by ADI R19 16 2 RP1, RP2 Resistor Pack R_742 17 1 T1 ADT1-1WT AWT1-1T Digi-Key CTS/742C163220JTR Mini-Circuits 18 1 U1 74LVTH162374 CMOS Register TSSOP-48 19 1 U4 AD9245BCP ADC (DUT) CSP-32 Analog Devices, Inc. X 20 1 U5 74VCX86M SOIC-14 Fairchild 21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X X 22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. 23 1 T2 MACOM Transformer ETC1-1-13 1-1 TX MACOM/ETC1-1-13 24 5 R1, R2, R9, R38, R39 Chip Resistor 0603 SELECT 25 3 R14, R18, R35 Chip Resistor 0603 25 Ω 0603 10 kΩ 26 2 R40, R41 Chip Resistor 27 1 R34 Chip Resistor 1.2 kΩ 28 1 R33 Chip Resistor 100 Ω Total 82 34 1 These items are included in the PCB design, but are omitted at assembly. Rev. B | Page 24 of 28 AD9245 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 0.60 MAX 32 1 3.25 3.10 SQ 2.95 BOTTOM VIEW 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 46. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32-1) Dimensions shown in millimeters ORDERING GUIDE AD9245 Products AD9245BCP-801 AD9245BCPRL7–801 AD9245BCPZ-801, 2 AD9245BCPZRL7-801, 2 AD9245BCP-80EB1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Evaluation Board Package Outline CP-32-1 CP-32-1 CP-32-1 CP-32-1 1 It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. 2 Z = Lead Free. Rev. B | Page 25 of 28 AD9245 NOTES Rev. B | Page 26 of 28 AD9245 NOTES Rev. B | Page 27 of 28 AD9245 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03583-0-10/03(B) Rev. B | Page 28 of 28