Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators ADCMP606/ADCMP607 Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCC + 0.2 V CML-compatible output stage 1.25 ns propagation delay 50 mW @ 2.5V VCC Shutdown pin Single-pin control for programmable hysteresis and latch (ADCMP607 only) Power supply rejection > 60 dB −40°C to +125°C operation APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) FUNCTIONAL BLOCK DIAGRAM VCCI VCCO (ADCMP607 ONLY) VP NONINVERTING INPUT Q OUTPUT ADCMP606/ ADCMP607 CML Q OUTPUT VN INVERTING INPUT LE/HYS INPUT (ADCMP607 ONLY) SDN INPUT (ADCMP607 ONLY) 05917-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADCMP606 and ADCMP607 are very fast comparators fabricated on XFCB2, an Analog Devices, Inc. proprietary process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE − 0.5 V to VCC + 0.2 V, low noise, CML-compatible output drivers, and TTL-/CMOS-compatible latch inputs with adjustable hysteresis and/or shutdown inputs. The devices offer 1.25 ns propagation delay with 2.5 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a −0.5 V to +2.7 V input signal range up to a +5.5 V positive supply with a −0.5 V to +5.7 V input signal range. The ADCMP607 features split input/output supplies with no sequencing restrictions to support a wide input signal range with independent output swing control and power savings. The CML-compatible output stage is fully back-matched for superior performance. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. On the ADCMP607, latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP606 is available in a 6-lead SC70 package and the ADCMP607 is available in a 12-lead LFCSP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADCMP606/ADCMP607 TABLE OF CONTENTS Features .............................................................................................. 1 Power/Ground Layout and Bypassing..................................... 10 Applications....................................................................................... 1 CML-Compatible Output Stage ............................................... 10 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature........................................... 10 General Description ......................................................................... 1 Optimizing Performance........................................................... 10 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ........................... 11 Specifications..................................................................................... 3 Comparator Hysteresis .............................................................. 11 Electrical Characteristics............................................................. 3 Crossover Bias Points................................................................. 12 Timing Information ......................................................................... 5 Minimum Input Slew Rate Requirement ................................ 12 Absolute Maximum Ratings............................................................ 6 Typical Application Circuits ......................................................... 13 Thermal Resistance ...................................................................... 6 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions............................. 7 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 Application Information................................................................ 10 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADCMP606/ADCMP607 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCCI = VCCO =2.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE PIN CHARACTERISTICS (ADCMP606 Only) VIH VIL IIH IOL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP607 Only) VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Minimum VCCO for Operation Without External Termination (ADCMP607) Symbol Conditions Min VP, VN VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V −0.5 −0.2 VOS IP, IN −5.0 −5.0 −2.0 ±2 −0.1 V to VCC −0.5 V to VCC + 0.5 V 200 100 1 700 350 85 VCCI = 2.5 V, VCCO = 2.5 V, VCM = −0.2 V to +2.7 V VCCI = 2..5 V, VCCO = 5.5 V RHYS = ∞ 50 Hysteresis is shut off Latch mode guaranteed VIH = VCC VIL = 0.4 V 2.0 −0.2 −6 −0.1 Current sink 0 μA Hysteresis = 120 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV 1.145 55 Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V 10% output swing VOD = 100 mV, output valid VCCO = 2.5 V to 5.5 V RI = 50 Ω, VCCO = 2.5 V RI = 50 Ω, VCCO = 2.5 V TA = −40°C, VOL = VCC − 0.7 2.0 −0.2 −6 CP, CN AV CMRR tS tH tPLOH, tPLOL tPL tSD tH VOH VOL Typ Rev. 0 | Page 3 of 16 Max Unit VCC + 0.2 VCC + 0.2 VCC +5.0 +5.0 2.0 V V V mV μA μA pF kΩ kΩ dB dB 50 dB mV <0.1 +0.4 1.25 75 −1.5 2.3 30 25 +0.4 VCC +0.8 +6 +0.1 V V μA mA 1.35 110 V kΩ ns ns ns ns VCCO +0.6 +6 −0.1 V V μA mA ns ns VCC + 0.1 VCC − 0.35 V V V <1 35 VCC − 0.1 VCC − 0.5 2.7 ADCMP606/ADCMP607 Parameter AC PERFORMANCE 1 Rise Time /Fall time Conditions tR t F 10% to 90%, VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V, VOD = 50 mV, VCC = 2.5 V, VOD = 10 mV VOD = 50 mV Propagation Delay tPD Propagation Delay Skew—Rising to Falling Transition Overdrive Dispersion Common-Mode Dispersion Input Stage Bandwidth RMS Random Jitter Minimum Pulse Width TPINSKEW Output Skew Q to Q TDIFFSKEW POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP607) Positive Supply Current (ADCMP606) Input Section Supply Current (ADCMP607) Output Section Supply Current (ADCMP607) Power Dissipation Power Supply Rejection Ratio Shutdown Mode ICCI Shutdown Mode ICCO 1 Symbol Min 10 mV < VOD < 125 mV −0.2 V < VCM < VCC + 0.2 V RJ PWMIN VCCI VCCO VCCI − VCCO VCCI − VCCO IVCC IVCCI IVCCO IVCCO PD PD PSRR VOD = 200 mV, 0.5 V/ns VCCI = VCCO = 5.5 V, PWOUT = 90% of PWIN 50% Operating Nonoperating VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V 2.5 2.5 −3.0 −6 11 16 0.5 VCCI = 2.5 V VCCI = 5.5 V VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5 V VCCI =2.5 V to 5 V VCCI =2.5 V to 5 V 10 16 30 90 −50 200 −30 VIN = 100 mV square input at 50 MHz, VCM = 2.5 V, VCCI = VCCO = 2.5 V, unless otherwise noted. Rev. 0 | Page 4 of 16 Typ Max Unit 160 ps 1.2 ns 2.1 40 ns ps 2.3 150 750 2 1.1 ns ps MHz ps ns 20 ps 17.5 20.5 1.1 5.5 5.5 +3.0 +6 21 26 1.5 V V V V mA mA mA 15.8 18 46 110 18 25 55 150 240 800 30 mA mA mW mW dB μA μA ADCMP606/ADCMP607 TIMING INFORMATION Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2. 1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VN ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 05917-025 50% Q OUTPUT Figure 2. System Timing Diagram Table 2. Timing Descriptions Symbol tF Timing Output fall time tH Minimum hold time tPDH Input to output high delay tPDL Input to output low delay tPL tPLOH Minimum latch enable pulse width Latch enable to output high delay tPLOL Latch enable to output low delay tR Output rise time tS Minimum setup time VOD Voltage overdrive Description Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Minimum time that the latch enable signal must be high to acquire an input signal change. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Difference between the input voltages VA and VB. Rev. 0 | Page 5 of 16 ADCMP606/ADCMP607 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI − VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V −0.5 V to +6.0 V −6.0 V to +6.0 V THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. −0.5 V to VCCI + 0.5 V ±(VCCI + 0.5 V) ±50 mA Table 4. Thermal Resistance −0.5 V to VCCO + 0.5 V ±50 mA Package Type ADCMP606 SC70 6-Lead ADCMP607 LFCSP 12-Lead 1 −0.5 V to VCCO + 0.5 V ±50 mA ±50 mA Measurement in still air. ESD CAUTION −40°C to +125°C 150°C −65°C to +150°C Rev. 0 | Page 6 of 16 θJA1 426 62 Unit °C/W °C/W ADCMP606/ADCMP607 ADCMP606 5 VCCI /VCCO TOP VIEW (Not to Scale) 4 VN VEE 3 Figure 3. ADCMP606 Pin Configuration 10 Q ADCMP607 TOP VIEW (Not to Scale) VP 4 VP 3 VCCI 2 PIN 1 INDICATOR 9 VEE 8 LE/HYS 7 SDN 05917-003 VCCO 1 VN 6 Q 05917-002 VEE 2 6 VEE 5 Q 1 11 VEE 12 Q PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. ADCMP607 Pin Configuration Table 5. ADCMP606 (SC70-6) Pin Function Descriptions Pin No. 1 Mnemonic Q 2 3 4 5 6 VEE VP VN VCCI/VCCO Q Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Input Section Supply/Output Section Supply. Shared pin. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VIN. Table 6. ADCMP607 (LFCSP-12) Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VCCO VCCI VEE VP VEE VN SDN LE/HYS VEE Q 11 12 VEE Q Heat Sink Paddle VEE Description Output Section Supply. Input Section Supply. Negative Supply Voltage. Noninverting Analog Input. Negative Supply Voltage. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Negative Supply Voltage. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. 0 | Page 7 of 16 ADCMP606/ADCMP607 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted. 800 250 600 200 400 VCC = 5.5V HYSTERESIS (mV) CURRENT (µA) VCC = 2.5V 200 0 –200 150 –40°C 100 +25°C –400 50 –600 1 2 3 4 LE/HYS PIN (V) 5 6 7 05917-026 0 0 0 –2 Figure 5. LE/HYS Pin I/V Curve 400 150 350 –16 –18 300 VCC = 2.5V HYSTERESIS (mV) 100 VCC = 5.5V 50 0 –50 250 200 150 VCC = 2.5V 100 –100 50 0 1 2 3 4 SDN PIN (V) 5 6 7 0 05917-007 –1 50 100 150 200 250 300 350 400 450 500 550 600 650 HYS RESISTOR (kΩ) Figure 6. SDN I/V Curve 05917-005 CURRENT (µA) –6 –8 –10 –12 –14 LE/HYS PIN CURRENT (µA) Figure 8. Hysteresis vs. LE/HYS Pin Current 200 –150 –4 05917-004 +125°C –800 –1 Figure 9. Hysteresis vs. RHYS 10 3.5 8 6 0 –2 –4 –40°C –6 +25°C –8 2.5 2.0 PROPAGATION DELAY FALL 1.5 +125°C –10 –1.0 –0.5 0 0.5 1.0 1.5 2.0 VCM AT VCC = 2.5V 2.5 3.0 3.5 1.0 05917-006 IB (µA) 2 PROPAGATION DELAY RISE 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 OVERDRIVE (mV) Figure 10. Propagation Delay vs. Input Overdrive Figure 7. Input Bias Current vs. Common-Mode Voltage Rev. 0 | Page 8 of 16 05917-009 PROPAGATION DELAY (nS) 3.0 4 ADCMP606/ADCMP607 1.4 5.550V Q 1.3 1.2 Q 0.2 0.6 1.0 1.4 1.8 2.2 VCM AT VCC = 2.5V 2.6 5.050V 05917-010 1.1 –0.2 3.0 Figure 11. Propagation Delay vs. Input Common Mode Figure 13. Output Waveform at VCC = 5.5 V 2.550V Q Q 2.050V 1.000ns/DIV 1.000ns/DIV Figure 12 .Output Waveform at VCC = 2.5 V Rev. 0 | Page 9 of 16 05917-012 PROPAGATION DELAY RISE ns 05917-011 PROPAGATION DELAY (ns) PROPAGATION DELAY FALL ns ADCMP606/ADCMP607 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP606/ADCMP607 comparators are very high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 μF bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. CML-COMPATIBLE OUTPUT STAGE Specified propagation delay dispersion performance can be achieved by using proper transmission line terminations. The outputs of the ADCMP606 and ADCMP607 are designed to drive 400 mV directly into a 50 Ω cable or into transmission lines terminated using either microstrip or strip line techniques with 50 Ω referenced to VCC. The CML output stage is shown in the simplified schematic diagram in Figure 14. Each output is backterminated with 50 Ω for best transmission line matching. VCCO 50Ω Q Q GND 05917-013 16mA Figure 14. Simplified Schematic Diagram of CML-Compatible Output Stage If these high speed signals must be routed more than a centimeter, then either microstrip or strip line techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion. It is also possible to operate the outputs with the internal termination only if greater output swing is desired. This can be especially useful for driving inputs on CMOS devices intended for full swing ECL and PECL, or for generating pseudo PECL levels. To avoid deep saturation of the outputs and resulting pulse dispersion, VCCO must be kept above the specified minimum output low level (see the Electrical Characteristics section). The line length driven should be kept as short as possible. USING/DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility. It can safely be left floating or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 Ω. This allows the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Driving this pin high or floating the pin removes all hysteresis. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC. OPTIMIZING PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulse width dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling. Rev. 0 | Page 10 of 16 ADCMP606/ADCMP607 The ADCMP606/ADCMP607 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI − 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). new switching threshold becomes −VH/2. The comparator remains in the high state until the new threshold, −VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. OUTPUT Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 15 and Figure 16). The device dispersion is typically 2.3 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because each device has very closely matched delays for positive-going and negative-going inputs as well as very low output skews. 500mV OVERDRIVE INPUT VOLTAGE 10mV OVERDRIVE VN ± VOS Q/Q OUTPUT VOL –VH 2 0 +VH 2 INPUT Figure 17. Comparator Hysteresis Transfer Function The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. This ADCMP607 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable, stable manner. Leaving the LE/HYS pin disconnected or driving this pin high removes hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 18 illustrates typical hysteresis applied as a function of the external resistor value, and Figure 7 illustrates typical hysteresis as a function of the current. 05917-014 DISPERSION VOH 05917-016 COMPARATOR PROPAGATION DELAY DISPERSION Figure 15. Propagation Delay—Overdrive Dispersion INPUT VOLTAGE 1V/ns VN ± VOS 10V/ns 400 350 COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. Figure 17 shows the transfer function for a comparator with hysteresis. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2, and the Rev. 0 | Page 11 of 16 250 200 150 VCC = 2.5V 100 50 0 50 100 150 200 250 300 350 400 450 500 550 600 650 HYS RESISTOR (kΩ) Figure 18. Hysteresis vs. RHYS Control Resistor 05917-017 Figure 16. Propagation Delay—Slew Rate Dispersion HYSTERESIS (mV) Q/Q OUTPUT 300 05917-015 DISPERSION ADCMP606/ADCMP607 The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7 kΩ ± 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the LE/HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. CROSSOVER BIAS POINTS In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and the measured offset voltages and currents change. The ADCMP606/ADCMP607 comparators slightly elaborate on this scheme. Crossover points are found at approximately 0.6 V and 1.6 V common mode. MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PC Board design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation is observed. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PC board. In many applications, chattering is not harmful. Rev. 0 | Page 12 of 16 ADCMP606/ADCMP607 TYPICAL APPLICATION CIRCUITS 2.5V TO 5V 0.1µF 50Ω 2kΩ 2kΩ 50Ω 5V 50Ω CML OUTPUT ADCMP606 0.1µF 50Ω CML PWM OUTPUT ADCMP606 05917-018 INPUT Figure 19. Self-Biased, 50% Slicer INPUT 2.5V ±50mV 3.3V INPUT 2.5V REF 10kΩ 10kΩ ADCMP601 CML OUTPUT ADCMP606 100Ω 10kΩ LE/HYS 150pF 100kΩ 05917-019 LVDS 50Ω 05917-022 50Ω Figure 23. Oscillator and Pulse-Width Modulator Figure 20. LVDS to CML 2.5V TO 5V 5V 50Ω 10kΩ 82pF 50Ω ADCMP607 50Ω CML OUTPUT ADCMP607 50Ω DIGITAL INPUT LE/HYS LE/HYS 74 VHC 1G07 CONTROL VOLTAGE 0V TO 2.5V 05917-020 10kΩ 10kΩ Figure 21. Current-Controlled Oscillator 150kΩ Figure 24. Hysteresis Adjustment with Latch +2.5V – 3V VCCI 3.3V VCCI 1N4001 100Ω ADCMP607 50Ω ADCMP607 50Ω OUTPUT 3.3V PECL 05917-021 LVDS 50Ω VCCO 50Ω VCCO –2.5V VEE Figure 22 .Fake PECL Levels Using a Series Diode 05917-024 CONTROL VOLTAGE 05917-023 150kΩ Figure 25 .Ground-Referenced CML with ±3 V Input Range Rev. 0 | Page 13 of 16 ADCMP606/ADCMP607 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 6 5 4 1 2 3 2.40 2.10 1.80 PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 0.80 0.30 0.15 0.10 MAX 0.40 0.10 0.46 0.36 0.26 0.22 0.08 SEATING PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 26. 6-Lead Thin Shrink Small Outline Transistor Package (SC70) (KS-6) Dimensions shown in millimeters 3.00 BSC SQ 0.60 MAX 0.45 PIN 1 INDICATOR 0.75 0.55 0.35 9 2.75 BSC SQ TOP VIEW 10 11 12 8 12° MAX SEATING PLANE 1.30 SQ 1.15 6 5 4 3 0.25 MIN 0.50 BSC 0.80 MAX 0.65 TYP 1.00 0.85 0.80 *1.45 1 2 7 EXPOSED PAD (BOTTOM VIEW) PIN 1 INDICATOR 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 27. 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 3 mm × 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP606BKSZ-R21 ADCMP606BKSZ-RL1 ADCMP606BKSZ-REEL71 ADCMP607BCPZ-R21 ADCMP607BCPZ-R71 ADCMP607BCPZ-WP1 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ) Z = Pb-free part. Rev. 0 | Page 14 of 16 Package Option KS-6 KS-6 KS-6 CP-12-1 CP-12-1 CP-12-1 Branding G0S G0S G0S G0H G0H G0H ADCMP606/ADCMP607 NOTES Rev. 0 | Page 15 of 16 ADCMP606/ADCMP607 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05917-0-10/06(0) Rev. 0 | Page 16 of 16